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Commit | Line | Data |
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ae2f26aa MCC |
1 | ================ |
2 | SMP IRQ affinity | |
3 | ================ | |
4 | ||
18404756 | 5 | ChangeLog: |
ae2f26aa MCC |
6 | - Started by Ingo Molnar <[email protected]> |
7 | - Update by Max Krasnyansky <[email protected]> | |
1da177e4 | 8 | |
1da177e4 | 9 | |
4b060420 MT |
10 | /proc/irq/IRQ#/smp_affinity and /proc/irq/IRQ#/smp_affinity_list specify |
11 | which target CPUs are permitted for a given IRQ source. It's a bitmask | |
12 | (smp_affinity) or cpu list (smp_affinity_list) of allowed CPUs. It's not | |
13 | allowed to turn off all CPUs, and if an IRQ controller does not support | |
14 | IRQ affinity then the value will not change from the default of all cpus. | |
1da177e4 | 15 | |
18404756 MK |
16 | /proc/irq/default_smp_affinity specifies default affinity mask that applies |
17 | to all non-active IRQs. Once IRQ is allocated/activated its affinity bitmask | |
18 | will be set to the default mask. It can then be changed as described above. | |
19 | Default mask is 0xffffffff. | |
20 | ||
1da177e4 | 21 | Here is an example of restricting IRQ44 (eth1) to CPU0-3 then restricting |
ae2f26aa | 22 | it to CPU4-7 (this is an 8-CPU SMP box):: |
1da177e4 | 23 | |
ae2f26aa MCC |
24 | [root@moon 44]# cd /proc/irq/44 |
25 | [root@moon 44]# cat smp_affinity | |
26 | ffffffff | |
18404756 | 27 | |
ae2f26aa MCC |
28 | [root@moon 44]# echo 0f > smp_affinity |
29 | [root@moon 44]# cat smp_affinity | |
30 | 0000000f | |
31 | [root@moon 44]# ping -f h | |
32 | PING hell (195.4.7.3): 56 data bytes | |
33 | ... | |
34 | --- hell ping statistics --- | |
35 | 6029 packets transmitted, 6027 packets received, 0% packet loss | |
36 | round-trip min/avg/max = 0.1/0.1/0.4 ms | |
37 | [root@moon 44]# cat /proc/interrupts | grep 'CPU\|44:' | |
38 | CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 | |
39 | 44: 1068 1785 1785 1783 0 0 0 0 IO-APIC-level eth1 | |
18404756 MK |
40 | |
41 | As can be seen from the line above IRQ44 was delivered only to the first four | |
42 | processors (0-3). | |
43 | Now lets restrict that IRQ to CPU(4-7). | |
44 | ||
ae2f26aa MCC |
45 | :: |
46 | ||
47 | [root@moon 44]# echo f0 > smp_affinity | |
48 | [root@moon 44]# cat smp_affinity | |
49 | 000000f0 | |
50 | [root@moon 44]# ping -f h | |
51 | PING hell (195.4.7.3): 56 data bytes | |
52 | .. | |
53 | --- hell ping statistics --- | |
54 | 2779 packets transmitted, 2777 packets received, 0% packet loss | |
55 | round-trip min/avg/max = 0.1/0.5/585.4 ms | |
56 | [root@moon 44]# cat /proc/interrupts | 'CPU\|44:' | |
57 | CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 | |
58 | 44: 1068 1785 1785 1783 1784 1069 1070 1069 IO-APIC-level eth1 | |
18404756 MK |
59 | |
60 | This time around IRQ44 was delivered only to the last four processors. | |
61 | i.e counters for the CPU0-3 did not change. | |
1da177e4 | 62 | |
ae2f26aa | 63 | Here is an example of limiting that same irq (44) to cpus 1024 to 1031:: |
4b060420 | 64 | |
ae2f26aa MCC |
65 | [root@moon 44]# echo 1024-1031 > smp_affinity_list |
66 | [root@moon 44]# cat smp_affinity_list | |
67 | 1024-1031 | |
4b060420 MT |
68 | |
69 | Note that to do this with a bitmask would require 32 bitmasks of zero | |
70 | to follow the pertinent one. |