[linux.git] / arch / mips / kernel / mips-mt.c

/*
 * General MIPS MT support routines, usable in AP/SP, SMVP, or SMTC kernels
 * Copyright (C) 2005 Mips Technologies, Inc
 */

#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/security.h>

#include <asm/cpu.h>
#include <asm/processor.h>
#include <linux/atomic.h>
#include <asm/system.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/mipsmtregs.h>
#include <asm/r4kcache.h>
#include <asm/cacheflush.h>

int vpelimit;

static int __init maxvpes(char *str)
{
	get_option(&str, &vpelimit);

	return 1;
}

__setup("maxvpes=", maxvpes);

int tclimit;

static int __init maxtcs(char *str)
{
	get_option(&str, &tclimit);

	return 1;
}

__setup("maxtcs=", maxtcs);

/*
 * Dump new MIPS MT state for the core. Does not leave TCs halted.
 * Takes an argument which taken to be a pre-call MVPControl value.
 */

void mips_mt_regdump(unsigned long mvpctl)
{
	unsigned long flags;
	unsigned long vpflags;
	unsigned long mvpconf0;
	int nvpe;
	int ntc;
	int i;
	int tc;
	unsigned long haltval;
	unsigned long tcstatval;
#ifdef CONFIG_MIPS_MT_SMTC
	void smtc_soft_dump(void);
#endif /* CONFIG_MIPT_MT_SMTC */

	local_irq_save(flags);
	vpflags = dvpe();
	printk("=== MIPS MT State Dump ===\n");
	printk("-- Global State --\n");
	printk("   MVPControl Passed: %08lx\n", mvpctl);
	printk("   MVPControl Read: %08lx\n", vpflags);
	printk("   MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
	ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
	printk("-- per-VPE State --\n");
	for (i = 0; i < nvpe; i++) {
		for (tc = 0; tc < ntc; tc++) {
			settc(tc);
			if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
				printk("  VPE %d\n", i);
				printk("   VPEControl : %08lx\n",
				       read_vpe_c0_vpecontrol());
				printk("   VPEConf0 : %08lx\n",
				       read_vpe_c0_vpeconf0());
				printk("   VPE%d.Status : %08lx\n",
				       i, read_vpe_c0_status());
				printk("   VPE%d.EPC : %08lx %pS\n",
				       i, read_vpe_c0_epc(),
				       (void *) read_vpe_c0_epc());
				printk("   VPE%d.Cause : %08lx\n",
				       i, read_vpe_c0_cause());
				printk("   VPE%d.Config7 : %08lx\n",
				       i, read_vpe_c0_config7());
				break; /* Next VPE */
			}
		}
	}
	printk("-- per-TC State --\n");
	for (tc = 0; tc < ntc; tc++) {
		settc(tc);
		if (read_tc_c0_tcbind() == read_c0_tcbind()) {
			/* Are we dumping ourself?  */
			haltval = 0; /* Then we're not halted, and mustn't be */
			tcstatval = flags; /* And pre-dump TCStatus is flags */
			printk("  TC %d (current TC with VPE EPC above)\n", tc);
		} else {
			haltval = read_tc_c0_tchalt();
			write_tc_c0_tchalt(1);
			tcstatval = read_tc_c0_tcstatus();
			printk("  TC %d\n", tc);
		}
		printk("   TCStatus : %08lx\n", tcstatval);
		printk("   TCBind : %08lx\n", read_tc_c0_tcbind());
		printk("   TCRestart : %08lx %pS\n",
		       read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
		printk("   TCHalt : %08lx\n", haltval);
		printk("   TCContext : %08lx\n", read_tc_c0_tccontext());
		if (!haltval)
			write_tc_c0_tchalt(0);
	}
#ifdef CONFIG_MIPS_MT_SMTC
	smtc_soft_dump();
#endif /* CONFIG_MIPT_MT_SMTC */
	printk("===========================\n");
	evpe(vpflags);
	local_irq_restore(flags);
}

static int mt_opt_norps;
static int mt_opt_rpsctl = -1;
static int mt_opt_nblsu = -1;
static int mt_opt_forceconfig7;
static int mt_opt_config7 = -1;

static int __init rps_disable(char *s)
{
	mt_opt_norps = 1;
	return 1;
}
__setup("norps", rps_disable);

static int __init rpsctl_set(char *str)
{
	get_option(&str, &mt_opt_rpsctl);
	return 1;
}
__setup("rpsctl=", rpsctl_set);

static int __init nblsu_set(char *str)
{
	get_option(&str, &mt_opt_nblsu);
	return 1;
}
__setup("nblsu=", nblsu_set);

static int __init config7_set(char *str)
{
	get_option(&str, &mt_opt_config7);
	mt_opt_forceconfig7 = 1;
	return 1;
}
__setup("config7=", config7_set);

/* Experimental cache flush control parameters that should go away some day */
int mt_protiflush;
int mt_protdflush;
int mt_n_iflushes = 1;
int mt_n_dflushes = 1;

static int __init set_protiflush(char *s)
{
	mt_protiflush = 1;
	return 1;
}
__setup("protiflush", set_protiflush);

static int __init set_protdflush(char *s)
{
	mt_protdflush = 1;
	return 1;
}
__setup("protdflush", set_protdflush);

static int __init niflush(char *s)
{
	get_option(&s, &mt_n_iflushes);
	return 1;
}
__setup("niflush=", niflush);

static int __init ndflush(char *s)
{
	get_option(&s, &mt_n_dflushes);
	return 1;
}
__setup("ndflush=", ndflush);

static unsigned int itc_base;

static int __init set_itc_base(char *str)
{
	get_option(&str, &itc_base);
	return 1;
}

__setup("itcbase=", set_itc_base);

void mips_mt_set_cpuoptions(void)
{
	unsigned int oconfig7 = read_c0_config7();
	unsigned int nconfig7 = oconfig7;

	if (mt_opt_norps) {
		printk("\"norps\" option deprectated: use \"rpsctl=\"\n");
	}
	if (mt_opt_rpsctl >= 0) {
		printk("34K return prediction stack override set to %d.\n",
			mt_opt_rpsctl);
		if (mt_opt_rpsctl)
			nconfig7 |= (1 << 2);
		else
			nconfig7 &= ~(1 << 2);
	}
	if (mt_opt_nblsu >= 0) {
		printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
		if (mt_opt_nblsu)
			nconfig7 |= (1 << 5);
		else
			nconfig7 &= ~(1 << 5);
	}
	if (mt_opt_forceconfig7) {
		printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
		nconfig7 = mt_opt_config7;
	}
	if (oconfig7 != nconfig7) {
		__asm__ __volatile("sync");
		write_c0_config7(nconfig7);
		ehb();
		printk("Config7: 0x%08x\n", read_c0_config7());
	}

	/* Report Cache management debug options */
	if (mt_protiflush)
		printk("I-cache flushes single-threaded\n");
	if (mt_protdflush)
		printk("D-cache flushes single-threaded\n");
	if (mt_n_iflushes != 1)
		printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
	if (mt_n_dflushes != 1)
		printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);

	if (itc_base != 0) {
		/*
		 * Configure ITC mapping.  This code is very
		 * specific to the 34K core family, which uses
		 * a special mode bit ("ITC") in the ErrCtl
		 * register to enable access to ITC control
		 * registers via cache "tag" operations.
		 */
		unsigned long ectlval;
		unsigned long itcblkgrn;

		/* ErrCtl register is known as "ecc" to Linux */
		ectlval = read_c0_ecc();
		write_c0_ecc(ectlval | (0x1 << 26));
		ehb();
#define INDEX_0 (0x80000000)
#define INDEX_8 (0x80000008)
		/* Read "cache tag" for Dcache pseudo-index 8 */
		cache_op(Index_Load_Tag_D, INDEX_8);
		ehb();
		itcblkgrn = read_c0_dtaglo();
		itcblkgrn &= 0xfffe0000;
		/* Set for 128 byte pitch of ITC cells */
		itcblkgrn |= 0x00000c00;
		/* Stage in Tag register */
		write_c0_dtaglo(itcblkgrn);
		ehb();
		/* Write out to ITU with CACHE op */
		cache_op(Index_Store_Tag_D, INDEX_8);
		/* Now set base address, and turn ITC on with 0x1 bit */
		write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
		ehb();
		/* Write out to ITU with CACHE op */
		cache_op(Index_Store_Tag_D, INDEX_0);
		write_c0_ecc(ectlval);
		ehb();
		printk("Mapped %ld ITC cells starting at 0x%08x\n",
			((itcblkgrn & 0x7fe00000) >> 20), itc_base);
	}
}

/*
 * Function to protect cache flushes from concurrent execution
 * depends on MP software model chosen.
 */

void mt_cflush_lockdown(void)
{
#ifdef CONFIG_MIPS_MT_SMTC
	void smtc_cflush_lockdown(void);

	smtc_cflush_lockdown();
#endif /* CONFIG_MIPS_MT_SMTC */
	/* FILL IN VSMP and AP/SP VERSIONS HERE */
}

void mt_cflush_release(void)
{
#ifdef CONFIG_MIPS_MT_SMTC
	void smtc_cflush_release(void);

	smtc_cflush_release();
#endif /* CONFIG_MIPS_MT_SMTC */
	/* FILL IN VSMP and AP/SP VERSIONS HERE */
}

struct class *mt_class;

static int __init mt_init(void)
{
	struct class *mtc;

	mtc = class_create(THIS_MODULE, "mt");
	if (IS_ERR(mtc))
		return PTR_ERR(mtc);

	mt_class = mtc;

	return 0;
}

subsys_initcall(mt_init);
Commit	Line	Data
41c594ab RB	1	/*
	2	* General MIPS MT support routines, usable in AP/SP, SMVP, or SMTC kernels
	3	* Copyright (C) 2005 Mips Technologies, Inc
	4	*/
	5
27a3bbaf	6	#include <linux/device.h>
41c594ab RB	7	#include <linux/kernel.h>
41c594ab RB	8	#include <linux/sched.h>
73bc256d	9	#include <linux/export.h>
41c594ab	10	#include <linux/interrupt.h>
f72af3cf	11	#include <linux/security.h>
41c594ab RB	12
	13	#include <asm/cpu.h>
	14	#include <asm/processor.h>
60063497	15	#include <linux/atomic.h>
41c594ab RB	16	#include <asm/system.h>
	17	#include <asm/hardirq.h>
	18	#include <asm/mmu_context.h>
41c594ab RB	19	#include <asm/mipsmtregs.h>
	20	#include <asm/r4kcache.h>
	21	#include <asm/cacheflush.h>
	22
07cc0c9e RB	23	int vpelimit;
	24
	25	static int __init maxvpes(char *str)
	26	{
	27	get_option(&str, &vpelimit);
	28
	29	return 1;
	30	}
	31
	32	__setup("maxvpes=", maxvpes);
	33
	34	int tclimit;
	35
	36	static int __init maxtcs(char *str)
	37	{
	38	get_option(&str, &tclimit);
	39
	40	return 1;
	41	}
	42
	43	__setup("maxtcs=", maxtcs);
	44
41c594ab RB	45	/*
	46	* Dump new MIPS MT state for the core. Does not leave TCs halted.
	47	* Takes an argument which taken to be a pre-call MVPControl value.
	48	*/
	49
	50	void mips_mt_regdump(unsigned long mvpctl)
	51	{
	52	unsigned long flags;
	53	unsigned long vpflags;
	54	unsigned long mvpconf0;
	55	int nvpe;
	56	int ntc;
	57	int i;
	58	int tc;
	59	unsigned long haltval;
	60	unsigned long tcstatval;
	61	#ifdef CONFIG_MIPS_MT_SMTC
	62	void smtc_soft_dump(void);
	63	#endif /* CONFIG_MIPT_MT_SMTC */
	64
	65	local_irq_save(flags);
	66	vpflags = dvpe();
	67	printk("=== MIPS MT State Dump ===\n");
	68	printk("-- Global State --\n");
	69	printk(" MVPControl Passed: %08lx\n", mvpctl);
	70	printk(" MVPControl Read: %08lx\n", vpflags);
	71	printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
	72	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
	73	ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
	74	printk("-- per-VPE State --\n");
d223a861 RB	75	for (i = 0; i < nvpe; i++) {
d223a861 RB	76	for (tc = 0; tc < ntc; tc++) {
41c594ab	77	settc(tc);
d223a861 RB	78	if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
	79	printk(" VPE %d\n", i);
	80	printk(" VPEControl : %08lx\n",
	81	read_vpe_c0_vpecontrol());
	82	printk(" VPEConf0 : %08lx\n",
	83	read_vpe_c0_vpeconf0());
	84	printk(" VPE%d.Status : %08lx\n",
	85	i, read_vpe_c0_status());
b012cffe RB	86	printk(" VPE%d.EPC : %08lx %pS\n",
	87	i, read_vpe_c0_epc(),
	88	(void *) read_vpe_c0_epc());
d223a861 RB	89	printk(" VPE%d.Cause : %08lx\n",
	90	i, read_vpe_c0_cause());
	91	printk(" VPE%d.Config7 : %08lx\n",
	92	i, read_vpe_c0_config7());
	93	break; /* Next VPE */
	94	}
41c594ab	95	}
41c594ab RB	96	}
41c594ab RB	97	printk("-- per-TC State --\n");
d223a861	98	for (tc = 0; tc < ntc; tc++) {
41c594ab	99	settc(tc);
d223a861	100	if (read_tc_c0_tcbind() == read_c0_tcbind()) {
41c594ab RB	101	/* Are we dumping ourself? */
	102	haltval = 0; /* Then we're not halted, and mustn't be */
	103	tcstatval = flags; /* And pre-dump TCStatus is flags */
	104	printk(" TC %d (current TC with VPE EPC above)\n", tc);
	105	} else {
	106	haltval = read_tc_c0_tchalt();
	107	write_tc_c0_tchalt(1);
	108	tcstatval = read_tc_c0_tcstatus();
	109	printk(" TC %d\n", tc);
	110	}
	111	printk(" TCStatus : %08lx\n", tcstatval);
	112	printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
b012cffe RB	113	printk(" TCRestart : %08lx %pS\n",
b012cffe RB	114	read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
41c594ab RB	115	printk(" TCHalt : %08lx\n", haltval);
	116	printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
	117	if (!haltval)
	118	write_tc_c0_tchalt(0);
	119	}
	120	#ifdef CONFIG_MIPS_MT_SMTC
	121	smtc_soft_dump();
	122	#endif /* CONFIG_MIPT_MT_SMTC */
	123	printk("===========================\n");
	124	evpe(vpflags);
	125	local_irq_restore(flags);
	126	}
	127
982f6ffe	128	static int mt_opt_norps;
41c594ab RB	129	static int mt_opt_rpsctl = -1;
41c594ab RB	130	static int mt_opt_nblsu = -1;
982f6ffe	131	static int mt_opt_forceconfig7;
41c594ab RB	132	static int mt_opt_config7 = -1;
	133
	134	static int __init rps_disable(char *s)
	135	{
	136	mt_opt_norps = 1;
	137	return 1;
	138	}
	139	__setup("norps", rps_disable);
	140
	141	static int __init rpsctl_set(char *str)
	142	{
	143	get_option(&str, &mt_opt_rpsctl);
	144	return 1;
	145	}
	146	__setup("rpsctl=", rpsctl_set);
	147
	148	static int __init nblsu_set(char *str)
	149	{
	150	get_option(&str, &mt_opt_nblsu);
	151	return 1;
	152	}
	153	__setup("nblsu=", nblsu_set);
	154
	155	static int __init config7_set(char *str)
	156	{
	157	get_option(&str, &mt_opt_config7);
	158	mt_opt_forceconfig7 = 1;
	159	return 1;
	160	}
	161	__setup("config7=", config7_set);
	162
	163	/* Experimental cache flush control parameters that should go away some day */
982f6ffe RB	164	int mt_protiflush;
982f6ffe RB	165	int mt_protdflush;
41c594ab RB	166	int mt_n_iflushes = 1;
	167	int mt_n_dflushes = 1;
	168
	169	static int __init set_protiflush(char *s)
	170	{
	171	mt_protiflush = 1;
	172	return 1;
	173	}
	174	__setup("protiflush", set_protiflush);
	175
	176	static int __init set_protdflush(char *s)
	177	{
	178	mt_protdflush = 1;
	179	return 1;
	180	}
	181	__setup("protdflush", set_protdflush);
	182
	183	static int __init niflush(char *s)
	184	{
	185	get_option(&s, &mt_n_iflushes);
	186	return 1;
	187	}
	188	__setup("niflush=", niflush);
	189
	190	static int __init ndflush(char *s)
	191	{
	192	get_option(&s, &mt_n_dflushes);
	193	return 1;
	194	}
	195	__setup("ndflush=", ndflush);
41c594ab	196
982f6ffe	197	static unsigned int itc_base;
41c594ab RB	198
	199	static int __init set_itc_base(char *str)
	200	{
	201	get_option(&str, &itc_base);
	202	return 1;
	203	}
	204
	205	__setup("itcbase=", set_itc_base);
	206
	207	void mips_mt_set_cpuoptions(void)
	208	{
	209	unsigned int oconfig7 = read_c0_config7();
	210	unsigned int nconfig7 = oconfig7;
	211
	212	if (mt_opt_norps) {
	213	printk("\"norps\" option deprectated: use \"rpsctl=\"\n");
	214	}
	215	if (mt_opt_rpsctl >= 0) {
	216	printk("34K return prediction stack override set to %d.\n",
	217	mt_opt_rpsctl);
	218	if (mt_opt_rpsctl)
	219	nconfig7 \|= (1 << 2);
	220	else
	221	nconfig7 &= ~(1 << 2);
	222	}
	223	if (mt_opt_nblsu >= 0) {
	224	printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
	225	if (mt_opt_nblsu)
	226	nconfig7 \|= (1 << 5);
	227	else
	228	nconfig7 &= ~(1 << 5);
	229	}
	230	if (mt_opt_forceconfig7) {
	231	printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
	232	nconfig7 = mt_opt_config7;
	233	}
	234	if (oconfig7 != nconfig7) {
	235	__asm__ __volatile("sync");
	236	write_c0_config7(nconfig7);
49a89efb	237	ehb();
41c594ab RB	238	printk("Config7: 0x%08x\n", read_c0_config7());
	239	}
	240
	241	/* Report Cache management debug options */
	242	if (mt_protiflush)
	243	printk("I-cache flushes single-threaded\n");
	244	if (mt_protdflush)
	245	printk("D-cache flushes single-threaded\n");
	246	if (mt_n_iflushes != 1)
	247	printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
	248	if (mt_n_dflushes != 1)
	249	printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);
	250
41c594ab RB	251	if (itc_base != 0) {
	252	/*
	253	* Configure ITC mapping. This code is very
	254	* specific to the 34K core family, which uses
	255	* a special mode bit ("ITC") in the ErrCtl
	256	* register to enable access to ITC control
	257	* registers via cache "tag" operations.
	258	*/
	259	unsigned long ectlval;
	260	unsigned long itcblkgrn;
	261
	262	/* ErrCtl register is known as "ecc" to Linux */
	263	ectlval = read_c0_ecc();
	264	write_c0_ecc(ectlval \| (0x1 << 26));
	265	ehb();
	266	#define INDEX_0 (0x80000000)
	267	#define INDEX_8 (0x80000008)
	268	/* Read "cache tag" for Dcache pseudo-index 8 */
	269	cache_op(Index_Load_Tag_D, INDEX_8);
	270	ehb();
	271	itcblkgrn = read_c0_dtaglo();
	272	itcblkgrn &= 0xfffe0000;
	273	/* Set for 128 byte pitch of ITC cells */
	274	itcblkgrn \|= 0x00000c00;
	275	/* Stage in Tag register */
	276	write_c0_dtaglo(itcblkgrn);
	277	ehb();
	278	/* Write out to ITU with CACHE op */
	279	cache_op(Index_Store_Tag_D, INDEX_8);
	280	/* Now set base address, and turn ITC on with 0x1 bit */
	281	write_c0_dtaglo((itc_base & 0xfffffc00) \| 0x1 );
	282	ehb();
	283	/* Write out to ITU with CACHE op */
	284	cache_op(Index_Store_Tag_D, INDEX_0);
	285	write_c0_ecc(ectlval);
	286	ehb();
	287	printk("Mapped %ld ITC cells starting at 0x%08x\n",
	288	((itcblkgrn & 0x7fe00000) >> 20), itc_base);
	289	}
	290	}
	291
	292	/*
	293	* Function to protect cache flushes from concurrent execution
	294	* depends on MP software model chosen.
	295	*/
	296
	297	void mt_cflush_lockdown(void)
	298	{
	299	#ifdef CONFIG_MIPS_MT_SMTC
	300	void smtc_cflush_lockdown(void);
	301
	302	smtc_cflush_lockdown();
	303	#endif /* CONFIG_MIPS_MT_SMTC */
	304	/* FILL IN VSMP and AP/SP VERSIONS HERE */
	305	}
	306
	307	void mt_cflush_release(void)
	308	{
	309	#ifdef CONFIG_MIPS_MT_SMTC
	310	void smtc_cflush_release(void);
	311
	312	smtc_cflush_release();
	313	#endif /* CONFIG_MIPS_MT_SMTC */
	314	/* FILL IN VSMP and AP/SP VERSIONS HERE */
315	}
27a3bbaf RB	316
	317	struct class *mt_class;
	318
	319	static int __init mt_init(void)
	320	{
	321	struct class *mtc;
	322
	323	mtc = class_create(THIS_MODULE, "mt");
	324	if (IS_ERR(mtc))
	325	return PTR_ERR(mtc);
	326
	327	mt_class = mtc;
	328
	329	return 0;
	330	}
	331
	332	subsys_initcall(mt_init);