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[linux.git] / drivers / mfd / rtsx_pcr.c
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ada8a8a1
WW		 1/* Driver for Realtek PCI-Express card reader
2 *
09fd8678 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
ada8a8a1
WW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <[email protected]>
ada8a8a1
WW		 20 */
21
22#include <linux/pci.h>
23#include <linux/module.h>
aec17ea1 24#include <linux/slab.h>
ada8a8a1
WW		 25#include <linux/dma-mapping.h>
26#include <linux/highmem.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/idr.h>
30#include <linux/platform_device.h>
31#include <linux/mfd/core.h>
32#include <linux/mfd/rtsx_pci.h>
33#include <asm/unaligned.h>
34
35#include "rtsx_pcr.h"
36
37static bool msi_en = true;
38module_param(msi_en, bool, S_IRUGO | S_IWUSR);
39MODULE_PARM_DESC(msi_en, "Enable MSI");
40
41static DEFINE_IDR(rtsx_pci_idr);
42static DEFINE_SPINLOCK(rtsx_pci_lock);
43
44static struct mfd_cell rtsx_pcr_cells[] = {
45 [RTSX_SD_CARD] = {
46 .name = DRV_NAME_RTSX_PCI_SDMMC,
47 },
48 [RTSX_MS_CARD] = {
49 .name = DRV_NAME_RTSX_PCI_MS,
50 },
51};
52
36fcd06c 53static const struct pci_device_id rtsx_pci_ids[] = {
ada8a8a1
WW		 54 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
55 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
e1237932 57 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
4c4b8c10 58 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
9032eabd 59 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56cb3cc1 60 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
ada8a8a1
WW		 61 { 0, }
62};
63
64MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
65
66void rtsx_pci_start_run(struct rtsx_pcr *pcr)
67{
68 /* If pci device removed, don't queue idle work any more */
69 if (pcr->remove_pci)
70 return;
71
72 if (pcr->state != PDEV_STAT_RUN) {
73 pcr->state = PDEV_STAT_RUN;
74 if (pcr->ops->enable_auto_blink)
75 pcr->ops->enable_auto_blink(pcr);
773ccdfd
WW		 76
77 if (pcr->aspm_en)
78 rtsx_pci_write_config_byte(pcr, LCTLR, 0);
ada8a8a1
WW		 79 }
80
81 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
82}
83EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
84
85int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
86{
87 int i;
88 u32 val = HAIMR_WRITE_START;
89
90 val |= (u32)(addr & 0x3FFF) << 16;
91 val |= (u32)mask << 8;
92 val |= (u32)data;
93
94 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
95
96 for (i = 0; i < MAX_RW_REG_CNT; i++) {
97 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
98 if ((val & HAIMR_TRANS_END) == 0) {
99 if (data != (u8)val)
100 return -EIO;
101 return 0;
102 }
103 }
104
105 return -ETIMEDOUT;
106}
107EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
108
109int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
110{
111 u32 val = HAIMR_READ_START;
112 int i;
113
114 val |= (u32)(addr & 0x3FFF) << 16;
115 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
116
117 for (i = 0; i < MAX_RW_REG_CNT; i++) {
118 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
119 if ((val & HAIMR_TRANS_END) == 0)
120 break;
121 }
122
123 if (i >= MAX_RW_REG_CNT)
124 return -ETIMEDOUT;
125
126 if (data)
127 *data = (u8)(val & 0xFF);
128
129 return 0;
130}
131EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
132
133int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
134{
135 int err, i, finished = 0;
136 u8 tmp;
137
138 rtsx_pci_init_cmd(pcr);
139
140 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
141 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
142 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
143 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
144
145 err = rtsx_pci_send_cmd(pcr, 100);
146 if (err < 0)
147 return err;
148
149 for (i = 0; i < 100000; i++) {
150 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
151 if (err < 0)
152 return err;
153
154 if (!(tmp & 0x80)) {
155 finished = 1;
156 break;
157 }
158 }
159
160 if (!finished)
161 return -ETIMEDOUT;
162
163 return 0;
164}
165EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
166
167int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
168{
169 int err, i, finished = 0;
170 u16 data;
171 u8 *ptr, tmp;
172
173 rtsx_pci_init_cmd(pcr);
174
175 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
176 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
177
178 err = rtsx_pci_send_cmd(pcr, 100);
179 if (err < 0)
180 return err;
181
182 for (i = 0; i < 100000; i++) {
183 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
184 if (err < 0)
185 return err;
186
187 if (!(tmp & 0x80)) {
188 finished = 1;
189 break;
190 }
191 }
192
193 if (!finished)
194 return -ETIMEDOUT;
195
196 rtsx_pci_init_cmd(pcr);
197
198 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
199 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
200
201 err = rtsx_pci_send_cmd(pcr, 100);
202 if (err < 0)
203 return err;
204
205 ptr = rtsx_pci_get_cmd_data(pcr);
206 data = ((u16)ptr[1] << 8) | ptr[0];
207
208 if (val)
209 *val = data;
210
211 return 0;
212}
213EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
214
215void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
216{
217 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
218 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
219
220 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
221 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
222}
223EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
224
225void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
226 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
227{
228 unsigned long flags;
229 u32 val = 0;
230 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
231
232 val |= (u32)(cmd_type & 0x03) << 30;
233 val |= (u32)(reg_addr & 0x3FFF) << 16;
234 val |= (u32)mask << 8;
235 val |= (u32)data;
236
237 spin_lock_irqsave(&pcr->lock, flags);
238 ptr += pcr->ci;
239 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
240 put_unaligned_le32(val, ptr);
241 ptr++;
242 pcr->ci++;
243 }
244 spin_unlock_irqrestore(&pcr->lock, flags);
245}
246EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
247
248void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
249{
250 u32 val = 1 << 31;
251
252 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
253
254 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
255 /* Hardware Auto Response */
256 val |= 0x40000000;
257 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
258}
259EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
260
261int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
262{
263 struct completion trans_done;
264 u32 val = 1 << 31;
265 long timeleft;
266 unsigned long flags;
267 int err = 0;
268
269 spin_lock_irqsave(&pcr->lock, flags);
270
271 /* set up data structures for the wakeup system */
272 pcr->done = &trans_done;
273 pcr->trans_result = TRANS_NOT_READY;
274 init_completion(&trans_done);
275
276 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
277
278 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
279 /* Hardware Auto Response */
280 val |= 0x40000000;
281 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
282
283 spin_unlock_irqrestore(&pcr->lock, flags);
284
285 /* Wait for TRANS_OK_INT */
286 timeleft = wait_for_completion_interruptible_timeout(
287 &trans_done, msecs_to_jiffies(timeout));
288 if (timeleft <= 0) {
289 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
290 __func__, __LINE__);
291 err = -ETIMEDOUT;
292 goto finish_send_cmd;
293 }
294
295 spin_lock_irqsave(&pcr->lock, flags);
296 if (pcr->trans_result == TRANS_RESULT_FAIL)
297 err = -EINVAL;
298 else if (pcr->trans_result == TRANS_RESULT_OK)
299 err = 0;
300 else if (pcr->trans_result == TRANS_NO_DEVICE)
301 err = -ENODEV;
302 spin_unlock_irqrestore(&pcr->lock, flags);
303
304finish_send_cmd:
305 spin_lock_irqsave(&pcr->lock, flags);
306 pcr->done = NULL;
307 spin_unlock_irqrestore(&pcr->lock, flags);
308
309 if ((err < 0) && (err != -ENODEV))
310 rtsx_pci_stop_cmd(pcr);
311
312 if (pcr->finish_me)
313 complete(pcr->finish_me);
314
315 return err;
316}
317EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
318
319static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
320 dma_addr_t addr, unsigned int len, int end)
321{
322 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
323 u64 val;
324 u8 option = SG_VALID | SG_TRANS_DATA;
325
326 dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
327 (unsigned int)addr, len);
328
329 if (end)
330 option |= SG_END;
331 val = ((u64)addr << 32) | ((u64)len << 12) | option;
332
333 put_unaligned_le64(val, ptr);
ada8a8a1
WW		 334 pcr->sgi++;
335}
336
337int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
338 int num_sg, bool read, int timeout)
339{
340 struct completion trans_done;
341 u8 dir;
342 int err = 0, i, count;
343 long timeleft;
344 unsigned long flags;
345 struct scatterlist *sg;
346 enum dma_data_direction dma_dir;
347 u32 val;
348 dma_addr_t addr;
349 unsigned int len;
350
351 dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
352
353 /* don't transfer data during abort processing */
354 if (pcr->remove_pci)
355 return -EINVAL;
356
357 if ((sglist == NULL) || (num_sg <= 0))
358 return -EINVAL;
359
360 if (read) {
361 dir = DEVICE_TO_HOST;
362 dma_dir = DMA_FROM_DEVICE;
363 } else {
364 dir = HOST_TO_DEVICE;
365 dma_dir = DMA_TO_DEVICE;
366 }
367
368 count = dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
369 if (count < 1) {
370 dev_err(&(pcr->pci->dev), "scatterlist map failed\n");
371 return -EINVAL;
372 }
373 dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
374
375 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
376 pcr->sgi = 0;
377 for_each_sg(sglist, sg, count, i) {
378 addr = sg_dma_address(sg);
379 len = sg_dma_len(sg);
380 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
381 }
382
383 spin_lock_irqsave(&pcr->lock, flags);
384
385 pcr->done = &trans_done;
386 pcr->trans_result = TRANS_NOT_READY;
387 init_completion(&trans_done);
388 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
389 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
390
391 spin_unlock_irqrestore(&pcr->lock, flags);
392
393 timeleft = wait_for_completion_interruptible_timeout(
394 &trans_done, msecs_to_jiffies(timeout));
395 if (timeleft <= 0) {
396 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
397 __func__, __LINE__);
398 err = -ETIMEDOUT;
399 goto out;
400 }
401
402 spin_lock_irqsave(&pcr->lock, flags);
403
404 if (pcr->trans_result == TRANS_RESULT_FAIL)
405 err = -EINVAL;
406 else if (pcr->trans_result == TRANS_NO_DEVICE)
407 err = -ENODEV;
408
409 spin_unlock_irqrestore(&pcr->lock, flags);
410
411out:
412 spin_lock_irqsave(&pcr->lock, flags);
413 pcr->done = NULL;
414 spin_unlock_irqrestore(&pcr->lock, flags);
415
416 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
417
418 if ((err < 0) && (err != -ENODEV))
419 rtsx_pci_stop_cmd(pcr);
420
421 if (pcr->finish_me)
422 complete(pcr->finish_me);
423
424 return err;
425}
426EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
427
428int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
429{
430 int err;
431 int i, j;
432 u16 reg;
433 u8 *ptr;
434
435 if (buf_len > 512)
436 buf_len = 512;
437
438 ptr = buf;
439 reg = PPBUF_BASE2;
440 for (i = 0; i < buf_len / 256; i++) {
441 rtsx_pci_init_cmd(pcr);
442
443 for (j = 0; j < 256; j++)
444 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
445
446 err = rtsx_pci_send_cmd(pcr, 250);
447 if (err < 0)
448 return err;
449
450 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
451 ptr += 256;
452 }
453
454 if (buf_len % 256) {
455 rtsx_pci_init_cmd(pcr);
456
457 for (j = 0; j < buf_len % 256; j++)
458 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
459
460 err = rtsx_pci_send_cmd(pcr, 250);
461 if (err < 0)
462 return err;
463 }
464
465 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
466
467 return 0;
468}
469EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
470
471int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
472{
473 int err;
474 int i, j;
475 u16 reg;
476 u8 *ptr;
477
478 if (buf_len > 512)
479 buf_len = 512;
480
481 ptr = buf;
482 reg = PPBUF_BASE2;
483 for (i = 0; i < buf_len / 256; i++) {
484 rtsx_pci_init_cmd(pcr);
485
486 for (j = 0; j < 256; j++) {
487 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
488 reg++, 0xFF, *ptr);
489 ptr++;
490 }
491
492 err = rtsx_pci_send_cmd(pcr, 250);
493 if (err < 0)
494 return err;
495 }
496
497 if (buf_len % 256) {
498 rtsx_pci_init_cmd(pcr);
499
500 for (j = 0; j < buf_len % 256; j++) {
501 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
502 reg++, 0xFF, *ptr);
503 ptr++;
504 }
505
506 err = rtsx_pci_send_cmd(pcr, 250);
507 if (err < 0)
508 return err;
509 }
510
511 return 0;
512}
513EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
514
515static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
516{
517 int err;
518
519 rtsx_pci_init_cmd(pcr);
520
521 while (*tbl & 0xFFFF0000) {
522 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
523 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
524 tbl++;
525 }
526
527 err = rtsx_pci_send_cmd(pcr, 100);
528 if (err < 0)
529 return err;
530
531 return 0;
532}
533
534int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
535{
536 const u32 *tbl;
537
538 if (card == RTSX_SD_CARD)
539 tbl = pcr->sd_pull_ctl_enable_tbl;
540 else if (card == RTSX_MS_CARD)
541 tbl = pcr->ms_pull_ctl_enable_tbl;
542 else
543 return -EINVAL;
544
545 return rtsx_pci_set_pull_ctl(pcr, tbl);
546}
547EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
548
549int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
550{
551 const u32 *tbl;
552
553 if (card == RTSX_SD_CARD)
554 tbl = pcr->sd_pull_ctl_disable_tbl;
555 else if (card == RTSX_MS_CARD)
556 tbl = pcr->ms_pull_ctl_disable_tbl;
557 else
558 return -EINVAL;
559
560
561 return rtsx_pci_set_pull_ctl(pcr, tbl);
562}
563EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
564
565static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
566{
567 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
568
569 if (pcr->num_slots > 1)
570 pcr->bier |= MS_INT_EN;
571
572 /* Enable Bus Interrupt */
573 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
574
575 dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
576}
577
578static inline u8 double_ssc_depth(u8 depth)
579{
580 return ((depth > 1) ? (depth - 1) : depth);
581}
582
583static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
584{
585 if (div > CLK_DIV_1) {
586 if (ssc_depth > (div - 1))
587 ssc_depth -= (div - 1);
588 else
589 ssc_depth = SSC_DEPTH_4M;
590 }
591
592 return ssc_depth;
593}
594
595int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
596 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
597{
598 int err, clk;
eebbe254 599 u8 n, clk_divider, mcu_cnt, div;
ada8a8a1
WW		 600 u8 depth[] = {
601 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
602 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
603 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
604 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
605 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
606 };
607
608 if (initial_mode) {
609 /* We use 250k(around) here, in initial stage */
610 clk_divider = SD_CLK_DIVIDE_128;
611 card_clock = 30000000;
612 } else {
613 clk_divider = SD_CLK_DIVIDE_0;
614 }
615 err = rtsx_pci_write_register(pcr, SD_CFG1,
616 SD_CLK_DIVIDE_MASK, clk_divider);
617 if (err < 0)
618 return err;
619
620 card_clock /= 1000000;
621 dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
622
ada8a8a1
WW		 623 clk = card_clock;
624 if (!initial_mode && double_clk)
625 clk = card_clock * 2;
626 dev_dbg(&(pcr->pci->dev),
627 "Internal SSC clock: %dMHz (cur_clock = %d)\n",
628 clk, pcr->cur_clock);
629
630 if (clk == pcr->cur_clock)
631 return 0;
632
ab4e8f8b 633 if (pcr->ops->conv_clk_and_div_n)
678cacdf 634 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
ab4e8f8b 635 else
678cacdf 636 n = (u8)(clk - 2);
eebbe254 637 if ((clk <= 2) || (n > MAX_DIV_N_PCR))
ada8a8a1
WW		 638 return -EINVAL;
639
640 mcu_cnt = (u8)(125/clk + 3);
641 if (mcu_cnt > 15)
642 mcu_cnt = 15;
643
eebbe254 644 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
ada8a8a1 645 div = CLK_DIV_1;
eebbe254 646 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
ab4e8f8b 647 if (pcr->ops->conv_clk_and_div_n) {
678cacdf 648 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
ab4e8f8b 649 DIV_N_TO_CLK) * 2;
678cacdf 650 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
ab4e8f8b
WW		 651 CLK_TO_DIV_N);
652 } else {
678cacdf 653 n = (n + 2) * 2 - 2;
ab4e8f8b 654 }
ada8a8a1
WW		 655 div++;
656 }
678cacdf 657 dev_dbg(&(pcr->pci->dev), "n = %d, div = %d\n", n, div);
ada8a8a1
WW		 658
659 ssc_depth = depth[ssc_depth];
660 if (double_clk)
661 ssc_depth = double_ssc_depth(ssc_depth);
662
663 ssc_depth = revise_ssc_depth(ssc_depth, div);
664 dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
665
666 rtsx_pci_init_cmd(pcr);
667 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
668 CLK_LOW_FREQ, CLK_LOW_FREQ);
669 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
670 0xFF, (div << 4) | mcu_cnt);
671 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
672 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
673 SSC_DEPTH_MASK, ssc_depth);
678cacdf 674 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
ada8a8a1
WW		 675 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
676 if (vpclk) {
677 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
678 PHASE_NOT_RESET, 0);
679 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
680 PHASE_NOT_RESET, PHASE_NOT_RESET);
681 }
682
683 err = rtsx_pci_send_cmd(pcr, 2000);
684 if (err < 0)
685 return err;
686
687 /* Wait SSC clock stable */
688 udelay(10);
689 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
690 if (err < 0)
691 return err;
692
693 pcr->cur_clock = clk;
694 return 0;
695}
696EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
697
698int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
699{
700 if (pcr->ops->card_power_on)
701 return pcr->ops->card_power_on(pcr, card);
702
703 return 0;
704}
705EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
706
707int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
708{
709 if (pcr->ops->card_power_off)
710 return pcr->ops->card_power_off(pcr, card);
711
712 return 0;
713}
714EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
715
c3481955
WW		 716int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
717{
718 unsigned int cd_mask[] = {
719 [RTSX_SD_CARD] = SD_EXIST,
720 [RTSX_MS_CARD] = MS_EXIST
721 };
722
773ccdfd 723 if (!(pcr->flags & PCR_MS_PMOS)) {
c3481955
WW		 724 /* When using single PMOS, accessing card is not permitted
725 * if the existing card is not the designated one.
726 */
727 if (pcr->card_exist & (~cd_mask[card]))
728 return -EIO;
729 }
730
731 return 0;
732}
733EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
734
d817ac4e
WW		 735int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
736{
737 if (pcr->ops->switch_output_voltage)
738 return pcr->ops->switch_output_voltage(pcr, voltage);
739
740 return 0;
741}
742EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
743
ada8a8a1
WW		 744unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
745{
746 unsigned int val;
747
748 val = rtsx_pci_readl(pcr, RTSX_BIPR);
749 if (pcr->ops->cd_deglitch)
750 val = pcr->ops->cd_deglitch(pcr);
751
752 return val;
753}
754EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
755
756void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
757{
758 struct completion finish;
759
760 pcr->finish_me = &finish;
761 init_completion(&finish);
762
763 if (pcr->done)
764 complete(pcr->done);
765
766 if (!pcr->remove_pci)
767 rtsx_pci_stop_cmd(pcr);
768
769 wait_for_completion_interruptible_timeout(&finish,
770 msecs_to_jiffies(2));
771 pcr->finish_me = NULL;
772}
773EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
774
775static void rtsx_pci_card_detect(struct work_struct *work)
776{
777 struct delayed_work *dwork;
778 struct rtsx_pcr *pcr;
779 unsigned long flags;
504decc0 780 unsigned int card_detect = 0, card_inserted, card_removed;
ada8a8a1
WW		 781 u32 irq_status;
782
783 dwork = to_delayed_work(work);
784 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
785
786 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
787
504decc0 788 mutex_lock(&pcr->pcr_mutex);
ada8a8a1
WW		 789 spin_lock_irqsave(&pcr->lock, flags);
790
791 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
792 dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
793
504decc0
WW		 794 irq_status &= CARD_EXIST;
795 card_inserted = pcr->card_inserted & irq_status;
796 card_removed = pcr->card_removed;
797 pcr->card_inserted = 0;
798 pcr->card_removed = 0;
799
800 spin_unlock_irqrestore(&pcr->lock, flags);
801
802 if (card_inserted || card_removed) {
ada8a8a1
WW		 803 dev_dbg(&(pcr->pci->dev),
804 "card_inserted: 0x%x, card_removed: 0x%x\n",
504decc0 805 card_inserted, card_removed);
ada8a8a1
WW		 806
807 if (pcr->ops->cd_deglitch)
504decc0 808 card_inserted = pcr->ops->cd_deglitch(pcr);
ada8a8a1 809
504decc0 810 card_detect = card_inserted | card_removed;
c3481955
WW		 811
812 pcr->card_exist |= card_inserted;
813 pcr->card_exist &= ~card_removed;
ada8a8a1
WW		 814 }
815
504decc0 816 mutex_unlock(&pcr->pcr_mutex);
ada8a8a1 817
2d1484f5 818 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
ada8a8a1
WW		 819 pcr->slots[RTSX_SD_CARD].card_event(
820 pcr->slots[RTSX_SD_CARD].p_dev);
2d1484f5 821 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
ada8a8a1
WW		 822 pcr->slots[RTSX_MS_CARD].card_event(
823 pcr->slots[RTSX_MS_CARD].p_dev);
824}
825
826static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
827{
828 struct rtsx_pcr *pcr = dev_id;
829 u32 int_reg;
830
831 if (!pcr)
832 return IRQ_NONE;
833
834 spin_lock(&pcr->lock);
835
836 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
837 /* Clear interrupt flag */
838 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
839 if ((int_reg & pcr->bier) == 0) {
840 spin_unlock(&pcr->lock);
841 return IRQ_NONE;
842 }
843 if (int_reg == 0xFFFFFFFF) {
844 spin_unlock(&pcr->lock);
845 return IRQ_HANDLED;
846 }
847
848 int_reg &= (pcr->bier | 0x7FFFFF);
849
850 if (int_reg & SD_INT) {
851 if (int_reg & SD_EXIST) {
852 pcr->card_inserted |= SD_EXIST;
853 } else {
854 pcr->card_removed |= SD_EXIST;
855 pcr->card_inserted &= ~SD_EXIST;
856 }
857 }
858
859 if (int_reg & MS_INT) {
860 if (int_reg & MS_EXIST) {
861 pcr->card_inserted |= MS_EXIST;
862 } else {
863 pcr->card_removed |= MS_EXIST;
864 pcr->card_inserted &= ~MS_EXIST;
865 }
866 }
867
ada8a8a1
WW		 868 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
869 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
870 pcr->trans_result = TRANS_RESULT_FAIL;
871 if (pcr->done)
872 complete(pcr->done);
873 } else if (int_reg & TRANS_OK_INT) {
874 pcr->trans_result = TRANS_RESULT_OK;
875 if (pcr->done)
876 complete(pcr->done);
877 }
878 }
879
504decc0
WW		 880 if (pcr->card_inserted || pcr->card_removed)
881 schedule_delayed_work(&pcr->carddet_work,
882 msecs_to_jiffies(200));
883
ada8a8a1
WW		 884 spin_unlock(&pcr->lock);
885 return IRQ_HANDLED;
886}
887
888static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
889{
890 dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
891 __func__, pcr->msi_en, pcr->pci->irq);
892
893 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
894 pcr->msi_en ? 0 : IRQF_SHARED,
895 DRV_NAME_RTSX_PCI, pcr)) {
896 dev_err(&(pcr->pci->dev),
897 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
898 pcr->pci->irq);
899 return -1;
900 }
901
902 pcr->irq = pcr->pci->irq;
903 pci_intx(pcr->pci, !pcr->msi_en);
904
905 return 0;
906}
907
908static void rtsx_pci_idle_work(struct work_struct *work)
909{
910 struct delayed_work *dwork = to_delayed_work(work);
911 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
912
913 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
914
915 mutex_lock(&pcr->pcr_mutex);
916
917 pcr->state = PDEV_STAT_IDLE;
918
919 if (pcr->ops->disable_auto_blink)
920 pcr->ops->disable_auto_blink(pcr);
921 if (pcr->ops->turn_off_led)
922 pcr->ops->turn_off_led(pcr);
923
773ccdfd
WW		 924 if (pcr->aspm_en)
925 rtsx_pci_write_config_byte(pcr, LCTLR, pcr->aspm_en);
926
ada8a8a1
WW		 927 mutex_unlock(&pcr->pcr_mutex);
928}
929
5947c167
WW		 930static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
931{
932 if (pcr->ops->turn_off_led)
933 pcr->ops->turn_off_led(pcr);
934
935 rtsx_pci_writel(pcr, RTSX_BIER, 0);
936 pcr->bier = 0;
937
938 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
939 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
940
941 if (pcr->ops->force_power_down)
eb891c65 942 pcr->ops->force_power_down(pcr, pm_state);
5947c167
WW		 943}
944
ada8a8a1
WW		 945static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
946{
947 int err;
948
949 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
950
951 rtsx_pci_enable_bus_int(pcr);
952
953 /* Power on SSC */
954 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
955 if (err < 0)
956 return err;
957
958 /* Wait SSC power stable */
959 udelay(200);
960
961 if (pcr->ops->optimize_phy) {
962 err = pcr->ops->optimize_phy(pcr);
963 if (err < 0)
964 return err;
965 }
966
967 rtsx_pci_init_cmd(pcr);
968
969 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
970 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
971
972 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
973 /* Disable card clock */
974 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
ada8a8a1
WW		 975 /* Reset delink mode */
976 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
977 /* Card driving select */
773ccdfd
WW		 978 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
979 0xFF, pcr->card_drive_sel);
ada8a8a1
WW		 980 /* Enable SSC Clock */
981 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
982 0xFF, SSC_8X_EN | SSC_SEL_4M);
983 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
984 /* Disable cd_pwr_save */
985 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
986 /* Clear Link Ready Interrupt */
987 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
988 LINK_RDY_INT, LINK_RDY_INT);
989 /* Enlarge the estimation window of PERST# glitch
990 * to reduce the chance of invalid card interrupt
991 */
992 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
993 /* Update RC oscillator to 400k
994 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
995 * 1: 2M 0: 400k
996 */
997 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
998 /* Set interrupt write clear
999 * bit 1: U_elbi_if_rd_clr_en
1000 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1001 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1002 */
1003 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
ada8a8a1
WW		 1004
1005 err = rtsx_pci_send_cmd(pcr, 100);
1006 if (err < 0)
1007 return err;
1008
773ccdfd
WW		 1009 rtsx_pci_write_config_byte(pcr, LCTLR, 0);
1010
ada8a8a1
WW		 1011 /* Enable clk_request_n to enable clock power management */
1012 rtsx_pci_write_config_byte(pcr, 0x81, 1);
1013 /* Enter L1 when host tx idle */
1014 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
1015
1016 if (pcr->ops->extra_init_hw) {
1017 err = pcr->ops->extra_init_hw(pcr);
1018 if (err < 0)
1019 return err;
1020 }
1021
c3481955
WW		 1022 /* No CD interrupt if probing driver with card inserted.
1023 * So we need to initialize pcr->card_exist here.
1024 */
1025 if (pcr->ops->cd_deglitch)
1026 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1027 else
1028 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1029
ada8a8a1
WW		 1030 return 0;
1031}
1032
1033static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1034{
1035 int err;
1036
1037 spin_lock_init(&pcr->lock);
1038 mutex_init(&pcr->pcr_mutex);
1039
1040 switch (PCI_PID(pcr)) {
1041 default:
1042 case 0x5209:
1043 rts5209_init_params(pcr);
1044 break;
1045
1046 case 0x5229:
1047 rts5229_init_params(pcr);
1048 break;
1049
1050 case 0x5289:
1051 rtl8411_init_params(pcr);
1052 break;
e1237932
RT		 1053
1054 case 0x5227:
1055 rts5227_init_params(pcr);
1056 break;
4c4b8c10
WW		 1057
1058 case 0x5249:
1059 rts5249_init_params(pcr);
1060 break;
9032eabd
RT		 1061
1062 case 0x5287:
1063 rtl8411b_init_params(pcr);
1064 break;
56cb3cc1
MC		 1065
1066 case 0x5286:
1067 rtl8402_init_params(pcr);
1068 break;
ada8a8a1
WW		 1069 }
1070
1071 dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
1072 PCI_PID(pcr), pcr->ic_version);
1073
1074 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1075 GFP_KERNEL);
1076 if (!pcr->slots)
1077 return -ENOMEM;
1078
773ccdfd
WW		 1079 if (pcr->ops->fetch_vendor_settings)
1080 pcr->ops->fetch_vendor_settings(pcr);
1081
1082 dev_dbg(&(pcr->pci->dev), "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1083 dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1084 pcr->sd30_drive_sel_1v8);
1085 dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1086 pcr->sd30_drive_sel_3v3);
1087 dev_dbg(&(pcr->pci->dev), "pcr->card_drive_sel = 0x%x\n",
1088 pcr->card_drive_sel);
1089 dev_dbg(&(pcr->pci->dev), "pcr->flags = 0x%x\n", pcr->flags);
1090
ada8a8a1
WW		 1091 pcr->state = PDEV_STAT_IDLE;
1092 err = rtsx_pci_init_hw(pcr);
1093 if (err < 0) {
1094 kfree(pcr->slots);
1095 return err;
1096 }
1097
1098 return 0;
1099}
1100
612b95cd
GKH		 1101static int rtsx_pci_probe(struct pci_dev *pcidev,
1102 const struct pci_device_id *id)
ada8a8a1
WW		 1103{
1104 struct rtsx_pcr *pcr;
1105 struct pcr_handle *handle;
1106 u32 base, len;
1107 int ret, i;
1108
1109 dev_dbg(&(pcidev->dev),
1110 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1111 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1112 (int)pcidev->revision);
1113
f84ef042
WW		 1114 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1115 if (ret < 0)
1116 return ret;
1117
ada8a8a1
WW		 1118 ret = pci_enable_device(pcidev);
1119 if (ret)
1120 return ret;
1121
1122 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1123 if (ret)
1124 goto disable;
1125
1126 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1127 if (!pcr) {
1128 ret = -ENOMEM;
1129 goto release_pci;
1130 }
1131
1132 handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1133 if (!handle) {
1134 ret = -ENOMEM;
1135 goto free_pcr;
1136 }
1137 handle->pcr = pcr;
1138
9f12563d 1139 idr_preload(GFP_KERNEL);
ada8a8a1 1140 spin_lock(&rtsx_pci_lock);
9f12563d
TH		 1141 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1142 if (ret >= 0)
1143 pcr->id = ret;
ada8a8a1 1144 spin_unlock(&rtsx_pci_lock);
9f12563d
TH		 1145 idr_preload_end();
1146 if (ret < 0)
ada8a8a1
WW		 1147 goto free_handle;
1148
1149 pcr->pci = pcidev;
1150 dev_set_drvdata(&pcidev->dev, handle);
1151
1152 len = pci_resource_len(pcidev, 0);
1153 base = pci_resource_start(pcidev, 0);
1154 pcr->remap_addr = ioremap_nocache(base, len);
1155 if (!pcr->remap_addr) {
1156 ret = -ENOMEM;
af1192d7 1157 goto free_handle;
ada8a8a1
WW		 1158 }
1159
1160 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1161 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1162 GFP_KERNEL);
1163 if (pcr->rtsx_resv_buf == NULL) {
1164 ret = -ENXIO;
1165 goto unmap;
1166 }
1167 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1168 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1169 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1170 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1171
1172 pcr->card_inserted = 0;
1173 pcr->card_removed = 0;
1174 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1175 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1176
1177 pcr->msi_en = msi_en;
1178 if (pcr->msi_en) {
1179 ret = pci_enable_msi(pcidev);
1180 if (ret < 0)
1181 pcr->msi_en = false;
1182 }
1183
1184 ret = rtsx_pci_acquire_irq(pcr);
1185 if (ret < 0)
9d66b568 1186 goto disable_msi;
ada8a8a1
WW		 1187
1188 pci_set_master(pcidev);
1189 synchronize_irq(pcr->irq);
1190
1191 ret = rtsx_pci_init_chip(pcr);
1192 if (ret < 0)
1193 goto disable_irq;
1194
1195 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1196 rtsx_pcr_cells[i].platform_data = handle;
1197 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1198 }
1199 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1200 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1201 if (ret < 0)
1202 goto disable_irq;
1203
1204 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1205
1206 return 0;
1207
1208disable_irq:
1209 free_irq(pcr->irq, (void *)pcr);
9d66b568
JS		 1210disable_msi:
1211 if (pcr->msi_en)
1212 pci_disable_msi(pcr->pci);
ada8a8a1
WW		 1213 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1214 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1215unmap:
1216 iounmap(pcr->remap_addr);
ada8a8a1
WW		 1217free_handle:
1218 kfree(handle);
1219free_pcr:
1220 kfree(pcr);
1221release_pci:
1222 pci_release_regions(pcidev);
1223disable:
1224 pci_disable_device(pcidev);
1225
1226 return ret;
1227}
1228
612b95cd 1229static void rtsx_pci_remove(struct pci_dev *pcidev)
ada8a8a1
WW		 1230{
1231 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1232 struct rtsx_pcr *pcr = handle->pcr;
1233
1234 pcr->remove_pci = true;
1235
73beb63d
TG		 1236 /* Disable interrupts at the pcr level */
1237 spin_lock_irq(&pcr->lock);
1238 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1239 pcr->bier = 0;
1240 spin_unlock_irq(&pcr->lock);
1241
1242 cancel_delayed_work_sync(&pcr->carddet_work);
1243 cancel_delayed_work_sync(&pcr->idle_work);
ada8a8a1
WW		 1244
1245 mfd_remove_devices(&pcidev->dev);
1246
1247 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1248 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1249 free_irq(pcr->irq, (void *)pcr);
1250 if (pcr->msi_en)
1251 pci_disable_msi(pcr->pci);
1252 iounmap(pcr->remap_addr);
1253
ada8a8a1
WW		 1254 pci_release_regions(pcidev);
1255 pci_disable_device(pcidev);
1256
1257 spin_lock(&rtsx_pci_lock);
1258 idr_remove(&rtsx_pci_idr, pcr->id);
1259 spin_unlock(&rtsx_pci_lock);
1260
1261 kfree(pcr->slots);
1262 kfree(pcr);
1263 kfree(handle);
1264
1265 dev_dbg(&(pcidev->dev),
1266 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1267 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1268}
1269
1270#ifdef CONFIG_PM
1271
1272static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1273{
1274 struct pcr_handle *handle;
1275 struct rtsx_pcr *pcr;
ada8a8a1
WW		 1276
1277 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1278
1279 handle = pci_get_drvdata(pcidev);
1280 pcr = handle->pcr;
1281
1282 cancel_delayed_work(&pcr->carddet_work);
1283 cancel_delayed_work(&pcr->idle_work);
1284
1285 mutex_lock(&pcr->pcr_mutex);
1286
5947c167 1287 rtsx_pci_power_off(pcr, HOST_ENTER_S3);
ada8a8a1
WW		 1288
1289 pci_save_state(pcidev);
1290 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1291 pci_disable_device(pcidev);
1292 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1293
1294 mutex_unlock(&pcr->pcr_mutex);
5947c167 1295 return 0;
ada8a8a1
WW		 1296}
1297
1298static int rtsx_pci_resume(struct pci_dev *pcidev)
1299{
1300 struct pcr_handle *handle;
1301 struct rtsx_pcr *pcr;
1302 int ret = 0;
1303
1304 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1305
1306 handle = pci_get_drvdata(pcidev);
1307 pcr = handle->pcr;
1308
1309 mutex_lock(&pcr->pcr_mutex);
1310
1311 pci_set_power_state(pcidev, PCI_D0);
1312 pci_restore_state(pcidev);
1313 ret = pci_enable_device(pcidev);
1314 if (ret)
1315 goto out;
1316 pci_set_master(pcidev);
1317
1318 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1319 if (ret)
1320 goto out;
1321
1322 ret = rtsx_pci_init_hw(pcr);
1323 if (ret)
1324 goto out;
1325
1326 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1327
1328out:
1329 mutex_unlock(&pcr->pcr_mutex);
1330 return ret;
1331}
1332
5947c167
WW		 1333static void rtsx_pci_shutdown(struct pci_dev *pcidev)
1334{
1335 struct pcr_handle *handle;
1336 struct rtsx_pcr *pcr;
1337
1338 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1339
1340 handle = pci_get_drvdata(pcidev);
1341 pcr = handle->pcr;
1342 rtsx_pci_power_off(pcr, HOST_ENTER_S1);
1343
1344 pci_disable_device(pcidev);
1345}
1346
ada8a8a1
WW		 1347#else /* CONFIG_PM */
1348
1349#define rtsx_pci_suspend NULL
1350#define rtsx_pci_resume NULL
5947c167 1351#define rtsx_pci_shutdown NULL
ada8a8a1
WW		 1352
1353#endif /* CONFIG_PM */
1354
1355static struct pci_driver rtsx_pci_driver = {
1356 .name = DRV_NAME_RTSX_PCI,
1357 .id_table = rtsx_pci_ids,
1358 .probe = rtsx_pci_probe,
612b95cd 1359 .remove = rtsx_pci_remove,
ada8a8a1
WW		 1360 .suspend = rtsx_pci_suspend,
1361 .resume = rtsx_pci_resume,
5947c167 1362 .shutdown = rtsx_pci_shutdown,
ada8a8a1
WW		 1363};
1364module_pci_driver(rtsx_pci_driver);
1365
1366MODULE_LICENSE("GPL");
1367MODULE_AUTHOR("Wei WANG <[email protected]>");
1368MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
Empty description
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