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f6e2e6b6 | 1 | /* |
bf3118c1 | 2 | * Copyright (C) 2007-2009 Advanced Micro Devices, Inc. |
f6e2e6b6 JR |
3 | * Author: Joerg Roedel <[email protected]> |
4 | * Leo Duran <[email protected]> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
22 | #include <linux/gfp.h> | |
23 | #include <linux/list.h> | |
7441e9cb | 24 | #include <linux/sysdev.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
f6e2e6b6 | 27 | #include <asm/pci-direct.h> |
6a9401a7 | 28 | #include <asm/amd_iommu_proto.h> |
f6e2e6b6 | 29 | #include <asm/amd_iommu_types.h> |
c6da992e | 30 | #include <asm/amd_iommu.h> |
46a7fa27 | 31 | #include <asm/iommu.h> |
1d9b16d1 | 32 | #include <asm/gart.h> |
ea1b0d39 | 33 | #include <asm/x86_init.h> |
f6e2e6b6 JR |
34 | |
35 | /* | |
36 | * definitions for the ACPI scanning code | |
37 | */ | |
f6e2e6b6 | 38 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
39 | |
40 | #define ACPI_IVHD_TYPE 0x10 | |
41 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
42 | #define ACPI_IVMD_TYPE 0x21 | |
43 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
44 | ||
45 | #define IVHD_DEV_ALL 0x01 | |
46 | #define IVHD_DEV_SELECT 0x02 | |
47 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
48 | #define IVHD_DEV_RANGE_END 0x04 | |
49 | #define IVHD_DEV_ALIAS 0x42 | |
50 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
51 | #define IVHD_DEV_EXT_SELECT 0x46 | |
52 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
53 | ||
6da7342f JR |
54 | #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 |
55 | #define IVHD_FLAG_PASSPW_EN_MASK 0x02 | |
56 | #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 | |
57 | #define IVHD_FLAG_ISOC_EN_MASK 0x08 | |
f6e2e6b6 JR |
58 | |
59 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
60 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
61 | ||
62 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
63 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
64 | #define ACPI_DEVFLAG_NMI 0x04 | |
65 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
66 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
67 | #define ACPI_DEVFLAG_LINT0 0x40 | |
68 | #define ACPI_DEVFLAG_LINT1 0x80 | |
69 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
70 | ||
b65233a9 JR |
71 | /* |
72 | * ACPI table definitions | |
73 | * | |
74 | * These data structures are laid over the table to parse the important values | |
75 | * out of it. | |
76 | */ | |
77 | ||
78 | /* | |
79 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
80 | * or more ivhd_entrys. | |
81 | */ | |
f6e2e6b6 JR |
82 | struct ivhd_header { |
83 | u8 type; | |
84 | u8 flags; | |
85 | u16 length; | |
86 | u16 devid; | |
87 | u16 cap_ptr; | |
88 | u64 mmio_phys; | |
89 | u16 pci_seg; | |
90 | u16 info; | |
91 | u32 reserved; | |
92 | } __attribute__((packed)); | |
93 | ||
b65233a9 JR |
94 | /* |
95 | * A device entry describing which devices a specific IOMMU translates and | |
96 | * which requestor ids they use. | |
97 | */ | |
f6e2e6b6 JR |
98 | struct ivhd_entry { |
99 | u8 type; | |
100 | u16 devid; | |
101 | u8 flags; | |
102 | u32 ext; | |
103 | } __attribute__((packed)); | |
104 | ||
b65233a9 JR |
105 | /* |
106 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
107 | * ranges for devices and regions that should be unity mapped. | |
108 | */ | |
f6e2e6b6 JR |
109 | struct ivmd_header { |
110 | u8 type; | |
111 | u8 flags; | |
112 | u16 length; | |
113 | u16 devid; | |
114 | u16 aux; | |
115 | u64 resv; | |
116 | u64 range_start; | |
117 | u64 range_length; | |
118 | } __attribute__((packed)); | |
119 | ||
fefda117 JR |
120 | bool amd_iommu_dump; |
121 | ||
c1cbebee JR |
122 | static int __initdata amd_iommu_detected; |
123 | ||
b65233a9 JR |
124 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
125 | to handle */ | |
2e22847f | 126 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 | 127 | we find in ACPI */ |
afa9fdc2 | 128 | bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 129 | |
2e22847f | 130 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 131 | system */ |
928abd25 | 132 | |
bb52777e JR |
133 | /* Array to assign indices to IOMMUs*/ |
134 | struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
135 | int amd_iommus_present; | |
136 | ||
318afd41 JR |
137 | /* IOMMUs have a non-present cache? */ |
138 | bool amd_iommu_np_cache __read_mostly; | |
139 | ||
aeb26f55 JR |
140 | /* |
141 | * List of protection domains - used during resume | |
142 | */ | |
143 | LIST_HEAD(amd_iommu_pd_list); | |
144 | spinlock_t amd_iommu_pd_lock; | |
145 | ||
b65233a9 JR |
146 | /* |
147 | * Pointer to the device table which is shared by all AMD IOMMUs | |
148 | * it is indexed by the PCI device id or the HT unit id and contains | |
149 | * information about the domain the device belongs to as well as the | |
150 | * page table root pointer. | |
151 | */ | |
928abd25 | 152 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
153 | |
154 | /* | |
155 | * The alias table is a driver specific data structure which contains the | |
156 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
157 | * More than one device can share the same requestor id. | |
158 | */ | |
928abd25 | 159 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
160 | |
161 | /* | |
162 | * The rlookup table is used to find the IOMMU which is responsible | |
163 | * for a specific device. It is also indexed by the PCI device id. | |
164 | */ | |
928abd25 | 165 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 | 166 | |
b65233a9 JR |
167 | /* |
168 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
169 | * to know which ones are already in use. | |
170 | */ | |
928abd25 JR |
171 | unsigned long *amd_iommu_pd_alloc_bitmap; |
172 | ||
b65233a9 JR |
173 | static u32 dev_table_size; /* size of the device table */ |
174 | static u32 alias_table_size; /* size of the alias table */ | |
175 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 176 | |
208ec8c9 JR |
177 | static inline void update_last_devid(u16 devid) |
178 | { | |
179 | if (devid > amd_iommu_last_bdf) | |
180 | amd_iommu_last_bdf = devid; | |
181 | } | |
182 | ||
c571484e JR |
183 | static inline unsigned long tbl_size(int entry_size) |
184 | { | |
185 | unsigned shift = PAGE_SHIFT + | |
421f909c | 186 | get_order(((int)amd_iommu_last_bdf + 1) * entry_size); |
c571484e JR |
187 | |
188 | return 1UL << shift; | |
189 | } | |
190 | ||
b65233a9 JR |
191 | /**************************************************************************** |
192 | * | |
193 | * AMD IOMMU MMIO register space handling functions | |
194 | * | |
195 | * These functions are used to program the IOMMU device registers in | |
196 | * MMIO space required for that driver. | |
197 | * | |
198 | ****************************************************************************/ | |
3e8064ba | 199 | |
b65233a9 JR |
200 | /* |
201 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
202 | * exclusion range are passed through untranslated | |
203 | */ | |
05f92db9 | 204 | static void iommu_set_exclusion_range(struct amd_iommu *iommu) |
b2026aa2 JR |
205 | { |
206 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
207 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
208 | u64 entry; | |
209 | ||
210 | if (!iommu->exclusion_start) | |
211 | return; | |
212 | ||
213 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
214 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
215 | &entry, sizeof(entry)); | |
216 | ||
217 | entry = limit; | |
218 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
219 | &entry, sizeof(entry)); | |
220 | } | |
221 | ||
b65233a9 | 222 | /* Programs the physical address of the device table into the IOMMU hardware */ |
b2026aa2 JR |
223 | static void __init iommu_set_device_table(struct amd_iommu *iommu) |
224 | { | |
f609891f | 225 | u64 entry; |
b2026aa2 JR |
226 | |
227 | BUG_ON(iommu->mmio_base == NULL); | |
228 | ||
229 | entry = virt_to_phys(amd_iommu_dev_table); | |
230 | entry |= (dev_table_size >> 12) - 1; | |
231 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
232 | &entry, sizeof(entry)); | |
233 | } | |
234 | ||
b65233a9 | 235 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
05f92db9 | 236 | static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
237 | { |
238 | u32 ctrl; | |
239 | ||
240 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
241 | ctrl |= (1 << bit); | |
242 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
243 | } | |
244 | ||
ca020711 | 245 | static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
246 | { |
247 | u32 ctrl; | |
248 | ||
199d0d50 | 249 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
250 | ctrl &= ~(1 << bit); |
251 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
252 | } | |
253 | ||
b65233a9 | 254 | /* Function to enable the hardware */ |
05f92db9 | 255 | static void iommu_enable(struct amd_iommu *iommu) |
b2026aa2 | 256 | { |
4c6f40d4 | 257 | printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n", |
a4e267c8 | 258 | dev_name(&iommu->dev->dev), iommu->cap_ptr); |
b2026aa2 JR |
259 | |
260 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); | |
b2026aa2 JR |
261 | } |
262 | ||
92ac4320 | 263 | static void iommu_disable(struct amd_iommu *iommu) |
126c52be | 264 | { |
a8c485bb CW |
265 | /* Disable command buffer */ |
266 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
267 | ||
268 | /* Disable event logging and event interrupts */ | |
269 | iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); | |
270 | iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); | |
271 | ||
272 | /* Disable IOMMU hardware itself */ | |
92ac4320 | 273 | iommu_feature_disable(iommu, CONTROL_IOMMU_EN); |
126c52be JR |
274 | } |
275 | ||
b65233a9 JR |
276 | /* |
277 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
278 | * the system has one. | |
279 | */ | |
6c56747b JR |
280 | static u8 * __init iommu_map_mmio_space(u64 address) |
281 | { | |
282 | u8 *ret; | |
283 | ||
284 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) | |
285 | return NULL; | |
286 | ||
287 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | |
288 | if (ret != NULL) | |
289 | return ret; | |
290 | ||
291 | release_mem_region(address, MMIO_REGION_LENGTH); | |
292 | ||
293 | return NULL; | |
294 | } | |
295 | ||
296 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
297 | { | |
298 | if (iommu->mmio_base) | |
299 | iounmap(iommu->mmio_base); | |
300 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
301 | } | |
302 | ||
b65233a9 JR |
303 | /**************************************************************************** |
304 | * | |
305 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
306 | * parsing. In this pass we try to find out the highest device id this | |
307 | * code has to handle. Upon this information the size of the shared data | |
308 | * structures is determined later. | |
309 | * | |
310 | ****************************************************************************/ | |
311 | ||
b514e555 JR |
312 | /* |
313 | * This function calculates the length of a given IVHD entry | |
314 | */ | |
315 | static inline int ivhd_entry_length(u8 *ivhd) | |
316 | { | |
317 | return 0x04 << (*ivhd >> 6); | |
318 | } | |
319 | ||
b65233a9 JR |
320 | /* |
321 | * This function reads the last device id the IOMMU has to handle from the PCI | |
322 | * capability header for this IOMMU | |
323 | */ | |
3e8064ba JR |
324 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
325 | { | |
326 | u32 cap; | |
327 | ||
328 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 329 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
330 | |
331 | return 0; | |
332 | } | |
333 | ||
b65233a9 JR |
334 | /* |
335 | * After reading the highest device id from the IOMMU PCI capability header | |
336 | * this function looks if there is a higher device id defined in the ACPI table | |
337 | */ | |
3e8064ba JR |
338 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
339 | { | |
340 | u8 *p = (void *)h, *end = (void *)h; | |
341 | struct ivhd_entry *dev; | |
342 | ||
343 | p += sizeof(*h); | |
344 | end += h->length; | |
345 | ||
346 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
347 | PCI_SLOT(h->devid), | |
348 | PCI_FUNC(h->devid), | |
349 | h->cap_ptr); | |
350 | ||
351 | while (p < end) { | |
352 | dev = (struct ivhd_entry *)p; | |
353 | switch (dev->type) { | |
354 | case IVHD_DEV_SELECT: | |
355 | case IVHD_DEV_RANGE_END: | |
356 | case IVHD_DEV_ALIAS: | |
357 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 358 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 359 | update_last_devid(dev->devid); |
3e8064ba JR |
360 | break; |
361 | default: | |
362 | break; | |
363 | } | |
b514e555 | 364 | p += ivhd_entry_length(p); |
3e8064ba JR |
365 | } |
366 | ||
367 | WARN_ON(p != end); | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
b65233a9 JR |
372 | /* |
373 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
374 | * id which we need to handle. This is the first of three functions which parse | |
375 | * the ACPI table. So we check the checksum here. | |
376 | */ | |
3e8064ba JR |
377 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
378 | { | |
379 | int i; | |
380 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
381 | struct ivhd_header *h; | |
382 | ||
383 | /* | |
384 | * Validate checksum here so we don't need to do it when | |
385 | * we actually parse the table | |
386 | */ | |
387 | for (i = 0; i < table->length; ++i) | |
388 | checksum += p[i]; | |
389 | if (checksum != 0) | |
390 | /* ACPI table corrupt */ | |
391 | return -ENODEV; | |
392 | ||
393 | p += IVRS_HEADER_LENGTH; | |
394 | ||
395 | end += table->length; | |
396 | while (p < end) { | |
397 | h = (struct ivhd_header *)p; | |
398 | switch (h->type) { | |
399 | case ACPI_IVHD_TYPE: | |
400 | find_last_devid_from_ivhd(h); | |
401 | break; | |
402 | default: | |
403 | break; | |
404 | } | |
405 | p += h->length; | |
406 | } | |
407 | WARN_ON(p != end); | |
408 | ||
409 | return 0; | |
410 | } | |
411 | ||
b65233a9 JR |
412 | /**************************************************************************** |
413 | * | |
414 | * The following functions belong the the code path which parses the ACPI table | |
415 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
416 | * data structures, initialize the device/alias/rlookup table and also | |
417 | * basically initialize the hardware. | |
418 | * | |
419 | ****************************************************************************/ | |
420 | ||
421 | /* | |
422 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
423 | * write commands to that buffer later and the IOMMU will execute them | |
424 | * asynchronously | |
425 | */ | |
b36ca91e JR |
426 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
427 | { | |
d0312b21 | 428 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 429 | get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
430 | |
431 | if (cmd_buf == NULL) | |
432 | return NULL; | |
433 | ||
434 | iommu->cmd_buf_size = CMD_BUFFER_SIZE; | |
435 | ||
58492e12 JR |
436 | return cmd_buf; |
437 | } | |
438 | ||
93f1cc67 JR |
439 | /* |
440 | * This function resets the command buffer if the IOMMU stopped fetching | |
441 | * commands from it. | |
442 | */ | |
443 | void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) | |
444 | { | |
445 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
446 | ||
447 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
448 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
449 | ||
450 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | |
451 | } | |
452 | ||
58492e12 JR |
453 | /* |
454 | * This function writes the command buffer address to the hardware and | |
455 | * enables it. | |
456 | */ | |
457 | static void iommu_enable_command_buffer(struct amd_iommu *iommu) | |
458 | { | |
459 | u64 entry; | |
460 | ||
461 | BUG_ON(iommu->cmd_buf == NULL); | |
462 | ||
463 | entry = (u64)virt_to_phys(iommu->cmd_buf); | |
b36ca91e | 464 | entry |= MMIO_CMD_SIZE_512; |
58492e12 | 465 | |
b36ca91e | 466 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, |
58492e12 | 467 | &entry, sizeof(entry)); |
b36ca91e | 468 | |
93f1cc67 | 469 | amd_iommu_reset_cmd_buffer(iommu); |
b36ca91e JR |
470 | } |
471 | ||
472 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
473 | { | |
23c1713f JR |
474 | free_pages((unsigned long)iommu->cmd_buf, |
475 | get_order(iommu->cmd_buf_size)); | |
b36ca91e JR |
476 | } |
477 | ||
335503e5 JR |
478 | /* allocates the memory where the IOMMU will log its events to */ |
479 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
480 | { | |
335503e5 JR |
481 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
482 | get_order(EVT_BUFFER_SIZE)); | |
483 | ||
484 | if (iommu->evt_buf == NULL) | |
485 | return NULL; | |
486 | ||
1bc6f838 JR |
487 | iommu->evt_buf_size = EVT_BUFFER_SIZE; |
488 | ||
58492e12 JR |
489 | return iommu->evt_buf; |
490 | } | |
491 | ||
492 | static void iommu_enable_event_buffer(struct amd_iommu *iommu) | |
493 | { | |
494 | u64 entry; | |
495 | ||
496 | BUG_ON(iommu->evt_buf == NULL); | |
497 | ||
335503e5 | 498 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; |
58492e12 | 499 | |
335503e5 JR |
500 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, |
501 | &entry, sizeof(entry)); | |
502 | ||
09067207 JR |
503 | /* set head and tail to zero manually */ |
504 | writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
505 | writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
506 | ||
58492e12 | 507 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); |
335503e5 JR |
508 | } |
509 | ||
510 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
511 | { | |
512 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
513 | } | |
514 | ||
b65233a9 | 515 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
516 | static void set_dev_entry_bit(u16 devid, u8 bit) |
517 | { | |
518 | int i = (bit >> 5) & 0x07; | |
519 | int _bit = bit & 0x1f; | |
520 | ||
521 | amd_iommu_dev_table[devid].data[i] |= (1 << _bit); | |
522 | } | |
523 | ||
c5cca146 JR |
524 | static int get_dev_entry_bit(u16 devid, u8 bit) |
525 | { | |
526 | int i = (bit >> 5) & 0x07; | |
527 | int _bit = bit & 0x1f; | |
528 | ||
529 | return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit; | |
530 | } | |
531 | ||
532 | ||
533 | void amd_iommu_apply_erratum_63(u16 devid) | |
534 | { | |
535 | int sysmgt; | |
536 | ||
537 | sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | | |
538 | (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); | |
539 | ||
540 | if (sysmgt == 0x01) | |
541 | set_dev_entry_bit(devid, DEV_ENTRY_IW); | |
542 | } | |
543 | ||
5ff4789d JR |
544 | /* Writes the specific IOMMU for a device into the rlookup table */ |
545 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
546 | { | |
547 | amd_iommu_rlookup_table[devid] = iommu; | |
548 | } | |
549 | ||
b65233a9 JR |
550 | /* |
551 | * This function takes the device specific flags read from the ACPI | |
552 | * table and sets up the device table entry with that information | |
553 | */ | |
5ff4789d JR |
554 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
555 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
556 | { |
557 | if (flags & ACPI_DEVFLAG_INITPASS) | |
558 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
559 | if (flags & ACPI_DEVFLAG_EXTINT) | |
560 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
561 | if (flags & ACPI_DEVFLAG_NMI) | |
562 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
563 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
564 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
565 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
566 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
567 | if (flags & ACPI_DEVFLAG_LINT0) | |
568 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
569 | if (flags & ACPI_DEVFLAG_LINT1) | |
570 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 571 | |
c5cca146 JR |
572 | amd_iommu_apply_erratum_63(devid); |
573 | ||
5ff4789d | 574 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
575 | } |
576 | ||
b65233a9 JR |
577 | /* |
578 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
579 | * it | |
580 | */ | |
3566b778 JR |
581 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
582 | { | |
583 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
584 | ||
585 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
586 | return; | |
587 | ||
588 | if (iommu) { | |
b65233a9 JR |
589 | /* |
590 | * We only can configure exclusion ranges per IOMMU, not | |
591 | * per device. But we can enable the exclusion range per | |
592 | * device. This is done here | |
593 | */ | |
3566b778 JR |
594 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
595 | iommu->exclusion_start = m->range_start; | |
596 | iommu->exclusion_length = m->range_length; | |
597 | } | |
598 | } | |
599 | ||
b65233a9 JR |
600 | /* |
601 | * This function reads some important data from the IOMMU PCI space and | |
602 | * initializes the driver data structure with it. It reads the hardware | |
603 | * capabilities and the first/last device entries | |
604 | */ | |
5d0c8e49 JR |
605 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
606 | { | |
5d0c8e49 | 607 | int cap_ptr = iommu->cap_ptr; |
a80dc3e0 | 608 | u32 range, misc; |
5d0c8e49 | 609 | |
3eaf28a1 JR |
610 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
611 | &iommu->cap); | |
612 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
613 | &range); | |
a80dc3e0 JR |
614 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, |
615 | &misc); | |
5d0c8e49 | 616 | |
d591b0a3 JR |
617 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), |
618 | MMIO_GET_FD(range)); | |
619 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
620 | MMIO_GET_LD(range)); | |
a80dc3e0 | 621 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); |
5d0c8e49 JR |
622 | } |
623 | ||
b65233a9 JR |
624 | /* |
625 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
626 | * initializes the hardware and our data structures with it. | |
627 | */ | |
5d0c8e49 JR |
628 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
629 | struct ivhd_header *h) | |
630 | { | |
631 | u8 *p = (u8 *)h; | |
632 | u8 *end = p, flags = 0; | |
633 | u16 dev_i, devid = 0, devid_start = 0, devid_to = 0; | |
634 | u32 ext_flags = 0; | |
58a3bee5 | 635 | bool alias = false; |
5d0c8e49 JR |
636 | struct ivhd_entry *e; |
637 | ||
638 | /* | |
639 | * First set the recommended feature enable bits from ACPI | |
640 | * into the IOMMU control registers | |
641 | */ | |
6da7342f | 642 | h->flags & IVHD_FLAG_HT_TUN_EN_MASK ? |
5d0c8e49 JR |
643 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : |
644 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
645 | ||
6da7342f | 646 | h->flags & IVHD_FLAG_PASSPW_EN_MASK ? |
5d0c8e49 JR |
647 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : |
648 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
649 | ||
6da7342f | 650 | h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ? |
5d0c8e49 JR |
651 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : |
652 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
653 | ||
6da7342f | 654 | h->flags & IVHD_FLAG_ISOC_EN_MASK ? |
5d0c8e49 JR |
655 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : |
656 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
657 | ||
658 | /* | |
659 | * make IOMMU memory accesses cache coherent | |
660 | */ | |
661 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
662 | ||
663 | /* | |
664 | * Done. Now parse the device entries | |
665 | */ | |
666 | p += sizeof(struct ivhd_header); | |
667 | end += h->length; | |
668 | ||
42a698f4 | 669 | |
5d0c8e49 JR |
670 | while (p < end) { |
671 | e = (struct ivhd_entry *)p; | |
672 | switch (e->type) { | |
673 | case IVHD_DEV_ALL: | |
42a698f4 JR |
674 | |
675 | DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x" | |
676 | " last device %02x:%02x.%x flags: %02x\n", | |
677 | PCI_BUS(iommu->first_device), | |
678 | PCI_SLOT(iommu->first_device), | |
679 | PCI_FUNC(iommu->first_device), | |
680 | PCI_BUS(iommu->last_device), | |
681 | PCI_SLOT(iommu->last_device), | |
682 | PCI_FUNC(iommu->last_device), | |
683 | e->flags); | |
684 | ||
5d0c8e49 JR |
685 | for (dev_i = iommu->first_device; |
686 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
687 | set_dev_entry_from_acpi(iommu, dev_i, |
688 | e->flags, 0); | |
5d0c8e49 JR |
689 | break; |
690 | case IVHD_DEV_SELECT: | |
42a698f4 JR |
691 | |
692 | DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " | |
693 | "flags: %02x\n", | |
694 | PCI_BUS(e->devid), | |
695 | PCI_SLOT(e->devid), | |
696 | PCI_FUNC(e->devid), | |
697 | e->flags); | |
698 | ||
5d0c8e49 | 699 | devid = e->devid; |
5ff4789d | 700 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
701 | break; |
702 | case IVHD_DEV_SELECT_RANGE_START: | |
42a698f4 JR |
703 | |
704 | DUMP_printk(" DEV_SELECT_RANGE_START\t " | |
705 | "devid: %02x:%02x.%x flags: %02x\n", | |
706 | PCI_BUS(e->devid), | |
707 | PCI_SLOT(e->devid), | |
708 | PCI_FUNC(e->devid), | |
709 | e->flags); | |
710 | ||
5d0c8e49 JR |
711 | devid_start = e->devid; |
712 | flags = e->flags; | |
713 | ext_flags = 0; | |
58a3bee5 | 714 | alias = false; |
5d0c8e49 JR |
715 | break; |
716 | case IVHD_DEV_ALIAS: | |
42a698f4 JR |
717 | |
718 | DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " | |
719 | "flags: %02x devid_to: %02x:%02x.%x\n", | |
720 | PCI_BUS(e->devid), | |
721 | PCI_SLOT(e->devid), | |
722 | PCI_FUNC(e->devid), | |
723 | e->flags, | |
724 | PCI_BUS(e->ext >> 8), | |
725 | PCI_SLOT(e->ext >> 8), | |
726 | PCI_FUNC(e->ext >> 8)); | |
727 | ||
5d0c8e49 JR |
728 | devid = e->devid; |
729 | devid_to = e->ext >> 8; | |
7a6a3a08 | 730 | set_dev_entry_from_acpi(iommu, devid , e->flags, 0); |
7455aab1 | 731 | set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); |
5d0c8e49 JR |
732 | amd_iommu_alias_table[devid] = devid_to; |
733 | break; | |
734 | case IVHD_DEV_ALIAS_RANGE: | |
42a698f4 JR |
735 | |
736 | DUMP_printk(" DEV_ALIAS_RANGE\t\t " | |
737 | "devid: %02x:%02x.%x flags: %02x " | |
738 | "devid_to: %02x:%02x.%x\n", | |
739 | PCI_BUS(e->devid), | |
740 | PCI_SLOT(e->devid), | |
741 | PCI_FUNC(e->devid), | |
742 | e->flags, | |
743 | PCI_BUS(e->ext >> 8), | |
744 | PCI_SLOT(e->ext >> 8), | |
745 | PCI_FUNC(e->ext >> 8)); | |
746 | ||
5d0c8e49 JR |
747 | devid_start = e->devid; |
748 | flags = e->flags; | |
749 | devid_to = e->ext >> 8; | |
750 | ext_flags = 0; | |
58a3bee5 | 751 | alias = true; |
5d0c8e49 JR |
752 | break; |
753 | case IVHD_DEV_EXT_SELECT: | |
42a698f4 JR |
754 | |
755 | DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " | |
756 | "flags: %02x ext: %08x\n", | |
757 | PCI_BUS(e->devid), | |
758 | PCI_SLOT(e->devid), | |
759 | PCI_FUNC(e->devid), | |
760 | e->flags, e->ext); | |
761 | ||
5d0c8e49 | 762 | devid = e->devid; |
5ff4789d JR |
763 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
764 | e->ext); | |
5d0c8e49 JR |
765 | break; |
766 | case IVHD_DEV_EXT_SELECT_RANGE: | |
42a698f4 JR |
767 | |
768 | DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " | |
769 | "%02x:%02x.%x flags: %02x ext: %08x\n", | |
770 | PCI_BUS(e->devid), | |
771 | PCI_SLOT(e->devid), | |
772 | PCI_FUNC(e->devid), | |
773 | e->flags, e->ext); | |
774 | ||
5d0c8e49 JR |
775 | devid_start = e->devid; |
776 | flags = e->flags; | |
777 | ext_flags = e->ext; | |
58a3bee5 | 778 | alias = false; |
5d0c8e49 JR |
779 | break; |
780 | case IVHD_DEV_RANGE_END: | |
42a698f4 JR |
781 | |
782 | DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", | |
783 | PCI_BUS(e->devid), | |
784 | PCI_SLOT(e->devid), | |
785 | PCI_FUNC(e->devid)); | |
786 | ||
5d0c8e49 JR |
787 | devid = e->devid; |
788 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
7a6a3a08 | 789 | if (alias) { |
5d0c8e49 | 790 | amd_iommu_alias_table[dev_i] = devid_to; |
7a6a3a08 JR |
791 | set_dev_entry_from_acpi(iommu, |
792 | devid_to, flags, ext_flags); | |
793 | } | |
794 | set_dev_entry_from_acpi(iommu, dev_i, | |
795 | flags, ext_flags); | |
5d0c8e49 JR |
796 | } |
797 | break; | |
798 | default: | |
799 | break; | |
800 | } | |
801 | ||
b514e555 | 802 | p += ivhd_entry_length(p); |
5d0c8e49 JR |
803 | } |
804 | } | |
805 | ||
b65233a9 | 806 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
807 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
808 | { | |
809 | u16 i; | |
810 | ||
811 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
812 | set_iommu_for_device(iommu, i); | |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
e47d402d JR |
817 | static void __init free_iommu_one(struct amd_iommu *iommu) |
818 | { | |
819 | free_command_buffer(iommu); | |
335503e5 | 820 | free_event_buffer(iommu); |
e47d402d JR |
821 | iommu_unmap_mmio_space(iommu); |
822 | } | |
823 | ||
824 | static void __init free_iommu_all(void) | |
825 | { | |
826 | struct amd_iommu *iommu, *next; | |
827 | ||
3bd22172 | 828 | for_each_iommu_safe(iommu, next) { |
e47d402d JR |
829 | list_del(&iommu->list); |
830 | free_iommu_one(iommu); | |
831 | kfree(iommu); | |
832 | } | |
833 | } | |
834 | ||
b65233a9 JR |
835 | /* |
836 | * This function clues the initialization function for one IOMMU | |
837 | * together and also allocates the command buffer and programs the | |
838 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
839 | */ | |
e47d402d JR |
840 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
841 | { | |
842 | spin_lock_init(&iommu->lock); | |
bb52777e JR |
843 | |
844 | /* Add IOMMU to internal data structures */ | |
e47d402d | 845 | list_add_tail(&iommu->list, &amd_iommu_list); |
bb52777e JR |
846 | iommu->index = amd_iommus_present++; |
847 | ||
848 | if (unlikely(iommu->index >= MAX_IOMMUS)) { | |
849 | WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n"); | |
850 | return -ENOSYS; | |
851 | } | |
852 | ||
853 | /* Index is fine - add IOMMU to the array */ | |
854 | amd_iommus[iommu->index] = iommu; | |
e47d402d JR |
855 | |
856 | /* | |
857 | * Copy data from ACPI table entry to the iommu struct | |
858 | */ | |
3eaf28a1 JR |
859 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); |
860 | if (!iommu->dev) | |
861 | return 1; | |
862 | ||
e47d402d | 863 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 864 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
865 | iommu->mmio_phys = h->mmio_phys; |
866 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
867 | if (!iommu->mmio_base) | |
868 | return -ENOMEM; | |
869 | ||
e47d402d JR |
870 | iommu->cmd_buf = alloc_command_buffer(iommu); |
871 | if (!iommu->cmd_buf) | |
872 | return -ENOMEM; | |
873 | ||
335503e5 JR |
874 | iommu->evt_buf = alloc_event_buffer(iommu); |
875 | if (!iommu->evt_buf) | |
876 | return -ENOMEM; | |
877 | ||
a80dc3e0 JR |
878 | iommu->int_enabled = false; |
879 | ||
e47d402d JR |
880 | init_iommu_from_pci(iommu); |
881 | init_iommu_from_acpi(iommu, h); | |
882 | init_iommu_devices(iommu); | |
883 | ||
318afd41 JR |
884 | if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) |
885 | amd_iommu_np_cache = true; | |
886 | ||
8a66712b | 887 | return pci_enable_device(iommu->dev); |
e47d402d JR |
888 | } |
889 | ||
b65233a9 JR |
890 | /* |
891 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
892 | * IOMMU structure and initializes it with init_iommu_one() | |
893 | */ | |
e47d402d JR |
894 | static int __init init_iommu_all(struct acpi_table_header *table) |
895 | { | |
896 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
897 | struct ivhd_header *h; | |
898 | struct amd_iommu *iommu; | |
899 | int ret; | |
900 | ||
e47d402d JR |
901 | end += table->length; |
902 | p += IVRS_HEADER_LENGTH; | |
903 | ||
904 | while (p < end) { | |
905 | h = (struct ivhd_header *)p; | |
906 | switch (*p) { | |
907 | case ACPI_IVHD_TYPE: | |
9c72041f | 908 | |
ae908c22 | 909 | DUMP_printk("device: %02x:%02x.%01x cap: %04x " |
9c72041f JR |
910 | "seg: %d flags: %01x info %04x\n", |
911 | PCI_BUS(h->devid), PCI_SLOT(h->devid), | |
912 | PCI_FUNC(h->devid), h->cap_ptr, | |
913 | h->pci_seg, h->flags, h->info); | |
914 | DUMP_printk(" mmio-addr: %016llx\n", | |
915 | h->mmio_phys); | |
916 | ||
e47d402d JR |
917 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); |
918 | if (iommu == NULL) | |
919 | return -ENOMEM; | |
920 | ret = init_iommu_one(iommu, h); | |
921 | if (ret) | |
922 | return ret; | |
923 | break; | |
924 | default: | |
925 | break; | |
926 | } | |
927 | p += h->length; | |
928 | ||
929 | } | |
930 | WARN_ON(p != end); | |
931 | ||
932 | return 0; | |
933 | } | |
934 | ||
a80dc3e0 JR |
935 | /**************************************************************************** |
936 | * | |
937 | * The following functions initialize the MSI interrupts for all IOMMUs | |
938 | * in the system. Its a bit challenging because there could be multiple | |
939 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
940 | * pci_dev. | |
941 | * | |
942 | ****************************************************************************/ | |
943 | ||
9f800de3 | 944 | static int iommu_setup_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
945 | { |
946 | int r; | |
a80dc3e0 JR |
947 | |
948 | if (pci_enable_msi(iommu->dev)) | |
949 | return 1; | |
950 | ||
951 | r = request_irq(iommu->dev->irq, amd_iommu_int_handler, | |
952 | IRQF_SAMPLE_RANDOM, | |
4c6f40d4 | 953 | "AMD-Vi", |
a80dc3e0 JR |
954 | NULL); |
955 | ||
956 | if (r) { | |
957 | pci_disable_msi(iommu->dev); | |
958 | return 1; | |
959 | } | |
960 | ||
fab6afa3 | 961 | iommu->int_enabled = true; |
58492e12 JR |
962 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); |
963 | ||
a80dc3e0 JR |
964 | return 0; |
965 | } | |
966 | ||
05f92db9 | 967 | static int iommu_init_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
968 | { |
969 | if (iommu->int_enabled) | |
970 | return 0; | |
971 | ||
d91cecdd | 972 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) |
a80dc3e0 JR |
973 | return iommu_setup_msi(iommu); |
974 | ||
975 | return 1; | |
976 | } | |
977 | ||
b65233a9 JR |
978 | /**************************************************************************** |
979 | * | |
980 | * The next functions belong to the third pass of parsing the ACPI | |
981 | * table. In this last pass the memory mapping requirements are | |
982 | * gathered (like exclusion and unity mapping reanges). | |
983 | * | |
984 | ****************************************************************************/ | |
985 | ||
be2a022c JR |
986 | static void __init free_unity_maps(void) |
987 | { | |
988 | struct unity_map_entry *entry, *next; | |
989 | ||
990 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
991 | list_del(&entry->list); | |
992 | kfree(entry); | |
993 | } | |
994 | } | |
995 | ||
b65233a9 | 996 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
997 | static int __init init_exclusion_range(struct ivmd_header *m) |
998 | { | |
999 | int i; | |
1000 | ||
1001 | switch (m->type) { | |
1002 | case ACPI_IVMD_TYPE: | |
1003 | set_device_exclusion_range(m->devid, m); | |
1004 | break; | |
1005 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 1006 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
1007 | set_device_exclusion_range(i, m); |
1008 | break; | |
1009 | case ACPI_IVMD_TYPE_RANGE: | |
1010 | for (i = m->devid; i <= m->aux; ++i) | |
1011 | set_device_exclusion_range(i, m); | |
1012 | break; | |
1013 | default: | |
1014 | break; | |
1015 | } | |
1016 | ||
1017 | return 0; | |
1018 | } | |
1019 | ||
b65233a9 | 1020 | /* called for unity map ACPI definition */ |
be2a022c JR |
1021 | static int __init init_unity_map_range(struct ivmd_header *m) |
1022 | { | |
1023 | struct unity_map_entry *e = 0; | |
02acc43a | 1024 | char *s; |
be2a022c JR |
1025 | |
1026 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
1027 | if (e == NULL) | |
1028 | return -ENOMEM; | |
1029 | ||
1030 | switch (m->type) { | |
1031 | default: | |
0bc252f4 JR |
1032 | kfree(e); |
1033 | return 0; | |
be2a022c | 1034 | case ACPI_IVMD_TYPE: |
02acc43a | 1035 | s = "IVMD_TYPEi\t\t\t"; |
be2a022c JR |
1036 | e->devid_start = e->devid_end = m->devid; |
1037 | break; | |
1038 | case ACPI_IVMD_TYPE_ALL: | |
02acc43a | 1039 | s = "IVMD_TYPE_ALL\t\t"; |
be2a022c JR |
1040 | e->devid_start = 0; |
1041 | e->devid_end = amd_iommu_last_bdf; | |
1042 | break; | |
1043 | case ACPI_IVMD_TYPE_RANGE: | |
02acc43a | 1044 | s = "IVMD_TYPE_RANGE\t\t"; |
be2a022c JR |
1045 | e->devid_start = m->devid; |
1046 | e->devid_end = m->aux; | |
1047 | break; | |
1048 | } | |
1049 | e->address_start = PAGE_ALIGN(m->range_start); | |
1050 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
1051 | e->prot = m->flags >> 1; | |
1052 | ||
02acc43a JR |
1053 | DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" |
1054 | " range_start: %016llx range_end: %016llx flags: %x\n", s, | |
1055 | PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start), | |
1056 | PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end), | |
1057 | PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), | |
1058 | e->address_start, e->address_end, m->flags); | |
1059 | ||
be2a022c JR |
1060 | list_add_tail(&e->list, &amd_iommu_unity_map); |
1061 | ||
1062 | return 0; | |
1063 | } | |
1064 | ||
b65233a9 | 1065 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
1066 | static int __init init_memory_definitions(struct acpi_table_header *table) |
1067 | { | |
1068 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1069 | struct ivmd_header *m; | |
1070 | ||
be2a022c JR |
1071 | end += table->length; |
1072 | p += IVRS_HEADER_LENGTH; | |
1073 | ||
1074 | while (p < end) { | |
1075 | m = (struct ivmd_header *)p; | |
1076 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
1077 | init_exclusion_range(m); | |
1078 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
1079 | init_unity_map_range(m); | |
1080 | ||
1081 | p += m->length; | |
1082 | } | |
1083 | ||
1084 | return 0; | |
1085 | } | |
1086 | ||
9f5f5fb3 JR |
1087 | /* |
1088 | * Init the device table to not allow DMA access for devices and | |
1089 | * suppress all page faults | |
1090 | */ | |
1091 | static void init_device_table(void) | |
1092 | { | |
1093 | u16 devid; | |
1094 | ||
1095 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
1096 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
1097 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
1098 | } |
1099 | } | |
1100 | ||
b65233a9 JR |
1101 | /* |
1102 | * This function finally enables all IOMMUs found in the system after | |
1103 | * they have been initialized | |
1104 | */ | |
05f92db9 | 1105 | static void enable_iommus(void) |
8736197b JR |
1106 | { |
1107 | struct amd_iommu *iommu; | |
1108 | ||
3bd22172 | 1109 | for_each_iommu(iommu) { |
a8c485bb | 1110 | iommu_disable(iommu); |
58492e12 JR |
1111 | iommu_set_device_table(iommu); |
1112 | iommu_enable_command_buffer(iommu); | |
1113 | iommu_enable_event_buffer(iommu); | |
8736197b | 1114 | iommu_set_exclusion_range(iommu); |
a80dc3e0 | 1115 | iommu_init_msi(iommu); |
8736197b JR |
1116 | iommu_enable(iommu); |
1117 | } | |
1118 | } | |
1119 | ||
92ac4320 JR |
1120 | static void disable_iommus(void) |
1121 | { | |
1122 | struct amd_iommu *iommu; | |
1123 | ||
1124 | for_each_iommu(iommu) | |
1125 | iommu_disable(iommu); | |
1126 | } | |
1127 | ||
7441e9cb JR |
1128 | /* |
1129 | * Suspend/Resume support | |
1130 | * disable suspend until real resume implemented | |
1131 | */ | |
1132 | ||
1133 | static int amd_iommu_resume(struct sys_device *dev) | |
1134 | { | |
736501ee JR |
1135 | /* re-load the hardware */ |
1136 | enable_iommus(); | |
1137 | ||
1138 | /* | |
1139 | * we have to flush after the IOMMUs are enabled because a | |
1140 | * disabled IOMMU will never execute the commands we send | |
1141 | */ | |
736501ee | 1142 | amd_iommu_flush_all_devices(); |
6a047d8b | 1143 | amd_iommu_flush_all_domains(); |
736501ee | 1144 | |
7441e9cb JR |
1145 | return 0; |
1146 | } | |
1147 | ||
1148 | static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state) | |
1149 | { | |
736501ee JR |
1150 | /* disable IOMMUs to go out of the way for BIOS */ |
1151 | disable_iommus(); | |
1152 | ||
1153 | return 0; | |
7441e9cb JR |
1154 | } |
1155 | ||
1156 | static struct sysdev_class amd_iommu_sysdev_class = { | |
1157 | .name = "amd_iommu", | |
1158 | .suspend = amd_iommu_suspend, | |
1159 | .resume = amd_iommu_resume, | |
1160 | }; | |
1161 | ||
1162 | static struct sys_device device_amd_iommu = { | |
1163 | .id = 0, | |
1164 | .cls = &amd_iommu_sysdev_class, | |
1165 | }; | |
1166 | ||
b65233a9 JR |
1167 | /* |
1168 | * This is the core init function for AMD IOMMU hardware in the system. | |
1169 | * This function is called from the generic x86 DMA layer initialization | |
1170 | * code. | |
1171 | * | |
1172 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
1173 | * three times: | |
1174 | * | |
1175 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1176 | * Upon this information the size of the data structures is | |
1177 | * determined that needs to be allocated. | |
1178 | * | |
1179 | * 2 pass) Initialize the data structures just allocated with the | |
1180 | * information in the ACPI table about available AMD IOMMUs | |
1181 | * in the system. It also maps the PCI devices in the | |
1182 | * system to specific IOMMUs | |
1183 | * | |
1184 | * 3 pass) After the basic data structures are allocated and | |
1185 | * initialized we update them with information about memory | |
1186 | * remapping requirements parsed out of the ACPI table in | |
1187 | * this last pass. | |
1188 | * | |
1189 | * After that the hardware is initialized and ready to go. In the last | |
1190 | * step we do some Linux specific things like registering the driver in | |
1191 | * the dma_ops interface and initializing the suspend/resume support | |
1192 | * functions. Finally it prints some information about AMD IOMMUs and | |
1193 | * the driver state and enables the hardware. | |
1194 | */ | |
ea1b0d39 | 1195 | static int __init amd_iommu_init(void) |
fe74c9cf JR |
1196 | { |
1197 | int i, ret = 0; | |
1198 | ||
fe74c9cf JR |
1199 | /* |
1200 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1201 | * we need to handle. Upon this information the shared data | |
1202 | * structures for the IOMMUs in the system will be allocated | |
1203 | */ | |
1204 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
1205 | return -ENODEV; | |
1206 | ||
c571484e JR |
1207 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1208 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1209 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf JR |
1210 | |
1211 | ret = -ENOMEM; | |
1212 | ||
1213 | /* Device table - directly used by all IOMMUs */ | |
5dc8bff0 | 1214 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1215 | get_order(dev_table_size)); |
1216 | if (amd_iommu_dev_table == NULL) | |
1217 | goto out; | |
1218 | ||
1219 | /* | |
1220 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1221 | * IOMMU see for that device | |
1222 | */ | |
1223 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1224 | get_order(alias_table_size)); | |
1225 | if (amd_iommu_alias_table == NULL) | |
1226 | goto free; | |
1227 | ||
1228 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1229 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1230 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1231 | get_order(rlookup_table_size)); |
1232 | if (amd_iommu_rlookup_table == NULL) | |
1233 | goto free; | |
1234 | ||
5dc8bff0 JR |
1235 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1236 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1237 | get_order(MAX_DOMAIN_ID/8)); |
1238 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
1239 | goto free; | |
1240 | ||
9f5f5fb3 JR |
1241 | /* init the device table */ |
1242 | init_device_table(); | |
1243 | ||
fe74c9cf | 1244 | /* |
5dc8bff0 | 1245 | * let all alias entries point to itself |
fe74c9cf | 1246 | */ |
3a61ec38 | 1247 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1248 | amd_iommu_alias_table[i] = i; |
1249 | ||
fe74c9cf JR |
1250 | /* |
1251 | * never allocate domain 0 because its used as the non-allocated and | |
1252 | * error value placeholder | |
1253 | */ | |
1254 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1255 | ||
aeb26f55 JR |
1256 | spin_lock_init(&amd_iommu_pd_lock); |
1257 | ||
fe74c9cf JR |
1258 | /* |
1259 | * now the data structures are allocated and basically initialized | |
1260 | * start the real acpi table scan | |
1261 | */ | |
1262 | ret = -ENODEV; | |
1263 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
1264 | goto free; | |
1265 | ||
1266 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) | |
1267 | goto free; | |
1268 | ||
129d6aba | 1269 | ret = sysdev_class_register(&amd_iommu_sysdev_class); |
8736197b JR |
1270 | if (ret) |
1271 | goto free; | |
1272 | ||
129d6aba | 1273 | ret = sysdev_register(&device_amd_iommu); |
7441e9cb JR |
1274 | if (ret) |
1275 | goto free; | |
1276 | ||
4751a951 JR |
1277 | if (iommu_pass_through) |
1278 | ret = amd_iommu_init_passthrough(); | |
1279 | else | |
1280 | ret = amd_iommu_init_dma_ops(); | |
7441e9cb JR |
1281 | if (ret) |
1282 | goto free; | |
1283 | ||
8736197b JR |
1284 | enable_iommus(); |
1285 | ||
4751a951 JR |
1286 | if (iommu_pass_through) |
1287 | goto out; | |
1288 | ||
afa9fdc2 | 1289 | if (amd_iommu_unmap_flush) |
4c6f40d4 | 1290 | printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n"); |
1c655773 | 1291 | else |
4c6f40d4 | 1292 | printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n"); |
1c655773 | 1293 | |
338bac52 | 1294 | x86_platform.iommu_shutdown = disable_iommus; |
fe74c9cf JR |
1295 | out: |
1296 | return ret; | |
1297 | ||
1298 | free: | |
d58befd3 JR |
1299 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, |
1300 | get_order(MAX_DOMAIN_ID/8)); | |
fe74c9cf | 1301 | |
9a836de0 JR |
1302 | free_pages((unsigned long)amd_iommu_rlookup_table, |
1303 | get_order(rlookup_table_size)); | |
fe74c9cf | 1304 | |
9a836de0 JR |
1305 | free_pages((unsigned long)amd_iommu_alias_table, |
1306 | get_order(alias_table_size)); | |
fe74c9cf | 1307 | |
9a836de0 JR |
1308 | free_pages((unsigned long)amd_iommu_dev_table, |
1309 | get_order(dev_table_size)); | |
fe74c9cf JR |
1310 | |
1311 | free_iommu_all(); | |
1312 | ||
1313 | free_unity_maps(); | |
1314 | ||
1315 | goto out; | |
1316 | } | |
1317 | ||
b65233a9 JR |
1318 | /**************************************************************************** |
1319 | * | |
1320 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1321 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1322 | * IOMMUs | |
1323 | * | |
1324 | ****************************************************************************/ | |
ae7877de JR |
1325 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1326 | { | |
1327 | return 0; | |
1328 | } | |
1329 | ||
1330 | void __init amd_iommu_detect(void) | |
1331 | { | |
75f1cdf1 | 1332 | if (no_iommu || (iommu_detected && !gart_iommu_aperture)) |
ae7877de JR |
1333 | return; |
1334 | ||
ae7877de JR |
1335 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1336 | iommu_detected = 1; | |
c1cbebee | 1337 | amd_iommu_detected = 1; |
ea1b0d39 | 1338 | x86_init.iommu.iommu_init = amd_iommu_init; |
ae7877de JR |
1339 | } |
1340 | } | |
1341 | ||
b65233a9 JR |
1342 | /**************************************************************************** |
1343 | * | |
1344 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1345 | * options. | |
1346 | * | |
1347 | ****************************************************************************/ | |
1348 | ||
fefda117 JR |
1349 | static int __init parse_amd_iommu_dump(char *str) |
1350 | { | |
1351 | amd_iommu_dump = true; | |
1352 | ||
1353 | return 1; | |
1354 | } | |
1355 | ||
918ad6c5 JR |
1356 | static int __init parse_amd_iommu_options(char *str) |
1357 | { | |
1358 | for (; *str; ++str) { | |
695b5676 | 1359 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 1360 | amd_iommu_unmap_flush = true; |
918ad6c5 JR |
1361 | } |
1362 | ||
1363 | return 1; | |
1364 | } | |
1365 | ||
fefda117 | 1366 | __setup("amd_iommu_dump", parse_amd_iommu_dump); |
918ad6c5 | 1367 | __setup("amd_iommu=", parse_amd_iommu_options); |