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Commit | Line | Data |
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9e60fdcf | 1 | /* |
1e191695 | 2 | * PCA953x 4/8/16/24/40 bit I/O ports |
9e60fdcf | 3 | * |
4 | * Copyright (C) 2005 Ben Gardner <[email protected]> | |
5 | * Copyright (C) 2007 Marvell International Ltd. | |
6 | * | |
7 | * Derived from drivers/i2c/chips/pca9539.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
d120c17f | 16 | #include <linux/gpio.h> |
89ea8bbe | 17 | #include <linux/interrupt.h> |
9e60fdcf | 18 | #include <linux/i2c.h> |
5877457a | 19 | #include <linux/platform_data/pca953x.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
9b8e3ec3 | 21 | #include <asm/unaligned.h> |
1965d303 | 22 | #include <linux/of_platform.h> |
f32517bf | 23 | #include <linux/acpi.h> |
9e60fdcf | 24 | |
33226ffd HZ |
25 | #define PCA953X_INPUT 0 |
26 | #define PCA953X_OUTPUT 1 | |
27 | #define PCA953X_INVERT 2 | |
28 | #define PCA953X_DIRECTION 3 | |
29 | ||
ae79c190 AS |
30 | #define REG_ADDR_AI 0x80 |
31 | ||
33226ffd HZ |
32 | #define PCA957X_IN 0 |
33 | #define PCA957X_INVRT 1 | |
34 | #define PCA957X_BKEN 2 | |
35 | #define PCA957X_PUPD 3 | |
36 | #define PCA957X_CFG 4 | |
37 | #define PCA957X_OUT 5 | |
38 | #define PCA957X_MSK 6 | |
39 | #define PCA957X_INTS 7 | |
40 | ||
44896bea YL |
41 | #define PCAL953X_IN_LATCH 34 |
42 | #define PCAL953X_INT_MASK 37 | |
43 | #define PCAL953X_INT_STAT 38 | |
44 | ||
33226ffd HZ |
45 | #define PCA_GPIO_MASK 0x00FF |
46 | #define PCA_INT 0x0100 | |
44896bea | 47 | #define PCA_PCAL 0x0200 |
33226ffd HZ |
48 | #define PCA953X_TYPE 0x1000 |
49 | #define PCA957X_TYPE 0x2000 | |
c6664149 AS |
50 | #define PCA_TYPE_MASK 0xF000 |
51 | ||
52 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | |
89ea8bbe | 53 | |
3760f736 | 54 | static const struct i2c_device_id pca953x_id[] = { |
89f5df01 | 55 | { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, |
33226ffd HZ |
56 | { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, |
57 | { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, | |
58 | { "pca9536", 4 | PCA953X_TYPE, }, | |
59 | { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, | |
60 | { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, | |
61 | { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, | |
62 | { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, | |
63 | { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, | |
64 | { "pca9556", 8 | PCA953X_TYPE, }, | |
65 | { "pca9557", 8 | PCA953X_TYPE, }, | |
66 | { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, | |
67 | { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, | |
eb32b5aa | 68 | { "pca9698", 40 | PCA953X_TYPE, }, |
33226ffd HZ |
69 | |
70 | { "max7310", 8 | PCA953X_TYPE, }, | |
71 | { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, | |
72 | { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, | |
73 | { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, | |
74 | { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, | |
75 | { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, | |
76 | { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, | |
ae79c190 | 77 | { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, |
2db8aba8 | 78 | { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, |
e73760a6 | 79 | { "xra1202", 8 | PCA953X_TYPE }, |
3760f736 | 80 | { } |
f5e8ff48 | 81 | }; |
3760f736 | 82 | MODULE_DEVICE_TABLE(i2c, pca953x_id); |
9e60fdcf | 83 | |
f32517bf | 84 | static const struct acpi_device_id pca953x_acpi_ids[] = { |
44896bea | 85 | { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, |
f32517bf AS |
86 | { } |
87 | }; | |
88 | MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); | |
89 | ||
f5f0b7aa GC |
90 | #define MAX_BANK 5 |
91 | #define BANK_SZ 8 | |
92 | ||
93 | #define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ) | |
94 | ||
f3dc3630 | 95 | struct pca953x_chip { |
9e60fdcf | 96 | unsigned gpio_start; |
f5f0b7aa GC |
97 | u8 reg_output[MAX_BANK]; |
98 | u8 reg_direction[MAX_BANK]; | |
6e20fb18 | 99 | struct mutex i2c_lock; |
9e60fdcf | 100 | |
89ea8bbe MZ |
101 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
102 | struct mutex irq_lock; | |
f5f0b7aa GC |
103 | u8 irq_mask[MAX_BANK]; |
104 | u8 irq_stat[MAX_BANK]; | |
105 | u8 irq_trig_raise[MAX_BANK]; | |
106 | u8 irq_trig_fall[MAX_BANK]; | |
89ea8bbe MZ |
107 | #endif |
108 | ||
9e60fdcf | 109 | struct i2c_client *client; |
110 | struct gpio_chip gpio_chip; | |
62154991 | 111 | const char *const *names; |
33226ffd | 112 | int chip_type; |
c6664149 | 113 | unsigned long driver_data; |
9e60fdcf | 114 | }; |
115 | ||
f5f0b7aa GC |
116 | static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val, |
117 | int off) | |
118 | { | |
119 | int ret; | |
120 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
121 | int offset = off / BANK_SZ; | |
122 | ||
123 | ret = i2c_smbus_read_byte_data(chip->client, | |
124 | (reg << bank_shift) + offset); | |
125 | *val = ret; | |
126 | ||
127 | if (ret < 0) { | |
128 | dev_err(&chip->client->dev, "failed reading register\n"); | |
129 | return ret; | |
130 | } | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
135 | static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val, | |
136 | int off) | |
137 | { | |
138 | int ret = 0; | |
139 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
140 | int offset = off / BANK_SZ; | |
141 | ||
142 | ret = i2c_smbus_write_byte_data(chip->client, | |
143 | (reg << bank_shift) + offset, val); | |
144 | ||
145 | if (ret < 0) { | |
146 | dev_err(&chip->client->dev, "failed writing register\n"); | |
147 | return ret; | |
148 | } | |
149 | ||
150 | return 0; | |
151 | } | |
152 | ||
153 | static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) | |
9e60fdcf | 154 | { |
33226ffd | 155 | int ret = 0; |
f5e8ff48 GL |
156 | |
157 | if (chip->gpio_chip.ngpio <= 8) | |
f5f0b7aa GC |
158 | ret = i2c_smbus_write_byte_data(chip->client, reg, *val); |
159 | else if (chip->gpio_chip.ngpio >= 24) { | |
160 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
96b70641 | 161 | ret = i2c_smbus_write_i2c_block_data(chip->client, |
f5f0b7aa GC |
162 | (reg << bank_shift) | REG_ADDR_AI, |
163 | NBANK(chip), val); | |
50e44430 | 164 | } else { |
33226ffd HZ |
165 | switch (chip->chip_type) { |
166 | case PCA953X_TYPE: | |
167 | ret = i2c_smbus_write_word_data(chip->client, | |
9b8e3ec3 | 168 | reg << 1, cpu_to_le16(get_unaligned((u16 *)val))); |
33226ffd HZ |
169 | break; |
170 | case PCA957X_TYPE: | |
171 | ret = i2c_smbus_write_byte_data(chip->client, reg << 1, | |
f5f0b7aa | 172 | val[0]); |
33226ffd HZ |
173 | if (ret < 0) |
174 | break; | |
175 | ret = i2c_smbus_write_byte_data(chip->client, | |
176 | (reg << 1) + 1, | |
f5f0b7aa | 177 | val[1]); |
33226ffd HZ |
178 | break; |
179 | } | |
180 | } | |
f5e8ff48 GL |
181 | |
182 | if (ret < 0) { | |
183 | dev_err(&chip->client->dev, "failed writing register\n"); | |
ab5dc372 | 184 | return ret; |
f5e8ff48 GL |
185 | } |
186 | ||
187 | return 0; | |
9e60fdcf | 188 | } |
189 | ||
f5f0b7aa | 190 | static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) |
9e60fdcf | 191 | { |
192 | int ret; | |
193 | ||
96b70641 | 194 | if (chip->gpio_chip.ngpio <= 8) { |
f5e8ff48 | 195 | ret = i2c_smbus_read_byte_data(chip->client, reg); |
96b70641 | 196 | *val = ret; |
f5f0b7aa GC |
197 | } else if (chip->gpio_chip.ngpio >= 24) { |
198 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
199 | ||
96b70641 | 200 | ret = i2c_smbus_read_i2c_block_data(chip->client, |
f5f0b7aa GC |
201 | (reg << bank_shift) | REG_ADDR_AI, |
202 | NBANK(chip), val); | |
96b70641 | 203 | } else { |
f5e8ff48 | 204 | ret = i2c_smbus_read_word_data(chip->client, reg << 1); |
f5f0b7aa GC |
205 | val[0] = (u16)ret & 0xFF; |
206 | val[1] = (u16)ret >> 8; | |
96b70641 | 207 | } |
9e60fdcf | 208 | if (ret < 0) { |
209 | dev_err(&chip->client->dev, "failed reading register\n"); | |
ab5dc372 | 210 | return ret; |
9e60fdcf | 211 | } |
212 | ||
9e60fdcf | 213 | return 0; |
214 | } | |
215 | ||
f3dc3630 | 216 | static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 217 | { |
468e67f6 | 218 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 219 | u8 reg_val; |
33226ffd | 220 | int ret, offset = 0; |
9e60fdcf | 221 | |
6e20fb18 | 222 | mutex_lock(&chip->i2c_lock); |
f5f0b7aa | 223 | reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ)); |
33226ffd HZ |
224 | |
225 | switch (chip->chip_type) { | |
226 | case PCA953X_TYPE: | |
227 | offset = PCA953X_DIRECTION; | |
228 | break; | |
229 | case PCA957X_TYPE: | |
230 | offset = PCA957X_CFG; | |
231 | break; | |
232 | } | |
f5f0b7aa | 233 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 234 | if (ret) |
6e20fb18 | 235 | goto exit; |
9e60fdcf | 236 | |
f5f0b7aa | 237 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
238 | ret = 0; |
239 | exit: | |
240 | mutex_unlock(&chip->i2c_lock); | |
241 | return ret; | |
9e60fdcf | 242 | } |
243 | ||
f3dc3630 | 244 | static int pca953x_gpio_direction_output(struct gpio_chip *gc, |
9e60fdcf | 245 | unsigned off, int val) |
246 | { | |
468e67f6 | 247 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 248 | u8 reg_val; |
33226ffd | 249 | int ret, offset = 0; |
9e60fdcf | 250 | |
6e20fb18 | 251 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 252 | /* set output level */ |
253 | if (val) | |
f5f0b7aa GC |
254 | reg_val = chip->reg_output[off / BANK_SZ] |
255 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 256 | else |
f5f0b7aa GC |
257 | reg_val = chip->reg_output[off / BANK_SZ] |
258 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 259 | |
33226ffd HZ |
260 | switch (chip->chip_type) { |
261 | case PCA953X_TYPE: | |
262 | offset = PCA953X_OUTPUT; | |
263 | break; | |
264 | case PCA957X_TYPE: | |
265 | offset = PCA957X_OUT; | |
266 | break; | |
267 | } | |
f5f0b7aa | 268 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 269 | if (ret) |
6e20fb18 | 270 | goto exit; |
9e60fdcf | 271 | |
f5f0b7aa | 272 | chip->reg_output[off / BANK_SZ] = reg_val; |
9e60fdcf | 273 | |
274 | /* then direction */ | |
f5f0b7aa | 275 | reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ)); |
33226ffd HZ |
276 | switch (chip->chip_type) { |
277 | case PCA953X_TYPE: | |
278 | offset = PCA953X_DIRECTION; | |
279 | break; | |
280 | case PCA957X_TYPE: | |
281 | offset = PCA957X_CFG; | |
282 | break; | |
283 | } | |
f5f0b7aa | 284 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 285 | if (ret) |
6e20fb18 | 286 | goto exit; |
9e60fdcf | 287 | |
f5f0b7aa | 288 | chip->reg_direction[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
289 | ret = 0; |
290 | exit: | |
291 | mutex_unlock(&chip->i2c_lock); | |
292 | return ret; | |
9e60fdcf | 293 | } |
294 | ||
f3dc3630 | 295 | static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) |
9e60fdcf | 296 | { |
468e67f6 | 297 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
ae79c190 | 298 | u32 reg_val; |
33226ffd | 299 | int ret, offset = 0; |
9e60fdcf | 300 | |
6e20fb18 | 301 | mutex_lock(&chip->i2c_lock); |
33226ffd HZ |
302 | switch (chip->chip_type) { |
303 | case PCA953X_TYPE: | |
304 | offset = PCA953X_INPUT; | |
305 | break; | |
306 | case PCA957X_TYPE: | |
307 | offset = PCA957X_IN; | |
308 | break; | |
309 | } | |
f5f0b7aa | 310 | ret = pca953x_read_single(chip, offset, ®_val, off); |
6e20fb18 | 311 | mutex_unlock(&chip->i2c_lock); |
9e60fdcf | 312 | if (ret < 0) { |
313 | /* NOTE: diagnostic already emitted; that's all we should | |
314 | * do unless gpio_*_value_cansleep() calls become different | |
315 | * from their nonsleeping siblings (and report faults). | |
316 | */ | |
317 | return 0; | |
318 | } | |
319 | ||
40a625da | 320 | return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0; |
9e60fdcf | 321 | } |
322 | ||
f3dc3630 | 323 | static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) |
9e60fdcf | 324 | { |
468e67f6 | 325 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa | 326 | u8 reg_val; |
33226ffd | 327 | int ret, offset = 0; |
9e60fdcf | 328 | |
6e20fb18 | 329 | mutex_lock(&chip->i2c_lock); |
9e60fdcf | 330 | if (val) |
f5f0b7aa GC |
331 | reg_val = chip->reg_output[off / BANK_SZ] |
332 | | (1u << (off % BANK_SZ)); | |
9e60fdcf | 333 | else |
f5f0b7aa GC |
334 | reg_val = chip->reg_output[off / BANK_SZ] |
335 | & ~(1u << (off % BANK_SZ)); | |
9e60fdcf | 336 | |
33226ffd HZ |
337 | switch (chip->chip_type) { |
338 | case PCA953X_TYPE: | |
339 | offset = PCA953X_OUTPUT; | |
340 | break; | |
341 | case PCA957X_TYPE: | |
342 | offset = PCA957X_OUT; | |
343 | break; | |
344 | } | |
f5f0b7aa | 345 | ret = pca953x_write_single(chip, offset, reg_val, off); |
9e60fdcf | 346 | if (ret) |
6e20fb18 | 347 | goto exit; |
9e60fdcf | 348 | |
f5f0b7aa | 349 | chip->reg_output[off / BANK_SZ] = reg_val; |
6e20fb18 RS |
350 | exit: |
351 | mutex_unlock(&chip->i2c_lock); | |
9e60fdcf | 352 | } |
353 | ||
b4818afe PR |
354 | |
355 | static void pca953x_gpio_set_multiple(struct gpio_chip *gc, | |
356 | unsigned long *mask, unsigned long *bits) | |
357 | { | |
468e67f6 | 358 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
b4818afe PR |
359 | u8 reg_val[MAX_BANK]; |
360 | int ret, offset = 0; | |
361 | int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); | |
362 | int bank; | |
363 | ||
364 | switch (chip->chip_type) { | |
365 | case PCA953X_TYPE: | |
366 | offset = PCA953X_OUTPUT; | |
367 | break; | |
368 | case PCA957X_TYPE: | |
369 | offset = PCA957X_OUT; | |
370 | break; | |
371 | } | |
372 | ||
373 | memcpy(reg_val, chip->reg_output, NBANK(chip)); | |
374 | mutex_lock(&chip->i2c_lock); | |
375 | for(bank=0; bank<NBANK(chip); bank++) { | |
e0a8604f GU |
376 | unsigned bankmask = mask[bank / sizeof(*mask)] >> |
377 | ((bank % sizeof(*mask)) * 8); | |
b4818afe | 378 | if(bankmask) { |
e0a8604f GU |
379 | unsigned bankval = bits[bank / sizeof(*bits)] >> |
380 | ((bank % sizeof(*bits)) * 8); | |
b4818afe PR |
381 | reg_val[bank] = (reg_val[bank] & ~bankmask) | bankval; |
382 | } | |
383 | } | |
384 | ret = i2c_smbus_write_i2c_block_data(chip->client, offset << bank_shift, NBANK(chip), reg_val); | |
385 | if (ret) | |
386 | goto exit; | |
387 | ||
388 | memcpy(chip->reg_output, reg_val, NBANK(chip)); | |
389 | exit: | |
390 | mutex_unlock(&chip->i2c_lock); | |
391 | } | |
392 | ||
f5e8ff48 | 393 | static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) |
9e60fdcf | 394 | { |
395 | struct gpio_chip *gc; | |
396 | ||
397 | gc = &chip->gpio_chip; | |
398 | ||
f3dc3630 GL |
399 | gc->direction_input = pca953x_gpio_direction_input; |
400 | gc->direction_output = pca953x_gpio_direction_output; | |
401 | gc->get = pca953x_gpio_get_value; | |
402 | gc->set = pca953x_gpio_set_value; | |
b4818afe | 403 | gc->set_multiple = pca953x_gpio_set_multiple; |
9fb1f39e | 404 | gc->can_sleep = true; |
9e60fdcf | 405 | |
406 | gc->base = chip->gpio_start; | |
f5e8ff48 GL |
407 | gc->ngpio = gpios; |
408 | gc->label = chip->client->name; | |
58383c78 | 409 | gc->parent = &chip->client->dev; |
d72cbed0 | 410 | gc->owner = THIS_MODULE; |
77906a54 | 411 | gc->names = chip->names; |
9e60fdcf | 412 | } |
413 | ||
89ea8bbe | 414 | #ifdef CONFIG_GPIO_PCA953X_IRQ |
6f5cfc0e | 415 | static void pca953x_irq_mask(struct irq_data *d) |
89ea8bbe | 416 | { |
7bcbce55 | 417 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 418 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 419 | |
f5f0b7aa | 420 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); |
89ea8bbe MZ |
421 | } |
422 | ||
6f5cfc0e | 423 | static void pca953x_irq_unmask(struct irq_data *d) |
89ea8bbe | 424 | { |
7bcbce55 | 425 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 426 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe | 427 | |
f5f0b7aa | 428 | chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); |
89ea8bbe MZ |
429 | } |
430 | ||
6f5cfc0e | 431 | static void pca953x_irq_bus_lock(struct irq_data *d) |
89ea8bbe | 432 | { |
7bcbce55 | 433 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 434 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
89ea8bbe MZ |
435 | |
436 | mutex_lock(&chip->irq_lock); | |
437 | } | |
438 | ||
6f5cfc0e | 439 | static void pca953x_irq_bus_sync_unlock(struct irq_data *d) |
89ea8bbe | 440 | { |
7bcbce55 | 441 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 442 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
443 | u8 new_irqs; |
444 | int level, i; | |
44896bea YL |
445 | u8 invert_irq_mask[MAX_BANK]; |
446 | ||
447 | if (chip->driver_data & PCA_PCAL) { | |
448 | /* Enable latch on interrupt-enabled inputs */ | |
449 | pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); | |
450 | ||
451 | for (i = 0; i < NBANK(chip); i++) | |
452 | invert_irq_mask[i] = ~chip->irq_mask[i]; | |
453 | ||
454 | /* Unmask enabled interrupts */ | |
455 | pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask); | |
456 | } | |
a2cb9aeb MZ |
457 | |
458 | /* Look for any newly setup interrupt */ | |
f5f0b7aa GC |
459 | for (i = 0; i < NBANK(chip); i++) { |
460 | new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i]; | |
461 | new_irqs &= ~chip->reg_direction[i]; | |
462 | ||
463 | while (new_irqs) { | |
464 | level = __ffs(new_irqs); | |
465 | pca953x_gpio_direction_input(&chip->gpio_chip, | |
466 | level + (BANK_SZ * i)); | |
467 | new_irqs &= ~(1 << level); | |
468 | } | |
a2cb9aeb | 469 | } |
89ea8bbe MZ |
470 | |
471 | mutex_unlock(&chip->irq_lock); | |
472 | } | |
473 | ||
6f5cfc0e | 474 | static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) |
89ea8bbe | 475 | { |
7bcbce55 | 476 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
468e67f6 | 477 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
f5f0b7aa GC |
478 | int bank_nb = d->hwirq / BANK_SZ; |
479 | u8 mask = 1 << (d->hwirq % BANK_SZ); | |
89ea8bbe MZ |
480 | |
481 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | |
482 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | |
6f5cfc0e | 483 | d->irq, type); |
89ea8bbe MZ |
484 | return -EINVAL; |
485 | } | |
486 | ||
487 | if (type & IRQ_TYPE_EDGE_FALLING) | |
f5f0b7aa | 488 | chip->irq_trig_fall[bank_nb] |= mask; |
89ea8bbe | 489 | else |
f5f0b7aa | 490 | chip->irq_trig_fall[bank_nb] &= ~mask; |
89ea8bbe MZ |
491 | |
492 | if (type & IRQ_TYPE_EDGE_RISING) | |
f5f0b7aa | 493 | chip->irq_trig_raise[bank_nb] |= mask; |
89ea8bbe | 494 | else |
f5f0b7aa | 495 | chip->irq_trig_raise[bank_nb] &= ~mask; |
89ea8bbe | 496 | |
a2cb9aeb | 497 | return 0; |
89ea8bbe MZ |
498 | } |
499 | ||
500 | static struct irq_chip pca953x_irq_chip = { | |
501 | .name = "pca953x", | |
6f5cfc0e LB |
502 | .irq_mask = pca953x_irq_mask, |
503 | .irq_unmask = pca953x_irq_unmask, | |
504 | .irq_bus_lock = pca953x_irq_bus_lock, | |
505 | .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, | |
506 | .irq_set_type = pca953x_irq_set_type, | |
89ea8bbe MZ |
507 | }; |
508 | ||
b6ac1280 | 509 | static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending) |
89ea8bbe | 510 | { |
f5f0b7aa GC |
511 | u8 cur_stat[MAX_BANK]; |
512 | u8 old_stat[MAX_BANK]; | |
b6ac1280 JS |
513 | bool pending_seen = false; |
514 | bool trigger_seen = false; | |
515 | u8 trigger[MAX_BANK]; | |
f5f0b7aa | 516 | int ret, i, offset = 0; |
33226ffd | 517 | |
44896bea YL |
518 | if (chip->driver_data & PCA_PCAL) { |
519 | /* Read the current interrupt status from the device */ | |
520 | ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); | |
521 | if (ret) | |
522 | return false; | |
523 | ||
524 | /* Check latched inputs and clear interrupt status */ | |
525 | ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat); | |
526 | if (ret) | |
527 | return false; | |
528 | ||
529 | for (i = 0; i < NBANK(chip); i++) { | |
530 | /* Apply filter for rising/falling edge selection */ | |
531 | pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) | | |
532 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
533 | pending[i] &= trigger[i]; | |
534 | if (pending[i]) | |
535 | pending_seen = true; | |
536 | } | |
537 | ||
538 | return pending_seen; | |
539 | } | |
540 | ||
33226ffd HZ |
541 | switch (chip->chip_type) { |
542 | case PCA953X_TYPE: | |
543 | offset = PCA953X_INPUT; | |
544 | break; | |
545 | case PCA957X_TYPE: | |
546 | offset = PCA957X_IN; | |
547 | break; | |
548 | } | |
f5f0b7aa | 549 | ret = pca953x_read_regs(chip, offset, cur_stat); |
89ea8bbe | 550 | if (ret) |
b6ac1280 | 551 | return false; |
89ea8bbe MZ |
552 | |
553 | /* Remove output pins from the equation */ | |
f5f0b7aa GC |
554 | for (i = 0; i < NBANK(chip); i++) |
555 | cur_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe | 556 | |
f5f0b7aa | 557 | memcpy(old_stat, chip->irq_stat, NBANK(chip)); |
89ea8bbe | 558 | |
f5f0b7aa GC |
559 | for (i = 0; i < NBANK(chip); i++) { |
560 | trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i]; | |
b6ac1280 JS |
561 | if (trigger[i]) |
562 | trigger_seen = true; | |
f5f0b7aa GC |
563 | } |
564 | ||
b6ac1280 JS |
565 | if (!trigger_seen) |
566 | return false; | |
89ea8bbe | 567 | |
f5f0b7aa | 568 | memcpy(chip->irq_stat, cur_stat, NBANK(chip)); |
89ea8bbe | 569 | |
f5f0b7aa GC |
570 | for (i = 0; i < NBANK(chip); i++) { |
571 | pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) | | |
572 | (cur_stat[i] & chip->irq_trig_raise[i]); | |
573 | pending[i] &= trigger[i]; | |
b6ac1280 JS |
574 | if (pending[i]) |
575 | pending_seen = true; | |
f5f0b7aa | 576 | } |
89ea8bbe | 577 | |
b6ac1280 | 578 | return pending_seen; |
89ea8bbe MZ |
579 | } |
580 | ||
581 | static irqreturn_t pca953x_irq_handler(int irq, void *devid) | |
582 | { | |
583 | struct pca953x_chip *chip = devid; | |
f5f0b7aa GC |
584 | u8 pending[MAX_BANK]; |
585 | u8 level; | |
3275d072 | 586 | unsigned nhandled = 0; |
f5f0b7aa | 587 | int i; |
89ea8bbe | 588 | |
f5f0b7aa | 589 | if (!pca953x_irq_pending(chip, pending)) |
3275d072 | 590 | return IRQ_NONE; |
89ea8bbe | 591 | |
f5f0b7aa GC |
592 | for (i = 0; i < NBANK(chip); i++) { |
593 | while (pending[i]) { | |
594 | level = __ffs(pending[i]); | |
7bcbce55 | 595 | handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain, |
f5f0b7aa GC |
596 | level + (BANK_SZ * i))); |
597 | pending[i] &= ~(1 << level); | |
3275d072 | 598 | nhandled++; |
f5f0b7aa GC |
599 | } |
600 | } | |
89ea8bbe | 601 | |
3275d072 | 602 | return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE; |
89ea8bbe MZ |
603 | } |
604 | ||
605 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 606 | int irq_base) |
89ea8bbe MZ |
607 | { |
608 | struct i2c_client *client = chip->client; | |
f5f0b7aa | 609 | int ret, i, offset = 0; |
89ea8bbe | 610 | |
4bb93349 | 611 | if (client->irq && irq_base != -1 |
c6664149 | 612 | && (chip->driver_data & PCA_INT)) { |
89ea8bbe | 613 | |
33226ffd HZ |
614 | switch (chip->chip_type) { |
615 | case PCA953X_TYPE: | |
616 | offset = PCA953X_INPUT; | |
617 | break; | |
618 | case PCA957X_TYPE: | |
619 | offset = PCA957X_IN; | |
620 | break; | |
621 | } | |
f5f0b7aa | 622 | ret = pca953x_read_regs(chip, offset, chip->irq_stat); |
89ea8bbe | 623 | if (ret) |
b42748c9 | 624 | return ret; |
89ea8bbe MZ |
625 | |
626 | /* | |
627 | * There is no way to know which GPIO line generated the | |
628 | * interrupt. We have to rely on the previous read for | |
629 | * this purpose. | |
630 | */ | |
f5f0b7aa GC |
631 | for (i = 0; i < NBANK(chip); i++) |
632 | chip->irq_stat[i] &= chip->reg_direction[i]; | |
89ea8bbe MZ |
633 | mutex_init(&chip->irq_lock); |
634 | ||
b42748c9 LW |
635 | ret = devm_request_threaded_irq(&client->dev, |
636 | client->irq, | |
89ea8bbe MZ |
637 | NULL, |
638 | pca953x_irq_handler, | |
91329132 TS |
639 | IRQF_TRIGGER_LOW | IRQF_ONESHOT | |
640 | IRQF_SHARED, | |
89ea8bbe MZ |
641 | dev_name(&client->dev), chip); |
642 | if (ret) { | |
643 | dev_err(&client->dev, "failed to request irq %d\n", | |
644 | client->irq); | |
0e8f2fda | 645 | return ret; |
89ea8bbe MZ |
646 | } |
647 | ||
7bcbce55 LW |
648 | ret = gpiochip_irqchip_add(&chip->gpio_chip, |
649 | &pca953x_irq_chip, | |
650 | irq_base, | |
651 | handle_simple_irq, | |
652 | IRQ_TYPE_NONE); | |
653 | if (ret) { | |
654 | dev_err(&client->dev, | |
655 | "could not connect irqchip to gpiochip\n"); | |
656 | return ret; | |
657 | } | |
fdd50409 GS |
658 | |
659 | gpiochip_set_chained_irqchip(&chip->gpio_chip, | |
660 | &pca953x_irq_chip, | |
661 | client->irq, NULL); | |
89ea8bbe MZ |
662 | } |
663 | ||
664 | return 0; | |
89ea8bbe MZ |
665 | } |
666 | ||
89ea8bbe MZ |
667 | #else /* CONFIG_GPIO_PCA953X_IRQ */ |
668 | static int pca953x_irq_setup(struct pca953x_chip *chip, | |
c6dcf592 | 669 | int irq_base) |
89ea8bbe MZ |
670 | { |
671 | struct i2c_client *client = chip->client; | |
89ea8bbe | 672 | |
c6664149 | 673 | if (irq_base != -1 && (chip->driver_data & PCA_INT)) |
89ea8bbe MZ |
674 | dev_warn(&client->dev, "interrupt support not compiled in\n"); |
675 | ||
676 | return 0; | |
677 | } | |
89ea8bbe MZ |
678 | #endif |
679 | ||
3836309d | 680 | static int device_pca953x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
681 | { |
682 | int ret; | |
f5f0b7aa | 683 | u8 val[MAX_BANK]; |
33226ffd | 684 | |
f5f0b7aa | 685 | ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output); |
33226ffd HZ |
686 | if (ret) |
687 | goto out; | |
688 | ||
f5f0b7aa GC |
689 | ret = pca953x_read_regs(chip, PCA953X_DIRECTION, |
690 | chip->reg_direction); | |
33226ffd HZ |
691 | if (ret) |
692 | goto out; | |
693 | ||
694 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
695 | if (invert) |
696 | memset(val, 0xFF, NBANK(chip)); | |
697 | else | |
698 | memset(val, 0, NBANK(chip)); | |
699 | ||
700 | ret = pca953x_write_regs(chip, PCA953X_INVERT, val); | |
33226ffd HZ |
701 | out: |
702 | return ret; | |
703 | } | |
704 | ||
3836309d | 705 | static int device_pca957x_init(struct pca953x_chip *chip, u32 invert) |
33226ffd HZ |
706 | { |
707 | int ret; | |
f5f0b7aa | 708 | u8 val[MAX_BANK]; |
33226ffd | 709 | |
f5f0b7aa | 710 | ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output); |
33226ffd HZ |
711 | if (ret) |
712 | goto out; | |
f5f0b7aa | 713 | ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction); |
33226ffd HZ |
714 | if (ret) |
715 | goto out; | |
716 | ||
717 | /* set platform specific polarity inversion */ | |
f5f0b7aa GC |
718 | if (invert) |
719 | memset(val, 0xFF, NBANK(chip)); | |
720 | else | |
721 | memset(val, 0, NBANK(chip)); | |
c75a3772 NK |
722 | ret = pca953x_write_regs(chip, PCA957X_INVRT, val); |
723 | if (ret) | |
724 | goto out; | |
33226ffd | 725 | |
20a8a968 | 726 | /* To enable register 6, 7 to control pull up and pull down */ |
f5f0b7aa | 727 | memset(val, 0x02, NBANK(chip)); |
c75a3772 NK |
728 | ret = pca953x_write_regs(chip, PCA957X_BKEN, val); |
729 | if (ret) | |
730 | goto out; | |
33226ffd HZ |
731 | |
732 | return 0; | |
733 | out: | |
734 | return ret; | |
735 | } | |
736 | ||
6f29c9af BD |
737 | static const struct of_device_id pca953x_dt_ids[]; |
738 | ||
3836309d | 739 | static int pca953x_probe(struct i2c_client *client, |
3760f736 | 740 | const struct i2c_device_id *id) |
9e60fdcf | 741 | { |
f3dc3630 GL |
742 | struct pca953x_platform_data *pdata; |
743 | struct pca953x_chip *chip; | |
6a7b36aa | 744 | int irq_base = 0; |
7ea2aa20 | 745 | int ret; |
6a7b36aa | 746 | u32 invert = 0; |
9e60fdcf | 747 | |
b42748c9 LW |
748 | chip = devm_kzalloc(&client->dev, |
749 | sizeof(struct pca953x_chip), GFP_KERNEL); | |
1965d303 NC |
750 | if (chip == NULL) |
751 | return -ENOMEM; | |
752 | ||
e56aee18 | 753 | pdata = dev_get_platdata(&client->dev); |
c6dcf592 DJ |
754 | if (pdata) { |
755 | irq_base = pdata->irq_base; | |
756 | chip->gpio_start = pdata->gpio_base; | |
757 | invert = pdata->invert; | |
758 | chip->names = pdata->names; | |
759 | } else { | |
4bb93349 MSP |
760 | chip->gpio_start = -1; |
761 | irq_base = 0; | |
1965d303 | 762 | } |
9e60fdcf | 763 | |
764 | chip->client = client; | |
765 | ||
f32517bf AS |
766 | if (id) { |
767 | chip->driver_data = id->driver_data; | |
768 | } else { | |
769 | const struct acpi_device_id *id; | |
6f29c9af | 770 | const struct of_device_id *match; |
f32517bf | 771 | |
6f29c9af BD |
772 | match = of_match_device(pca953x_dt_ids, &client->dev); |
773 | if (match) { | |
774 | chip->driver_data = (int)(uintptr_t)match->data; | |
775 | } else { | |
776 | id = acpi_match_device(pca953x_acpi_ids, &client->dev); | |
777 | if (!id) | |
778 | return -ENODEV; | |
f32517bf | 779 | |
6f29c9af BD |
780 | chip->driver_data = id->driver_data; |
781 | } | |
f32517bf AS |
782 | } |
783 | ||
c6664149 | 784 | chip->chip_type = PCA_CHIP_TYPE(chip->driver_data); |
77906a54 | 785 | |
6e20fb18 RS |
786 | mutex_init(&chip->i2c_lock); |
787 | ||
9e60fdcf | 788 | /* initialize cached registers from their original values. |
789 | * we can't share this chip with another i2c master. | |
790 | */ | |
c6664149 | 791 | pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); |
f5e8ff48 | 792 | |
33226ffd | 793 | if (chip->chip_type == PCA953X_TYPE) |
7ea2aa20 | 794 | ret = device_pca953x_init(chip, invert); |
33226ffd | 795 | else |
7ea2aa20 WS |
796 | ret = device_pca957x_init(chip, invert); |
797 | if (ret) | |
b42748c9 | 798 | return ret; |
9e60fdcf | 799 | |
0ece84f5 | 800 | ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip); |
89ea8bbe | 801 | if (ret) |
b42748c9 | 802 | return ret; |
f5e8ff48 | 803 | |
c6664149 | 804 | ret = pca953x_irq_setup(chip, irq_base); |
9e60fdcf | 805 | if (ret) |
b42748c9 | 806 | return ret; |
9e60fdcf | 807 | |
c6dcf592 | 808 | if (pdata && pdata->setup) { |
9e60fdcf | 809 | ret = pdata->setup(client, chip->gpio_chip.base, |
810 | chip->gpio_chip.ngpio, pdata->context); | |
811 | if (ret < 0) | |
812 | dev_warn(&client->dev, "setup failed, %d\n", ret); | |
813 | } | |
814 | ||
815 | i2c_set_clientdata(client, chip); | |
816 | return 0; | |
9e60fdcf | 817 | } |
818 | ||
f3dc3630 | 819 | static int pca953x_remove(struct i2c_client *client) |
9e60fdcf | 820 | { |
e56aee18 | 821 | struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev); |
f3dc3630 | 822 | struct pca953x_chip *chip = i2c_get_clientdata(client); |
9e60fdcf | 823 | int ret = 0; |
824 | ||
c6dcf592 | 825 | if (pdata && pdata->teardown) { |
9e60fdcf | 826 | ret = pdata->teardown(client, chip->gpio_chip.base, |
827 | chip->gpio_chip.ngpio, pdata->context); | |
828 | if (ret < 0) { | |
829 | dev_err(&client->dev, "%s failed, %d\n", | |
830 | "teardown", ret); | |
831 | return ret; | |
832 | } | |
833 | } | |
834 | ||
9e60fdcf | 835 | return 0; |
836 | } | |
837 | ||
6f29c9af BD |
838 | /* convenience to stop overlong match-table lines */ |
839 | #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) | |
840 | #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) | |
841 | ||
ed32620e | 842 | static const struct of_device_id pca953x_dt_ids[] = { |
6f29c9af BD |
843 | { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, |
844 | { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, | |
845 | { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, | |
846 | { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, | |
847 | { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, | |
848 | { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, | |
849 | { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, | |
850 | { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, | |
851 | { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, | |
852 | { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, | |
853 | { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, | |
854 | { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, | |
855 | { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, | |
856 | { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, | |
857 | ||
858 | { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, | |
859 | { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, | |
860 | { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, | |
861 | { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, | |
862 | ||
863 | { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, | |
864 | { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, | |
865 | { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, | |
866 | { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, | |
867 | ||
868 | { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), }, | |
869 | ||
870 | { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, | |
ed32620e MR |
871 | { } |
872 | }; | |
873 | ||
874 | MODULE_DEVICE_TABLE(of, pca953x_dt_ids); | |
875 | ||
f3dc3630 | 876 | static struct i2c_driver pca953x_driver = { |
9e60fdcf | 877 | .driver = { |
f3dc3630 | 878 | .name = "pca953x", |
ed32620e | 879 | .of_match_table = pca953x_dt_ids, |
f32517bf | 880 | .acpi_match_table = ACPI_PTR(pca953x_acpi_ids), |
9e60fdcf | 881 | }, |
f3dc3630 GL |
882 | .probe = pca953x_probe, |
883 | .remove = pca953x_remove, | |
3760f736 | 884 | .id_table = pca953x_id, |
9e60fdcf | 885 | }; |
886 | ||
f3dc3630 | 887 | static int __init pca953x_init(void) |
9e60fdcf | 888 | { |
f3dc3630 | 889 | return i2c_add_driver(&pca953x_driver); |
9e60fdcf | 890 | } |
2f8d1197 DB |
891 | /* register after i2c postcore initcall and before |
892 | * subsys initcalls that may rely on these GPIOs | |
893 | */ | |
894 | subsys_initcall(pca953x_init); | |
9e60fdcf | 895 | |
f3dc3630 | 896 | static void __exit pca953x_exit(void) |
9e60fdcf | 897 | { |
f3dc3630 | 898 | i2c_del_driver(&pca953x_driver); |
9e60fdcf | 899 | } |
f3dc3630 | 900 | module_exit(pca953x_exit); |
9e60fdcf | 901 | |
902 | MODULE_AUTHOR("eric miao <[email protected]>"); | |
f3dc3630 | 903 | MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); |
9e60fdcf | 904 | MODULE_LICENSE("GPL"); |