[linux.git] / drivers / ptp / ptp_pch.c

/*
 * PTP 1588 clock using the EG20T PCH
 *
 * Copyright (C) 2010 OMICRON electronics GmbH
 * Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
 *
 * This code was derived from the IXP46X driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
 */

#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/slab.h>

#define STATION_ADDR_LEN	20
#define PCI_DEVICE_ID_PCH_1588	0x8819
#define IO_MEM_BAR 1

#define DEFAULT_ADDEND 0xA0000000
#define TICKS_NS_SHIFT  5
#define N_EXT_TS	2

enum pch_status {
	PCH_SUCCESS,
	PCH_INVALIDPARAM,
	PCH_NOTIMESTAMP,
	PCH_INTERRUPTMODEINUSE,
	PCH_FAILED,
	PCH_UNSUPPORTED,
};
/**
 * struct pch_ts_regs - IEEE 1588 registers
 */
struct pch_ts_regs {
	u32 control;
	u32 event;
	u32 addend;
	u32 accum;
	u32 test;
	u32 ts_compare;
	u32 rsystime_lo;
	u32 rsystime_hi;
	u32 systime_lo;
	u32 systime_hi;
	u32 trgt_lo;
	u32 trgt_hi;
	u32 asms_lo;
	u32 asms_hi;
	u32 amms_lo;
	u32 amms_hi;
	u32 ch_control;
	u32 ch_event;
	u32 tx_snap_lo;
	u32 tx_snap_hi;
	u32 rx_snap_lo;
	u32 rx_snap_hi;
	u32 src_uuid_lo;
	u32 src_uuid_hi;
	u32 can_status;
	u32 can_snap_lo;
	u32 can_snap_hi;
	u32 ts_sel;
	u32 ts_st[6];
	u32 reserve1[14];
	u32 stl_max_set_en;
	u32 stl_max_set;
	u32 reserve2[13];
	u32 srst;
};

#define PCH_TSC_RESET		(1 << 0)
#define PCH_TSC_TTM_MASK	(1 << 1)
#define PCH_TSC_ASMS_MASK	(1 << 2)
#define PCH_TSC_AMMS_MASK	(1 << 3)
#define PCH_TSC_PPSM_MASK	(1 << 4)
#define PCH_TSE_TTIPEND		(1 << 1)
#define PCH_TSE_SNS		(1 << 2)
#define PCH_TSE_SNM		(1 << 3)
#define PCH_TSE_PPS		(1 << 4)
#define PCH_CC_MM		(1 << 0)
#define PCH_CC_TA		(1 << 1)

#define PCH_CC_MODE_SHIFT	16
#define PCH_CC_MODE_MASK	0x001F0000
#define PCH_CC_VERSION		(1 << 31)
#define PCH_CE_TXS		(1 << 0)
#define PCH_CE_RXS		(1 << 1)
#define PCH_CE_OVR		(1 << 0)
#define PCH_CE_VAL		(1 << 1)
#define PCH_ECS_ETH		(1 << 0)

#define PCH_ECS_CAN		(1 << 1)
#define PCH_STATION_BYTES	6

#define PCH_IEEE1588_ETH	(1 << 0)
#define PCH_IEEE1588_CAN	(1 << 1)
/**
 * struct pch_dev - Driver private data
 */
struct pch_dev {
	struct pch_ts_regs __iomem *regs;
	struct ptp_clock *ptp_clock;
	struct ptp_clock_info caps;
	int exts0_enabled;
	int exts1_enabled;

	u32 mem_base;
	u32 mem_size;
	u32 irq;
	struct pci_dev *pdev;
	spinlock_t register_lock;
};

/**
 * struct pch_params - 1588 module parameter
 */
struct pch_params {
	u8 station[STATION_ADDR_LEN];
};

/* structure to hold the module parameters */
static struct pch_params pch_param = {
	"00:00:00:00:00:00"
};

/*
 * Register access functions
 */
static inline void pch_eth_enable_set(struct pch_dev *chip)
{
	u32 val;
	/* SET the eth_enable bit */
	val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH);
	iowrite32(val, (&chip->regs->ts_sel));
}

static u64 pch_systime_read(struct pch_ts_regs __iomem *regs)
{
	u64 ns;
	u32 lo, hi;

	lo = ioread32(&regs->systime_lo);
	hi = ioread32(&regs->systime_hi);

	ns = ((u64) hi) << 32;
	ns |= lo;
	ns <<= TICKS_NS_SHIFT;

	return ns;
}

static void pch_systime_write(struct pch_ts_regs __iomem *regs, u64 ns)
{
	u32 hi, lo;

	ns >>= TICKS_NS_SHIFT;
	hi = ns >> 32;
	lo = ns & 0xffffffff;

	iowrite32(lo, &regs->systime_lo);
	iowrite32(hi, &regs->systime_hi);
}

static inline void pch_block_reset(struct pch_dev *chip)
{
	u32 val;
	/* Reset Hardware Assist block */
	val = ioread32(&chip->regs->control) | PCH_TSC_RESET;
	iowrite32(val, (&chip->regs->control));
	val = val & ~PCH_TSC_RESET;
	iowrite32(val, (&chip->regs->control));
}

u32 pch_ch_control_read(struct pci_dev *pdev)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);
	u32 val;

	val = ioread32(&chip->regs->ch_control);

	return val;
}
EXPORT_SYMBOL(pch_ch_control_read);

void pch_ch_control_write(struct pci_dev *pdev, u32 val)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);

	iowrite32(val, (&chip->regs->ch_control));
}
EXPORT_SYMBOL(pch_ch_control_write);

u32 pch_ch_event_read(struct pci_dev *pdev)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);
	u32 val;

	val = ioread32(&chip->regs->ch_event);

	return val;
}
EXPORT_SYMBOL(pch_ch_event_read);

void pch_ch_event_write(struct pci_dev *pdev, u32 val)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);

	iowrite32(val, (&chip->regs->ch_event));
}
EXPORT_SYMBOL(pch_ch_event_write);

u32 pch_src_uuid_lo_read(struct pci_dev *pdev)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);
	u32 val;

	val = ioread32(&chip->regs->src_uuid_lo);

	return val;
}
EXPORT_SYMBOL(pch_src_uuid_lo_read);

u32 pch_src_uuid_hi_read(struct pci_dev *pdev)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);
	u32 val;

	val = ioread32(&chip->regs->src_uuid_hi);

	return val;
}
EXPORT_SYMBOL(pch_src_uuid_hi_read);

u64 pch_rx_snap_read(struct pci_dev *pdev)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);
	u64 ns;
	u32 lo, hi;

	lo = ioread32(&chip->regs->rx_snap_lo);
	hi = ioread32(&chip->regs->rx_snap_hi);

	ns = ((u64) hi) << 32;
	ns |= lo;
	ns <<= TICKS_NS_SHIFT;

	return ns;
}
EXPORT_SYMBOL(pch_rx_snap_read);

u64 pch_tx_snap_read(struct pci_dev *pdev)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);
	u64 ns;
	u32 lo, hi;

	lo = ioread32(&chip->regs->tx_snap_lo);
	hi = ioread32(&chip->regs->tx_snap_hi);

	ns = ((u64) hi) << 32;
	ns |= lo;
	ns <<= TICKS_NS_SHIFT;

	return ns;
}
EXPORT_SYMBOL(pch_tx_snap_read);

/* This function enables all 64 bits in system time registers [high & low].
This is a work-around for non continuous value in the SystemTime Register*/
static void pch_set_system_time_count(struct pch_dev *chip)
{
	iowrite32(0x01, &chip->regs->stl_max_set_en);
	iowrite32(0xFFFFFFFF, &chip->regs->stl_max_set);
	iowrite32(0x00, &chip->regs->stl_max_set_en);
}

static void pch_reset(struct pch_dev *chip)
{
	/* Reset Hardware Assist */
	pch_block_reset(chip);

	/* enable all 32 bits in system time registers */
	pch_set_system_time_count(chip);
}

/**
 * pch_set_station_address() - This API sets the station address used by
 *				    IEEE 1588 hardware when looking at PTP
 *				    traffic on the  ethernet interface
 * @addr:	dress which contain the column separated address to be used.
 */
int pch_set_station_address(u8 *addr, struct pci_dev *pdev)
{
	s32 i;
	struct pch_dev *chip = pci_get_drvdata(pdev);

	/* Verify the parameter */
	if ((chip->regs == NULL) || addr == (u8 *)NULL) {
		dev_err(&pdev->dev,
			"invalid params returning PCH_INVALIDPARAM\n");
		return PCH_INVALIDPARAM;
	}
	/* For all station address bytes */
	for (i = 0; i < PCH_STATION_BYTES; i++) {
		u32 val;
		s32 tmp;

		tmp = hex_to_bin(addr[i * 3]);
		if (tmp < 0) {
			dev_err(&pdev->dev,
				"invalid params returning PCH_INVALIDPARAM\n");
			return PCH_INVALIDPARAM;
		}
		val = tmp * 16;
		tmp = hex_to_bin(addr[(i * 3) + 1]);
		if (tmp < 0) {
			dev_err(&pdev->dev,
				"invalid params returning PCH_INVALIDPARAM\n");
			return PCH_INVALIDPARAM;
		}
		val += tmp;
		/* Expects ':' separated addresses */
		if ((i < 5) && (addr[(i * 3) + 2] != ':')) {
			dev_err(&pdev->dev,
				"invalid params returning PCH_INVALIDPARAM\n");
			return PCH_INVALIDPARAM;
		}

		/* Ideally we should set the address only after validating
							 entire string */
		dev_dbg(&pdev->dev, "invoking pch_station_set\n");
		iowrite32(val, &chip->regs->ts_st[i]);
	}
	return 0;
}
EXPORT_SYMBOL(pch_set_station_address);

/*
 * Interrupt service routine
 */
static irqreturn_t isr(int irq, void *priv)
{
	struct pch_dev *pch_dev = priv;
	struct pch_ts_regs __iomem *regs = pch_dev->regs;
	struct ptp_clock_event event;
	u32 ack = 0, lo, hi, val;

	val = ioread32(&regs->event);

	if (val & PCH_TSE_SNS) {
		ack |= PCH_TSE_SNS;
		if (pch_dev->exts0_enabled) {
			hi = ioread32(&regs->asms_hi);
			lo = ioread32(&regs->asms_lo);
			event.type = PTP_CLOCK_EXTTS;
			event.index = 0;
			event.timestamp = ((u64) hi) << 32;
			event.timestamp |= lo;
			event.timestamp <<= TICKS_NS_SHIFT;
			ptp_clock_event(pch_dev->ptp_clock, &event);
		}
	}

	if (val & PCH_TSE_SNM) {
		ack |= PCH_TSE_SNM;
		if (pch_dev->exts1_enabled) {
			hi = ioread32(&regs->amms_hi);
			lo = ioread32(&regs->amms_lo);
			event.type = PTP_CLOCK_EXTTS;
			event.index = 1;
			event.timestamp = ((u64) hi) << 32;
			event.timestamp |= lo;
			event.timestamp <<= TICKS_NS_SHIFT;
			ptp_clock_event(pch_dev->ptp_clock, &event);
		}
	}

	if (val & PCH_TSE_TTIPEND)
		ack |= PCH_TSE_TTIPEND; /* this bit seems to be always set */

	if (ack) {
		iowrite32(ack, &regs->event);
		return IRQ_HANDLED;
	} else
		return IRQ_NONE;
}

/*
 * PTP clock operations
 */

static int ptp_pch_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
{
	u64 adj;
	u32 diff, addend;
	int neg_adj = 0;
	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
	struct pch_ts_regs __iomem *regs = pch_dev->regs;

	if (ppb < 0) {
		neg_adj = 1;
		ppb = -ppb;
	}
	addend = DEFAULT_ADDEND;
	adj = addend;
	adj *= ppb;
	diff = div_u64(adj, 1000000000ULL);

	addend = neg_adj ? addend - diff : addend + diff;

	iowrite32(addend, &regs->addend);

	return 0;
}

static int ptp_pch_adjtime(struct ptp_clock_info *ptp, s64 delta)
{
	s64 now;
	unsigned long flags;
	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
	struct pch_ts_regs __iomem *regs = pch_dev->regs;

	spin_lock_irqsave(&pch_dev->register_lock, flags);
	now = pch_systime_read(regs);
	now += delta;
	pch_systime_write(regs, now);
	spin_unlock_irqrestore(&pch_dev->register_lock, flags);

	return 0;
}

static int ptp_pch_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
{
	u64 ns;
	u32 remainder;
	unsigned long flags;
	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
	struct pch_ts_regs __iomem *regs = pch_dev->regs;

	spin_lock_irqsave(&pch_dev->register_lock, flags);
	ns = pch_systime_read(regs);
	spin_unlock_irqrestore(&pch_dev->register_lock, flags);

	ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
	ts->tv_nsec = remainder;
	return 0;
}

static int ptp_pch_settime(struct ptp_clock_info *ptp,
			   const struct timespec64 *ts)
{
	u64 ns;
	unsigned long flags;
	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
	struct pch_ts_regs __iomem *regs = pch_dev->regs;

	ns = ts->tv_sec * 1000000000ULL;
	ns += ts->tv_nsec;

	spin_lock_irqsave(&pch_dev->register_lock, flags);
	pch_systime_write(regs, ns);
	spin_unlock_irqrestore(&pch_dev->register_lock, flags);

	return 0;
}

static int ptp_pch_enable(struct ptp_clock_info *ptp,
			  struct ptp_clock_request *rq, int on)
{
	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);

	switch (rq->type) {
	case PTP_CLK_REQ_EXTTS:
		switch (rq->extts.index) {
		case 0:
			pch_dev->exts0_enabled = on ? 1 : 0;
			break;
		case 1:
			pch_dev->exts1_enabled = on ? 1 : 0;
			break;
		default:
			return -EINVAL;
		}
		return 0;
	default:
		break;
	}

	return -EOPNOTSUPP;
}

static struct ptp_clock_info ptp_pch_caps = {
	.owner		= THIS_MODULE,
	.name		= "PCH timer",
	.max_adj	= 50000000,
	.n_ext_ts	= N_EXT_TS,
	.n_pins		= 0,
	.pps		= 0,
	.adjfreq	= ptp_pch_adjfreq,
	.adjtime	= ptp_pch_adjtime,
	.gettime64	= ptp_pch_gettime,
	.settime64	= ptp_pch_settime,
	.enable		= ptp_pch_enable,
};


#ifdef CONFIG_PM
static s32 pch_suspend(struct pci_dev *pdev, pm_message_t state)
{
	pci_disable_device(pdev);
	pci_enable_wake(pdev, PCI_D3hot, 0);

	if (pci_save_state(pdev) != 0) {
		dev_err(&pdev->dev, "could not save PCI config state\n");
		return -ENOMEM;
	}
	pci_set_power_state(pdev, pci_choose_state(pdev, state));

	return 0;
}

static s32 pch_resume(struct pci_dev *pdev)
{
	s32 ret;

	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);
	ret = pci_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "pci_enable_device failed\n");
		return ret;
	}
	pci_enable_wake(pdev, PCI_D3hot, 0);
	return 0;
}
#else
#define pch_suspend NULL
#define pch_resume NULL
#endif

static void pch_remove(struct pci_dev *pdev)
{
	struct pch_dev *chip = pci_get_drvdata(pdev);

	ptp_clock_unregister(chip->ptp_clock);
	/* free the interrupt */
	if (pdev->irq != 0)
		free_irq(pdev->irq, chip);

	/* unmap the virtual IO memory space */
	if (chip->regs != NULL) {
		iounmap(chip->regs);
		chip->regs = NULL;
	}
	/* release the reserved IO memory space */
	if (chip->mem_base != 0) {
		release_mem_region(chip->mem_base, chip->mem_size);
		chip->mem_base = 0;
	}
	pci_disable_device(pdev);
	kfree(chip);
	dev_info(&pdev->dev, "complete\n");
}

static s32
pch_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	s32 ret;
	unsigned long flags;
	struct pch_dev *chip;

	chip = kzalloc(sizeof(struct pch_dev), GFP_KERNEL);
	if (chip == NULL)
		return -ENOMEM;

	/* enable the 1588 pci device */
	ret = pci_enable_device(pdev);
	if (ret != 0) {
		dev_err(&pdev->dev, "could not enable the pci device\n");
		goto err_pci_en;
	}

	chip->mem_base = pci_resource_start(pdev, IO_MEM_BAR);
	if (!chip->mem_base) {
		dev_err(&pdev->dev, "could not locate IO memory address\n");
		ret = -ENODEV;
		goto err_pci_start;
	}

	/* retrieve the available length of the IO memory space */
	chip->mem_size = pci_resource_len(pdev, IO_MEM_BAR);

	/* allocate the memory for the device registers */
	if (!request_mem_region(chip->mem_base, chip->mem_size, "1588_regs")) {
		dev_err(&pdev->dev,
			"could not allocate register memory space\n");
		ret = -EBUSY;
		goto err_req_mem_region;
	}

	/* get the virtual address to the 1588 registers */
	chip->regs = ioremap(chip->mem_base, chip->mem_size);

	if (!chip->regs) {
		dev_err(&pdev->dev, "Could not get virtual address\n");
		ret = -ENOMEM;
		goto err_ioremap;
	}

	chip->caps = ptp_pch_caps;
	chip->ptp_clock = ptp_clock_register(&chip->caps, &pdev->dev);
	if (IS_ERR(chip->ptp_clock)) {
		ret = PTR_ERR(chip->ptp_clock);
		goto err_ptp_clock_reg;
	}

	spin_lock_init(&chip->register_lock);

	ret = request_irq(pdev->irq, &isr, IRQF_SHARED, KBUILD_MODNAME, chip);
	if (ret != 0) {
		dev_err(&pdev->dev, "failed to get irq %d\n", pdev->irq);
		goto err_req_irq;
	}

	/* indicate success */
	chip->irq = pdev->irq;
	chip->pdev = pdev;
	pci_set_drvdata(pdev, chip);

	spin_lock_irqsave(&chip->register_lock, flags);
	/* reset the ieee1588 h/w */
	pch_reset(chip);

	iowrite32(DEFAULT_ADDEND, &chip->regs->addend);
	iowrite32(1, &chip->regs->trgt_lo);
	iowrite32(0, &chip->regs->trgt_hi);
	iowrite32(PCH_TSE_TTIPEND, &chip->regs->event);

	pch_eth_enable_set(chip);

	if (strcmp(pch_param.station, "00:00:00:00:00:00") != 0) {
		if (pch_set_station_address(pch_param.station, pdev) != 0) {
			dev_err(&pdev->dev,
			"Invalid station address parameter\n"
			"Module loaded but station address not set correctly\n"
			);
		}
	}
	spin_unlock_irqrestore(&chip->register_lock, flags);
	return 0;

err_req_irq:
	ptp_clock_unregister(chip->ptp_clock);
err_ptp_clock_reg:
	iounmap(chip->regs);
	chip->regs = NULL;

err_ioremap:
	release_mem_region(chip->mem_base, chip->mem_size);

err_req_mem_region:
	chip->mem_base = 0;

err_pci_start:
	pci_disable_device(pdev);

err_pci_en:
	kfree(chip);
	dev_err(&pdev->dev, "probe failed(ret=0x%x)\n", ret);

	return ret;
}

static const struct pci_device_id pch_ieee1588_pcidev_id[] = {
	{
	  .vendor = PCI_VENDOR_ID_INTEL,
	  .device = PCI_DEVICE_ID_PCH_1588
	 },
	{0}
};

static struct pci_driver pch_driver = {
	.name = KBUILD_MODNAME,
	.id_table = pch_ieee1588_pcidev_id,
	.probe = pch_probe,
	.remove = pch_remove,
	.suspend = pch_suspend,
	.resume = pch_resume,
};

static void __exit ptp_pch_exit(void)
{
	pci_unregister_driver(&pch_driver);
}

static s32 __init ptp_pch_init(void)
{
	s32 ret;

	/* register the driver with the pci core */
	ret = pci_register_driver(&pch_driver);

	return ret;
}

module_init(ptp_pch_init);
module_exit(ptp_pch_exit);

module_param_string(station,
		    pch_param.station, sizeof(pch_param.station), 0444);
MODULE_PARM_DESC(station,
	 "IEEE 1588 station address to use - colon separated hex values");

MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <[email protected]>");
MODULE_DESCRIPTION("PTP clock using the EG20T timer");
MODULE_LICENSE("GPL");
Commit	Line	Data
863d08ec TS	1	/*
	2	* PTP 1588 clock using the EG20T PCH
	3	*
	4	* Copyright (C) 2010 OMICRON electronics GmbH
	5	* Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
	6	*
	7	* This code was derived from the IXP46X driver.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; version 2 of the License.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
	21	*/
	22
	23	#include <linux/device.h>
	24	#include <linux/err.h>
	25	#include <linux/init.h>
	26	#include <linux/interrupt.h>
	27	#include <linux/io.h>
	28	#include <linux/irq.h>
	29	#include <linux/kernel.h>
	30	#include <linux/module.h>
	31	#include <linux/pci.h>
	32	#include <linux/ptp_clock_kernel.h>
769b0daf	33	#include <linux/slab.h>
863d08ec TS	34
	35	#define STATION_ADDR_LEN 20
	36	#define PCI_DEVICE_ID_PCH_1588 0x8819
	37	#define IO_MEM_BAR 1
	38
	39	#define DEFAULT_ADDEND 0xA0000000
	40	#define TICKS_NS_SHIFT 5
	41	#define N_EXT_TS 2
	42
	43	enum pch_status {
	44	PCH_SUCCESS,
	45	PCH_INVALIDPARAM,
	46	PCH_NOTIMESTAMP,
	47	PCH_INTERRUPTMODEINUSE,
	48	PCH_FAILED,
	49	PCH_UNSUPPORTED,
	50	};
	51	/**
	52	* struct pch_ts_regs - IEEE 1588 registers
	53	*/
	54	struct pch_ts_regs {
	55	u32 control;
	56	u32 event;
	57	u32 addend;
	58	u32 accum;
	59	u32 test;
	60	u32 ts_compare;
	61	u32 rsystime_lo;
	62	u32 rsystime_hi;
	63	u32 systime_lo;
	64	u32 systime_hi;
	65	u32 trgt_lo;
	66	u32 trgt_hi;
	67	u32 asms_lo;
	68	u32 asms_hi;
	69	u32 amms_lo;
	70	u32 amms_hi;
	71	u32 ch_control;
	72	u32 ch_event;
	73	u32 tx_snap_lo;
	74	u32 tx_snap_hi;
	75	u32 rx_snap_lo;
	76	u32 rx_snap_hi;
	77	u32 src_uuid_lo;
	78	u32 src_uuid_hi;
	79	u32 can_status;
	80	u32 can_snap_lo;
	81	u32 can_snap_hi;
	82	u32 ts_sel;
	83	u32 ts_st[6];
	84	u32 reserve1[14];
	85	u32 stl_max_set_en;
	86	u32 stl_max_set;
	87	u32 reserve2[13];
	88	u32 srst;
	89	};
	90
	91	#define PCH_TSC_RESET (1 << 0)
	92	#define PCH_TSC_TTM_MASK (1 << 1)
	93	#define PCH_TSC_ASMS_MASK (1 << 2)
	94	#define PCH_TSC_AMMS_MASK (1 << 3)
	95	#define PCH_TSC_PPSM_MASK (1 << 4)
	96	#define PCH_TSE_TTIPEND (1 << 1)
	97	#define PCH_TSE_SNS (1 << 2)
98	#define PCH_TSE_SNM (1 << 3)
99	#define PCH_TSE_PPS (1 << 4)
100	#define PCH_CC_MM (1 << 0)
101	#define PCH_CC_TA (1 << 1)
102
103	#define PCH_CC_MODE_SHIFT 16
104	#define PCH_CC_MODE_MASK 0x001F0000
105	#define PCH_CC_VERSION (1 << 31)
106	#define PCH_CE_TXS (1 << 0)
107	#define PCH_CE_RXS (1 << 1)
108	#define PCH_CE_OVR (1 << 0)
109	#define PCH_CE_VAL (1 << 1)
110	#define PCH_ECS_ETH (1 << 0)
111
112	#define PCH_ECS_CAN (1 << 1)
113	#define PCH_STATION_BYTES 6
114
115	#define PCH_IEEE1588_ETH (1 << 0)
116	#define PCH_IEEE1588_CAN (1 << 1)
117	/**
118	* struct pch_dev - Driver private data
119	*/
120	struct pch_dev {
7d3ac5c7	121	struct pch_ts_regs __iomem *regs;
863d08ec TS	122	struct ptp_clock *ptp_clock;
	123	struct ptp_clock_info caps;
	124	int exts0_enabled;
	125	int exts1_enabled;
	126
	127	u32 mem_base;
	128	u32 mem_size;
	129	u32 irq;
	130	struct pci_dev *pdev;
	131	spinlock_t register_lock;
	132	};
	133
	134	/**
	135	* struct pch_params - 1588 module parameter
	136	*/
	137	struct pch_params {
	138	u8 station[STATION_ADDR_LEN];
	139	};
	140
	141	/* structure to hold the module parameters */
	142	static struct pch_params pch_param = {
	143	"00:00:00:00:00:00"
	144	};
	145
	146	/*
	147	* Register access functions
	148	*/
	149	static inline void pch_eth_enable_set(struct pch_dev *chip)
	150	{
	151	u32 val;
	152	/* SET the eth_enable bit */
	153	val = ioread32(&chip->regs->ts_sel) \| (PCH_ECS_ETH);
	154	iowrite32(val, (&chip->regs->ts_sel));
	155	}
	156
7d3ac5c7	157	static u64 pch_systime_read(struct pch_ts_regs __iomem *regs)
863d08ec TS	158	{
	159	u64 ns;
	160	u32 lo, hi;
	161
	162	lo = ioread32(&regs->systime_lo);
	163	hi = ioread32(&regs->systime_hi);
	164
	165	ns = ((u64) hi) << 32;
	166	ns \|= lo;
	167	ns <<= TICKS_NS_SHIFT;
	168
	169	return ns;
	170	}
	171
7d3ac5c7	172	static void pch_systime_write(struct pch_ts_regs __iomem *regs, u64 ns)
863d08ec TS	173	{
	174	u32 hi, lo;
	175
	176	ns >>= TICKS_NS_SHIFT;
	177	hi = ns >> 32;
	178	lo = ns & 0xffffffff;
	179
	180	iowrite32(lo, &regs->systime_lo);
	181	iowrite32(hi, &regs->systime_hi);
	182	}
	183
	184	static inline void pch_block_reset(struct pch_dev *chip)
	185	{
	186	u32 val;
	187	/* Reset Hardware Assist block */
	188	val = ioread32(&chip->regs->control) \| PCH_TSC_RESET;
	189	iowrite32(val, (&chip->regs->control));
	190	val = val & ~PCH_TSC_RESET;
	191	iowrite32(val, (&chip->regs->control));
	192	}
	193
	194	u32 pch_ch_control_read(struct pci_dev *pdev)
	195	{
	196	struct pch_dev *chip = pci_get_drvdata(pdev);
	197	u32 val;
	198
	199	val = ioread32(&chip->regs->ch_control);
	200
	201	return val;
	202	}
	203	EXPORT_SYMBOL(pch_ch_control_read);
	204
	205	void pch_ch_control_write(struct pci_dev *pdev, u32 val)
	206	{
	207	struct pch_dev *chip = pci_get_drvdata(pdev);
	208
	209	iowrite32(val, (&chip->regs->ch_control));
	210	}
	211	EXPORT_SYMBOL(pch_ch_control_write);
	212
	213	u32 pch_ch_event_read(struct pci_dev *pdev)
	214	{
	215	struct pch_dev *chip = pci_get_drvdata(pdev);
	216	u32 val;
	217
	218	val = ioread32(&chip->regs->ch_event);
	219
	220	return val;
	221	}
	222	EXPORT_SYMBOL(pch_ch_event_read);
	223
	224	void pch_ch_event_write(struct pci_dev *pdev, u32 val)
	225	{
	226	struct pch_dev *chip = pci_get_drvdata(pdev);
	227
	228	iowrite32(val, (&chip->regs->ch_event));
	229	}
	230	EXPORT_SYMBOL(pch_ch_event_write);
	231
	232	u32 pch_src_uuid_lo_read(struct pci_dev *pdev)
	233	{
	234	struct pch_dev *chip = pci_get_drvdata(pdev);
	235	u32 val;
	236
237	val = ioread32(&chip->regs->src_uuid_lo);
238
239	return val;
240	}
241	EXPORT_SYMBOL(pch_src_uuid_lo_read);
242
243	u32 pch_src_uuid_hi_read(struct pci_dev *pdev)
244	{
245	struct pch_dev *chip = pci_get_drvdata(pdev);
246	u32 val;
247
248	val = ioread32(&chip->regs->src_uuid_hi);
249
250	return val;
251	}
252	EXPORT_SYMBOL(pch_src_uuid_hi_read);
253
254	u64 pch_rx_snap_read(struct pci_dev *pdev)
255	{
256	struct pch_dev *chip = pci_get_drvdata(pdev);
257	u64 ns;
258	u32 lo, hi;
259
260	lo = ioread32(&chip->regs->rx_snap_lo);
261	hi = ioread32(&chip->regs->rx_snap_hi);
262
263	ns = ((u64) hi) << 32;
264	ns \|= lo;
d50566c7	265	ns <<= TICKS_NS_SHIFT;
863d08ec TS	266
	267	return ns;
	268	}
	269	EXPORT_SYMBOL(pch_rx_snap_read);
	270
	271	u64 pch_tx_snap_read(struct pci_dev *pdev)
	272	{
	273	struct pch_dev *chip = pci_get_drvdata(pdev);
	274	u64 ns;
	275	u32 lo, hi;
	276
	277	lo = ioread32(&chip->regs->tx_snap_lo);
	278	hi = ioread32(&chip->regs->tx_snap_hi);
	279
	280	ns = ((u64) hi) << 32;
	281	ns \|= lo;
d50566c7	282	ns <<= TICKS_NS_SHIFT;
863d08ec TS	283
	284	return ns;
	285	}
	286	EXPORT_SYMBOL(pch_tx_snap_read);
	287
	288	/* This function enables all 64 bits in system time registers [high & low].
	289	This is a work-around for non continuous value in the SystemTime Register*/
	290	static void pch_set_system_time_count(struct pch_dev *chip)
	291	{
	292	iowrite32(0x01, &chip->regs->stl_max_set_en);
	293	iowrite32(0xFFFFFFFF, &chip->regs->stl_max_set);
	294	iowrite32(0x00, &chip->regs->stl_max_set_en);
	295	}
	296
	297	static void pch_reset(struct pch_dev *chip)
	298	{
	299	/* Reset Hardware Assist */
	300	pch_block_reset(chip);
	301
	302	/* enable all 32 bits in system time registers */
	303	pch_set_system_time_count(chip);
	304	}
	305
	306	/**
	307	* pch_set_station_address() - This API sets the station address used by
	308	* IEEE 1588 hardware when looking at PTP
	309	* traffic on the ethernet interface
	310	* @addr: dress which contain the column separated address to be used.
	311	*/
17cdedf3	312	int pch_set_station_address(u8 addr, struct pci_dev pdev)
863d08ec TS	313	{
	314	s32 i;
	315	struct pch_dev *chip = pci_get_drvdata(pdev);
	316
	317	/* Verify the parameter */
7d3ac5c7	318	if ((chip->regs == NULL) \|\| addr == (u8 *)NULL) {
863d08ec TS	319	dev_err(&pdev->dev,
	320	"invalid params returning PCH_INVALIDPARAM\n");
	321	return PCH_INVALIDPARAM;
	322	}
	323	/* For all station address bytes */
	324	for (i = 0; i < PCH_STATION_BYTES; i++) {
	325	u32 val;
	326	s32 tmp;
	327
	328	tmp = hex_to_bin(addr[i * 3]);
	329	if (tmp < 0) {
	330	dev_err(&pdev->dev,
	331	"invalid params returning PCH_INVALIDPARAM\n");
	332	return PCH_INVALIDPARAM;
	333	}
	334	val = tmp * 16;
	335	tmp = hex_to_bin(addr[(i * 3) + 1]);
	336	if (tmp < 0) {
	337	dev_err(&pdev->dev,
	338	"invalid params returning PCH_INVALIDPARAM\n");
	339	return PCH_INVALIDPARAM;
	340	}
	341	val += tmp;
	342	/* Expects ':' separated addresses */
	343	if ((i < 5) && (addr[(i * 3) + 2] != ':')) {
	344	dev_err(&pdev->dev,
	345	"invalid params returning PCH_INVALIDPARAM\n");
	346	return PCH_INVALIDPARAM;
	347	}
	348
	349	/* Ideally we should set the address only after validating
	350	entire string */
	351	dev_dbg(&pdev->dev, "invoking pch_station_set\n");
	352	iowrite32(val, &chip->regs->ts_st[i]);
	353	}
	354	return 0;
	355	}
17cdedf3	356	EXPORT_SYMBOL(pch_set_station_address);
863d08ec TS	357
	358	/*
	359	* Interrupt service routine
	360	*/
	361	static irqreturn_t isr(int irq, void *priv)
	362	{
	363	struct pch_dev *pch_dev = priv;
7d3ac5c7	364	struct pch_ts_regs __iomem *regs = pch_dev->regs;
863d08ec TS	365	struct ptp_clock_event event;
	366	u32 ack = 0, lo, hi, val;
	367
	368	val = ioread32(&regs->event);
	369
	370	if (val & PCH_TSE_SNS) {
	371	ack \|= PCH_TSE_SNS;
	372	if (pch_dev->exts0_enabled) {
	373	hi = ioread32(&regs->asms_hi);
	374	lo = ioread32(&regs->asms_lo);
	375	event.type = PTP_CLOCK_EXTTS;
	376	event.index = 0;
	377	event.timestamp = ((u64) hi) << 32;
	378	event.timestamp \|= lo;
	379	event.timestamp <<= TICKS_NS_SHIFT;
	380	ptp_clock_event(pch_dev->ptp_clock, &event);
	381	}
	382	}
	383
	384	if (val & PCH_TSE_SNM) {
	385	ack \|= PCH_TSE_SNM;
	386	if (pch_dev->exts1_enabled) {
	387	hi = ioread32(&regs->amms_hi);
	388	lo = ioread32(&regs->amms_lo);
	389	event.type = PTP_CLOCK_EXTTS;
	390	event.index = 1;
	391	event.timestamp = ((u64) hi) << 32;
	392	event.timestamp \|= lo;
	393	event.timestamp <<= TICKS_NS_SHIFT;
	394	ptp_clock_event(pch_dev->ptp_clock, &event);
	395	}
	396	}
	397
	398	if (val & PCH_TSE_TTIPEND)
	399	ack \|= PCH_TSE_TTIPEND; /* this bit seems to be always set */
	400
	401	if (ack) {
	402	iowrite32(ack, &regs->event);
	403	return IRQ_HANDLED;
	404	} else
	405	return IRQ_NONE;
	406	}
	407
	408	/*
	409	* PTP clock operations
	410	*/
	411
	412	static int ptp_pch_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
	413	{
	414	u64 adj;
	415	u32 diff, addend;
	416	int neg_adj = 0;
	417	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
7d3ac5c7	418	struct pch_ts_regs __iomem *regs = pch_dev->regs;
863d08ec TS	419
	420	if (ppb < 0) {
	421	neg_adj = 1;
	422	ppb = -ppb;
	423	}
	424	addend = DEFAULT_ADDEND;
	425	adj = addend;
	426	adj *= ppb;
	427	diff = div_u64(adj, 1000000000ULL);
	428
	429	addend = neg_adj ? addend - diff : addend + diff;
	430
	431	iowrite32(addend, &regs->addend);
	432
	433	return 0;
	434	}
	435
	436	static int ptp_pch_adjtime(struct ptp_clock_info *ptp, s64 delta)
	437	{
	438	s64 now;
	439	unsigned long flags;
	440	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
7d3ac5c7	441	struct pch_ts_regs __iomem *regs = pch_dev->regs;
863d08ec TS	442
	443	spin_lock_irqsave(&pch_dev->register_lock, flags);
	444	now = pch_systime_read(regs);
	445	now += delta;
	446	pch_systime_write(regs, now);
	447	spin_unlock_irqrestore(&pch_dev->register_lock, flags);
	448
	449	return 0;
	450	}
	451
a043a729	452	static int ptp_pch_gettime(struct ptp_clock_info ptp, struct timespec64 ts)
863d08ec TS	453	{
	454	u64 ns;
	455	u32 remainder;
	456	unsigned long flags;
	457	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
7d3ac5c7	458	struct pch_ts_regs __iomem *regs = pch_dev->regs;
863d08ec TS	459
	460	spin_lock_irqsave(&pch_dev->register_lock, flags);
	461	ns = pch_systime_read(regs);
	462	spin_unlock_irqrestore(&pch_dev->register_lock, flags);
	463
	464	ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
	465	ts->tv_nsec = remainder;
	466	return 0;
	467	}
	468
	469	static int ptp_pch_settime(struct ptp_clock_info *ptp,
a043a729	470	const struct timespec64 *ts)
863d08ec TS	471	{
	472	u64 ns;
	473	unsigned long flags;
	474	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
7d3ac5c7	475	struct pch_ts_regs __iomem *regs = pch_dev->regs;
863d08ec TS	476
	477	ns = ts->tv_sec * 1000000000ULL;
	478	ns += ts->tv_nsec;
	479
	480	spin_lock_irqsave(&pch_dev->register_lock, flags);
	481	pch_systime_write(regs, ns);
	482	spin_unlock_irqrestore(&pch_dev->register_lock, flags);
	483
	484	return 0;
	485	}
	486
	487	static int ptp_pch_enable(struct ptp_clock_info *ptp,
	488	struct ptp_clock_request *rq, int on)
	489	{
	490	struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
	491
	492	switch (rq->type) {
	493	case PTP_CLK_REQ_EXTTS:
	494	switch (rq->extts.index) {
	495	case 0:
	496	pch_dev->exts0_enabled = on ? 1 : 0;
	497	break;
	498	case 1:
	499	pch_dev->exts1_enabled = on ? 1 : 0;
	500	break;
	501	default:
	502	return -EINVAL;
	503	}
	504	return 0;
	505	default:
	506	break;
	507	}
	508
	509	return -EOPNOTSUPP;
	510	}
	511
	512	static struct ptp_clock_info ptp_pch_caps = {
	513	.owner = THIS_MODULE,
	514	.name = "PCH timer",
	515	.max_adj = 50000000,
	516	.n_ext_ts = N_EXT_TS,
4986b4f0	517	.n_pins = 0,
863d08ec TS	518	.pps = 0,
	519	.adjfreq = ptp_pch_adjfreq,
	520	.adjtime = ptp_pch_adjtime,
a043a729 RC	521	.gettime64 = ptp_pch_gettime,
a043a729 RC	522	.settime64 = ptp_pch_settime,
863d08ec TS	523	.enable = ptp_pch_enable,
	524	};
	525
	526
	527	#ifdef CONFIG_PM
	528	static s32 pch_suspend(struct pci_dev *pdev, pm_message_t state)
	529	{
	530	pci_disable_device(pdev);
	531	pci_enable_wake(pdev, PCI_D3hot, 0);
	532
	533	if (pci_save_state(pdev) != 0) {
	534	dev_err(&pdev->dev, "could not save PCI config state\n");
	535	return -ENOMEM;
	536	}
	537	pci_set_power_state(pdev, pci_choose_state(pdev, state));
	538
	539	return 0;
	540	}
	541
	542	static s32 pch_resume(struct pci_dev *pdev)
	543	{
	544	s32 ret;
	545
	546	pci_set_power_state(pdev, PCI_D0);
	547	pci_restore_state(pdev);
	548	ret = pci_enable_device(pdev);
	549	if (ret) {
	550	dev_err(&pdev->dev, "pci_enable_device failed\n");
	551	return ret;
	552	}
	553	pci_enable_wake(pdev, PCI_D3hot, 0);
	554	return 0;
	555	}
	556	#else
	557	#define pch_suspend NULL
	558	#define pch_resume NULL
	559	#endif
	560
b1f7c8cc	561	static void pch_remove(struct pci_dev *pdev)
863d08ec TS	562	{
	563	struct pch_dev *chip = pci_get_drvdata(pdev);
	564
	565	ptp_clock_unregister(chip->ptp_clock);
	566	/* free the interrupt */
	567	if (pdev->irq != 0)
	568	free_irq(pdev->irq, chip);
	569
	570	/* unmap the virtual IO memory space */
7d3ac5c7	571	if (chip->regs != NULL) {
863d08ec	572	iounmap(chip->regs);
7d3ac5c7	573	chip->regs = NULL;
863d08ec TS	574	}
	575	/* release the reserved IO memory space */
	576	if (chip->mem_base != 0) {
	577	release_mem_region(chip->mem_base, chip->mem_size);
	578	chip->mem_base = 0;
	579	}
	580	pci_disable_device(pdev);
	581	kfree(chip);
	582	dev_info(&pdev->dev, "complete\n");
	583	}
	584
5c0a4256	585	static s32
863d08ec TS	586	pch_probe(struct pci_dev pdev, const struct pci_device_id id)
	587	{
	588	s32 ret;
	589	unsigned long flags;
	590	struct pch_dev *chip;
	591
	592	chip = kzalloc(sizeof(struct pch_dev), GFP_KERNEL);
	593	if (chip == NULL)
	594	return -ENOMEM;
	595
	596	/* enable the 1588 pci device */
	597	ret = pci_enable_device(pdev);
	598	if (ret != 0) {
	599	dev_err(&pdev->dev, "could not enable the pci device\n");
	600	goto err_pci_en;
	601	}
	602
	603	chip->mem_base = pci_resource_start(pdev, IO_MEM_BAR);
	604	if (!chip->mem_base) {
	605	dev_err(&pdev->dev, "could not locate IO memory address\n");
	606	ret = -ENODEV;
	607	goto err_pci_start;
	608	}
	609
	610	/* retrieve the available length of the IO memory space */
	611	chip->mem_size = pci_resource_len(pdev, IO_MEM_BAR);
	612
	613	/* allocate the memory for the device registers */
	614	if (!request_mem_region(chip->mem_base, chip->mem_size, "1588_regs")) {
	615	dev_err(&pdev->dev,
	616	"could not allocate register memory space\n");
	617	ret = -EBUSY;
	618	goto err_req_mem_region;
	619	}
	620
	621	/* get the virtual address to the 1588 registers */
	622	chip->regs = ioremap(chip->mem_base, chip->mem_size);
	623
	624	if (!chip->regs) {
	625	dev_err(&pdev->dev, "Could not get virtual address\n");
	626	ret = -ENOMEM;
	627	goto err_ioremap;
	628	}
	629
	630	chip->caps = ptp_pch_caps;
1ef76158	631	chip->ptp_clock = ptp_clock_register(&chip->caps, &pdev->dev);
0d8c3e77 WY	632	if (IS_ERR(chip->ptp_clock)) {
	633	ret = PTR_ERR(chip->ptp_clock);
	634	goto err_ptp_clock_reg;
	635	}
863d08ec TS	636
	637	spin_lock_init(&chip->register_lock);
	638
	639	ret = request_irq(pdev->irq, &isr, IRQF_SHARED, KBUILD_MODNAME, chip);
	640	if (ret != 0) {
	641	dev_err(&pdev->dev, "failed to get irq %d\n", pdev->irq);
	642	goto err_req_irq;
	643	}
	644
	645	/* indicate success */
	646	chip->irq = pdev->irq;
	647	chip->pdev = pdev;
	648	pci_set_drvdata(pdev, chip);
	649
	650	spin_lock_irqsave(&chip->register_lock, flags);
	651	/* reset the ieee1588 h/w */
	652	pch_reset(chip);
	653
	654	iowrite32(DEFAULT_ADDEND, &chip->regs->addend);
	655	iowrite32(1, &chip->regs->trgt_lo);
	656	iowrite32(0, &chip->regs->trgt_hi);
	657	iowrite32(PCH_TSE_TTIPEND, &chip->regs->event);
863d08ec TS	658
	659	pch_eth_enable_set(chip);
	660
	661	if (strcmp(pch_param.station, "00:00:00:00:00:00") != 0) {
	662	if (pch_set_station_address(pch_param.station, pdev) != 0) {
	663	dev_err(&pdev->dev,
	664	"Invalid station address parameter\n"
	665	"Module loaded but station address not set correctly\n"
	666	);
	667	}
	668	}
	669	spin_unlock_irqrestore(&chip->register_lock, flags);
	670	return 0;
	671
	672	err_req_irq:
	673	ptp_clock_unregister(chip->ptp_clock);
0d8c3e77	674	err_ptp_clock_reg:
863d08ec	675	iounmap(chip->regs);
7d3ac5c7	676	chip->regs = NULL;
863d08ec TS	677
	678	err_ioremap:
	679	release_mem_region(chip->mem_base, chip->mem_size);
	680
	681	err_req_mem_region:
	682	chip->mem_base = 0;
	683
	684	err_pci_start:
	685	pci_disable_device(pdev);
	686
	687	err_pci_en:
	688	kfree(chip);
	689	dev_err(&pdev->dev, "probe failed(ret=0x%x)\n", ret);
	690
	691	return ret;
	692	}
	693
9baa3c34	694	static const struct pci_device_id pch_ieee1588_pcidev_id[] = {
863d08ec TS	695	{
	696	.vendor = PCI_VENDOR_ID_INTEL,
	697	.device = PCI_DEVICE_ID_PCH_1588
	698	},
	699	{0}
	700	};
	701
d8d78949	702	static struct pci_driver pch_driver = {
863d08ec TS	703	.name = KBUILD_MODNAME,
	704	.id_table = pch_ieee1588_pcidev_id,
	705	.probe = pch_probe,
	706	.remove = pch_remove,
	707	.suspend = pch_suspend,
	708	.resume = pch_resume,
	709	};
	710
	711	static void __exit ptp_pch_exit(void)
	712	{
d8d78949	713	pci_unregister_driver(&pch_driver);
863d08ec TS	714	}
	715
	716	static s32 __init ptp_pch_init(void)
	717	{
	718	s32 ret;
	719
	720	/* register the driver with the pci core */
d8d78949	721	ret = pci_register_driver(&pch_driver);
863d08ec TS	722
	723	return ret;
	724	}
	725
	726	module_init(ptp_pch_init);
	727	module_exit(ptp_pch_exit);
	728
7d3ac5c7 S	729	module_param_string(station,
7d3ac5c7 S	730	pch_param.station, sizeof(pch_param.station), 0444);
863d08ec	731	MODULE_PARM_DESC(station,
55c31b5b	732	"IEEE 1588 station address to use - colon separated hex values");
863d08ec TS	733
	734	MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <[email protected]>");
	735	MODULE_DESCRIPTION("PTP clock using the EG20T timer");
	736	MODULE_LICENSE("GPL");