[linux.git] / drivers / pci / access.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/pci.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/wait.h>

#include "pci.h"

/*
 * This interrupt-safe spinlock protects all accesses to PCI
 * configuration space.
 */

DEFINE_RAW_SPINLOCK(pci_lock);

/*
 * Wrappers for all PCI configuration access functions.  They just check
 * alignment, do locking and call the low-level functions pointed to
 * by pci_dev->ops.
 */

#define PCI_byte_BAD 0
#define PCI_word_BAD (pos & 1)
#define PCI_dword_BAD (pos & 3)

#ifdef CONFIG_PCI_LOCKLESS_CONFIG
# define pci_lock_config(f)	do { (void)(f); } while (0)
# define pci_unlock_config(f)	do { (void)(f); } while (0)
#else
# define pci_lock_config(f)	raw_spin_lock_irqsave(&pci_lock, f)
# define pci_unlock_config(f)	raw_spin_unlock_irqrestore(&pci_lock, f)
#endif

#define PCI_OP_READ(size, type, len) \
int noinline pci_bus_read_config_##size \
	(struct pci_bus *bus, unsigned int devfn, int pos, type *value)	\
{									\
	int res;							\
	unsigned long flags;						\
	u32 data = 0;							\
	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;	\
	pci_lock_config(flags);						\
	res = bus->ops->read(bus, devfn, pos, len, &data);		\
	if (res)							\
		PCI_SET_ERROR_RESPONSE(value);				\
	else								\
		*value = (type)data;					\
	pci_unlock_config(flags);					\
	return res;							\
}

#define PCI_OP_WRITE(size, type, len) \
int noinline pci_bus_write_config_##size \
	(struct pci_bus *bus, unsigned int devfn, int pos, type value)	\
{									\
	int res;							\
	unsigned long flags;						\
	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;	\
	pci_lock_config(flags);						\
	res = bus->ops->write(bus, devfn, pos, len, value);		\
	pci_unlock_config(flags);					\
	return res;							\
}

PCI_OP_READ(byte, u8, 1)
PCI_OP_READ(word, u16, 2)
PCI_OP_READ(dword, u32, 4)
PCI_OP_WRITE(byte, u8, 1)
PCI_OP_WRITE(word, u16, 2)
PCI_OP_WRITE(dword, u32, 4)

EXPORT_SYMBOL(pci_bus_read_config_byte);
EXPORT_SYMBOL(pci_bus_read_config_word);
EXPORT_SYMBOL(pci_bus_read_config_dword);
EXPORT_SYMBOL(pci_bus_write_config_byte);
EXPORT_SYMBOL(pci_bus_write_config_word);
EXPORT_SYMBOL(pci_bus_write_config_dword);

int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
			    int where, int size, u32 *val)
{
	void __iomem *addr;

	addr = bus->ops->map_bus(bus, devfn, where);
	if (!addr)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (size == 1)
		*val = readb(addr);
	else if (size == 2)
		*val = readw(addr);
	else
		*val = readl(addr);

	return PCIBIOS_SUCCESSFUL;
}
EXPORT_SYMBOL_GPL(pci_generic_config_read);

int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
			     int where, int size, u32 val)
{
	void __iomem *addr;

	addr = bus->ops->map_bus(bus, devfn, where);
	if (!addr)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (size == 1)
		writeb(val, addr);
	else if (size == 2)
		writew(val, addr);
	else
		writel(val, addr);

	return PCIBIOS_SUCCESSFUL;
}
EXPORT_SYMBOL_GPL(pci_generic_config_write);

int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
			      int where, int size, u32 *val)
{
	void __iomem *addr;

	addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
	if (!addr)
		return PCIBIOS_DEVICE_NOT_FOUND;

	*val = readl(addr);

	if (size <= 2)
		*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);

	return PCIBIOS_SUCCESSFUL;
}
EXPORT_SYMBOL_GPL(pci_generic_config_read32);

int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
			       int where, int size, u32 val)
{
	void __iomem *addr;
	u32 mask, tmp;

	addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
	if (!addr)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (size == 4) {
		writel(val, addr);
		return PCIBIOS_SUCCESSFUL;
	}

	/*
	 * In general, hardware that supports only 32-bit writes on PCI is
	 * not spec-compliant.  For example, software may perform a 16-bit
	 * write.  If the hardware only supports 32-bit accesses, we must
	 * do a 32-bit read, merge in the 16 bits we intend to write,
	 * followed by a 32-bit write.  If the 16 bits we *don't* intend to
	 * write happen to have any RW1C (write-one-to-clear) bits set, we
	 * just inadvertently cleared something we shouldn't have.
	 */
	if (!bus->unsafe_warn) {
		dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
			 size, pci_domain_nr(bus), bus->number,
			 PCI_SLOT(devfn), PCI_FUNC(devfn), where);
		bus->unsafe_warn = 1;
	}

	mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
	tmp = readl(addr) & mask;
	tmp |= val << ((where & 0x3) * 8);
	writel(tmp, addr);

	return PCIBIOS_SUCCESSFUL;
}
EXPORT_SYMBOL_GPL(pci_generic_config_write32);

/**
 * pci_bus_set_ops - Set raw operations of pci bus
 * @bus:	pci bus struct
 * @ops:	new raw operations
 *
 * Return previous raw operations
 */
struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
{
	struct pci_ops *old_ops;
	unsigned long flags;

	raw_spin_lock_irqsave(&pci_lock, flags);
	old_ops = bus->ops;
	bus->ops = ops;
	raw_spin_unlock_irqrestore(&pci_lock, flags);
	return old_ops;
}
EXPORT_SYMBOL(pci_bus_set_ops);

/*
 * The following routines are to prevent the user from accessing PCI config
 * space when it's unsafe to do so.  Some devices require this during BIST and
 * we're required to prevent it during D-state transitions.
 *
 * We have a bit per device to indicate it's blocked and a global wait queue
 * for callers to sleep on until devices are unblocked.
 */
static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);

static noinline void pci_wait_cfg(struct pci_dev *dev)
	__must_hold(&pci_lock)
{
	do {
		raw_spin_unlock_irq(&pci_lock);
		wait_event(pci_cfg_wait, !dev->block_cfg_access);
		raw_spin_lock_irq(&pci_lock);
	} while (dev->block_cfg_access);
}

/* Returns 0 on success, negative values indicate error. */
#define PCI_USER_READ_CONFIG(size, type)					\
int pci_user_read_config_##size						\
	(struct pci_dev *dev, int pos, type *val)			\
{									\
	int ret = PCIBIOS_SUCCESSFUL;					\
	u32 data = -1;							\
	if (PCI_##size##_BAD)						\
		return -EINVAL;						\
	raw_spin_lock_irq(&pci_lock);				\
	if (unlikely(dev->block_cfg_access))				\
		pci_wait_cfg(dev);					\
	ret = dev->bus->ops->read(dev->bus, dev->devfn,			\
					pos, sizeof(type), &data);	\
	raw_spin_unlock_irq(&pci_lock);				\
	if (ret)							\
		PCI_SET_ERROR_RESPONSE(val);				\
	else								\
		*val = (type)data;					\
	return pcibios_err_to_errno(ret);				\
}									\
EXPORT_SYMBOL_GPL(pci_user_read_config_##size);

/* Returns 0 on success, negative values indicate error. */
#define PCI_USER_WRITE_CONFIG(size, type)				\
int pci_user_write_config_##size					\
	(struct pci_dev *dev, int pos, type val)			\
{									\
	int ret = PCIBIOS_SUCCESSFUL;					\
	if (PCI_##size##_BAD)						\
		return -EINVAL;						\
	raw_spin_lock_irq(&pci_lock);				\
	if (unlikely(dev->block_cfg_access))				\
		pci_wait_cfg(dev);					\
	ret = dev->bus->ops->write(dev->bus, dev->devfn,		\
					pos, sizeof(type), val);	\
	raw_spin_unlock_irq(&pci_lock);				\
	return pcibios_err_to_errno(ret);				\
}									\
EXPORT_SYMBOL_GPL(pci_user_write_config_##size);

PCI_USER_READ_CONFIG(byte, u8)
PCI_USER_READ_CONFIG(word, u16)
PCI_USER_READ_CONFIG(dword, u32)
PCI_USER_WRITE_CONFIG(byte, u8)
PCI_USER_WRITE_CONFIG(word, u16)
PCI_USER_WRITE_CONFIG(dword, u32)

/**
 * pci_cfg_access_lock - Lock PCI config reads/writes
 * @dev:	pci device struct
 *
 * When access is locked, any userspace reads or writes to config
 * space and concurrent lock requests will sleep until access is
 * allowed via pci_cfg_access_unlock() again.
 */
void pci_cfg_access_lock(struct pci_dev *dev)
{
	might_sleep();

	raw_spin_lock_irq(&pci_lock);
	if (dev->block_cfg_access)
		pci_wait_cfg(dev);
	dev->block_cfg_access = 1;
	raw_spin_unlock_irq(&pci_lock);
}
EXPORT_SYMBOL_GPL(pci_cfg_access_lock);

/**
 * pci_cfg_access_trylock - try to lock PCI config reads/writes
 * @dev:	pci device struct
 *
 * Same as pci_cfg_access_lock, but will return 0 if access is
 * already locked, 1 otherwise. This function can be used from
 * atomic contexts.
 */
bool pci_cfg_access_trylock(struct pci_dev *dev)
{
	unsigned long flags;
	bool locked = true;

	raw_spin_lock_irqsave(&pci_lock, flags);
	if (dev->block_cfg_access)
		locked = false;
	else
		dev->block_cfg_access = 1;
	raw_spin_unlock_irqrestore(&pci_lock, flags);

	return locked;
}
EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);

/**
 * pci_cfg_access_unlock - Unlock PCI config reads/writes
 * @dev:	pci device struct
 *
 * This function allows PCI config accesses to resume.
 */
void pci_cfg_access_unlock(struct pci_dev *dev)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&pci_lock, flags);

	/*
	 * This indicates a problem in the caller, but we don't need
	 * to kill them, unlike a double-block above.
	 */
	WARN_ON(!dev->block_cfg_access);

	dev->block_cfg_access = 0;
	raw_spin_unlock_irqrestore(&pci_lock, flags);

	wake_up_all(&pci_cfg_wait);
}
EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);

static inline int pcie_cap_version(const struct pci_dev *dev)
{
	return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
}

bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
{
	int type = pci_pcie_type(dev);

	return type == PCI_EXP_TYPE_ENDPOINT ||
	       type == PCI_EXP_TYPE_LEG_END ||
	       type == PCI_EXP_TYPE_ROOT_PORT ||
	       type == PCI_EXP_TYPE_UPSTREAM ||
	       type == PCI_EXP_TYPE_DOWNSTREAM ||
	       type == PCI_EXP_TYPE_PCI_BRIDGE ||
	       type == PCI_EXP_TYPE_PCIE_BRIDGE;
}

static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
{
	return pcie_downstream_port(dev) &&
	       pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
}

bool pcie_cap_has_rtctl(const struct pci_dev *dev)
{
	int type = pci_pcie_type(dev);

	return type == PCI_EXP_TYPE_ROOT_PORT ||
	       type == PCI_EXP_TYPE_RC_EC;
}

static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
{
	if (!pci_is_pcie(dev))
		return false;

	switch (pos) {
	case PCI_EXP_FLAGS:
		return true;
	case PCI_EXP_DEVCAP:
	case PCI_EXP_DEVCTL:
	case PCI_EXP_DEVSTA:
		return true;
	case PCI_EXP_LNKCAP:
	case PCI_EXP_LNKCTL:
	case PCI_EXP_LNKSTA:
		return pcie_cap_has_lnkctl(dev);
	case PCI_EXP_SLTCAP:
	case PCI_EXP_SLTCTL:
	case PCI_EXP_SLTSTA:
		return pcie_cap_has_sltctl(dev);
	case PCI_EXP_RTCTL:
	case PCI_EXP_RTCAP:
	case PCI_EXP_RTSTA:
		return pcie_cap_has_rtctl(dev);
	case PCI_EXP_DEVCAP2:
	case PCI_EXP_DEVCTL2:
	case PCI_EXP_LNKCAP2:
	case PCI_EXP_LNKCTL2:
	case PCI_EXP_LNKSTA2:
		return pcie_cap_version(dev) > 1;
	default:
		return false;
	}
}

/*
 * Note that these accessor functions are only for the "PCI Express
 * Capability" (see PCIe spec r3.0, sec 7.8).  They do not apply to the
 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
 */
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
{
	int ret;

	*val = 0;
	if (pos & 1)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (pcie_capability_reg_implemented(dev, pos)) {
		ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
		/*
		 * Reset *val to 0 if pci_read_config_word() fails; it may
		 * have been written as 0xFFFF (PCI_ERROR_RESPONSE) if the
		 * config read failed on PCI.
		 */
		if (ret)
			*val = 0;
		return ret;
	}

	/*
	 * For Functions that do not implement the Slot Capabilities,
	 * Slot Status, and Slot Control registers, these spaces must
	 * be hardwired to 0b, with the exception of the Presence Detect
	 * State bit in the Slot Status register of Downstream Ports,
	 * which must be hardwired to 1b.  (PCIe Base Spec 3.0, sec 7.8)
	 */
	if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
	    pos == PCI_EXP_SLTSTA)
		*val = PCI_EXP_SLTSTA_PDS;

	return 0;
}
EXPORT_SYMBOL(pcie_capability_read_word);

int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
{
	int ret;

	*val = 0;
	if (pos & 3)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (pcie_capability_reg_implemented(dev, pos)) {
		ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
		/*
		 * Reset *val to 0 if pci_read_config_dword() fails; it may
		 * have been written as 0xFFFFFFFF (PCI_ERROR_RESPONSE) if
		 * the config read failed on PCI.
		 */
		if (ret)
			*val = 0;
		return ret;
	}

	if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
	    pos == PCI_EXP_SLTSTA)
		*val = PCI_EXP_SLTSTA_PDS;

	return 0;
}
EXPORT_SYMBOL(pcie_capability_read_dword);

int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
{
	if (pos & 1)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (!pcie_capability_reg_implemented(dev, pos))
		return 0;

	return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
}
EXPORT_SYMBOL(pcie_capability_write_word);

int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
{
	if (pos & 3)
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (!pcie_capability_reg_implemented(dev, pos))
		return 0;

	return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
}
EXPORT_SYMBOL(pcie_capability_write_dword);

int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
				       u16 clear, u16 set)
{
	int ret;
	u16 val;

	ret = pcie_capability_read_word(dev, pos, &val);
	if (!ret) {
		val &= ~clear;
		val |= set;
		ret = pcie_capability_write_word(dev, pos, val);
	}

	return ret;
}
EXPORT_SYMBOL(pcie_capability_clear_and_set_word);

int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
					u32 clear, u32 set)
{
	int ret;
	u32 val;

	ret = pcie_capability_read_dword(dev, pos, &val);
	if (!ret) {
		val &= ~clear;
		val |= set;
		ret = pcie_capability_write_dword(dev, pos, val);
	}

	return ret;
}
EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);

int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
{
	if (pci_dev_is_disconnected(dev)) {
		PCI_SET_ERROR_RESPONSE(val);
		return PCIBIOS_DEVICE_NOT_FOUND;
	}
	return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
}
EXPORT_SYMBOL(pci_read_config_byte);

int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
{
	if (pci_dev_is_disconnected(dev)) {
		PCI_SET_ERROR_RESPONSE(val);
		return PCIBIOS_DEVICE_NOT_FOUND;
	}
	return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
}
EXPORT_SYMBOL(pci_read_config_word);

int pci_read_config_dword(const struct pci_dev *dev, int where,
					u32 *val)
{
	if (pci_dev_is_disconnected(dev)) {
		PCI_SET_ERROR_RESPONSE(val);
		return PCIBIOS_DEVICE_NOT_FOUND;
	}
	return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
}
EXPORT_SYMBOL(pci_read_config_dword);

int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
{
	if (pci_dev_is_disconnected(dev))
		return PCIBIOS_DEVICE_NOT_FOUND;
	return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
}
EXPORT_SYMBOL(pci_write_config_byte);

int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
{
	if (pci_dev_is_disconnected(dev))
		return PCIBIOS_DEVICE_NOT_FOUND;
	return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
}
EXPORT_SYMBOL(pci_write_config_word);

int pci_write_config_dword(const struct pci_dev *dev, int where,
					 u32 val)
{
	if (pci_dev_is_disconnected(dev))
		return PCIBIOS_DEVICE_NOT_FOUND;
	return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
}
EXPORT_SYMBOL(pci_write_config_dword);
Commit	Line	Data
7328c8f4	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	#include <linux/pci.h>
1da177e4 LT	3	#include <linux/module.h>
5a0e3ad6	4	#include <linux/slab.h>
1da177e4	5	#include <linux/ioport.h>
7ea7e98f	6	#include <linux/wait.h>
1da177e4	7
48b19148 AB	8	#include "pci.h"
48b19148 AB	9
1da177e4 LT	10	/*
	11	* This interrupt-safe spinlock protects all accesses to PCI
	12	* configuration space.
	13	*/
	14
a2e27787	15	DEFINE_RAW_SPINLOCK(pci_lock);
1da177e4 LT	16
1da177e4 LT	17	/*
df62ab5e BH	18	* Wrappers for all PCI configuration access functions. They just check
	19	* alignment, do locking and call the low-level functions pointed to
	20	* by pci_dev->ops.
1da177e4 LT	21	*/
	22
	23	#define PCI_byte_BAD 0
	24	#define PCI_word_BAD (pos & 1)
	25	#define PCI_dword_BAD (pos & 3)
	26
714fe383 TG	27	#ifdef CONFIG_PCI_LOCKLESS_CONFIG
	28	# define pci_lock_config(f) do { (void)(f); } while (0)
	29	# define pci_unlock_config(f) do { (void)(f); } while (0)
	30	#else
	31	# define pci_lock_config(f) raw_spin_lock_irqsave(&pci_lock, f)
	32	# define pci_unlock_config(f) raw_spin_unlock_irqrestore(&pci_lock, f)
	33	#endif
	34
ff3ce480	35	#define PCI_OP_READ(size, type, len) \
5180fd91	36	int noinline pci_bus_read_config_##size \
1da177e4 LT	37	(struct pci_bus bus, unsigned int devfn, int pos, type value) \
	38	{ \
	39	int res; \
	40	unsigned long flags; \
	41	u32 data = 0; \
	42	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
714fe383	43	pci_lock_config(flags); \
1da177e4	44	res = bus->ops->read(bus, devfn, pos, len, &data); \
f4f7eb43 NN	45	if (res) \
	46	PCI_SET_ERROR_RESPONSE(value); \
	47	else \
	48	*value = (type)data; \
714fe383	49	pci_unlock_config(flags); \
1da177e4 LT	50	return res; \
	51	}
	52
ff3ce480	53	#define PCI_OP_WRITE(size, type, len) \
5180fd91	54	int noinline pci_bus_write_config_##size \
1da177e4 LT	55	(struct pci_bus *bus, unsigned int devfn, int pos, type value) \
	56	{ \
	57	int res; \
	58	unsigned long flags; \
	59	if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
714fe383	60	pci_lock_config(flags); \
1da177e4	61	res = bus->ops->write(bus, devfn, pos, len, value); \
714fe383	62	pci_unlock_config(flags); \
1da177e4 LT	63	return res; \
	64	}
	65
	66	PCI_OP_READ(byte, u8, 1)
	67	PCI_OP_READ(word, u16, 2)
	68	PCI_OP_READ(dword, u32, 4)
	69	PCI_OP_WRITE(byte, u8, 1)
	70	PCI_OP_WRITE(word, u16, 2)
	71	PCI_OP_WRITE(dword, u32, 4)
	72
	73	EXPORT_SYMBOL(pci_bus_read_config_byte);
	74	EXPORT_SYMBOL(pci_bus_read_config_word);
	75	EXPORT_SYMBOL(pci_bus_read_config_dword);
	76	EXPORT_SYMBOL(pci_bus_write_config_byte);
	77	EXPORT_SYMBOL(pci_bus_write_config_word);
	78	EXPORT_SYMBOL(pci_bus_write_config_dword);
e04b0ea2	79
1f94a94f RH	80	int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
	81	int where, int size, u32 *val)
	82	{
	83	void __iomem *addr;
	84
	85	addr = bus->ops->map_bus(bus, devfn, where);
316df706	86	if (!addr)
1f94a94f	87	return PCIBIOS_DEVICE_NOT_FOUND;
1f94a94f RH	88
	89	if (size == 1)
	90	*val = readb(addr);
	91	else if (size == 2)
	92	*val = readw(addr);
	93	else
	94	*val = readl(addr);
	95
	96	return PCIBIOS_SUCCESSFUL;
	97	}
	98	EXPORT_SYMBOL_GPL(pci_generic_config_read);
	99
	100	int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
	101	int where, int size, u32 val)
	102	{
	103	void __iomem *addr;
	104
	105	addr = bus->ops->map_bus(bus, devfn, where);
	106	if (!addr)
	107	return PCIBIOS_DEVICE_NOT_FOUND;
	108
	109	if (size == 1)
	110	writeb(val, addr);
	111	else if (size == 2)
	112	writew(val, addr);
	113	else
	114	writel(val, addr);
	115
	116	return PCIBIOS_SUCCESSFUL;
	117	}
	118	EXPORT_SYMBOL_GPL(pci_generic_config_write);
	119
	120	int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
	121	int where, int size, u32 *val)
	122	{
	123	void __iomem *addr;
	124
	125	addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
316df706	126	if (!addr)
1f94a94f	127	return PCIBIOS_DEVICE_NOT_FOUND;
1f94a94f RH	128
	129	*val = readl(addr);
	130
	131	if (size <= 2)
	132	val = (val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
	133
	134	return PCIBIOS_SUCCESSFUL;
	135	}
	136	EXPORT_SYMBOL_GPL(pci_generic_config_read32);
	137
	138	int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
	139	int where, int size, u32 val)
	140	{
	141	void __iomem *addr;
	142	u32 mask, tmp;
	143
	144	addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
	145	if (!addr)
	146	return PCIBIOS_DEVICE_NOT_FOUND;
	147
	148	if (size == 4) {
	149	writel(val, addr);
	150	return PCIBIOS_SUCCESSFUL;
1f94a94f RH	151	}
1f94a94f RH	152
fb265923 BH	153	/*
	154	* In general, hardware that supports only 32-bit writes on PCI is
	155	* not spec-compliant. For example, software may perform a 16-bit
	156	* write. If the hardware only supports 32-bit accesses, we must
	157	* do a 32-bit read, merge in the 16 bits we intend to write,
	158	* followed by a 32-bit write. If the 16 bits we don't intend to
	159	* write happen to have any RW1C (write-one-to-clear) bits set, we
	160	* just inadvertently cleared something we shouldn't have.
	161	*/
92c45b63 MT	162	if (!bus->unsafe_warn) {
	163	dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
	164	size, pci_domain_nr(bus), bus->number,
	165	PCI_SLOT(devfn), PCI_FUNC(devfn), where);
	166	bus->unsafe_warn = 1;
	167	}
fb265923 BH	168
fb265923 BH	169	mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
1f94a94f RH	170	tmp = readl(addr) & mask;
	171	tmp \|= val << ((where & 0x3) * 8);
	172	writel(tmp, addr);
	173
	174	return PCIBIOS_SUCCESSFUL;
	175	}
	176	EXPORT_SYMBOL_GPL(pci_generic_config_write32);
	177
a72b46c3 YH	178	/**
	179	* pci_bus_set_ops - Set raw operations of pci bus
	180	* @bus: pci bus struct
	181	* @ops: new raw operations
	182	*
	183	* Return previous raw operations
	184	*/
	185	struct pci_ops pci_bus_set_ops(struct pci_bus bus, struct pci_ops *ops)
	186	{
	187	struct pci_ops *old_ops;
	188	unsigned long flags;
	189
511dd98c	190	raw_spin_lock_irqsave(&pci_lock, flags);
a72b46c3 YH	191	old_ops = bus->ops;
a72b46c3 YH	192	bus->ops = ops;
511dd98c	193	raw_spin_unlock_irqrestore(&pci_lock, flags);
a72b46c3 YH	194	return old_ops;
	195	}
	196	EXPORT_SYMBOL(pci_bus_set_ops);
287d19ce	197
7ea7e98f MW	198	/*
	199	* The following routines are to prevent the user from accessing PCI config
	200	* space when it's unsafe to do so. Some devices require this during BIST and
	201	* we're required to prevent it during D-state transitions.
	202	*
	203	* We have a bit per device to indicate it's blocked and a global wait queue
	204	* for callers to sleep on until devices are unblocked.
	205	*/
fb51ccbf	206	static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
e04b0ea2	207
fb51ccbf	208	static noinline void pci_wait_cfg(struct pci_dev *dev)
2a7e32d0	209	__must_hold(&pci_lock)
7ea7e98f	210	{
7ea7e98f	211	do {
511dd98c	212	raw_spin_unlock_irq(&pci_lock);
2a7e32d0	213	wait_event(pci_cfg_wait, !dev->block_cfg_access);
511dd98c	214	raw_spin_lock_irq(&pci_lock);
fb51ccbf	215	} while (dev->block_cfg_access);
e04b0ea2 BK	216	}
e04b0ea2 BK	217
34e32072	218	/* Returns 0 on success, negative values indicate error. */
ff3ce480	219	#define PCI_USER_READ_CONFIG(size, type) \
e04b0ea2 BK	220	int pci_user_read_config_##size \
	221	(struct pci_dev dev, int pos, type val) \
	222	{ \
d97ffe23	223	int ret = PCIBIOS_SUCCESSFUL; \
e04b0ea2	224	u32 data = -1; \
34e32072 GT	225	if (PCI_##size##_BAD) \
34e32072 GT	226	return -EINVAL; \
511dd98c	227	raw_spin_lock_irq(&pci_lock); \
fb51ccbf JK	228	if (unlikely(dev->block_cfg_access)) \
fb51ccbf JK	229	pci_wait_cfg(dev); \
7ea7e98f	230	ret = dev->bus->ops->read(dev->bus, dev->devfn, \
e04b0ea2	231	pos, sizeof(type), &data); \
511dd98c	232	raw_spin_unlock_irq(&pci_lock); \
f4f7eb43 NN	233	if (ret) \
	234	PCI_SET_ERROR_RESPONSE(val); \
	235	else \
	236	*val = (type)data; \
d97ffe23	237	return pcibios_err_to_errno(ret); \
c63587d7 AW	238	} \
c63587d7 AW	239	EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
e04b0ea2	240
34e32072	241	/* Returns 0 on success, negative values indicate error. */
ff3ce480	242	#define PCI_USER_WRITE_CONFIG(size, type) \
e04b0ea2 BK	243	int pci_user_write_config_##size \
	244	(struct pci_dev *dev, int pos, type val) \
	245	{ \
d97ffe23	246	int ret = PCIBIOS_SUCCESSFUL; \
34e32072 GT	247	if (PCI_##size##_BAD) \
34e32072 GT	248	return -EINVAL; \
511dd98c	249	raw_spin_lock_irq(&pci_lock); \
fb51ccbf JK	250	if (unlikely(dev->block_cfg_access)) \
fb51ccbf JK	251	pci_wait_cfg(dev); \
7ea7e98f	252	ret = dev->bus->ops->write(dev->bus, dev->devfn, \
e04b0ea2	253	pos, sizeof(type), val); \
511dd98c	254	raw_spin_unlock_irq(&pci_lock); \
d97ffe23	255	return pcibios_err_to_errno(ret); \
c63587d7 AW	256	} \
c63587d7 AW	257	EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
e04b0ea2 BK	258
	259	PCI_USER_READ_CONFIG(byte, u8)
	260	PCI_USER_READ_CONFIG(word, u16)
	261	PCI_USER_READ_CONFIG(dword, u32)
	262	PCI_USER_WRITE_CONFIG(byte, u8)
	263	PCI_USER_WRITE_CONFIG(word, u16)
	264	PCI_USER_WRITE_CONFIG(dword, u32)
	265
	266	/**
fb51ccbf	267	* pci_cfg_access_lock - Lock PCI config reads/writes
e04b0ea2 BK	268	* @dev: pci device struct
e04b0ea2 BK	269	*
fb51ccbf JK	270	* When access is locked, any userspace reads or writes to config
fb51ccbf JK	271	* space and concurrent lock requests will sleep until access is
0b131b13	272	* allowed via pci_cfg_access_unlock() again.
7ea7e98f	273	*/
fb51ccbf JK	274	void pci_cfg_access_lock(struct pci_dev *dev)
	275	{
	276	might_sleep();
	277
	278	raw_spin_lock_irq(&pci_lock);
	279	if (dev->block_cfg_access)
	280	pci_wait_cfg(dev);
	281	dev->block_cfg_access = 1;
	282	raw_spin_unlock_irq(&pci_lock);
	283	}
	284	EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
	285
	286	/**
	287	* pci_cfg_access_trylock - try to lock PCI config reads/writes
	288	* @dev: pci device struct
	289	*
	290	* Same as pci_cfg_access_lock, but will return 0 if access is
	291	* already locked, 1 otherwise. This function can be used from
	292	* atomic contexts.
	293	*/
	294	bool pci_cfg_access_trylock(struct pci_dev *dev)
e04b0ea2 BK	295	{
e04b0ea2 BK	296	unsigned long flags;
fb51ccbf	297	bool locked = true;
e04b0ea2	298
511dd98c	299	raw_spin_lock_irqsave(&pci_lock, flags);
fb51ccbf JK	300	if (dev->block_cfg_access)
	301	locked = false;
	302	else
	303	dev->block_cfg_access = 1;
511dd98c	304	raw_spin_unlock_irqrestore(&pci_lock, flags);
7ea7e98f	305
fb51ccbf	306	return locked;
e04b0ea2	307	}
fb51ccbf	308	EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
e04b0ea2 BK	309
e04b0ea2 BK	310	/**
fb51ccbf	311	* pci_cfg_access_unlock - Unlock PCI config reads/writes
e04b0ea2 BK	312	* @dev: pci device struct
e04b0ea2 BK	313	*
fb51ccbf	314	* This function allows PCI config accesses to resume.
7ea7e98f	315	*/
fb51ccbf	316	void pci_cfg_access_unlock(struct pci_dev *dev)
e04b0ea2 BK	317	{
	318	unsigned long flags;
	319
511dd98c	320	raw_spin_lock_irqsave(&pci_lock, flags);
7ea7e98f	321
df62ab5e BH	322	/*
	323	* This indicates a problem in the caller, but we don't need
	324	* to kill them, unlike a double-block above.
	325	*/
fb51ccbf	326	WARN_ON(!dev->block_cfg_access);
7ea7e98f	327
fb51ccbf	328	dev->block_cfg_access = 0;
511dd98c	329	raw_spin_unlock_irqrestore(&pci_lock, flags);
cdcb33f9 BH	330
cdcb33f9 BH	331	wake_up_all(&pci_cfg_wait);
e04b0ea2	332	}
fb51ccbf	333	EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
8c0d3a02 JL	334
	335	static inline int pcie_cap_version(const struct pci_dev *dev)
	336	{
1c531d82	337	return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
8c0d3a02 JL	338	}
8c0d3a02 JL	339
7a1562d4	340	bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
8c0d3a02 JL	341	{
	342	int type = pci_pcie_type(dev);
	343
c8b303d0	344	return type == PCI_EXP_TYPE_ENDPOINT \|\|
d3694d4f BH	345	type == PCI_EXP_TYPE_LEG_END \|\|
	346	type == PCI_EXP_TYPE_ROOT_PORT \|\|
	347	type == PCI_EXP_TYPE_UPSTREAM \|\|
	348	type == PCI_EXP_TYPE_DOWNSTREAM \|\|
	349	type == PCI_EXP_TYPE_PCI_BRIDGE \|\|
	350	type == PCI_EXP_TYPE_PCIE_BRIDGE;
8c0d3a02 JL	351	}
	352
	353	static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
	354	{
ffb4d602	355	return pcie_downstream_port(dev) &&
6d3a1741	356	pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
8c0d3a02 JL	357	}
8c0d3a02 JL	358
af65d1ad	359	bool pcie_cap_has_rtctl(const struct pci_dev *dev)
8c0d3a02 JL	360	{
	361	int type = pci_pcie_type(dev);
	362
c8b303d0	363	return type == PCI_EXP_TYPE_ROOT_PORT \|\|
8c0d3a02 JL	364	type == PCI_EXP_TYPE_RC_EC;
	365	}
	366
	367	static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
	368	{
	369	if (!pci_is_pcie(dev))
	370	return false;
	371
	372	switch (pos) {
969daa34	373	case PCI_EXP_FLAGS:
8c0d3a02 JL	374	return true;
	375	case PCI_EXP_DEVCAP:
	376	case PCI_EXP_DEVCTL:
	377	case PCI_EXP_DEVSTA:
fed24515	378	return true;
8c0d3a02 JL	379	case PCI_EXP_LNKCAP:
	380	case PCI_EXP_LNKCTL:
	381	case PCI_EXP_LNKSTA:
	382	return pcie_cap_has_lnkctl(dev);
	383	case PCI_EXP_SLTCAP:
	384	case PCI_EXP_SLTCTL:
	385	case PCI_EXP_SLTSTA:
	386	return pcie_cap_has_sltctl(dev);
	387	case PCI_EXP_RTCTL:
	388	case PCI_EXP_RTCAP:
	389	case PCI_EXP_RTSTA:
	390	return pcie_cap_has_rtctl(dev);
	391	case PCI_EXP_DEVCAP2:
	392	case PCI_EXP_DEVCTL2:
	393	case PCI_EXP_LNKCAP2:
	394	case PCI_EXP_LNKCTL2:
	395	case PCI_EXP_LNKSTA2:
	396	return pcie_cap_version(dev) > 1;
	397	default:
	398	return false;
	399	}
	400	}
	401
	402	/*
	403	* Note that these accessor functions are only for the "PCI Express
	404	* Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
	405	* other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
	406	*/
	407	int pcie_capability_read_word(struct pci_dev dev, int pos, u16 val)
	408	{
	409	int ret;
	410
	411	*val = 0;
	412	if (pos & 1)
b9153581	413	return PCIBIOS_BAD_REGISTER_NUMBER;
8c0d3a02 JL	414
	415	if (pcie_capability_reg_implemented(dev, pos)) {
	416	ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
	417	/*
289e3ea3 NN	418	* Reset *val to 0 if pci_read_config_word() fails; it may
	419	* have been written as 0xFFFF (PCI_ERROR_RESPONSE) if the
	420	* config read failed on PCI.
8c0d3a02 JL	421	*/
	422	if (ret)
	423	*val = 0;
	424	return ret;
	425	}
	426
	427	/*
	428	* For Functions that do not implement the Slot Capabilities,
	429	* Slot Status, and Slot Control registers, these spaces must
	430	* be hardwired to 0b, with the exception of the Presence Detect
	431	* State bit in the Slot Status register of Downstream Ports,
	432	* which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
	433	*/
ffb4d602 BH	434	if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
ffb4d602 BH	435	pos == PCI_EXP_SLTSTA)
8c0d3a02	436	*val = PCI_EXP_SLTSTA_PDS;
8c0d3a02 JL	437
	438	return 0;
	439	}
	440	EXPORT_SYMBOL(pcie_capability_read_word);
	441
	442	int pcie_capability_read_dword(struct pci_dev dev, int pos, u32 val)
	443	{
	444	int ret;
	445
	446	*val = 0;
	447	if (pos & 3)
b9153581	448	return PCIBIOS_BAD_REGISTER_NUMBER;
8c0d3a02 JL	449
	450	if (pcie_capability_reg_implemented(dev, pos)) {
	451	ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
	452	/*
289e3ea3 NN	453	* Reset *val to 0 if pci_read_config_dword() fails; it may
	454	* have been written as 0xFFFFFFFF (PCI_ERROR_RESPONSE) if
	455	* the config read failed on PCI.
8c0d3a02 JL	456	*/
	457	if (ret)
	458	*val = 0;
	459	return ret;
	460	}
	461
ffb4d602 BH	462	if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
ffb4d602 BH	463	pos == PCI_EXP_SLTSTA)
8c0d3a02	464	*val = PCI_EXP_SLTSTA_PDS;
8c0d3a02 JL	465
	466	return 0;
	467	}
	468	EXPORT_SYMBOL(pcie_capability_read_dword);
	469
	470	int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
	471	{
	472	if (pos & 1)
b9153581	473	return PCIBIOS_BAD_REGISTER_NUMBER;
8c0d3a02 JL	474
	475	if (!pcie_capability_reg_implemented(dev, pos))
	476	return 0;
	477
	478	return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
	479	}
	480	EXPORT_SYMBOL(pcie_capability_write_word);
	481
	482	int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
	483	{
	484	if (pos & 3)
b9153581	485	return PCIBIOS_BAD_REGISTER_NUMBER;
8c0d3a02 JL	486
	487	if (!pcie_capability_reg_implemented(dev, pos))
	488	return 0;
	489
	490	return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
	491	}
	492	EXPORT_SYMBOL(pcie_capability_write_dword);
	493
	494	int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
	495	u16 clear, u16 set)
	496	{
	497	int ret;
	498	u16 val;
	499
	500	ret = pcie_capability_read_word(dev, pos, &val);
	501	if (!ret) {
	502	val &= ~clear;
	503	val \|= set;
	504	ret = pcie_capability_write_word(dev, pos, val);
	505	}
	506
	507	return ret;
	508	}
	509	EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
	510
	511	int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
	512	u32 clear, u32 set)
	513	{
	514	int ret;
	515	u32 val;
	516
	517	ret = pcie_capability_read_dword(dev, pos, &val);
	518	if (!ret) {
	519	val &= ~clear;
	520	val \|= set;
	521	ret = pcie_capability_write_dword(dev, pos, val);
	522	}
	523
	524	return ret;
	525	}
	526	EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
d3881e50 KB	527
	528	int pci_read_config_byte(const struct pci_dev dev, int where, u8 val)
	529	{
4b103883	530	if (pci_dev_is_disconnected(dev)) {
9bc9310c	531	PCI_SET_ERROR_RESPONSE(val);
449e2f9e	532	return PCIBIOS_DEVICE_NOT_FOUND;
4b103883	533	}
d3881e50 KB	534	return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
	535	}
	536	EXPORT_SYMBOL(pci_read_config_byte);
	537
	538	int pci_read_config_word(const struct pci_dev dev, int where, u16 val)
	539	{
4b103883	540	if (pci_dev_is_disconnected(dev)) {
9bc9310c	541	PCI_SET_ERROR_RESPONSE(val);
449e2f9e	542	return PCIBIOS_DEVICE_NOT_FOUND;
4b103883	543	}
d3881e50 KB	544	return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
	545	}
	546	EXPORT_SYMBOL(pci_read_config_word);
	547
	548	int pci_read_config_dword(const struct pci_dev *dev, int where,
	549	u32 *val)
	550	{
4b103883	551	if (pci_dev_is_disconnected(dev)) {
9bc9310c	552	PCI_SET_ERROR_RESPONSE(val);
449e2f9e	553	return PCIBIOS_DEVICE_NOT_FOUND;
4b103883	554	}
d3881e50 KB	555	return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
	556	}
	557	EXPORT_SYMBOL(pci_read_config_dword);
	558
	559	int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
	560	{
4b103883	561	if (pci_dev_is_disconnected(dev))
449e2f9e	562	return PCIBIOS_DEVICE_NOT_FOUND;
d3881e50 KB	563	return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
	564	}
	565	EXPORT_SYMBOL(pci_write_config_byte);
	566
	567	int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
	568	{
4b103883	569	if (pci_dev_is_disconnected(dev))
449e2f9e	570	return PCIBIOS_DEVICE_NOT_FOUND;
d3881e50 KB	571	return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
	572	}
	573	EXPORT_SYMBOL(pci_write_config_word);
	574
	575	int pci_write_config_dword(const struct pci_dev *dev, int where,
	576	u32 val)
	577	{
4b103883	578	if (pci_dev_is_disconnected(dev))
449e2f9e	579	return PCIBIOS_DEVICE_NOT_FOUND;
d3881e50 KB	580	return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
	581	}
	582	EXPORT_SYMBOL(pci_write_config_dword);