[linux.git] / drivers / spi / spi-xilinx.c

/*
 * Xilinx SPI controller driver (master mode only)
 *
 * Author: MontaVista Software, Inc.
 *	[email protected]
 *
 * Copyright (c) 2010 Secret Lab Technologies, Ltd.
 * Copyright (c) 2009 Intel Corporation
 * 2002-2007 (c) MontaVista Software, Inc.

 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/spi/xilinx_spi.h>
#include <linux/io.h>

#define XILINX_SPI_MAX_CS	32

#define XILINX_SPI_NAME "xilinx_spi"

/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
 * Product Specification", DS464
 */
#define XSPI_CR_OFFSET		0x60	/* Control Register */

#define XSPI_CR_LOOP		0x01
#define XSPI_CR_ENABLE		0x02
#define XSPI_CR_MASTER_MODE	0x04
#define XSPI_CR_CPOL		0x08
#define XSPI_CR_CPHA		0x10
#define XSPI_CR_MODE_MASK	(XSPI_CR_CPHA | XSPI_CR_CPOL | \
				 XSPI_CR_LSB_FIRST | XSPI_CR_LOOP)
#define XSPI_CR_TXFIFO_RESET	0x20
#define XSPI_CR_RXFIFO_RESET	0x40
#define XSPI_CR_MANUAL_SSELECT	0x80
#define XSPI_CR_TRANS_INHIBIT	0x100
#define XSPI_CR_LSB_FIRST	0x200

#define XSPI_SR_OFFSET		0x64	/* Status Register */

#define XSPI_SR_RX_EMPTY_MASK	0x01	/* Receive FIFO is empty */
#define XSPI_SR_RX_FULL_MASK	0x02	/* Receive FIFO is full */
#define XSPI_SR_TX_EMPTY_MASK	0x04	/* Transmit FIFO is empty */
#define XSPI_SR_TX_FULL_MASK	0x08	/* Transmit FIFO is full */
#define XSPI_SR_MODE_FAULT_MASK	0x10	/* Mode fault error */

#define XSPI_TXD_OFFSET		0x68	/* Data Transmit Register */
#define XSPI_RXD_OFFSET		0x6c	/* Data Receive Register */

#define XSPI_SSR_OFFSET		0x70	/* 32-bit Slave Select Register */

/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
 * IPIF registers are 32 bit
 */
#define XIPIF_V123B_DGIER_OFFSET	0x1c	/* IPIF global int enable reg */
#define XIPIF_V123B_GINTR_ENABLE	0x80000000

#define XIPIF_V123B_IISR_OFFSET		0x20	/* IPIF interrupt status reg */
#define XIPIF_V123B_IIER_OFFSET		0x28	/* IPIF interrupt enable reg */

#define XSPI_INTR_MODE_FAULT		0x01	/* Mode fault error */
#define XSPI_INTR_SLAVE_MODE_FAULT	0x02	/* Selected as slave while
						 * disabled */
#define XSPI_INTR_TX_EMPTY		0x04	/* TxFIFO is empty */
#define XSPI_INTR_TX_UNDERRUN		0x08	/* TxFIFO was underrun */
#define XSPI_INTR_RX_FULL		0x10	/* RxFIFO is full */
#define XSPI_INTR_RX_OVERRUN		0x20	/* RxFIFO was overrun */
#define XSPI_INTR_TX_HALF_EMPTY		0x40	/* TxFIFO is half empty */

#define XIPIF_V123B_RESETR_OFFSET	0x40	/* IPIF reset register */
#define XIPIF_V123B_RESET_MASK		0x0a	/* the value to write */

struct xilinx_spi {
	/* bitbang has to be first */
	struct spi_bitbang bitbang;
	struct completion done;
	void __iomem	*regs;	/* virt. address of the control registers */

	int		irq;

	u8 *rx_ptr;		/* pointer in the Tx buffer */
	const u8 *tx_ptr;	/* pointer in the Rx buffer */
	u8 bytes_per_word;
	int buffer_size;	/* buffer size in words */
	u32 cs_inactive;	/* Level of the CS pins when inactive*/
	unsigned int (*read_fn)(void __iomem *);
	void (*write_fn)(u32, void __iomem *);
};

static void xspi_write32(u32 val, void __iomem *addr)
{
	iowrite32(val, addr);
}

static unsigned int xspi_read32(void __iomem *addr)
{
	return ioread32(addr);
}

static void xspi_write32_be(u32 val, void __iomem *addr)
{
	iowrite32be(val, addr);
}

static unsigned int xspi_read32_be(void __iomem *addr)
{
	return ioread32be(addr);
}

static void xilinx_spi_tx(struct xilinx_spi *xspi)
{
	u32 data = 0;

	if (!xspi->tx_ptr) {
		xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
		return;
	}

	switch (xspi->bytes_per_word) {
	case 1:
		data = *(u8 *)(xspi->tx_ptr);
		break;
	case 2:
		data = *(u16 *)(xspi->tx_ptr);
		break;
	case 4:
		data = *(u32 *)(xspi->tx_ptr);
		break;
	}

	xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET);
	xspi->tx_ptr += xspi->bytes_per_word;
}

static void xilinx_spi_rx(struct xilinx_spi *xspi)
{
	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);

	if (!xspi->rx_ptr)
		return;

	switch (xspi->bytes_per_word) {
	case 1:
		*(u8 *)(xspi->rx_ptr) = data;
		break;
	case 2:
		*(u16 *)(xspi->rx_ptr) = data;
		break;
	case 4:
		*(u32 *)(xspi->rx_ptr) = data;
		break;
	}

	xspi->rx_ptr += xspi->bytes_per_word;
}

static void xspi_init_hw(struct xilinx_spi *xspi)
{
	void __iomem *regs_base = xspi->regs;

	/* Reset the SPI device */
	xspi->write_fn(XIPIF_V123B_RESET_MASK,
		regs_base + XIPIF_V123B_RESETR_OFFSET);
	/* Enable the transmit empty interrupt, which we use to determine
	 * progress on the transmission.
	 */
	xspi->write_fn(XSPI_INTR_TX_EMPTY,
			regs_base + XIPIF_V123B_IIER_OFFSET);
	/* Disable the global IPIF interrupt */
	xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
	/* Deselect the slave on the SPI bus */
	xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
	/* Disable the transmitter, enable Manual Slave Select Assertion,
	 * put SPI controller into master mode, and enable it */
	xspi->write_fn(XSPI_CR_MANUAL_SSELECT |	XSPI_CR_MASTER_MODE |
		XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |	XSPI_CR_RXFIFO_RESET,
		regs_base + XSPI_CR_OFFSET);
}

static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
{
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	u16 cr;
	u32 cs;

	if (is_on == BITBANG_CS_INACTIVE) {
		/* Deselect the slave on the SPI bus */
		xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
		return;
	}

	/* Set the SPI clock phase and polarity */
	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)	& ~XSPI_CR_MODE_MASK;
	if (spi->mode & SPI_CPHA)
		cr |= XSPI_CR_CPHA;
	if (spi->mode & SPI_CPOL)
		cr |= XSPI_CR_CPOL;
	if (spi->mode & SPI_LSB_FIRST)
		cr |= XSPI_CR_LSB_FIRST;
	if (spi->mode & SPI_LOOP)
		cr |= XSPI_CR_LOOP;
	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);

	/* We do not check spi->max_speed_hz here as the SPI clock
	 * frequency is not software programmable (the IP block design
	 * parameter)
	 */

	cs = xspi->cs_inactive;
	cs ^= BIT(spi->chip_select);

	/* Activate the chip select */
	xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
}

/* spi_bitbang requires custom setup_transfer() to be defined if there is a
 * custom txrx_bufs().
 */
static int xilinx_spi_setup_transfer(struct spi_device *spi,
		struct spi_transfer *t)
{
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);

	if (spi->mode & SPI_CS_HIGH)
		xspi->cs_inactive &= ~BIT(spi->chip_select);
	else
		xspi->cs_inactive |= BIT(spi->chip_select);

	return 0;
}

static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	int remaining_words;	/* the number of words left to transfer */
	bool use_irq = false;
	u16 cr = 0;

	/* We get here with transmitter inhibited */

	xspi->tx_ptr = t->tx_buf;
	xspi->rx_ptr = t->rx_buf;
	remaining_words = t->len / xspi->bytes_per_word;

	if (xspi->irq >= 0 &&  remaining_words > xspi->buffer_size) {
		u32 isr;
		use_irq = true;
		/* Inhibit irq to avoid spurious irqs on tx_empty*/
		cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
		xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
			       xspi->regs + XSPI_CR_OFFSET);
		/* ACK old irqs (if any) */
		isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
		if (isr)
			xspi->write_fn(isr,
				       xspi->regs + XIPIF_V123B_IISR_OFFSET);
		/* Enable the global IPIF interrupt */
		xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
				xspi->regs + XIPIF_V123B_DGIER_OFFSET);
		reinit_completion(&xspi->done);
	}

	while (remaining_words) {
		int n_words, tx_words, rx_words;
		u32 sr;
		int stalled;

		n_words = min(remaining_words, xspi->buffer_size);

		tx_words = n_words;
		while (tx_words--)
			xilinx_spi_tx(xspi);

		/* Start the transfer by not inhibiting the transmitter any
		 * longer
		 */

		if (use_irq) {
			xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
			wait_for_completion(&xspi->done);
			/* A transmit has just completed. Process received data
			 * and check for more data to transmit. Always inhibit
			 * the transmitter while the Isr refills the transmit
			 * register/FIFO, or make sure it is stopped if we're
			 * done.
			 */
			xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
				       xspi->regs + XSPI_CR_OFFSET);
			sr = XSPI_SR_TX_EMPTY_MASK;
		} else
			sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);

		/* Read out all the data from the Rx FIFO */
		rx_words = n_words;
		stalled = 10;
		while (rx_words) {
			if (rx_words == n_words && !(stalled--) &&
			    !(sr & XSPI_SR_TX_EMPTY_MASK) &&
			    (sr & XSPI_SR_RX_EMPTY_MASK)) {
				dev_err(&spi->dev,
					"Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n");
				xspi_init_hw(xspi);
				return -EIO;
			}

			if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) {
				xilinx_spi_rx(xspi);
				rx_words--;
				continue;
			}

			sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
			if (!(sr & XSPI_SR_RX_EMPTY_MASK)) {
				xilinx_spi_rx(xspi);
				rx_words--;
			}
		}

		remaining_words -= n_words;
	}

	if (use_irq) {
		xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
		xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
	}

	return t->len;
}


/* This driver supports single master mode only. Hence Tx FIFO Empty
 * is the only interrupt we care about.
 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
 * Fault are not to happen.
 */
static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
{
	struct xilinx_spi *xspi = dev_id;
	u32 ipif_isr;

	/* Get the IPIF interrupts, and clear them immediately */
	ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
	xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);

	if (ipif_isr & XSPI_INTR_TX_EMPTY) {	/* Transmission completed */
		complete(&xspi->done);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
{
	u8 sr;
	int n_words = 0;

	/*
	 * Before the buffer_size detection we reset the core
	 * to make sure we start with a clean state.
	 */
	xspi->write_fn(XIPIF_V123B_RESET_MASK,
		xspi->regs + XIPIF_V123B_RESETR_OFFSET);

	/* Fill the Tx FIFO with as many words as possible */
	do {
		xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
		sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
		n_words++;
	} while (!(sr & XSPI_SR_TX_FULL_MASK));

	return n_words;
}

static const struct of_device_id xilinx_spi_of_match[] = {
	{ .compatible = "xlnx,axi-quad-spi-1.00.a", },
	{ .compatible = "xlnx,xps-spi-2.00.a", },
	{ .compatible = "xlnx,xps-spi-2.00.b", },
	{}
};
MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);

static int xilinx_spi_probe(struct platform_device *pdev)
{
	struct xilinx_spi *xspi;
	struct xspi_platform_data *pdata;
	struct resource *res;
	int ret, num_cs = 0, bits_per_word = 8;
	struct spi_master *master;
	u32 tmp;
	u8 i;

	pdata = dev_get_platdata(&pdev->dev);
	if (pdata) {
		num_cs = pdata->num_chipselect;
		bits_per_word = pdata->bits_per_word;
	} else {
		of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
					  &num_cs);
	}

	if (!num_cs) {
		dev_err(&pdev->dev,
			"Missing slave select configuration data\n");
		return -EINVAL;
	}

	if (num_cs > XILINX_SPI_MAX_CS) {
		dev_err(&pdev->dev, "Invalid number of spi slaves\n");
		return -EINVAL;
	}

	master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
	if (!master)
		return -ENODEV;

	/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP |
			    SPI_CS_HIGH;

	xspi = spi_master_get_devdata(master);
	xspi->cs_inactive = 0xffffffff;
	xspi->bitbang.master = master;
	xspi->bitbang.chipselect = xilinx_spi_chipselect;
	xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
	xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
	init_completion(&xspi->done);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	xspi->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(xspi->regs)) {
		ret = PTR_ERR(xspi->regs);
		goto put_master;
	}

	master->bus_num = pdev->id;
	master->num_chipselect = num_cs;
	master->dev.of_node = pdev->dev.of_node;

	/*
	 * Detect endianess on the IP via loop bit in CR. Detection
	 * must be done before reset is sent because incorrect reset
	 * value generates error interrupt.
	 * Setup little endian helper functions first and try to use them
	 * and check if bit was correctly setup or not.
	 */
	xspi->read_fn = xspi_read32;
	xspi->write_fn = xspi_write32;

	xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
	tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
	tmp &= XSPI_CR_LOOP;
	if (tmp != XSPI_CR_LOOP) {
		xspi->read_fn = xspi_read32_be;
		xspi->write_fn = xspi_write32_be;
	}

	master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
	xspi->bytes_per_word = bits_per_word / 8;
	xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);

	xspi->irq = platform_get_irq(pdev, 0);
	if (xspi->irq < 0 && xspi->irq != -ENXIO) {
		ret = xspi->irq;
		goto put_master;
	} else if (xspi->irq >= 0) {
		/* Register for SPI Interrupt */
		ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
				dev_name(&pdev->dev), xspi);
		if (ret)
			goto put_master;
	}

	/* SPI controller initializations */
	xspi_init_hw(xspi);

	ret = spi_bitbang_start(&xspi->bitbang);
	if (ret) {
		dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
		goto put_master;
	}

	dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
		(unsigned long long)res->start, xspi->regs, xspi->irq);

	if (pdata) {
		for (i = 0; i < pdata->num_devices; i++)
			spi_new_device(master, pdata->devices + i);
	}

	platform_set_drvdata(pdev, master);
	return 0;

put_master:
	spi_master_put(master);

	return ret;
}

static int xilinx_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct xilinx_spi *xspi = spi_master_get_devdata(master);
	void __iomem *regs_base = xspi->regs;

	spi_bitbang_stop(&xspi->bitbang);

	/* Disable all the interrupts just in case */
	xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
	/* Disable the global IPIF interrupt */
	xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);

	spi_master_put(xspi->bitbang.master);

	return 0;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:" XILINX_SPI_NAME);

static struct platform_driver xilinx_spi_driver = {
	.probe = xilinx_spi_probe,
	.remove = xilinx_spi_remove,
	.driver = {
		.name = XILINX_SPI_NAME,
		.of_match_table = xilinx_spi_of_match,
	},
};
module_platform_driver(xilinx_spi_driver);

MODULE_AUTHOR("MontaVista Software, Inc. <[email protected]>");
MODULE_DESCRIPTION("Xilinx SPI driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
ae918c02	1	/*
ae918c02 AK	2	* Xilinx SPI controller driver (master mode only)
	3	*
	4	* Author: MontaVista Software, Inc.
	5	* [email protected]
	6	*
8fd8821b GL	7	* Copyright (c) 2010 Secret Lab Technologies, Ltd.
	8	* Copyright (c) 2009 Intel Corporation
	9	* 2002-2007 (c) MontaVista Software, Inc.
	10
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
ae918c02 AK	14	*/
	15
	16	#include <linux/module.h>
ae918c02	17	#include <linux/interrupt.h>
eae6cb31	18	#include <linux/of.h>
8fd8821b	19	#include <linux/platform_device.h>
ae918c02 AK	20	#include <linux/spi/spi.h>
ae918c02 AK	21	#include <linux/spi/spi_bitbang.h>
d5af91a1	22	#include <linux/spi/xilinx_spi.h>
eae6cb31	23	#include <linux/io.h>
d5af91a1	24
eb25f16c RR	25	#define XILINX_SPI_MAX_CS 32
eb25f16c RR	26
fc3ba952	27	#define XILINX_SPI_NAME "xilinx_spi"
ae918c02 AK	28
	29	/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
	30	* Product Specification", DS464
	31	*/
c9da2e12	32	#define XSPI_CR_OFFSET 0x60 /* Control Register */
ae918c02	33
082339bc	34	#define XSPI_CR_LOOP 0x01
ae918c02 AK	35	#define XSPI_CR_ENABLE 0x02
	36	#define XSPI_CR_MASTER_MODE 0x04
	37	#define XSPI_CR_CPOL 0x08
	38	#define XSPI_CR_CPHA 0x10
bca690db	39	#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA \| XSPI_CR_CPOL \| \
0240f945	40	XSPI_CR_LSB_FIRST \| XSPI_CR_LOOP)
ae918c02 AK	41	#define XSPI_CR_TXFIFO_RESET 0x20
	42	#define XSPI_CR_RXFIFO_RESET 0x40
	43	#define XSPI_CR_MANUAL_SSELECT 0x80
	44	#define XSPI_CR_TRANS_INHIBIT 0x100
c9da2e12	45	#define XSPI_CR_LSB_FIRST 0x200
ae918c02	46
c9da2e12	47	#define XSPI_SR_OFFSET 0x64 /* Status Register */
ae918c02 AK	48
	49	#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
	50	#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
	51	#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
	52	#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
	53	#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
	54
c9da2e12 RR	55	#define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
c9da2e12 RR	56	#define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
ae918c02 AK	57
	58	#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
	59
	60	/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
	61	* IPIF registers are 32 bit
	62	*/
	63	#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
	64	#define XIPIF_V123B_GINTR_ENABLE 0x80000000
	65
	66	#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
	67	#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
	68
	69	#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
	70	#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
	71	* disabled */
	72	#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
	73	#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
	74	#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
	75	#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
c9da2e12	76	#define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
ae918c02 AK	77
	78	#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
	79	#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
	80
	81	struct xilinx_spi {
	82	/* bitbang has to be first */
	83	struct spi_bitbang bitbang;
	84	struct completion done;
ae918c02 AK	85	void __iomem regs; / virt. address of the control registers */
ae918c02 AK	86
9ca1273b	87	int irq;
ae918c02	88
ae918c02 AK	89	u8 rx_ptr; / pointer in the Tx buffer */
ae918c02 AK	90	const u8 tx_ptr; / pointer in the Rx buffer */
17aaaa80	91	u8 bytes_per_word;
4c9a7614	92	int buffer_size; /* buffer size in words */
f9c6ef6c	93	u32 cs_inactive; /* Level of the CS pins when inactive*/
6ff8672a JH	94	unsigned int (read_fn)(void __iomem );
6ff8672a JH	95	void (write_fn)(u32, void __iomem );
ae918c02 AK	96	};
ae918c02 AK	97
0635287a MB	98	static void xspi_write32(u32 val, void __iomem *addr)
	99	{
	100	iowrite32(val, addr);
	101	}
	102
	103	static unsigned int xspi_read32(void __iomem *addr)
	104	{
	105	return ioread32(addr);
	106	}
	107
	108	static void xspi_write32_be(u32 val, void __iomem *addr)
	109	{
	110	iowrite32be(val, addr);
	111	}
	112
	113	static unsigned int xspi_read32_be(void __iomem *addr)
	114	{
	115	return ioread32be(addr);
	116	}
	117
24ba5e59	118	static void xilinx_spi_tx(struct xilinx_spi *xspi)
c9da2e12	119	{
34093cb9 RR	120	u32 data = 0;
34093cb9 RR	121
c3092941 RR	122	if (!xspi->tx_ptr) {
	123	xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
	124	return;
	125	}
34093cb9 RR	126
	127	switch (xspi->bytes_per_word) {
	128	case 1:
	129	data = (u8 )(xspi->tx_ptr);
	130	break;
	131	case 2:
	132	data = (u16 )(xspi->tx_ptr);
	133	break;
	134	case 4:
	135	data = (u32 )(xspi->tx_ptr);
	136	break;
	137	}
	138
	139	xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET);
17aaaa80	140	xspi->tx_ptr += xspi->bytes_per_word;
c9da2e12 RR	141	}
c9da2e12 RR	142
24ba5e59	143	static void xilinx_spi_rx(struct xilinx_spi *xspi)
c9da2e12 RR	144	{
c9da2e12 RR	145	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
c9da2e12	146
24ba5e59 RR	147	if (!xspi->rx_ptr)
24ba5e59 RR	148	return;
c9da2e12	149
17aaaa80 RR	150	switch (xspi->bytes_per_word) {
17aaaa80 RR	151	case 1:
24ba5e59 RR	152	(u8 )(xspi->rx_ptr) = data;
24ba5e59 RR	153	break;
17aaaa80	154	case 2:
24ba5e59 RR	155	(u16 )(xspi->rx_ptr) = data;
24ba5e59 RR	156	break;
17aaaa80	157	case 4:
c9da2e12	158	(u32 )(xspi->rx_ptr) = data;
24ba5e59	159	break;
c9da2e12	160	}
24ba5e59	161
17aaaa80	162	xspi->rx_ptr += xspi->bytes_per_word;
c9da2e12 RR	163	}
c9da2e12 RR	164
86fc5935	165	static void xspi_init_hw(struct xilinx_spi *xspi)
ae918c02	166	{
86fc5935 RR	167	void __iomem *regs_base = xspi->regs;
86fc5935 RR	168
ae918c02	169	/* Reset the SPI device */
86fc5935 RR	170	xspi->write_fn(XIPIF_V123B_RESET_MASK,
86fc5935 RR	171	regs_base + XIPIF_V123B_RESETR_OFFSET);
899929ba RR	172	/* Enable the transmit empty interrupt, which we use to determine
	173	* progress on the transmission.
	174	*/
	175	xspi->write_fn(XSPI_INTR_TX_EMPTY,
	176	regs_base + XIPIF_V123B_IIER_OFFSET);
22417352 RR	177	/* Disable the global IPIF interrupt */
22417352 RR	178	xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
ae918c02	179	/* Deselect the slave on the SPI bus */
86fc5935	180	xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
ae918c02 AK	181	/* Disable the transmitter, enable Manual Slave Select Assertion,
ae918c02 AK	182	* put SPI controller into master mode, and enable it */
22417352 RR	183	xspi->write_fn(XSPI_CR_MANUAL_SSELECT \| XSPI_CR_MASTER_MODE \|
	184	XSPI_CR_ENABLE \| XSPI_CR_TXFIFO_RESET \| XSPI_CR_RXFIFO_RESET,
	185	regs_base + XSPI_CR_OFFSET);
ae918c02 AK	186	}
	187
	188	static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
	189	{
	190	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
f9c6ef6c RR	191	u16 cr;
f9c6ef6c RR	192	u32 cs;
ae918c02 AK	193
	194	if (is_on == BITBANG_CS_INACTIVE) {
	195	/* Deselect the slave on the SPI bus */
f9c6ef6c RR	196	xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
f9c6ef6c RR	197	return;
ae918c02	198	}
f9c6ef6c RR	199
	200	/* Set the SPI clock phase and polarity */
	201	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK;
	202	if (spi->mode & SPI_CPHA)
	203	cr \|= XSPI_CR_CPHA;
	204	if (spi->mode & SPI_CPOL)
	205	cr \|= XSPI_CR_CPOL;
	206	if (spi->mode & SPI_LSB_FIRST)
	207	cr \|= XSPI_CR_LSB_FIRST;
	208	if (spi->mode & SPI_LOOP)
	209	cr \|= XSPI_CR_LOOP;
	210	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
	211
	212	/* We do not check spi->max_speed_hz here as the SPI clock
	213	* frequency is not software programmable (the IP block design
	214	* parameter)
	215	*/
	216
	217	cs = xspi->cs_inactive;
	218	cs ^= BIT(spi->chip_select);
	219
	220	/* Activate the chip select */
	221	xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
ae918c02 AK	222	}
	223
	224	/* spi_bitbang requires custom setup_transfer() to be defined if there is a
9bf46f6d	225	* custom txrx_bufs().
ae918c02 AK	226	*/
	227	static int xilinx_spi_setup_transfer(struct spi_device *spi,
	228	struct spi_transfer *t)
	229	{
f9c6ef6c RR	230	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	231
	232	if (spi->mode & SPI_CS_HIGH)
	233	xspi->cs_inactive &= ~BIT(spi->chip_select);
	234	else
	235	xspi->cs_inactive \|= BIT(spi->chip_select);
	236
ae918c02 AK	237	return 0;
	238	}
	239
ae918c02 AK	240	static int xilinx_spi_txrx_bufs(struct spi_device spi, struct spi_transfer t)
	241	{
	242	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
b563bfb8	243	int remaining_words; /* the number of words left to transfer */
22417352 RR	244	bool use_irq = false;
22417352 RR	245	u16 cr = 0;
ae918c02 AK	246
	247	/* We get here with transmitter inhibited */
	248
	249	xspi->tx_ptr = t->tx_buf;
	250	xspi->rx_ptr = t->rx_buf;
b563bfb8	251	remaining_words = t->len / xspi->bytes_per_word;
ae918c02	252
22417352	253	if (xspi->irq >= 0 && remaining_words > xspi->buffer_size) {
74346841	254	u32 isr;
22417352	255	use_irq = true;
22417352 RR	256	/* Inhibit irq to avoid spurious irqs on tx_empty*/
	257	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
	258	xspi->write_fn(cr \| XSPI_CR_TRANS_INHIBIT,
	259	xspi->regs + XSPI_CR_OFFSET);
74346841 RR	260	/* ACK old irqs (if any) */
	261	isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
	262	if (isr)
	263	xspi->write_fn(isr,
	264	xspi->regs + XIPIF_V123B_IISR_OFFSET);
	265	/* Enable the global IPIF interrupt */
	266	xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
	267	xspi->regs + XIPIF_V123B_DGIER_OFFSET);
	268	reinit_completion(&xspi->done);
22417352 RR	269	}
22417352 RR	270
b563bfb8	271	while (remaining_words) {
b563bfb8	272	int n_words, tx_words, rx_words;
eca37c7c	273	u32 sr;
5a1314fa	274	int stalled;
68c315bb	275
b563bfb8	276	n_words = min(remaining_words, xspi->buffer_size);
4c9a7614	277
b563bfb8 RR	278	tx_words = n_words;
	279	while (tx_words--)
	280	xilinx_spi_tx(xspi);
68c315bb PC	281
	282	/* Start the transfer by not inhibiting the transmitter any
	283	* longer
	284	*/
68c315bb	285
22417352	286	if (use_irq) {
d9f58812	287	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
5fe11cc0	288	wait_for_completion(&xspi->done);
eca37c7c RR	289	/* A transmit has just completed. Process received data
	290	* and check for more data to transmit. Always inhibit
	291	* the transmitter while the Isr refills the transmit
	292	* register/FIFO, or make sure it is stopped if we're
	293	* done.
	294	*/
d9f58812	295	xspi->write_fn(cr \| XSPI_CR_TRANS_INHIBIT,
eca37c7c RR	296	xspi->regs + XSPI_CR_OFFSET);
	297	sr = XSPI_SR_TX_EMPTY_MASK;
	298	} else
	299	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
68c315bb PC	300
68c315bb PC	301	/* Read out all the data from the Rx FIFO */
b563bfb8	302	rx_words = n_words;
5a1314fa	303	stalled = 10;
eca37c7c	304	while (rx_words) {
5a1314fa RR	305	if (rx_words == n_words && !(stalled--) &&
	306	!(sr & XSPI_SR_TX_EMPTY_MASK) &&
	307	(sr & XSPI_SR_RX_EMPTY_MASK)) {
	308	dev_err(&spi->dev,
	309	"Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n");
	310	xspi_init_hw(xspi);
	311	return -EIO;
	312	}
	313
eca37c7c RR	314	if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) {
	315	xilinx_spi_rx(xspi);
	316	rx_words--;
	317	continue;
	318	}
	319
	320	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
	321	if (!(sr & XSPI_SR_RX_EMPTY_MASK)) {
	322	xilinx_spi_rx(xspi);
	323	rx_words--;
	324	}
	325	}
b563bfb8 RR	326
b563bfb8 RR	327	remaining_words -= n_words;
68c315bb	328	}
ae918c02	329
16ea9b8a	330	if (use_irq) {
22417352	331	xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
16ea9b8a RR	332	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
16ea9b8a RR	333	}
22417352	334
d79b2d07	335	return t->len;
ae918c02 AK	336	}
	337
	338
	339	/* This driver supports single master mode only. Hence Tx FIFO Empty
	340	* is the only interrupt we care about.
	341	* Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
	342	* Fault are not to happen.
	343	*/
	344	static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
	345	{
	346	struct xilinx_spi *xspi = dev_id;
	347	u32 ipif_isr;
	348
	349	/* Get the IPIF interrupts, and clear them immediately */
86fc5935 RR	350	ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
86fc5935 RR	351	xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
ae918c02 AK	352
ae918c02 AK	353	if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
68c315bb	354	complete(&xspi->done);
d3364847	355	return IRQ_HANDLED;
ae918c02 AK	356	}
ae918c02 AK	357
d3364847	358	return IRQ_NONE;
ae918c02 AK	359	}
ae918c02 AK	360
4c9a7614 RR	361	static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
	362	{
	363	u8 sr;
	364	int n_words = 0;
	365
	366	/*
	367	* Before the buffer_size detection we reset the core
	368	* to make sure we start with a clean state.
	369	*/
	370	xspi->write_fn(XIPIF_V123B_RESET_MASK,
	371	xspi->regs + XIPIF_V123B_RESETR_OFFSET);
	372
	373	/* Fill the Tx FIFO with as many words as possible */
	374	do {
	375	xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
	376	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
	377	n_words++;
	378	} while (!(sr & XSPI_SR_TX_FULL_MASK));
	379
	380	return n_words;
	381	}
	382
eae6cb31	383	static const struct of_device_id xilinx_spi_of_match[] = {
a094c2fa	384	{ .compatible = "xlnx,axi-quad-spi-1.00.a", },
eae6cb31 GL	385	{ .compatible = "xlnx,xps-spi-2.00.a", },
	386	{ .compatible = "xlnx,xps-spi-2.00.b", },
	387	{}
	388	};
	389	MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
eae6cb31	390
7cb2abd0	391	static int xilinx_spi_probe(struct platform_device *pdev)
ae918c02	392	{
ae918c02	393	struct xilinx_spi *xspi;
d81c0bbb	394	struct xspi_platform_data *pdata;
ad3fdbca	395	struct resource *res;
7b3b7432	396	int ret, num_cs = 0, bits_per_word = 8;
d81c0bbb	397	struct spi_master *master;
082339bc	398	u32 tmp;
d81c0bbb MB	399	u8 i;
d81c0bbb MB	400
8074cf06	401	pdata = dev_get_platdata(&pdev->dev);
d81c0bbb MB	402	if (pdata) {
	403	num_cs = pdata->num_chipselect;
	404	bits_per_word = pdata->bits_per_word;
be3acdff MS	405	} else {
	406	of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
	407	&num_cs);
d81c0bbb	408	}
ae918c02	409
d81c0bbb	410	if (!num_cs) {
7cb2abd0 MB	411	dev_err(&pdev->dev,
7cb2abd0 MB	412	"Missing slave select configuration data\n");
d81c0bbb MB	413	return -EINVAL;
	414	}
	415
eb25f16c RR	416	if (num_cs > XILINX_SPI_MAX_CS) {
	417	dev_err(&pdev->dev, "Invalid number of spi slaves\n");
	418	return -EINVAL;
	419	}
	420
7cb2abd0	421	master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
d5af91a1	422	if (!master)
d81c0bbb	423	return -ENODEV;
ae918c02	424
e7db06b5	425	/* the spi->mode bits understood by this driver: */
f9c6ef6c RR	426	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_LSB_FIRST \| SPI_LOOP \|
f9c6ef6c RR	427	SPI_CS_HIGH;
e7db06b5	428
ae918c02	429	xspi = spi_master_get_devdata(master);
f9c6ef6c	430	xspi->cs_inactive = 0xffffffff;
94c69f76	431	xspi->bitbang.master = master;
ae918c02 AK	432	xspi->bitbang.chipselect = xilinx_spi_chipselect;
	433	xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
	434	xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
ae918c02 AK	435	init_completion(&xspi->done);
ae918c02 AK	436
ad3fdbca MS	437	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ad3fdbca MS	438	xspi->regs = devm_ioremap_resource(&pdev->dev, res);
c40537d0 MB	439	if (IS_ERR(xspi->regs)) {
c40537d0 MB	440	ret = PTR_ERR(xspi->regs);
ae918c02	441	goto put_master;
ae918c02 AK	442	}
ae918c02 AK	443
4b153a21	444	master->bus_num = pdev->id;
91565c40	445	master->num_chipselect = num_cs;
7cb2abd0	446	master->dev.of_node = pdev->dev.of_node;
082339bc MS	447
	448	/*
	449	* Detect endianess on the IP via loop bit in CR. Detection
	450	* must be done before reset is sent because incorrect reset
	451	* value generates error interrupt.
	452	* Setup little endian helper functions first and try to use them
	453	* and check if bit was correctly setup or not.
	454	*/
0635287a MB	455	xspi->read_fn = xspi_read32;
0635287a MB	456	xspi->write_fn = xspi_write32;
082339bc MS	457
	458	xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
	459	tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
	460	tmp &= XSPI_CR_LOOP;
	461	if (tmp != XSPI_CR_LOOP) {
0635287a MB	462	xspi->read_fn = xspi_read32_be;
0635287a MB	463	xspi->write_fn = xspi_write32_be;
86fc5935	464	}
082339bc	465
9bf46f6d	466	master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
17aaaa80	467	xspi->bytes_per_word = bits_per_word / 8;
4c9a7614 RR	468	xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);
4c9a7614 RR	469
7b3b7432	470	xspi->irq = platform_get_irq(pdev, 0);
4db9bf54 LPC	471	if (xspi->irq < 0 && xspi->irq != -ENXIO) {
	472	ret = xspi->irq;
	473	goto put_master;
	474	} else if (xspi->irq >= 0) {
5fe11cc0 RR	475	/* Register for SPI Interrupt */
	476	ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
	477	dev_name(&pdev->dev), xspi);
	478	if (ret)
	479	goto put_master;
7b3b7432 MS	480	}
7b3b7432 MS	481
5fe11cc0 RR	482	/* SPI controller initializations */
5fe11cc0 RR	483	xspi_init_hw(xspi);
ae918c02	484
d5af91a1 RR	485	ret = spi_bitbang_start(&xspi->bitbang);
d5af91a1 RR	486	if (ret) {
7cb2abd0	487	dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
7b3b7432	488	goto put_master;
eae6cb31 GL	489	}
eae6cb31 GL	490
7cb2abd0	491	dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
ad3fdbca	492	(unsigned long long)res->start, xspi->regs, xspi->irq);
8fd8821b	493
eae6cb31 GL	494	if (pdata) {
	495	for (i = 0; i < pdata->num_devices; i++)
	496	spi_new_device(master, pdata->devices + i);
	497	}
8fd8821b	498
7cb2abd0	499	platform_set_drvdata(pdev, master);
8fd8821b	500	return 0;
ae918c02	501
ae918c02 AK	502	put_master:
ae918c02 AK	503	spi_master_put(master);
d81c0bbb MB	504
d81c0bbb MB	505	return ret;
8fd8821b GL	506	}
8fd8821b GL	507
7cb2abd0	508	static int xilinx_spi_remove(struct platform_device *pdev)
8fd8821b	509	{
7cb2abd0	510	struct spi_master *master = platform_get_drvdata(pdev);
d81c0bbb	511	struct xilinx_spi *xspi = spi_master_get_devdata(master);
7b3b7432	512	void __iomem *regs_base = xspi->regs;
ae918c02 AK	513
ae918c02 AK	514	spi_bitbang_stop(&xspi->bitbang);
7b3b7432 MS	515
	516	/* Disable all the interrupts just in case */
	517	xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
	518	/* Disable the global IPIF interrupt */
	519	xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
ff82c587	520
d5af91a1	521	spi_master_put(xspi->bitbang.master);
8fd8821b GL	522
	523	return 0;
	524	}
	525
	526	/* work with hotplug and coldplug */
	527	MODULE_ALIAS("platform:" XILINX_SPI_NAME);
	528
	529	static struct platform_driver xilinx_spi_driver = {
	530	.probe = xilinx_spi_probe,
fd4a319b	531	.remove = xilinx_spi_remove,
8fd8821b GL	532	.driver = {
8fd8821b GL	533	.name = XILINX_SPI_NAME,
eae6cb31	534	.of_match_table = xilinx_spi_of_match,
8fd8821b GL	535	},
8fd8821b GL	536	};
940ab889	537	module_platform_driver(xilinx_spi_driver);
8fd8821b	538
ae918c02 AK	539	MODULE_AUTHOR("MontaVista Software, Inc. <[email protected]>");
	540	MODULE_DESCRIPTION("Xilinx SPI driver");
	541	MODULE_LICENSE("GPL");