[linux.git] / drivers / gpio / gpio-stmpe.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License, version 2
 * Author: Rabin Vincent <[email protected]> for ST-Ericsson
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/mfd/stmpe.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_RE, REG_FE, REG_IE };

#define CACHE_NR_REGS	3
/* No variant has more than 24 GPIOs */
#define CACHE_NR_BANKS	(24 / 8)

struct stmpe_gpio {
	struct gpio_chip chip;
	struct stmpe *stmpe;
	struct device *dev;
	struct mutex irq_lock;
	struct irq_domain *domain;
	unsigned norequest_mask;

	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
{
	return container_of(chip, struct stmpe_gpio, chip);
}

static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	return !!(ret & mask);
}

static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	u8 reg = stmpe->regs[which] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	/*
	 * Some variants have single register for gpio set/clear functionality.
	 * For them we need to write 0 to clear and 1 to set.
	 */
	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
		stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	else
		stmpe_reg_write(stmpe, reg, mask);
}

static int stmpe_gpio_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	stmpe_gpio_set(chip, offset, val);

	return stmpe_set_bits(stmpe, reg, mask, mask);
}

static int stmpe_gpio_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	return stmpe_set_bits(stmpe, reg, mask, 0);
}

static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);

	return irq_create_mapping(stmpe_gpio->domain, offset);
}

static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;

	if (stmpe_gpio->norequest_mask & (1 << offset))
		return -EINVAL;

	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
}

static struct gpio_chip template_chip = {
	.label			= "stmpe",
	.owner			= THIS_MODULE,
	.direction_input	= stmpe_gpio_direction_input,
	.get			= stmpe_gpio_get,
	.direction_output	= stmpe_gpio_direction_output,
	.set			= stmpe_gpio_set,
	.to_irq			= stmpe_gpio_to_irq,
	.request		= stmpe_gpio_request,
	.can_sleep		= true,
};

static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
		return -EINVAL;

	/* STMPE801 doesn't have RE and FE registers */
	if (stmpe_gpio->stmpe->partnum == STMPE801)
		return 0;

	if (type == IRQ_TYPE_EDGE_RISING)
		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;

	if (type == IRQ_TYPE_EDGE_FALLING)
		stmpe_gpio->regs[REG_FE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;

	return 0;
}

static void stmpe_gpio_irq_lock(struct irq_data *d)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);

	mutex_lock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	static const u8 regmap[] = {
		[REG_RE]	= STMPE_IDX_GPRER_LSB,
		[REG_FE]	= STMPE_IDX_GPFER_LSB,
		[REG_IE]	= STMPE_IDX_IEGPIOR_LSB,
	};
	int i, j;

	for (i = 0; i < CACHE_NR_REGS; i++) {
		/* STMPE801 doesn't have RE and FE registers */
		if ((stmpe->partnum == STMPE801) &&
				(i != REG_IE))
			continue;

		for (j = 0; j < num_banks; j++) {
			u8 old = stmpe_gpio->oldregs[i][j];
			u8 new = stmpe_gpio->regs[i][j];

			if (new == old)
				continue;

			stmpe_gpio->oldregs[i][j] = new;
			stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
		}
	}

	mutex_unlock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_mask(struct irq_data *d)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
}

static void stmpe_gpio_irq_unmask(struct irq_data *d)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] |= mask;
}

static struct irq_chip stmpe_gpio_irq_chip = {
	.name			= "stmpe-gpio",
	.irq_bus_lock		= stmpe_gpio_irq_lock,
	.irq_bus_sync_unlock	= stmpe_gpio_irq_sync_unlock,
	.irq_mask		= stmpe_gpio_irq_mask,
	.irq_unmask		= stmpe_gpio_irq_unmask,
	.irq_set_type		= stmpe_gpio_irq_set_type,
};

static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
{
	struct stmpe_gpio *stmpe_gpio = dev;
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	u8 status[num_banks];
	int ret;
	int i;

	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < num_banks; i++) {
		int bank = num_banks - i - 1;
		unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
		unsigned int stat = status[i];

		stat &= enabled;
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = bank * 8 + bit;
			int child_irq = irq_find_mapping(stmpe_gpio->domain,
							 line);

			handle_nested_irq(child_irq);
			stat &= ~(1 << bit);
		}

		stmpe_reg_write(stmpe, statmsbreg + i, status[i]);

		/* Edge detect register is not present on 801 */
		if (stmpe->partnum != STMPE801)
			stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
					+ i, status[i]);
	}

	return IRQ_HANDLED;
}

static int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int irq,
			      irq_hw_number_t hwirq)
{
	struct stmpe_gpio *stmpe_gpio = d->host_data;

	if (!stmpe_gpio)
		return -EINVAL;

	irq_set_chip_data(irq, stmpe_gpio);
	irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
				 handle_simple_irq);
	irq_set_nested_thread(irq, 1);
#ifdef CONFIG_ARM
	set_irq_flags(irq, IRQF_VALID);
#else
	irq_set_noprobe(irq);
#endif

	return 0;
}

static void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
{
#ifdef CONFIG_ARM
	set_irq_flags(irq, 0);
#endif
	irq_set_chip_and_handler(irq, NULL, NULL);
	irq_set_chip_data(irq, NULL);
}

static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
	.unmap = stmpe_gpio_irq_unmap,
	.map = stmpe_gpio_irq_map,
	.xlate = irq_domain_xlate_twocell,
};

static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio,
		struct device_node *np)
{
	stmpe_gpio->domain = irq_domain_add_simple(np,
				stmpe_gpio->chip.ngpio, 0,
				&stmpe_gpio_irq_simple_ops, stmpe_gpio);
	if (!stmpe_gpio->domain) {
		dev_err(stmpe_gpio->dev, "failed to create irqdomain\n");
		return -ENOSYS;
	}

	return 0;
}

static int stmpe_gpio_probe(struct platform_device *pdev)
{
	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
	struct device_node *np = pdev->dev.of_node;
	struct stmpe_gpio_platform_data *pdata;
	struct stmpe_gpio *stmpe_gpio;
	int ret;
	int irq = 0;

	pdata = stmpe->pdata->gpio;

	irq = platform_get_irq(pdev, 0);

	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
	if (!stmpe_gpio)
		return -ENOMEM;

	mutex_init(&stmpe_gpio->irq_lock);

	stmpe_gpio->dev = &pdev->dev;
	stmpe_gpio->stmpe = stmpe;
	stmpe_gpio->chip = template_chip;
	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	stmpe_gpio->chip.dev = &pdev->dev;
#ifdef CONFIG_OF
	stmpe_gpio->chip.of_node = np;
#endif
	stmpe_gpio->chip.base = -1;

	if (pdata)
		stmpe_gpio->norequest_mask = pdata->norequest_mask;
	else if (np)
		of_property_read_u32(np, "st,norequest-mask",
				&stmpe_gpio->norequest_mask);

	if (irq < 0)
		dev_info(&pdev->dev,
			"device configured in no-irq mode; "
			"irqs are not available\n");

	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	if (ret)
		goto out_free;

	if (irq >= 0) {
		ret = stmpe_gpio_irq_init(stmpe_gpio, np);
		if (ret)
			goto out_disable;

		ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
				IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
		if (ret) {
			dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
			goto out_disable;
		}
	}

	ret = gpiochip_add(&stmpe_gpio->chip);
	if (ret) {
		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
		goto out_freeirq;
	}

	if (pdata && pdata->setup)
		pdata->setup(stmpe, stmpe_gpio->chip.base);

	platform_set_drvdata(pdev, stmpe_gpio);

	return 0;

out_freeirq:
	if (irq >= 0)
		free_irq(irq, stmpe_gpio);
out_disable:
	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
out_free:
	kfree(stmpe_gpio);
	return ret;
}

static int stmpe_gpio_remove(struct platform_device *pdev)
{
	struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
	int irq = platform_get_irq(pdev, 0);
	int ret;

	if (pdata && pdata->remove)
		pdata->remove(stmpe, stmpe_gpio->chip.base);

	ret = gpiochip_remove(&stmpe_gpio->chip);
	if (ret < 0) {
		dev_err(stmpe_gpio->dev,
			"unable to remove gpiochip: %d\n", ret);
		return ret;
	}

	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);

	if (irq >= 0)
		free_irq(irq, stmpe_gpio);

	kfree(stmpe_gpio);

	return 0;
}

static struct platform_driver stmpe_gpio_driver = {
	.driver.name	= "stmpe-gpio",
	.driver.owner	= THIS_MODULE,
	.probe		= stmpe_gpio_probe,
	.remove		= stmpe_gpio_remove,
};

static int __init stmpe_gpio_init(void)
{
	return platform_driver_register(&stmpe_gpio_driver);
}
subsys_initcall(stmpe_gpio_init);

static void __exit stmpe_gpio_exit(void)
{
	platform_driver_unregister(&stmpe_gpio_driver);
}
module_exit(stmpe_gpio_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("STMPExxxx GPIO driver");
MODULE_AUTHOR("Rabin Vincent <[email protected]>");
Commit	Line	Data
03f822f5 RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License, version 2
	5	* Author: Rabin Vincent <[email protected]> for ST-Ericsson
	6	*/
	7
	8	#include <linux/module.h>
	9	#include <linux/init.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/slab.h>
	12	#include <linux/gpio.h>
	13	#include <linux/irq.h>
fc13d5a5	14	#include <linux/irqdomain.h>
03f822f5	15	#include <linux/interrupt.h>
86605cfe	16	#include <linux/of.h>
03f822f5 RV	17	#include <linux/mfd/stmpe.h>
	18
	19	/*
	20	* These registers are modified under the irq bus lock and cached to avoid
	21	* unnecessary writes in bus_sync_unlock.
	22	*/
	23	enum { REG_RE, REG_FE, REG_IE };
	24
	25	#define CACHE_NR_REGS 3
9e9dc7d9 LW	26	/* No variant has more than 24 GPIOs */
9e9dc7d9 LW	27	#define CACHE_NR_BANKS (24 / 8)
03f822f5 RV	28
	29	struct stmpe_gpio {
	30	struct gpio_chip chip;
	31	struct stmpe *stmpe;
	32	struct device *dev;
	33	struct mutex irq_lock;
fc13d5a5	34	struct irq_domain *domain;
b8e9cf0b	35	unsigned norequest_mask;
03f822f5 RV	36
	37	/* Caches of interrupt control registers for bus_lock */
	38	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	39	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	40	};
	41
	42	static inline struct stmpe_gpio to_stmpe_gpio(struct gpio_chip chip)
	43	{
	44	return container_of(chip, struct stmpe_gpio, chip);
	45	}
	46
	47	static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
	48	{
	49	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	50	struct stmpe *stmpe = stmpe_gpio->stmpe;
	51	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
	52	u8 mask = 1 << (offset % 8);
	53	int ret;
	54
	55	ret = stmpe_reg_read(stmpe, reg);
	56	if (ret < 0)
	57	return ret;
	58
7535b8be	59	return !!(ret & mask);
03f822f5 RV	60	}
	61
	62	static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	63	{
	64	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	65	struct stmpe *stmpe = stmpe_gpio->stmpe;
	66	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	67	u8 reg = stmpe->regs[which] - (offset / 8);
	68	u8 mask = 1 << (offset % 8);
	69
cccdceb9 VK	70	/*
	71	* Some variants have single register for gpio set/clear functionality.
	72	* For them we need to write 0 to clear and 1 to set.
	73	*/
	74	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
	75	stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	76	else
	77	stmpe_reg_write(stmpe, reg, mask);
03f822f5 RV	78	}
	79
	80	static int stmpe_gpio_direction_output(struct gpio_chip *chip,
	81	unsigned offset, int val)
	82	{
	83	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	84	struct stmpe *stmpe = stmpe_gpio->stmpe;
	85	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	86	u8 mask = 1 << (offset % 8);
	87
	88	stmpe_gpio_set(chip, offset, val);
	89
	90	return stmpe_set_bits(stmpe, reg, mask, mask);
	91	}
	92
	93	static int stmpe_gpio_direction_input(struct gpio_chip *chip,
	94	unsigned offset)
	95	{
	96	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	97	struct stmpe *stmpe = stmpe_gpio->stmpe;
	98	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	99	u8 mask = 1 << (offset % 8);
	100
	101	return stmpe_set_bits(stmpe, reg, mask, 0);
	102	}
	103
	104	static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	105	{
	106	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	107
fc13d5a5	108	return irq_create_mapping(stmpe_gpio->domain, offset);
03f822f5 RV	109	}
	110
	111	static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
	112	{
	113	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	114	struct stmpe *stmpe = stmpe_gpio->stmpe;
	115
b8e9cf0b WS	116	if (stmpe_gpio->norequest_mask & (1 << offset))
	117	return -EINVAL;
	118
03f822f5 RV	119	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
	120	}
	121
	122	static struct gpio_chip template_chip = {
	123	.label = "stmpe",
	124	.owner = THIS_MODULE,
	125	.direction_input = stmpe_gpio_direction_input,
	126	.get = stmpe_gpio_get,
	127	.direction_output = stmpe_gpio_direction_output,
	128	.set = stmpe_gpio_set,
	129	.to_irq = stmpe_gpio_to_irq,
	130	.request = stmpe_gpio_request,
9fb1f39e	131	.can_sleep = true,
03f822f5 RV	132	};
03f822f5 RV	133
2a866f39	134	static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
03f822f5	135	{
2a866f39	136	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
fc13d5a5	137	int offset = d->hwirq;
03f822f5 RV	138	int regoffset = offset / 8;
	139	int mask = 1 << (offset % 8);
	140
	141	if (type == IRQ_TYPE_LEVEL_LOW \|\| type == IRQ_TYPE_LEVEL_HIGH)
	142	return -EINVAL;
	143
cccdceb9 VK	144	/* STMPE801 doesn't have RE and FE registers */
	145	if (stmpe_gpio->stmpe->partnum == STMPE801)
	146	return 0;
	147
03f822f5 RV	148	if (type == IRQ_TYPE_EDGE_RISING)
	149	stmpe_gpio->regs[REG_RE][regoffset] \|= mask;
	150	else
	151	stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
	152
	153	if (type == IRQ_TYPE_EDGE_FALLING)
	154	stmpe_gpio->regs[REG_FE][regoffset] \|= mask;
	155	else
	156	stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
	157
	158	return 0;
	159	}
	160
2a866f39	161	static void stmpe_gpio_irq_lock(struct irq_data *d)
03f822f5	162	{
2a866f39	163	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
03f822f5 RV	164
	165	mutex_lock(&stmpe_gpio->irq_lock);
	166	}
	167
2a866f39	168	static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
03f822f5	169	{
2a866f39	170	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
03f822f5 RV	171	struct stmpe *stmpe = stmpe_gpio->stmpe;
	172	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	173	static const u8 regmap[] = {
	174	[REG_RE] = STMPE_IDX_GPRER_LSB,
	175	[REG_FE] = STMPE_IDX_GPFER_LSB,
	176	[REG_IE] = STMPE_IDX_IEGPIOR_LSB,
	177	};
	178	int i, j;
	179
	180	for (i = 0; i < CACHE_NR_REGS; i++) {
cccdceb9 VK	181	/* STMPE801 doesn't have RE and FE registers */
	182	if ((stmpe->partnum == STMPE801) &&
	183	(i != REG_IE))
	184	continue;
	185
03f822f5 RV	186	for (j = 0; j < num_banks; j++) {
	187	u8 old = stmpe_gpio->oldregs[i][j];
	188	u8 new = stmpe_gpio->regs[i][j];
	189
	190	if (new == old)
	191	continue;
	192
	193	stmpe_gpio->oldregs[i][j] = new;
	194	stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
	195	}
	196	}
	197
	198	mutex_unlock(&stmpe_gpio->irq_lock);
	199	}
	200
2a866f39	201	static void stmpe_gpio_irq_mask(struct irq_data *d)
03f822f5	202	{
2a866f39	203	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
fc13d5a5	204	int offset = d->hwirq;
03f822f5 RV	205	int regoffset = offset / 8;
	206	int mask = 1 << (offset % 8);
	207
	208	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
	209	}
	210
2a866f39	211	static void stmpe_gpio_irq_unmask(struct irq_data *d)
03f822f5	212	{
2a866f39	213	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
fc13d5a5	214	int offset = d->hwirq;
03f822f5 RV	215	int regoffset = offset / 8;
	216	int mask = 1 << (offset % 8);
	217
	218	stmpe_gpio->regs[REG_IE][regoffset] \|= mask;
	219	}
	220
	221	static struct irq_chip stmpe_gpio_irq_chip = {
	222	.name = "stmpe-gpio",
2a866f39 LB	223	.irq_bus_lock = stmpe_gpio_irq_lock,
	224	.irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
	225	.irq_mask = stmpe_gpio_irq_mask,
	226	.irq_unmask = stmpe_gpio_irq_unmask,
	227	.irq_set_type = stmpe_gpio_irq_set_type,
03f822f5 RV	228	};
	229
	230	static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
	231	{
	232	struct stmpe_gpio *stmpe_gpio = dev;
	233	struct stmpe *stmpe = stmpe_gpio->stmpe;
	234	u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	235	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	236	u8 status[num_banks];
	237	int ret;
	238	int i;
	239
	240	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	241	if (ret < 0)
	242	return IRQ_NONE;
	243
	244	for (i = 0; i < num_banks; i++) {
	245	int bank = num_banks - i - 1;
	246	unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
	247	unsigned int stat = status[i];
	248
	249	stat &= enabled;
	250	if (!stat)
	251	continue;
	252
	253	while (stat) {
	254	int bit = __ffs(stat);
	255	int line = bank * 8 + bit;
ed05e204 LW	256	int child_irq = irq_find_mapping(stmpe_gpio->domain,
ed05e204 LW	257	line);
03f822f5	258
ed05e204	259	handle_nested_irq(child_irq);
03f822f5 RV	260	stat &= ~(1 << bit);
	261	}
	262
	263	stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
cccdceb9 VK	264
	265	/* Edge detect register is not present on 801 */
	266	if (stmpe->partnum != STMPE801)
	267	stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
	268	+ i, status[i]);
03f822f5 RV	269	}
	270
	271	return IRQ_HANDLED;
	272	}
	273
ed05e204	274	static int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int irq,
8700d0af	275	irq_hw_number_t hwirq)
03f822f5	276	{
fc13d5a5 LJ	277	struct stmpe_gpio *stmpe_gpio = d->host_data;
	278
	279	if (!stmpe_gpio)
	280	return -EINVAL;
03f822f5	281
ed05e204 LW	282	irq_set_chip_data(irq, stmpe_gpio);
ed05e204 LW	283	irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
fc13d5a5	284	handle_simple_irq);
ed05e204	285	irq_set_nested_thread(irq, 1);
03f822f5	286	#ifdef CONFIG_ARM
ed05e204	287	set_irq_flags(irq, IRQF_VALID);
03f822f5	288	#else
ed05e204	289	irq_set_noprobe(irq);
03f822f5	290	#endif
03f822f5 RV	291
	292	return 0;
	293	}
	294
ed05e204	295	static void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
03f822f5	296	{
03f822f5	297	#ifdef CONFIG_ARM
ed05e204	298	set_irq_flags(irq, 0);
03f822f5	299	#endif
ed05e204 LW	300	irq_set_chip_and_handler(irq, NULL, NULL);
ed05e204 LW	301	irq_set_chip_data(irq, NULL);
fc13d5a5 LJ	302	}
	303
	304	static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
	305	.unmap = stmpe_gpio_irq_unmap,
	306	.map = stmpe_gpio_irq_map,
	307	.xlate = irq_domain_xlate_twocell,
	308	};
	309
9afd9b70 GF	310	static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio,
9afd9b70 GF	311	struct device_node *np)
fc13d5a5	312	{
9afd9b70	313	stmpe_gpio->domain = irq_domain_add_simple(np,
9e9dc7d9	314	stmpe_gpio->chip.ngpio, 0,
fc13d5a5 LJ	315	&stmpe_gpio_irq_simple_ops, stmpe_gpio);
	316	if (!stmpe_gpio->domain) {
	317	dev_err(stmpe_gpio->dev, "failed to create irqdomain\n");
	318	return -ENOSYS;
03f822f5	319	}
fc13d5a5 LJ	320
fc13d5a5 LJ	321	return 0;
03f822f5 RV	322	}
03f822f5 RV	323
3836309d	324	static int stmpe_gpio_probe(struct platform_device *pdev)
03f822f5 RV	325	{
03f822f5 RV	326	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
86605cfe	327	struct device_node *np = pdev->dev.of_node;
03f822f5 RV	328	struct stmpe_gpio_platform_data *pdata;
	329	struct stmpe_gpio *stmpe_gpio;
	330	int ret;
38040c85	331	int irq = 0;
03f822f5 RV	332
03f822f5 RV	333	pdata = stmpe->pdata->gpio;
03f822f5 RV	334
03f822f5 RV	335	irq = platform_get_irq(pdev, 0);
03f822f5 RV	336
	337	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
	338	if (!stmpe_gpio)
	339	return -ENOMEM;
	340
	341	mutex_init(&stmpe_gpio->irq_lock);
	342
	343	stmpe_gpio->dev = &pdev->dev;
	344	stmpe_gpio->stmpe = stmpe;
03f822f5 RV	345	stmpe_gpio->chip = template_chip;
	346	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	347	stmpe_gpio->chip.dev = &pdev->dev;
9afd9b70 GF	348	#ifdef CONFIG_OF
	349	stmpe_gpio->chip.of_node = np;
	350	#endif
9e9dc7d9	351	stmpe_gpio->chip.base = -1;
03f822f5	352
86605cfe VKS	353	if (pdata)
	354	stmpe_gpio->norequest_mask = pdata->norequest_mask;
	355	else if (np)
	356	of_property_read_u32(np, "st,norequest-mask",
	357	&stmpe_gpio->norequest_mask);
	358
9e9dc7d9	359	if (irq < 0)
38040c85 CB	360	dev_info(&pdev->dev,
	361	"device configured in no-irq mode; "
	362	"irqs are not available\n");
03f822f5 RV	363
	364	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	365	if (ret)
02bf0749	366	goto out_free;
03f822f5	367
38040c85	368	if (irq >= 0) {
9afd9b70	369	ret = stmpe_gpio_irq_init(stmpe_gpio, np);
38040c85 CB	370	if (ret)
38040c85 CB	371	goto out_disable;
03f822f5	372
38040c85 CB	373	ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
	374	IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
	375	if (ret) {
	376	dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
fc13d5a5	377	goto out_disable;
38040c85	378	}
03f822f5 RV	379	}
	380
	381	ret = gpiochip_add(&stmpe_gpio->chip);
	382	if (ret) {
	383	dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
	384	goto out_freeirq;
	385	}
	386
	387	if (pdata && pdata->setup)
	388	pdata->setup(stmpe, stmpe_gpio->chip.base);
	389
	390	platform_set_drvdata(pdev, stmpe_gpio);
	391
	392	return 0;
	393
	394	out_freeirq:
38040c85 CB	395	if (irq >= 0)
38040c85 CB	396	free_irq(irq, stmpe_gpio);
02bf0749 VK	397	out_disable:
02bf0749 VK	398	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
03f822f5 RV	399	out_free:
	400	kfree(stmpe_gpio);
	401	return ret;
	402	}
	403
206210ce	404	static int stmpe_gpio_remove(struct platform_device *pdev)
03f822f5 RV	405	{
	406	struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
	407	struct stmpe *stmpe = stmpe_gpio->stmpe;
	408	struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
	409	int irq = platform_get_irq(pdev, 0);
	410	int ret;
	411
	412	if (pdata && pdata->remove)
	413	pdata->remove(stmpe, stmpe_gpio->chip.base);
	414
	415	ret = gpiochip_remove(&stmpe_gpio->chip);
	416	if (ret < 0) {
	417	dev_err(stmpe_gpio->dev,
	418	"unable to remove gpiochip: %d\n", ret);
	419	return ret;
	420	}
	421
	422	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
	423
fc13d5a5	424	if (irq >= 0)
38040c85	425	free_irq(irq, stmpe_gpio);
fc13d5a5	426
03f822f5 RV	427	kfree(stmpe_gpio);
	428
	429	return 0;
	430	}
	431
	432	static struct platform_driver stmpe_gpio_driver = {
	433	.driver.name = "stmpe-gpio",
	434	.driver.owner = THIS_MODULE,
	435	.probe = stmpe_gpio_probe,
8283c4ff	436	.remove = stmpe_gpio_remove,
03f822f5 RV	437	};
	438
	439	static int __init stmpe_gpio_init(void)
	440	{
	441	return platform_driver_register(&stmpe_gpio_driver);
	442	}
	443	subsys_initcall(stmpe_gpio_init);
	444
	445	static void __exit stmpe_gpio_exit(void)
	446	{
	447	platform_driver_unregister(&stmpe_gpio_driver);
	448	}
	449	module_exit(stmpe_gpio_exit);
	450
	451	MODULE_LICENSE("GPL v2");
	452	MODULE_DESCRIPTION("STMPExxxx GPIO driver");
	453	MODULE_AUTHOR("Rabin Vincent <[email protected]>");