[linux.git] / drivers / pwm / pwm-omap-dmtimer.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2015 Neil Armstrong <[email protected]>
 * Copyright (c) 2014 Joachim Eastwood <[email protected]>
 * Copyright (c) 2012 NeilBrown <[email protected]>
 * Heavily based on earlier code which is:
 * Copyright (c) 2010 Grant Erickson <[email protected]>
 *
 * Also based on pwm-samsung.c
 *
 * Description:
 *   This file is the core OMAP support for the generic, Linux
 *   PWM driver / controller, using the OMAP's dual-mode timers
 *   with a timer counter that goes up. When it overflows it gets
 *   reloaded with the load value and the pwm output goes up.
 *   When counter matches with match register, the output goes down.
 *   Reference Manual: https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf
 *
 * Limitations:
 * - When PWM is stopped, timer counter gets stopped immediately. This
 *   doesn't allow the current PWM period to complete and stops abruptly.
 * - When PWM is running and changing both duty cycle and period,
 *   we cannot prevent in software that the output might produce
 *   a period with mixed settings. Especially when period/duty_cyle
 *   is updated while the pwm pin is high, current pwm period/duty_cycle
 *   can get updated as below based on the current timer counter:
 *   	- period for current cycle =  current_period + new period
 *   	- duty_cycle for current period = current period + new duty_cycle.
 * - PWM OMAP DM timer cannot change the polarity when pwm is active. When
 *   user requests a change in polarity when in active state:
 *	- PWM is stopped abruptly(without completing the current cycle)
 *	- Polarity is changed
 *	- A fresh cycle is started.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <clocksource/timer-ti-dm.h>
#include <linux/platform_data/dmtimer-omap.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/time.h>

#define DM_TIMER_LOAD_MIN 0xfffffffe
#define DM_TIMER_MAX      0xffffffff

/**
 * struct pwm_omap_dmtimer_chip - Structure representing a pwm chip
 *				  corresponding to omap dmtimer.
 * @chip:		PWM chip structure representing PWM controller
 * @mutex:		Mutex to protect pwm apply state
 * @dm_timer:		Pointer to omap dm timer.
 * @pdata:		Pointer to omap dm timer ops.
 * @dm_timer_pdev:	Pointer to omap dm timer platform device
 */
struct pwm_omap_dmtimer_chip {
	struct pwm_chip chip;
	/* Mutex to protect pwm apply state */
	struct mutex mutex;
	struct omap_dm_timer *dm_timer;
	const struct omap_dm_timer_ops *pdata;
	struct platform_device *dm_timer_pdev;
};

static inline struct pwm_omap_dmtimer_chip *
to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
}

/**
 * pwm_omap_dmtimer_get_clock_cycles() - Get clock cycles in a time frame
 * @clk_rate:	pwm timer clock rate
 * @ns:		time frame in nano seconds.
 *
 * Return number of clock cycles in a given period(ins ns).
 */
static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
{
	return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
}

/**
 * pwm_omap_dmtimer_start() - Start the pwm omap dm timer in pwm mode
 * @omap:	Pointer to pwm omap dm timer chip
 */
static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
{
	/*
	 * According to OMAP 4 TRM section 22.2.4.10 the counter should be
	 * started at 0xFFFFFFFE when overflow and match is used to ensure
	 * that the PWM line is toggled on the first event.
	 *
	 * Note that omap_dm_timer_enable/disable is for register access and
	 * not the timer counter itself.
	 */
	omap->pdata->enable(omap->dm_timer);
	omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
	omap->pdata->disable(omap->dm_timer);

	omap->pdata->start(omap->dm_timer);
}

/**
 * pwm_omap_dmtimer_is_enabled() -  Detect if the pwm is enabled.
 * @omap:	Pointer to pwm omap dm timer chip
 *
 * Return true if pwm is enabled else false.
 */
static bool pwm_omap_dmtimer_is_enabled(struct pwm_omap_dmtimer_chip *omap)
{
	u32 status;

	status = omap->pdata->get_pwm_status(omap->dm_timer);

	return !!(status & OMAP_TIMER_CTRL_ST);
}

/**
 * pwm_omap_dmtimer_polarity() -  Detect the polarity of pwm.
 * @omap:	Pointer to pwm omap dm timer chip
 *
 * Return the polarity of pwm.
 */
static int pwm_omap_dmtimer_polarity(struct pwm_omap_dmtimer_chip *omap)
{
	u32 status;

	status = omap->pdata->get_pwm_status(omap->dm_timer);

	return !!(status & OMAP_TIMER_CTRL_SCPWM);
}

/**
 * pwm_omap_dmtimer_config() - Update the configuration of pwm omap dm timer
 * @chip:	Pointer to PWM controller
 * @pwm:	Pointer to PWM channel
 * @duty_ns:	New duty cycle in nano seconds
 * @period_ns:	New period in nano seconds
 *
 * Return 0 if successfully changed the period/duty_cycle else appropriate
 * error.
 */
static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
				   struct pwm_device *pwm,
				   int duty_ns, int period_ns)
{
	struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
	u32 period_cycles, duty_cycles;
	u32 load_value, match_value;
	unsigned long clk_rate;
	struct clk *fclk;

	dev_dbg(chip->dev, "requested duty cycle: %d ns, period: %d ns\n",
		duty_ns, period_ns);

	if (duty_ns == pwm_get_duty_cycle(pwm) &&
	    period_ns == pwm_get_period(pwm))
		return 0;

	fclk = omap->pdata->get_fclk(omap->dm_timer);
	if (!fclk) {
		dev_err(chip->dev, "invalid pmtimer fclk\n");
		return -EINVAL;
	}

	clk_rate = clk_get_rate(fclk);
	if (!clk_rate) {
		dev_err(chip->dev, "invalid pmtimer fclk rate\n");
		return -EINVAL;
	}

	dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);

	/*
	 * Calculate the appropriate load and match values based on the
	 * specified period and duty cycle. The load value determines the
	 * period time and the match value determines the duty time.
	 *
	 * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
	 * Similarly, the active time lasts (match_value-load_value+1) cycles.
	 * The non-active time is the remainder: (DM_TIMER_MAX-match_value)
	 * clock cycles.
	 *
	 * NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
	 *
	 * References:
	 *   OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
	 *   AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
	 */
	period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
	duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);

	if (period_cycles < 2) {
		dev_info(chip->dev,
			 "period %d ns too short for clock rate %lu Hz\n",
			 period_ns, clk_rate);
		return -EINVAL;
	}

	if (duty_cycles < 1) {
		dev_dbg(chip->dev,
			"duty cycle %d ns is too short for clock rate %lu Hz\n",
			duty_ns, clk_rate);
		dev_dbg(chip->dev, "using minimum of 1 clock cycle\n");
		duty_cycles = 1;
	} else if (duty_cycles >= period_cycles) {
		dev_dbg(chip->dev,
			"duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
			duty_ns, period_ns, clk_rate);
		dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n");
		duty_cycles = period_cycles - 1;
	}

	dev_dbg(chip->dev, "effective duty cycle: %lld ns, period: %lld ns\n",
		DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles,
				      clk_rate),
		DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles,
				      clk_rate));

	load_value = (DM_TIMER_MAX - period_cycles) + 1;
	match_value = load_value + duty_cycles - 1;

	omap->pdata->set_load(omap->dm_timer, load_value);
	omap->pdata->set_match(omap->dm_timer, true, match_value);

	dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
		load_value, load_value,	match_value, match_value);

	return 0;
}

/**
 * pwm_omap_dmtimer_set_polarity() - Changes the polarity of the pwm dm timer.
 * @chip:	Pointer to PWM controller
 * @pwm:	Pointer to PWM channel
 * @polarity:	New pwm polarity to be set
 */
static void pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
					  struct pwm_device *pwm,
					  enum pwm_polarity polarity)
{
	struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
	bool enabled;

	/* Disable the PWM before changing the polarity. */
	enabled = pwm_omap_dmtimer_is_enabled(omap);
	if (enabled)
		omap->pdata->stop(omap->dm_timer);

	omap->pdata->set_pwm(omap->dm_timer,
			     polarity == PWM_POLARITY_INVERSED,
			     true, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
			     true);

	if (enabled)
		pwm_omap_dmtimer_start(omap);
}

/**
 * pwm_omap_dmtimer_apply() - Changes the state of the pwm omap dm timer.
 * @chip:	Pointer to PWM controller
 * @pwm:	Pointer to PWM channel
 * @state:	New state to apply
 *
 * Return 0 if successfully changed the state else appropriate error.
 */
static int pwm_omap_dmtimer_apply(struct pwm_chip *chip,
				  struct pwm_device *pwm,
				  const struct pwm_state *state)
{
	struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
	int ret = 0;

	mutex_lock(&omap->mutex);

	if (pwm_omap_dmtimer_is_enabled(omap) && !state->enabled) {
		omap->pdata->stop(omap->dm_timer);
		goto unlock_mutex;
	}

	if (pwm_omap_dmtimer_polarity(omap) != state->polarity)
		pwm_omap_dmtimer_set_polarity(chip, pwm, state->polarity);

	ret = pwm_omap_dmtimer_config(chip, pwm, state->duty_cycle,
				      state->period);
	if (ret)
		goto unlock_mutex;

	if (!pwm_omap_dmtimer_is_enabled(omap) && state->enabled) {
		omap->pdata->set_pwm(omap->dm_timer,
				     state->polarity == PWM_POLARITY_INVERSED,
				     true,
				     OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
				     true);
		pwm_omap_dmtimer_start(omap);
	}

unlock_mutex:
	mutex_unlock(&omap->mutex);

	return ret;
}

static const struct pwm_ops pwm_omap_dmtimer_ops = {
	.apply = pwm_omap_dmtimer_apply,
	.owner = THIS_MODULE,
};

static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct dmtimer_platform_data *timer_pdata;
	const struct omap_dm_timer_ops *pdata;
	struct platform_device *timer_pdev;
	struct pwm_omap_dmtimer_chip *omap;
	struct omap_dm_timer *dm_timer;
	struct device_node *timer;
	int ret = 0;
	u32 v;

	timer = of_parse_phandle(np, "ti,timers", 0);
	if (!timer)
		return -ENODEV;

	timer_pdev = of_find_device_by_node(timer);
	if (!timer_pdev) {
		dev_err(&pdev->dev, "Unable to find Timer pdev\n");
		ret = -ENODEV;
		goto err_find_timer_pdev;
	}

	timer_pdata = dev_get_platdata(&timer_pdev->dev);
	if (!timer_pdata) {
		dev_dbg(&pdev->dev,
			 "dmtimer pdata structure NULL, deferring probe\n");
		ret = -EPROBE_DEFER;
		goto err_platdata;
	}

	pdata = timer_pdata->timer_ops;

	if (!pdata || !pdata->request_by_node ||
	    !pdata->free ||
	    !pdata->enable ||
	    !pdata->disable ||
	    !pdata->get_fclk ||
	    !pdata->start ||
	    !pdata->stop ||
	    !pdata->set_load ||
	    !pdata->set_match ||
	    !pdata->set_pwm ||
	    !pdata->get_pwm_status ||
	    !pdata->set_prescaler ||
	    !pdata->write_counter) {
		dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
		ret = -EINVAL;
		goto err_platdata;
	}

	if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
		dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
		ret = -ENODEV;
		goto err_timer_property;
	}

	dm_timer = pdata->request_by_node(timer);
	if (!dm_timer) {
		ret = -EPROBE_DEFER;
		goto err_request_timer;
	}

	omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
	if (!omap) {
		ret = -ENOMEM;
		goto err_alloc_omap;
	}

	omap->pdata = pdata;
	omap->dm_timer = dm_timer;
	omap->dm_timer_pdev = timer_pdev;

	/*
	 * Ensure that the timer is stopped before we allow PWM core to call
	 * pwm_enable.
	 */
	if (pm_runtime_active(&omap->dm_timer_pdev->dev))
		omap->pdata->stop(omap->dm_timer);

	if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
		omap->pdata->set_prescaler(omap->dm_timer, v);

	/* setup dmtimer clock source */
	if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
		omap->pdata->set_source(omap->dm_timer, v);

	omap->chip.dev = &pdev->dev;
	omap->chip.ops = &pwm_omap_dmtimer_ops;
	omap->chip.npwm = 1;

	mutex_init(&omap->mutex);

	ret = pwmchip_add(&omap->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to register PWM\n");
		goto err_pwmchip_add;
	}

	of_node_put(timer);

	platform_set_drvdata(pdev, omap);

	return 0;

err_pwmchip_add:

	/*
	 * *omap is allocated using devm_kzalloc,
	 * so no free necessary here
	 */
err_alloc_omap:

	pdata->free(dm_timer);
err_request_timer:

err_timer_property:
err_platdata:

	put_device(&timer_pdev->dev);
err_find_timer_pdev:

	of_node_put(timer);

	return ret;
}

static int pwm_omap_dmtimer_remove(struct platform_device *pdev)
{
	struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);

	pwmchip_remove(&omap->chip);

	if (pm_runtime_active(&omap->dm_timer_pdev->dev))
		omap->pdata->stop(omap->dm_timer);

	omap->pdata->free(omap->dm_timer);

	put_device(&omap->dm_timer_pdev->dev);

	mutex_destroy(&omap->mutex);

	return 0;
}

static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
	{.compatible = "ti,omap-dmtimer-pwm"},
	{}
};
MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);

static struct platform_driver pwm_omap_dmtimer_driver = {
	.driver = {
		.name = "omap-dmtimer-pwm",
		.of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match),
	},
	.probe = pwm_omap_dmtimer_probe,
	.remove	= pwm_omap_dmtimer_remove,
};
module_platform_driver(pwm_omap_dmtimer_driver);

MODULE_AUTHOR("Grant Erickson <[email protected]>");
MODULE_AUTHOR("NeilBrown <[email protected]>");
MODULE_AUTHOR("Neil Armstrong <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
6604c655 NA	2	/*
	3	* Copyright (c) 2015 Neil Armstrong <[email protected]>
	4	* Copyright (c) 2014 Joachim Eastwood <[email protected]>
	5	* Copyright (c) 2012 NeilBrown <[email protected]>
	6	* Heavily based on earlier code which is:
	7	* Copyright (c) 2010 Grant Erickson <[email protected]>
	8	*
	9	* Also based on pwm-samsung.c
	10	*
6604c655 NA	11	* Description:
6604c655 NA	12	* This file is the core OMAP support for the generic, Linux
348fb6f7 LV	13	* PWM driver / controller, using the OMAP's dual-mode timers
	14	* with a timer counter that goes up. When it overflows it gets
	15	* reloaded with the load value and the pwm output goes up.
	16	* When counter matches with match register, the output goes down.
216a094d	17	* Reference Manual: https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf
348fb6f7 LV	18	*
	19	* Limitations:
	20	* - When PWM is stopped, timer counter gets stopped immediately. This
	21	* doesn't allow the current PWM period to complete and stops abruptly.
e793eef8 LV	22	* - When PWM is running and changing both duty cycle and period,
	23	* we cannot prevent in software that the output might produce
	24	* a period with mixed settings. Especially when period/duty_cyle
	25	* is updated while the pwm pin is high, current pwm period/duty_cycle
	26	* can get updated as below based on the current timer counter:
	27	* - period for current cycle = current_period + new period
	28	* - duty_cycle for current period = current period + new duty_cycle.
6b28fb6f LV	29	* - PWM OMAP DM timer cannot change the polarity when pwm is active. When
	30	* user requests a change in polarity when in active state:
	31	* - PWM is stopped abruptly(without completing the current cycle)
	32	* - Polarity is changed
	33	* - A fresh cycle is started.
6604c655 NA	34	*/
	35
	36	#include <linux/clk.h>
	37	#include <linux/err.h>
	38	#include <linux/kernel.h>
	39	#include <linux/module.h>
	40	#include <linux/mutex.h>
	41	#include <linux/of.h>
	42	#include <linux/of_platform.h>
54091b5f	43	#include <clocksource/timer-ti-dm.h>
b7290cf6	44	#include <linux/platform_data/dmtimer-omap.h>
6604c655 NA	45	#include <linux/platform_device.h>
	46	#include <linux/pm_runtime.h>
	47	#include <linux/pwm.h>
	48	#include <linux/slab.h>
	49	#include <linux/time.h>
	50
	51	#define DM_TIMER_LOAD_MIN 0xfffffffe
f8caa792	52	#define DM_TIMER_MAX 0xffffffff
6604c655	53
6b28fb6f LV	54	/**
	55	* struct pwm_omap_dmtimer_chip - Structure representing a pwm chip
	56	* corresponding to omap dmtimer.
	57	* @chip: PWM chip structure representing PWM controller
	58	* @mutex: Mutex to protect pwm apply state
	59	* @dm_timer: Pointer to omap dm timer.
	60	* @pdata: Pointer to omap dm timer ops.
dfd9b615	61	* @dm_timer_pdev: Pointer to omap dm timer platform device
6b28fb6f	62	*/
6604c655 NA	63	struct pwm_omap_dmtimer_chip {
6604c655 NA	64	struct pwm_chip chip;
6b28fb6f	65	/* Mutex to protect pwm apply state */
6604c655	66	struct mutex mutex;
54091b5f	67	struct omap_dm_timer *dm_timer;
b7290cf6	68	const struct omap_dm_timer_ops *pdata;
6604c655 NA	69	struct platform_device *dm_timer_pdev;
	70	};
	71
	72	static inline struct pwm_omap_dmtimer_chip *
	73	to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
	74	{
	75	return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
	76	}
	77
6b28fb6f LV	78	/**
	79	* pwm_omap_dmtimer_get_clock_cycles() - Get clock cycles in a time frame
	80	* @clk_rate: pwm timer clock rate
	81	* @ns: time frame in nano seconds.
	82	*
	83	* Return number of clock cycles in a given period(ins ns).
	84	*/
f8caa792	85	static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
6604c655	86	{
7b0883f3	87	return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
6604c655 NA	88	}
6604c655 NA	89
6b28fb6f LV	90	/**
	91	* pwm_omap_dmtimer_start() - Start the pwm omap dm timer in pwm mode
	92	* @omap: Pointer to pwm omap dm timer chip
	93	*/
6604c655 NA	94	static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
	95	{
	96	/*
	97	* According to OMAP 4 TRM section 22.2.4.10 the counter should be
	98	* started at 0xFFFFFFFE when overflow and match is used to ensure
	99	* that the PWM line is toggled on the first event.
	100	*
	101	* Note that omap_dm_timer_enable/disable is for register access and
	102	* not the timer counter itself.
	103	*/
	104	omap->pdata->enable(omap->dm_timer);
	105	omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
	106	omap->pdata->disable(omap->dm_timer);
	107
	108	omap->pdata->start(omap->dm_timer);
	109	}
	110
6b28fb6f LV	111	/**
	112	* pwm_omap_dmtimer_is_enabled() - Detect if the pwm is enabled.
	113	* @omap: Pointer to pwm omap dm timer chip
	114	*
	115	* Return true if pwm is enabled else false.
	116	*/
	117	static bool pwm_omap_dmtimer_is_enabled(struct pwm_omap_dmtimer_chip *omap)
6604c655	118	{
6b28fb6f	119	u32 status;
867beb60	120
6b28fb6f	121	status = omap->pdata->get_pwm_status(omap->dm_timer);
6604c655	122
6b28fb6f	123	return !!(status & OMAP_TIMER_CTRL_ST);
6604c655 NA	124	}
6604c655 NA	125
6b28fb6f LV	126	/**
	127	* pwm_omap_dmtimer_polarity() - Detect the polarity of pwm.
	128	* @omap: Pointer to pwm omap dm timer chip
	129	*
	130	* Return the polarity of pwm.
	131	*/
	132	static int pwm_omap_dmtimer_polarity(struct pwm_omap_dmtimer_chip *omap)
6604c655	133	{
6b28fb6f	134	u32 status;
6604c655	135
6b28fb6f LV	136	status = omap->pdata->get_pwm_status(omap->dm_timer);
	137
	138	return !!(status & OMAP_TIMER_CTRL_SCPWM);
6604c655 NA	139	}
6604c655 NA	140
6b28fb6f LV	141	/**
	142	* pwm_omap_dmtimer_config() - Update the configuration of pwm omap dm timer
	143	* @chip: Pointer to PWM controller
	144	* @pwm: Pointer to PWM channel
	145	* @duty_ns: New duty cycle in nano seconds
	146	* @period_ns: New period in nano seconds
	147	*
	148	* Return 0 if successfully changed the period/duty_cycle else appropriate
	149	* error.
	150	*/
6604c655 NA	151	static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
	152	struct pwm_device *pwm,
	153	int duty_ns, int period_ns)
	154	{
	155	struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
f8caa792 DR	156	u32 period_cycles, duty_cycles;
f8caa792 DR	157	u32 load_value, match_value;
6604c655	158	unsigned long clk_rate;
6b28fb6f	159	struct clk *fclk;
6604c655	160
922201d1 DR	161	dev_dbg(chip->dev, "requested duty cycle: %d ns, period: %d ns\n",
922201d1 DR	162	duty_ns, period_ns);
6604c655	163
6604c655	164	if (duty_ns == pwm_get_duty_cycle(pwm) &&
6b28fb6f	165	period_ns == pwm_get_period(pwm))
6604c655	166	return 0;
6604c655 NA	167
	168	fclk = omap->pdata->get_fclk(omap->dm_timer);
	169	if (!fclk) {
	170	dev_err(chip->dev, "invalid pmtimer fclk\n");
6b28fb6f	171	return -EINVAL;
6604c655 NA	172	}
	173
	174	clk_rate = clk_get_rate(fclk);
	175	if (!clk_rate) {
	176	dev_err(chip->dev, "invalid pmtimer fclk rate\n");
6b28fb6f	177	return -EINVAL;
6604c655 NA	178	}
	179
	180	dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
	181
	182	/*
	183	* Calculate the appropriate load and match values based on the
	184	* specified period and duty cycle. The load value determines the
f8caa792 DR	185	* period time and the match value determines the duty time.
	186	*
	187	* The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
	188	* Similarly, the active time lasts (match_value-load_value+1) cycles.
	189	* The non-active time is the remainder: (DM_TIMER_MAX-match_value)
	190	* clock cycles.
	191	*
cd378881 DR	192	* NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
cd378881 DR	193	*
f8caa792 DR	194	* References:
	195	* OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
	196	* AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
6604c655	197	*/
f8caa792 DR	198	period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
	199	duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
	200
cd378881 DR	201	if (period_cycles < 2) {
	202	dev_info(chip->dev,
	203	"period %d ns too short for clock rate %lu Hz\n",
	204	period_ns, clk_rate);
6b28fb6f	205	return -EINVAL;
cd378881 DR	206	}
	207
	208	if (duty_cycles < 1) {
	209	dev_dbg(chip->dev,
	210	"duty cycle %d ns is too short for clock rate %lu Hz\n",
	211	duty_ns, clk_rate);
	212	dev_dbg(chip->dev, "using minimum of 1 clock cycle\n");
	213	duty_cycles = 1;
	214	} else if (duty_cycles >= period_cycles) {
	215	dev_dbg(chip->dev,
	216	"duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
	217	duty_ns, period_ns, clk_rate);
	218	dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n");
	219	duty_cycles = period_cycles - 1;
	220	}
	221
922201d1 DR	222	dev_dbg(chip->dev, "effective duty cycle: %lld ns, period: %lld ns\n",
	223	DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles,
	224	clk_rate),
	225	DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles,
	226	clk_rate));
	227
f8caa792 DR	228	load_value = (DM_TIMER_MAX - period_cycles) + 1;
f8caa792 DR	229	match_value = load_value + duty_cycles - 1;
6604c655	230
02e6d546	231	omap->pdata->set_load(omap->dm_timer, load_value);
6604c655 NA	232	omap->pdata->set_match(omap->dm_timer, true, match_value);
	233
	234	dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
	235	load_value, load_value, match_value, match_value);
	236
6604c655 NA	237	return 0;
	238	}
	239
6b28fb6f LV	240	/**
	241	* pwm_omap_dmtimer_set_polarity() - Changes the polarity of the pwm dm timer.
	242	* @chip: Pointer to PWM controller
	243	* @pwm: Pointer to PWM channel
	244	* @polarity: New pwm polarity to be set
	245	*/
	246	static void pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
	247	struct pwm_device *pwm,
	248	enum pwm_polarity polarity)
6604c655 NA	249	{
6604c655 NA	250	struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
6b28fb6f LV	251	bool enabled;
	252
	253	/* Disable the PWM before changing the polarity. */
	254	enabled = pwm_omap_dmtimer_is_enabled(omap);
	255	if (enabled)
	256	omap->pdata->stop(omap->dm_timer);
6604c655	257
6604c655	258	omap->pdata->set_pwm(omap->dm_timer,
54091b5f LV	259	polarity == PWM_POLARITY_INVERSED,
	260	true, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
	261	true);
6b28fb6f LV	262
	263	if (enabled)
	264	pwm_omap_dmtimer_start(omap);
	265	}
	266
	267	/**
	268	* pwm_omap_dmtimer_apply() - Changes the state of the pwm omap dm timer.
	269	* @chip: Pointer to PWM controller
	270	* @pwm: Pointer to PWM channel
	271	* @state: New state to apply
	272	*
	273	* Return 0 if successfully changed the state else appropriate error.
	274	*/
	275	static int pwm_omap_dmtimer_apply(struct pwm_chip *chip,
	276	struct pwm_device *pwm,
	277	const struct pwm_state *state)
	278	{
	279	struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
	280	int ret = 0;
	281
	282	mutex_lock(&omap->mutex);
	283
	284	if (pwm_omap_dmtimer_is_enabled(omap) && !state->enabled) {
	285	omap->pdata->stop(omap->dm_timer);
	286	goto unlock_mutex;
	287	}
	288
	289	if (pwm_omap_dmtimer_polarity(omap) != state->polarity)
	290	pwm_omap_dmtimer_set_polarity(chip, pwm, state->polarity);
	291
	292	ret = pwm_omap_dmtimer_config(chip, pwm, state->duty_cycle,
	293	state->period);
	294	if (ret)
	295	goto unlock_mutex;
	296
	297	if (!pwm_omap_dmtimer_is_enabled(omap) && state->enabled) {
	298	omap->pdata->set_pwm(omap->dm_timer,
	299	state->polarity == PWM_POLARITY_INVERSED,
	300	true,
	301	OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
	302	true);
	303	pwm_omap_dmtimer_start(omap);
	304	}
	305
	306	unlock_mutex:
6604c655 NA	307	mutex_unlock(&omap->mutex);
6604c655 NA	308
6b28fb6f	309	return ret;
6604c655 NA	310	}
	311
	312	static const struct pwm_ops pwm_omap_dmtimer_ops = {
6b28fb6f	313	.apply = pwm_omap_dmtimer_apply,
6604c655 NA	314	.owner = THIS_MODULE,
	315	};
	316
	317	static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
	318	{
	319	struct device_node *np = pdev->dev.of_node;
b7290cf6 K	320	struct dmtimer_platform_data *timer_pdata;
b7290cf6 K	321	const struct omap_dm_timer_ops *pdata;
6b28fb6f LV	322	struct platform_device *timer_pdev;
6b28fb6f LV	323	struct pwm_omap_dmtimer_chip *omap;
54091b5f	324	struct omap_dm_timer *dm_timer;
6b28fb6f	325	struct device_node *timer;
b7290cf6	326	int ret = 0;
6b28fb6f	327	u32 v;
6604c655	328
b7290cf6 K	329	timer = of_parse_phandle(np, "ti,timers", 0);
	330	if (!timer)
	331	return -ENODEV;
	332
	333	timer_pdev = of_find_device_by_node(timer);
	334	if (!timer_pdev) {
	335	dev_err(&pdev->dev, "Unable to find Timer pdev\n");
	336	ret = -ENODEV;
c7cb3a1d	337	goto err_find_timer_pdev;
6604c655 NA	338	}
6604c655 NA	339
b7290cf6 K	340	timer_pdata = dev_get_platdata(&timer_pdev->dev);
b7290cf6 K	341	if (!timer_pdata) {
43725feb DR	342	dev_dbg(&pdev->dev,
	343	"dmtimer pdata structure NULL, deferring probe\n");
	344	ret = -EPROBE_DEFER;
c7cb3a1d	345	goto err_platdata;
b7290cf6 K	346	}
	347
	348	pdata = timer_pdata->timer_ops;
	349
	350	if (!pdata \|\| !pdata->request_by_node \|\|
6604c655 NA	351	!pdata->free \|\|
	352	!pdata->enable \|\|
	353	!pdata->disable \|\|
	354	!pdata->get_fclk \|\|
	355	!pdata->start \|\|
	356	!pdata->stop \|\|
	357	!pdata->set_load \|\|
	358	!pdata->set_match \|\|
	359	!pdata->set_pwm \|\|
6b28fb6f	360	!pdata->get_pwm_status \|\|
6604c655 NA	361	!pdata->set_prescaler \|\|
	362	!pdata->write_counter) {
	363	dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
b7290cf6	364	ret = -EINVAL;
c7cb3a1d	365	goto err_platdata;
6604c655 NA	366	}
6604c655 NA	367
6604c655 NA	368	if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
6604c655 NA	369	dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
b7290cf6	370	ret = -ENODEV;
c7cb3a1d	371	goto err_timer_property;
6604c655 NA	372	}
	373
	374	dm_timer = pdata->request_by_node(timer);
b7290cf6 K	375	if (!dm_timer) {
b7290cf6 K	376	ret = -EPROBE_DEFER;
c7cb3a1d	377	goto err_request_timer;
b7290cf6 K	378	}
b7290cf6 K	379
6604c655 NA	380	omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
6604c655 NA	381	if (!omap) {
c4cf7aa5 UKK	382	ret = -ENOMEM;
c4cf7aa5 UKK	383	goto err_alloc_omap;
6604c655 NA	384	}
	385
	386	omap->pdata = pdata;
	387	omap->dm_timer = dm_timer;
b7290cf6	388	omap->dm_timer_pdev = timer_pdev;
6604c655 NA	389
	390	/*
	391	* Ensure that the timer is stopped before we allow PWM core to call
	392	* pwm_enable.
	393	*/
	394	if (pm_runtime_active(&omap->dm_timer_pdev->dev))
	395	omap->pdata->stop(omap->dm_timer);
	396
a74a1982 ID	397	if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
	398	omap->pdata->set_prescaler(omap->dm_timer, v);
	399
	400	/* setup dmtimer clock source */
	401	if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
	402	omap->pdata->set_source(omap->dm_timer, v);
6604c655 NA	403
	404	omap->chip.dev = &pdev->dev;
	405	omap->chip.ops = &pwm_omap_dmtimer_ops;
6604c655	406	omap->chip.npwm = 1;
6604c655 NA	407
	408	mutex_init(&omap->mutex);
	409
b7290cf6 K	410	ret = pwmchip_add(&omap->chip);
b7290cf6 K	411	if (ret < 0) {
6604c655	412	dev_err(&pdev->dev, "failed to register PWM\n");
c4cf7aa5	413	goto err_pwmchip_add;
6604c655 NA	414	}
6604c655 NA	415
c4cf7aa5 UKK	416	of_node_put(timer);
c4cf7aa5 UKK	417
6604c655 NA	418	platform_set_drvdata(pdev, omap);
	419
	420	return 0;
c4cf7aa5 UKK	421
	422	err_pwmchip_add:
	423
	424	/*
	425	* *omap is allocated using devm_kzalloc,
	426	* so no free necessary here
	427	*/
	428	err_alloc_omap:
	429
	430	pdata->free(dm_timer);
c7cb3a1d UKK	431	err_request_timer:
	432
	433	err_timer_property:
	434	err_platdata:
	435
	436	put_device(&timer_pdev->dev);
	437	err_find_timer_pdev:
	438
c4cf7aa5 UKK	439	of_node_put(timer);
	440
	441	return ret;
6604c655 NA	442	}
	443
	444	static int pwm_omap_dmtimer_remove(struct platform_device *pdev)
	445	{
	446	struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);
43efdc8f	447
faaa2222	448	pwmchip_remove(&omap->chip);
6604c655 NA	449
	450	if (pm_runtime_active(&omap->dm_timer_pdev->dev))
	451	omap->pdata->stop(omap->dm_timer);
	452
	453	omap->pdata->free(omap->dm_timer);
	454
c7cb3a1d UKK	455	put_device(&omap->dm_timer_pdev->dev);
c7cb3a1d UKK	456
6604c655 NA	457	mutex_destroy(&omap->mutex);
6604c655 NA	458
43efdc8f	459	return 0;
6604c655 NA	460	}
	461
	462	static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
	463	{.compatible = "ti,omap-dmtimer-pwm"},
	464	{}
	465	};
	466	MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
	467
	468	static struct platform_driver pwm_omap_dmtimer_driver = {
	469	.driver = {
	470	.name = "omap-dmtimer-pwm",
	471	.of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match),
	472	},
	473	.probe = pwm_omap_dmtimer_probe,
	474	.remove = pwm_omap_dmtimer_remove,
	475	};
	476	module_platform_driver(pwm_omap_dmtimer_driver);
	477
	478	MODULE_AUTHOR("Grant Erickson <[email protected]>");
	479	MODULE_AUTHOR("NeilBrown <[email protected]>");
	480	MODULE_AUTHOR("Neil Armstrong <[email protected]>");
	481	MODULE_LICENSE("GPL v2");
	482	MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");