[linux.git] / drivers / pwm / pwm-meson.c

// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
 * PWM controller driver for Amlogic Meson SoCs.
 *
 * This PWM is only a set of Gates, Dividers and Counters:
 * PWM output is achieved by calculating a clock that permits calculating
 * two periods (low and high). The counter then has to be set to switch after
 * N cycles for the first half period.
 * The hardware has no "polarity" setting. This driver reverses the period
 * cycles (the low length is inverted with the high length) for
 * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
 * from the hardware.
 * Setting the duty cycle will disable and re-enable the PWM output.
 * Disabling the PWM stops the output immediately (without waiting for the
 * current period to complete first).
 *
 * The public S912 (GXM) datasheet contains some documentation for this PWM
 * controller starting on page 543:
 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
 * An updated version of this IP block is found in S922X (G12B) SoCs. The
 * datasheet contains the description for this IP block revision starting at
 * page 1084:
 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
 *
 * Copyright (c) 2016 BayLibre, SAS.
 * Author: Neil Armstrong <[email protected]>
 * Copyright (C) 2014 Amlogic, Inc.
 */

#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#define REG_PWM_A		0x0
#define REG_PWM_B		0x4
#define PWM_LOW_MASK		GENMASK(15, 0)
#define PWM_HIGH_MASK		GENMASK(31, 16)

#define REG_MISC_AB		0x8
#define MISC_B_CLK_EN		BIT(23)
#define MISC_A_CLK_EN		BIT(15)
#define MISC_CLK_DIV_MASK	0x7f
#define MISC_B_CLK_DIV_SHIFT	16
#define MISC_A_CLK_DIV_SHIFT	8
#define MISC_B_CLK_SEL_SHIFT	6
#define MISC_A_CLK_SEL_SHIFT	4
#define MISC_CLK_SEL_MASK	0x3
#define MISC_B_EN		BIT(1)
#define MISC_A_EN		BIT(0)

#define MESON_NUM_PWMS		2

static struct meson_pwm_channel_data {
	u8		reg_offset;
	u8		clk_sel_shift;
	u8		clk_div_shift;
	u32		clk_en_mask;
	u32		pwm_en_mask;
} meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
	{
		.reg_offset	= REG_PWM_A,
		.clk_sel_shift	= MISC_A_CLK_SEL_SHIFT,
		.clk_div_shift	= MISC_A_CLK_DIV_SHIFT,
		.clk_en_mask	= MISC_A_CLK_EN,
		.pwm_en_mask	= MISC_A_EN,
	},
	{
		.reg_offset	= REG_PWM_B,
		.clk_sel_shift	= MISC_B_CLK_SEL_SHIFT,
		.clk_div_shift	= MISC_B_CLK_DIV_SHIFT,
		.clk_en_mask	= MISC_B_CLK_EN,
		.pwm_en_mask	= MISC_B_EN,
	}
};

struct meson_pwm_channel {
	unsigned int hi;
	unsigned int lo;
	u8 pre_div;

	struct clk *clk_parent;
	struct clk_mux mux;
	struct clk *clk;
};

struct meson_pwm_data {
	const char * const *parent_names;
	unsigned int num_parents;
};

struct meson_pwm {
	struct pwm_chip chip;
	const struct meson_pwm_data *data;
	struct meson_pwm_channel channels[MESON_NUM_PWMS];
	void __iomem *base;
	/*
	 * Protects register (write) access to the REG_MISC_AB register
	 * that is shared between the two PWMs.
	 */
	spinlock_t lock;
};

static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
{
	return container_of(chip, struct meson_pwm, chip);
}

static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct meson_pwm *meson = to_meson_pwm(chip);
	struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
	struct device *dev = chip->dev;
	int err;

	if (channel->clk_parent) {
		err = clk_set_parent(channel->clk, channel->clk_parent);
		if (err < 0) {
			dev_err(dev, "failed to set parent %s for %s: %d\n",
				__clk_get_name(channel->clk_parent),
				__clk_get_name(channel->clk), err);
			return err;
		}
	}

	err = clk_prepare_enable(channel->clk);
	if (err < 0) {
		dev_err(dev, "failed to enable clock %s: %d\n",
			__clk_get_name(channel->clk), err);
		return err;
	}

	return 0;
}

static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct meson_pwm *meson = to_meson_pwm(chip);
	struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];

	clk_disable_unprepare(channel->clk);
}

static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm,
			  const struct pwm_state *state)
{
	struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
	unsigned int duty, period, pre_div, cnt, duty_cnt;
	unsigned long fin_freq;

	duty = state->duty_cycle;
	period = state->period;

	if (state->polarity == PWM_POLARITY_INVERSED)
		duty = period - duty;

	fin_freq = clk_get_rate(channel->clk);
	if (fin_freq == 0) {
		dev_err(meson->chip.dev, "invalid source clock frequency\n");
		return -EINVAL;
	}

	dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);

	pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL);
	if (pre_div > MISC_CLK_DIV_MASK) {
		dev_err(meson->chip.dev, "unable to get period pre_div\n");
		return -EINVAL;
	}

	cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1));
	if (cnt > 0xffff) {
		dev_err(meson->chip.dev, "unable to get period cnt\n");
		return -EINVAL;
	}

	dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
		pre_div, cnt);

	if (duty == period) {
		channel->pre_div = pre_div;
		channel->hi = cnt;
		channel->lo = 0;
	} else if (duty == 0) {
		channel->pre_div = pre_div;
		channel->hi = 0;
		channel->lo = cnt;
	} else {
		/* Then check is we can have the duty with the same pre_div */
		duty_cnt = div64_u64(fin_freq * (u64)duty,
				     NSEC_PER_SEC * (pre_div + 1));
		if (duty_cnt > 0xffff) {
			dev_err(meson->chip.dev, "unable to get duty cycle\n");
			return -EINVAL;
		}

		dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
			duty, pre_div, duty_cnt);

		channel->pre_div = pre_div;
		channel->hi = duty_cnt;
		channel->lo = cnt - duty_cnt;
	}

	return 0;
}

static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm)
{
	struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
	struct meson_pwm_channel_data *channel_data;
	unsigned long flags;
	u32 value;

	channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];

	spin_lock_irqsave(&meson->lock, flags);

	value = readl(meson->base + REG_MISC_AB);
	value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
	value |= channel->pre_div << channel_data->clk_div_shift;
	value |= channel_data->clk_en_mask;
	writel(value, meson->base + REG_MISC_AB);

	value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
		FIELD_PREP(PWM_LOW_MASK, channel->lo);
	writel(value, meson->base + channel_data->reg_offset);

	value = readl(meson->base + REG_MISC_AB);
	value |= channel_data->pwm_en_mask;
	writel(value, meson->base + REG_MISC_AB);

	spin_unlock_irqrestore(&meson->lock, flags);
}

static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm)
{
	unsigned long flags;
	u32 value;

	spin_lock_irqsave(&meson->lock, flags);

	value = readl(meson->base + REG_MISC_AB);
	value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
	writel(value, meson->base + REG_MISC_AB);

	spin_unlock_irqrestore(&meson->lock, flags);
}

static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   const struct pwm_state *state)
{
	struct meson_pwm *meson = to_meson_pwm(chip);
	struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
	int err = 0;

	if (!state->enabled) {
		if (state->polarity == PWM_POLARITY_INVERSED) {
			/*
			 * This IP block revision doesn't have an "always high"
			 * setting which we can use for "inverted disabled".
			 * Instead we achieve this using the same settings
			 * that we use a pre_div of 0 (to get the shortest
			 * possible duration for one "count") and
			 * "period == duty_cycle". This results in a signal
			 * which is LOW for one "count", while being HIGH for
			 * the rest of the (so the signal is HIGH for slightly
			 * less than 100% of the period, but this is the best
			 * we can achieve).
			 */
			channel->pre_div = 0;
			channel->hi = ~0;
			channel->lo = 0;

			meson_pwm_enable(meson, pwm);
		} else {
			meson_pwm_disable(meson, pwm);
		}
	} else {
		err = meson_pwm_calc(meson, pwm, state);
		if (err < 0)
			return err;

		meson_pwm_enable(meson, pwm);
	}

	return 0;
}

static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip,
					struct pwm_device *pwm, u32 cnt)
{
	struct meson_pwm *meson = to_meson_pwm(chip);
	struct meson_pwm_channel *channel;
	unsigned long fin_freq;
	u32 fin_ns;

	/* to_meson_pwm() can only be used after .get_state() is called */
	channel = &meson->channels[pwm->hwpwm];

	fin_freq = clk_get_rate(channel->clk);
	if (fin_freq == 0)
		return 0;

	fin_ns = div_u64(NSEC_PER_SEC, fin_freq);

	return cnt * fin_ns * (channel->pre_div + 1);
}

static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
				struct pwm_state *state)
{
	struct meson_pwm *meson = to_meson_pwm(chip);
	struct meson_pwm_channel_data *channel_data;
	struct meson_pwm_channel *channel;
	u32 value, tmp;

	if (!state)
		return;

	channel = &meson->channels[pwm->hwpwm];
	channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];

	value = readl(meson->base + REG_MISC_AB);

	tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask;
	state->enabled = (value & tmp) == tmp;

	tmp = value >> channel_data->clk_div_shift;
	channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp);

	value = readl(meson->base + channel_data->reg_offset);

	channel->lo = FIELD_GET(PWM_LOW_MASK, value);
	channel->hi = FIELD_GET(PWM_HIGH_MASK, value);

	if (channel->lo == 0) {
		state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
		state->duty_cycle = state->period;
	} else if (channel->lo >= channel->hi) {
		state->period = meson_pwm_cnt_to_ns(chip, pwm,
						    channel->lo + channel->hi);
		state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm,
							channel->hi);
	} else {
		state->period = 0;
		state->duty_cycle = 0;
	}
}

static const struct pwm_ops meson_pwm_ops = {
	.request = meson_pwm_request,
	.free = meson_pwm_free,
	.apply = meson_pwm_apply,
	.get_state = meson_pwm_get_state,
	.owner = THIS_MODULE,
};

static const char * const pwm_meson8b_parent_names[] = {
	"xtal", "vid_pll", "fclk_div4", "fclk_div3"
};

static const struct meson_pwm_data pwm_meson8b_data = {
	.parent_names = pwm_meson8b_parent_names,
	.num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
};

static const char * const pwm_gxbb_parent_names[] = {
	"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
};

static const struct meson_pwm_data pwm_gxbb_data = {
	.parent_names = pwm_gxbb_parent_names,
	.num_parents = ARRAY_SIZE(pwm_gxbb_parent_names),
};

/*
 * Only the 2 first inputs of the GXBB AO PWMs are valid
 * The last 2 are grounded
 */
static const char * const pwm_gxbb_ao_parent_names[] = {
	"xtal", "clk81"
};

static const struct meson_pwm_data pwm_gxbb_ao_data = {
	.parent_names = pwm_gxbb_ao_parent_names,
	.num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
};

static const char * const pwm_axg_ee_parent_names[] = {
	"xtal", "fclk_div5", "fclk_div4", "fclk_div3"
};

static const struct meson_pwm_data pwm_axg_ee_data = {
	.parent_names = pwm_axg_ee_parent_names,
	.num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
};

static const char * const pwm_axg_ao_parent_names[] = {
	"aoclk81", "xtal", "fclk_div4", "fclk_div5"
};

static const struct meson_pwm_data pwm_axg_ao_data = {
	.parent_names = pwm_axg_ao_parent_names,
	.num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
};

static const char * const pwm_g12a_ao_ab_parent_names[] = {
	"xtal", "aoclk81", "fclk_div4", "fclk_div5"
};

static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
	.parent_names = pwm_g12a_ao_ab_parent_names,
	.num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
};

static const char * const pwm_g12a_ao_cd_parent_names[] = {
	"xtal", "aoclk81",
};

static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
	.parent_names = pwm_g12a_ao_cd_parent_names,
	.num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
};

static const char * const pwm_g12a_ee_parent_names[] = {
	"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
};

static const struct meson_pwm_data pwm_g12a_ee_data = {
	.parent_names = pwm_g12a_ee_parent_names,
	.num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names),
};

static const struct of_device_id meson_pwm_matches[] = {
	{
		.compatible = "amlogic,meson8b-pwm",
		.data = &pwm_meson8b_data
	},
	{
		.compatible = "amlogic,meson-gxbb-pwm",
		.data = &pwm_gxbb_data
	},
	{
		.compatible = "amlogic,meson-gxbb-ao-pwm",
		.data = &pwm_gxbb_ao_data
	},
	{
		.compatible = "amlogic,meson-axg-ee-pwm",
		.data = &pwm_axg_ee_data
	},
	{
		.compatible = "amlogic,meson-axg-ao-pwm",
		.data = &pwm_axg_ao_data
	},
	{
		.compatible = "amlogic,meson-g12a-ee-pwm",
		.data = &pwm_g12a_ee_data
	},
	{
		.compatible = "amlogic,meson-g12a-ao-pwm-ab",
		.data = &pwm_g12a_ao_ab_data
	},
	{
		.compatible = "amlogic,meson-g12a-ao-pwm-cd",
		.data = &pwm_g12a_ao_cd_data
	},
	{},
};
MODULE_DEVICE_TABLE(of, meson_pwm_matches);

static int meson_pwm_init_channels(struct meson_pwm *meson)
{
	struct device *dev = meson->chip.dev;
	struct clk_init_data init;
	unsigned int i;
	char name[255];
	int err;

	for (i = 0; i < meson->chip.npwm; i++) {
		struct meson_pwm_channel *channel = &meson->channels[i];

		snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);

		init.name = name;
		init.ops = &clk_mux_ops;
		init.flags = 0;
		init.parent_names = meson->data->parent_names;
		init.num_parents = meson->data->num_parents;

		channel->mux.reg = meson->base + REG_MISC_AB;
		channel->mux.shift =
				meson_pwm_per_channel_data[i].clk_sel_shift;
		channel->mux.mask = MISC_CLK_SEL_MASK;
		channel->mux.flags = 0;
		channel->mux.lock = &meson->lock;
		channel->mux.table = NULL;
		channel->mux.hw.init = &init;

		channel->clk = devm_clk_register(dev, &channel->mux.hw);
		if (IS_ERR(channel->clk)) {
			err = PTR_ERR(channel->clk);
			dev_err(dev, "failed to register %s: %d\n", name, err);
			return err;
		}

		snprintf(name, sizeof(name), "clkin%u", i);

		channel->clk_parent = devm_clk_get_optional(dev, name);
		if (IS_ERR(channel->clk_parent))
			return PTR_ERR(channel->clk_parent);
	}

	return 0;
}

static int meson_pwm_probe(struct platform_device *pdev)
{
	struct meson_pwm *meson;
	int err;

	meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
	if (!meson)
		return -ENOMEM;

	meson->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(meson->base))
		return PTR_ERR(meson->base);

	spin_lock_init(&meson->lock);
	meson->chip.dev = &pdev->dev;
	meson->chip.ops = &meson_pwm_ops;
	meson->chip.npwm = MESON_NUM_PWMS;

	meson->data = of_device_get_match_data(&pdev->dev);

	err = meson_pwm_init_channels(meson);
	if (err < 0)
		return err;

	err = devm_pwmchip_add(&pdev->dev, &meson->chip);
	if (err < 0) {
		dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
		return err;
	}

	return 0;
}

static struct platform_driver meson_pwm_driver = {
	.driver = {
		.name = "meson-pwm",
		.of_match_table = meson_pwm_matches,
	},
	.probe = meson_pwm_probe,
};
module_platform_driver(meson_pwm_driver);

MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
MODULE_AUTHOR("Neil Armstrong <[email protected]>");
MODULE_LICENSE("Dual BSD/GPL");
Commit	Line	Data
1cdb4413	1	// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
211ed630	2	/*
4ae42ce7 MB	3	* PWM controller driver for Amlogic Meson SoCs.
	4	*
	5	* This PWM is only a set of Gates, Dividers and Counters:
	6	* PWM output is achieved by calculating a clock that permits calculating
	7	* two periods (low and high). The counter then has to be set to switch after
	8	* N cycles for the first half period.
	9	* The hardware has no "polarity" setting. This driver reverses the period
	10	* cycles (the low length is inverted with the high length) for
	11	* PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
	12	* from the hardware.
	13	* Setting the duty cycle will disable and re-enable the PWM output.
	14	* Disabling the PWM stops the output immediately (without waiting for the
	15	* current period to complete first).
	16	*
	17	* The public S912 (GXM) datasheet contains some documentation for this PWM
	18	* controller starting on page 543:
	19	* https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
	20	* An updated version of this IP block is found in S922X (G12B) SoCs. The
	21	* datasheet contains the description for this IP block revision starting at
	22	* page 1084:
	23	* https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
	24	*
211ed630 NA	25	* Copyright (c) 2016 BayLibre, SAS.
	26	* Author: Neil Armstrong <[email protected]>
	27	* Copyright (C) 2014 Amlogic, Inc.
211ed630 NA	28	*/
211ed630 NA	29
181164b6 MB	30	#include <linux/bitfield.h>
181164b6 MB	31	#include <linux/bits.h>
211ed630 NA	32	#include <linux/clk.h>
	33	#include <linux/clk-provider.h>
	34	#include <linux/err.h>
	35	#include <linux/io.h>
	36	#include <linux/kernel.h>
fb2081e8	37	#include <linux/math64.h>
211ed630 NA	38	#include <linux/module.h>
	39	#include <linux/of.h>
	40	#include <linux/of_device.h>
	41	#include <linux/platform_device.h>
	42	#include <linux/pwm.h>
	43	#include <linux/slab.h>
	44	#include <linux/spinlock.h>
	45
	46	#define REG_PWM_A 0x0
	47	#define REG_PWM_B 0x4
181164b6 MB	48	#define PWM_LOW_MASK GENMASK(15, 0)
181164b6 MB	49	#define PWM_HIGH_MASK GENMASK(31, 16)
211ed630 NA	50
	51	#define REG_MISC_AB 0x8
	52	#define MISC_B_CLK_EN BIT(23)
	53	#define MISC_A_CLK_EN BIT(15)
	54	#define MISC_CLK_DIV_MASK 0x7f
	55	#define MISC_B_CLK_DIV_SHIFT 16
	56	#define MISC_A_CLK_DIV_SHIFT 8
	57	#define MISC_B_CLK_SEL_SHIFT 6
	58	#define MISC_A_CLK_SEL_SHIFT 4
33cefd84	59	#define MISC_CLK_SEL_MASK 0x3
211ed630 NA	60	#define MISC_B_EN BIT(1)
	61	#define MISC_A_EN BIT(0)
	62
a50a49a4 MB	63	#define MESON_NUM_PWMS 2
a50a49a4 MB	64
8bbf3164 MB	65	static struct meson_pwm_channel_data {
	66	u8 reg_offset;
	67	u8 clk_sel_shift;
	68	u8 clk_div_shift;
	69	u32 clk_en_mask;
	70	u32 pwm_en_mask;
	71	} meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
	72	{
	73	.reg_offset = REG_PWM_A,
	74	.clk_sel_shift = MISC_A_CLK_SEL_SHIFT,
	75	.clk_div_shift = MISC_A_CLK_DIV_SHIFT,
	76	.clk_en_mask = MISC_A_CLK_EN,
	77	.pwm_en_mask = MISC_A_EN,
	78	},
	79	{
	80	.reg_offset = REG_PWM_B,
	81	.clk_sel_shift = MISC_B_CLK_SEL_SHIFT,
	82	.clk_div_shift = MISC_B_CLK_DIV_SHIFT,
	83	.clk_en_mask = MISC_B_CLK_EN,
	84	.pwm_en_mask = MISC_B_EN,
	85	}
211ed630 NA	86	};
	87
	88	struct meson_pwm_channel {
	89	unsigned int hi;
	90	unsigned int lo;
	91	u8 pre_div;
	92
211ed630 NA	93	struct clk *clk_parent;
	94	struct clk_mux mux;
	95	struct clk *clk;
	96	};
	97
	98	struct meson_pwm_data {
	99	const char * const *parent_names;
d396b20a	100	unsigned int num_parents;
211ed630 NA	101	};
	102
	103	struct meson_pwm {
	104	struct pwm_chip chip;
	105	const struct meson_pwm_data *data;
a50a49a4	106	struct meson_pwm_channel channels[MESON_NUM_PWMS];
211ed630	107	void __iomem *base;
f173747f MB	108	/*
	109	* Protects register (write) access to the REG_MISC_AB register
	110	* that is shared between the two PWMs.
	111	*/
211ed630 NA	112	spinlock_t lock;
	113	};
	114
	115	static inline struct meson_pwm to_meson_pwm(struct pwm_chip chip)
	116	{
	117	return container_of(chip, struct meson_pwm, chip);
	118	}
	119
	120	static int meson_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
	121	{
1064c6ba	122	struct meson_pwm *meson = to_meson_pwm(chip);
37349609	123	struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
211ed630 NA	124	struct device *dev = chip->dev;
	125	int err;
	126
211ed630 NA	127	if (channel->clk_parent) {
	128	err = clk_set_parent(channel->clk, channel->clk_parent);
	129	if (err < 0) {
	130	dev_err(dev, "failed to set parent %s for %s: %d\n",
	131	__clk_get_name(channel->clk_parent),
	132	__clk_get_name(channel->clk), err);
b33d232e	133	return err;
211ed630 NA	134	}
	135	}
	136
	137	err = clk_prepare_enable(channel->clk);
	138	if (err < 0) {
	139	dev_err(dev, "failed to enable clock %s: %d\n",
	140	__clk_get_name(channel->clk), err);
	141	return err;
	142	}
	143
5f97f18f	144	return 0;
211ed630 NA	145	}
	146
	147	static void meson_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	148	{
5f97f18f UKK	149	struct meson_pwm *meson = to_meson_pwm(chip);
5f97f18f UKK	150	struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
211ed630	151
cb971fdb	152	clk_disable_unprepare(channel->clk);
211ed630 NA	153	}
211ed630 NA	154
7e032162	155	static int meson_pwm_calc(struct meson_pwm meson, struct pwm_device pwm,
71523d18	156	const struct pwm_state *state)
211ed630	157	{
5f97f18f	158	struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
b79c3670	159	unsigned int duty, period, pre_div, cnt, duty_cnt;
437fb760	160	unsigned long fin_freq;
211ed630	161
b79c3670 MB	162	duty = state->duty_cycle;
	163	period = state->period;
	164
	165	if (state->polarity == PWM_POLARITY_INVERSED)
211ed630 NA	166	duty = period - duty;
211ed630 NA	167
211ed630 NA	168	fin_freq = clk_get_rate(channel->clk);
	169	if (fin_freq == 0) {
	170	dev_err(meson->chip.dev, "invalid source clock frequency\n");
	171	return -EINVAL;
	172	}
	173
	174	dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
211ed630	175
fb2081e8	176	pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL);
51496e44	177	if (pre_div > MISC_CLK_DIV_MASK) {
211ed630 NA	178	dev_err(meson->chip.dev, "unable to get period pre_div\n");
	179	return -EINVAL;
	180	}
	181
fb2081e8 MB	182	cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1));
	183	if (cnt > 0xffff) {
	184	dev_err(meson->chip.dev, "unable to get period cnt\n");
	185	return -EINVAL;
	186	}
	187
211ed630 NA	188	dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
	189	pre_div, cnt);
	190
	191	if (duty == period) {
	192	channel->pre_div = pre_div;
	193	channel->hi = cnt;
	194	channel->lo = 0;
	195	} else if (duty == 0) {
	196	channel->pre_div = pre_div;
	197	channel->hi = 0;
	198	channel->lo = cnt;
	199	} else {
	200	/* Then check is we can have the duty with the same pre_div */
fb2081e8 MB	201	duty_cnt = div64_u64(fin_freq * (u64)duty,
fb2081e8 MB	202	NSEC_PER_SEC * (pre_div + 1));
211ed630 NA	203	if (duty_cnt > 0xffff) {
	204	dev_err(meson->chip.dev, "unable to get duty cycle\n");
	205	return -EINVAL;
	206	}
	207
	208	dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
	209	duty, pre_div, duty_cnt);
	210
	211	channel->pre_div = pre_div;
	212	channel->hi = duty_cnt;
	213	channel->lo = cnt - duty_cnt;
	214	}
	215
	216	return 0;
	217	}
	218
084f1376	219	static void meson_pwm_enable(struct meson_pwm meson, struct pwm_device pwm)
211ed630	220	{
5f97f18f	221	struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
8bbf3164	222	struct meson_pwm_channel_data *channel_data;
f173747f	223	unsigned long flags;
8bbf3164	224	u32 value;
211ed630	225
8bbf3164	226	channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
211ed630	227
f173747f MB	228	spin_lock_irqsave(&meson->lock, flags);
f173747f MB	229
211ed630	230	value = readl(meson->base + REG_MISC_AB);
8bbf3164 MB	231	value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
	232	value \|= channel->pre_div << channel_data->clk_div_shift;
	233	value \|= channel_data->clk_en_mask;
211ed630 NA	234	writel(value, meson->base + REG_MISC_AB);
211ed630 NA	235
181164b6 MB	236	value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) \|
181164b6 MB	237	FIELD_PREP(PWM_LOW_MASK, channel->lo);
8bbf3164	238	writel(value, meson->base + channel_data->reg_offset);
211ed630 NA	239
211ed630 NA	240	value = readl(meson->base + REG_MISC_AB);
8bbf3164	241	value \|= channel_data->pwm_en_mask;
211ed630	242	writel(value, meson->base + REG_MISC_AB);
f173747f MB	243
f173747f MB	244	spin_unlock_irqrestore(&meson->lock, flags);
211ed630 NA	245	}
211ed630 NA	246
084f1376	247	static void meson_pwm_disable(struct meson_pwm meson, struct pwm_device pwm)
211ed630	248	{
f173747f	249	unsigned long flags;
8bbf3164	250	u32 value;
211ed630	251
f173747f MB	252	spin_lock_irqsave(&meson->lock, flags);
f173747f MB	253
211ed630	254	value = readl(meson->base + REG_MISC_AB);
8bbf3164	255	value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
211ed630	256	writel(value, meson->base + REG_MISC_AB);
f173747f MB	257
f173747f MB	258	spin_unlock_irqrestore(&meson->lock, flags);
211ed630 NA	259	}
	260
	261	static int meson_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	262	const struct pwm_state *state)
211ed630	263	{
211ed630	264	struct meson_pwm *meson = to_meson_pwm(chip);
5f97f18f	265	struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
211ed630 NA	266	int err = 0;
211ed630 NA	267
211ed630	268	if (!state->enabled) {
7341c785 MB	269	if (state->polarity == PWM_POLARITY_INVERSED) {
	270	/*
	271	* This IP block revision doesn't have an "always high"
	272	* setting which we can use for "inverted disabled".
	273	* Instead we achieve this using the same settings
	274	* that we use a pre_div of 0 (to get the shortest
	275	* possible duration for one "count") and
	276	* "period == duty_cycle". This results in a signal
	277	* which is LOW for one "count", while being HIGH for
	278	* the rest of the (so the signal is HIGH for slightly
	279	* less than 100% of the period, but this is the best
	280	* we can achieve).
	281	*/
	282	channel->pre_div = 0;
	283	channel->hi = ~0;
	284	channel->lo = 0;
	285
	286	meson_pwm_enable(meson, pwm);
	287	} else {
	288	meson_pwm_disable(meson, pwm);
	289	}
d6885b3e	290	} else {
7e032162	291	err = meson_pwm_calc(meson, pwm, state);
211ed630	292	if (err < 0)
f173747f	293	return err;
211ed630	294
084f1376	295	meson_pwm_enable(meson, pwm);
211ed630 NA	296	}
211ed630 NA	297
f173747f	298	return 0;
211ed630 NA	299	}
211ed630 NA	300
c375bcba MB	301	static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip,
	302	struct pwm_device *pwm, u32 cnt)
	303	{
	304	struct meson_pwm *meson = to_meson_pwm(chip);
	305	struct meson_pwm_channel *channel;
	306	unsigned long fin_freq;
	307	u32 fin_ns;
	308
	309	/* to_meson_pwm() can only be used after .get_state() is called */
	310	channel = &meson->channels[pwm->hwpwm];
	311
	312	fin_freq = clk_get_rate(channel->clk);
	313	if (fin_freq == 0)
	314	return 0;
	315
	316	fin_ns = div_u64(NSEC_PER_SEC, fin_freq);
	317
	318	return cnt * fin_ns * (channel->pre_div + 1);
	319	}
	320
211ed630 NA	321	static void meson_pwm_get_state(struct pwm_chip chip, struct pwm_device pwm,
	322	struct pwm_state *state)
	323	{
	324	struct meson_pwm *meson = to_meson_pwm(chip);
c375bcba MB	325	struct meson_pwm_channel_data *channel_data;
	326	struct meson_pwm_channel *channel;
	327	u32 value, tmp;
211ed630 NA	328
	329	if (!state)
	330	return;
	331
c375bcba MB	332	channel = &meson->channels[pwm->hwpwm];
c375bcba MB	333	channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
211ed630 NA	334
211ed630 NA	335	value = readl(meson->base + REG_MISC_AB);
c375bcba MB	336
	337	tmp = channel_data->pwm_en_mask \| channel_data->clk_en_mask;
	338	state->enabled = (value & tmp) == tmp;
	339
	340	tmp = value >> channel_data->clk_div_shift;
	341	channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp);
	342
	343	value = readl(meson->base + channel_data->reg_offset);
	344
	345	channel->lo = FIELD_GET(PWM_LOW_MASK, value);
	346	channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
	347
	348	if (channel->lo == 0) {
	349	state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
	350	state->duty_cycle = state->period;
	351	} else if (channel->lo >= channel->hi) {
	352	state->period = meson_pwm_cnt_to_ns(chip, pwm,
	353	channel->lo + channel->hi);
	354	state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm,
	355	channel->hi);
	356	} else {
	357	state->period = 0;
	358	state->duty_cycle = 0;
	359	}
211ed630 NA	360	}
	361
	362	static const struct pwm_ops meson_pwm_ops = {
	363	.request = meson_pwm_request,
	364	.free = meson_pwm_free,
	365	.apply = meson_pwm_apply,
	366	.get_state = meson_pwm_get_state,
	367	.owner = THIS_MODULE,
	368	};
	369
	370	static const char * const pwm_meson8b_parent_names[] = {
	371	"xtal", "vid_pll", "fclk_div4", "fclk_div3"
	372	};
	373
	374	static const struct meson_pwm_data pwm_meson8b_data = {
	375	.parent_names = pwm_meson8b_parent_names,
d396b20a	376	.num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
211ed630 NA	377	};
	378
	379	static const char * const pwm_gxbb_parent_names[] = {
	380	"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
	381	};
	382
	383	static const struct meson_pwm_data pwm_gxbb_data = {
	384	.parent_names = pwm_gxbb_parent_names,
d396b20a JB	385	.num_parents = ARRAY_SIZE(pwm_gxbb_parent_names),
	386	};
	387
	388	/*
	389	* Only the 2 first inputs of the GXBB AO PWMs are valid
	390	* The last 2 are grounded
	391	*/
	392	static const char * const pwm_gxbb_ao_parent_names[] = {
	393	"xtal", "clk81"
	394	};
	395
	396	static const struct meson_pwm_data pwm_gxbb_ao_data = {
	397	.parent_names = pwm_gxbb_ao_parent_names,
	398	.num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
211ed630 NA	399	};
211ed630 NA	400
bccaa3f9 JH	401	static const char * const pwm_axg_ee_parent_names[] = {
	402	"xtal", "fclk_div5", "fclk_div4", "fclk_div3"
	403	};
	404
	405	static const struct meson_pwm_data pwm_axg_ee_data = {
	406	.parent_names = pwm_axg_ee_parent_names,
	407	.num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
	408	};
	409
	410	static const char * const pwm_axg_ao_parent_names[] = {
	411	"aoclk81", "xtal", "fclk_div4", "fclk_div5"
	412	};
	413
	414	static const struct meson_pwm_data pwm_axg_ao_data = {
	415	.parent_names = pwm_axg_ao_parent_names,
	416	.num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
	417	};
	418
9bce02ef NA	419	static const char * const pwm_g12a_ao_ab_parent_names[] = {
	420	"xtal", "aoclk81", "fclk_div4", "fclk_div5"
	421	};
	422
	423	static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
	424	.parent_names = pwm_g12a_ao_ab_parent_names,
	425	.num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
	426	};
	427
f41efceb	428	static const char * const pwm_g12a_ao_cd_parent_names[] = {
9bce02ef	429	"xtal", "aoclk81",
f41efceb NA	430	};
	431
	432	static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
	433	.parent_names = pwm_g12a_ao_cd_parent_names,
	434	.num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
	435	};
	436
	437	static const char * const pwm_g12a_ee_parent_names[] = {
	438	"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
	439	};
	440
	441	static const struct meson_pwm_data pwm_g12a_ee_data = {
	442	.parent_names = pwm_g12a_ee_parent_names,
	443	.num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names),
	444	};
	445
211ed630	446	static const struct of_device_id meson_pwm_matches[] = {
d396b20a JB	447	{
	448	.compatible = "amlogic,meson8b-pwm",
	449	.data = &pwm_meson8b_data
	450	},
	451	{
	452	.compatible = "amlogic,meson-gxbb-pwm",
	453	.data = &pwm_gxbb_data
	454	},
	455	{
	456	.compatible = "amlogic,meson-gxbb-ao-pwm",
	457	.data = &pwm_gxbb_ao_data
	458	},
bccaa3f9 JH	459	{
	460	.compatible = "amlogic,meson-axg-ee-pwm",
	461	.data = &pwm_axg_ee_data
	462	},
	463	{
	464	.compatible = "amlogic,meson-axg-ao-pwm",
	465	.data = &pwm_axg_ao_data
	466	},
f41efceb NA	467	{
	468	.compatible = "amlogic,meson-g12a-ee-pwm",
	469	.data = &pwm_g12a_ee_data
	470	},
	471	{
	472	.compatible = "amlogic,meson-g12a-ao-pwm-ab",
9bce02ef	473	.data = &pwm_g12a_ao_ab_data
f41efceb NA	474	},
	475	{
	476	.compatible = "amlogic,meson-g12a-ao-pwm-cd",
	477	.data = &pwm_g12a_ao_cd_data
	478	},
211ed630 NA	479	{},
	480	};
	481	MODULE_DEVICE_TABLE(of, meson_pwm_matches);
	482
a50a49a4	483	static int meson_pwm_init_channels(struct meson_pwm *meson)
211ed630 NA	484	{
211ed630 NA	485	struct device *dev = meson->chip.dev;
211ed630 NA	486	struct clk_init_data init;
	487	unsigned int i;
	488	char name[255];
	489	int err;
	490
	491	for (i = 0; i < meson->chip.npwm; i++) {
a50a49a4	492	struct meson_pwm_channel *channel = &meson->channels[i];
211ed630	493
b96e9eb6	494	snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
211ed630 NA	495
	496	init.name = name;
	497	init.ops = &clk_mux_ops;
90b6c5c7	498	init.flags = 0;
211ed630	499	init.parent_names = meson->data->parent_names;
d396b20a	500	init.num_parents = meson->data->num_parents;
211ed630 NA	501
211ed630 NA	502	channel->mux.reg = meson->base + REG_MISC_AB;
8bbf3164 MB	503	channel->mux.shift =
8bbf3164 MB	504	meson_pwm_per_channel_data[i].clk_sel_shift;
33cefd84	505	channel->mux.mask = MISC_CLK_SEL_MASK;
211ed630 NA	506	channel->mux.flags = 0;
	507	channel->mux.lock = &meson->lock;
	508	channel->mux.table = NULL;
	509	channel->mux.hw.init = &init;
	510
	511	channel->clk = devm_clk_register(dev, &channel->mux.hw);
	512	if (IS_ERR(channel->clk)) {
	513	err = PTR_ERR(channel->clk);
	514	dev_err(dev, "failed to register %s: %d\n", name, err);
	515	return err;
	516	}
	517
	518	snprintf(name, sizeof(name), "clkin%u", i);
	519
ba4004c7 MB	520	channel->clk_parent = devm_clk_get_optional(dev, name);
	521	if (IS_ERR(channel->clk_parent))
	522	return PTR_ERR(channel->clk_parent);
211ed630 NA	523	}
	524
	525	return 0;
	526	}
	527
211ed630 NA	528	static int meson_pwm_probe(struct platform_device *pdev)
211ed630 NA	529	{
211ed630	530	struct meson_pwm *meson;
211ed630 NA	531	int err;
	532
	533	meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
	534	if (!meson)
	535	return -ENOMEM;
	536
17076b10	537	meson->base = devm_platform_ioremap_resource(pdev, 0);
211ed630 NA	538	if (IS_ERR(meson->base))
	539	return PTR_ERR(meson->base);
	540
c6999956	541	spin_lock_init(&meson->lock);
211ed630 NA	542	meson->chip.dev = &pdev->dev;
211ed630 NA	543	meson->chip.ops = &meson_pwm_ops;
a50a49a4	544	meson->chip.npwm = MESON_NUM_PWMS;
211ed630 NA	545
211ed630 NA	546	meson->data = of_device_get_match_data(&pdev->dev);
211ed630	547
a50a49a4	548	err = meson_pwm_init_channels(meson);
211ed630 NA	549	if (err < 0)
	550	return err;
	551
f41227eb	552	err = devm_pwmchip_add(&pdev->dev, &meson->chip);
211ed630 NA	553	if (err < 0) {
	554	dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
	555	return err;
	556	}
	557
211ed630 NA	558	return 0;
	559	}
	560
211ed630 NA	561	static struct platform_driver meson_pwm_driver = {
	562	.driver = {
	563	.name = "meson-pwm",
	564	.of_match_table = meson_pwm_matches,
	565	},
	566	.probe = meson_pwm_probe,
211ed630 NA	567	};
	568	module_platform_driver(meson_pwm_driver);
	569
211ed630 NA	570	MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
	571	MODULE_AUTHOR("Neil Armstrong <[email protected]>");
	572	MODULE_LICENSE("Dual BSD/GPL");