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sfc: Fix return value from efx_ethtool_set_rx_ntuple()
[linux.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <[email protected]>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
798b6b19 14 * the Free Software Foundation; either version 2 of the License.
baef58b1
SH		 15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
f15063cd
JP		 26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
14c85021 28#include <linux/in.h>
baef58b1
SH		 29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/if_vlan.h>
37#include <linux/ip.h>
38#include <linux/delay.h>
39#include <linux/crc32.h>
4075400b 40#include <linux/dma-mapping.h>
678aa1f6 41#include <linux/debugfs.h>
d43c36dc 42#include <linux/sched.h>
678aa1f6 43#include <linux/seq_file.h>
2cd8e5d3 44#include <linux/mii.h>
5a0e3ad6 45#include <linux/slab.h>
392bd0cb 46#include <linux/dmi.h>
baef58b1
SH		 47#include <asm/irq.h>
48
49#include "skge.h"
50
51#define DRV_NAME "skge"
bf9f56d5 52#define DRV_VERSION "1.13"
baef58b1
SH		 53
54#define DEFAULT_TX_RING_SIZE 128
55#define DEFAULT_RX_RING_SIZE 512
56#define MAX_TX_RING_SIZE 1024
9db96479 57#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 58#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 59#define RX_COPY_THRESHOLD 128
60#define RX_BUF_SIZE 1536
baef58b1
SH		 61#define PHY_RETRIES 1000
62#define ETH_JUMBO_MTU 9000
63#define TX_WATCHDOG (5 * HZ)
64#define NAPI_WEIGHT 64
6abebb53 65#define BLINK_MS 250
501fb72d 66#define LINK_HZ HZ
baef58b1 67
afa151b9
SH		 68#define SKGE_EEPROM_MAGIC 0x9933aabb
69
70
baef58b1 71MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
65ebe634 72MODULE_AUTHOR("Stephen Hemminger <[email protected]>");
baef58b1
SH		 73MODULE_LICENSE("GPL");
74MODULE_VERSION(DRV_VERSION);
75
67777f9b
JP		 76static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
77 NETIF_MSG_LINK | NETIF_MSG_IFUP |
78 NETIF_MSG_IFDOWN);
baef58b1
SH		 79
80static int debug = -1; /* defaults above */
81module_param(debug, int, 0);
82MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
83
a3aa1884 84static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = {
275834d1
SH		 85 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
86 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
87 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
88 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
f19841f5 89 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
2d2a3871 90 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
275834d1
SH		 91 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
92 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
93 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 94 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
f19841f5 95 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
baef58b1
SH		 96 { 0 }
97};
98MODULE_DEVICE_TABLE(pci, skge_id_table);
99
100static int skge_up(struct net_device *dev);
101static int skge_down(struct net_device *dev);
ee294dcd 102static void skge_phy_reset(struct skge_port *skge);
513f533e 103static void skge_tx_clean(struct net_device *dev);
2cd8e5d3
SH		 104static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
105static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 106static void genesis_get_stats(struct skge_port *skge, u64 *data);
107static void yukon_get_stats(struct skge_port *skge, u64 *data);
108static void yukon_init(struct skge_hw *hw, int port);
baef58b1 109static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 110static void genesis_link_up(struct skge_port *skge);
f80d032b 111static void skge_set_multicast(struct net_device *dev);
baef58b1 112
7e676d91 113/* Avoid conditionals by using array */
baef58b1
SH		 114static const int txqaddr[] = { Q_XA1, Q_XA2 };
115static const int rxqaddr[] = { Q_R1, Q_R2 };
116static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
117static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
4ebabfcb
SH		 118static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
119static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1 120
baef58b1
SH		 121static int skge_get_regs_len(struct net_device *dev)
122{
c3f8be96 123 return 0x4000;
baef58b1
SH		 124}
125
126/*
c3f8be96
SH		 127 * Returns copy of whole control register region
128 * Note: skip RAM address register because accessing it will
129 * cause bus hangs!
baef58b1
SH		 130 */
131static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
132 void *p)
133{
134 const struct skge_port *skge = netdev_priv(dev);
baef58b1 135 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 136
137 regs->version = 1;
c3f8be96
SH		 138 memset(p, 0, regs->len);
139 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 140
c3f8be96
SH		 141 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
142 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 143}
144
8f3f8193 145/* Wake on Lan only supported on Yukon chips with rev 1 or above */
a504e64a 146static u32 wol_supported(const struct skge_hw *hw)
baef58b1 147{
d17ecb23 148 if (hw->chip_id == CHIP_ID_GENESIS)
a504e64a 149 return 0;
d17ecb23
SH		 150
151 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
152 return 0;
153
154 return WAKE_MAGIC | WAKE_PHY;
a504e64a
SH		 155}
156
a504e64a
SH		 157static void skge_wol_init(struct skge_port *skge)
158{
159 struct skge_hw *hw = skge->hw;
160 int port = skge->port;
692412b3 161 u16 ctrl;
a504e64a 162
a504e64a
SH		 163 skge_write16(hw, B0_CTST, CS_RST_CLR);
164 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
165
692412b3
SH		 166 /* Turn on Vaux */
167 skge_write8(hw, B0_POWER_CTRL,
168 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
a504e64a 169
692412b3
SH		 170 /* WA code for COMA mode -- clear PHY reset */
171 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
172 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
173 u32 reg = skge_read32(hw, B2_GP_IO);
174 reg |= GP_DIR_9;
175 reg &= ~GP_IO_9;
176 skge_write32(hw, B2_GP_IO, reg);
177 }
a504e64a 178
692412b3
SH		 179 skge_write32(hw, SK_REG(port, GPHY_CTRL),
180 GPC_DIS_SLEEP |
181 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
182 GPC_ANEG_1 | GPC_RST_SET);
a504e64a 183
692412b3
SH		 184 skge_write32(hw, SK_REG(port, GPHY_CTRL),
185 GPC_DIS_SLEEP |
186 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
187 GPC_ANEG_1 | GPC_RST_CLR);
188
189 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
190
191 /* Force to 10/100 skge_reset will re-enable on resume */
192 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
67777f9b
JP		 193 (PHY_AN_100FULL | PHY_AN_100HALF |
194 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
692412b3
SH		 195 /* no 1000 HD/FD */
196 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
197 gm_phy_write(hw, port, PHY_MARV_CTRL,
198 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
199 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
a504e64a 200
a504e64a
SH		 201
202 /* Set GMAC to no flow control and auto update for speed/duplex */
203 gma_write16(hw, port, GM_GP_CTRL,
204 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
205 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
206
207 /* Set WOL address */
208 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
209 skge->netdev->dev_addr, ETH_ALEN);
210
211 /* Turn on appropriate WOL control bits */
212 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
213 ctrl = 0;
214 if (skge->wol & WAKE_PHY)
215 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
216 else
217 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
218
219 if (skge->wol & WAKE_MAGIC)
220 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
221 else
a419aef8 222 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
a504e64a
SH		 223
224 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
225 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
226
227 /* block receiver */
228 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 229}
230
231static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
232{
233 struct skge_port *skge = netdev_priv(dev);
234
a504e64a
SH		 235 wol->supported = wol_supported(skge->hw);
236 wol->wolopts = skge->wol;
baef58b1
SH		 237}
238
239static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
240{
241 struct skge_port *skge = netdev_priv(dev);
242 struct skge_hw *hw = skge->hw;
243
8e95a202
JP		 244 if ((wol->wolopts & ~wol_supported(hw)) ||
245 !device_can_wakeup(&hw->pdev->dev))
baef58b1
SH		 246 return -EOPNOTSUPP;
247
a504e64a 248 skge->wol = wol->wolopts;
5177b324
RW		 249
250 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
251
baef58b1
SH		 252 return 0;
253}
254
8f3f8193
SH		 255/* Determine supported/advertised modes based on hardware.
256 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 257 */
258static u32 skge_supported_modes(const struct skge_hw *hw)
259{
260 u32 supported;
261
5e1705dd 262 if (hw->copper) {
67777f9b
JP		 263 supported = (SUPPORTED_10baseT_Half |
264 SUPPORTED_10baseT_Full |
265 SUPPORTED_100baseT_Half |
266 SUPPORTED_100baseT_Full |
267 SUPPORTED_1000baseT_Half |
268 SUPPORTED_1000baseT_Full |
269 SUPPORTED_Autoneg |
270 SUPPORTED_TP);
31b619c5
SH		 271
272 if (hw->chip_id == CHIP_ID_GENESIS)
67777f9b
JP		 273 supported &= ~(SUPPORTED_10baseT_Half |
274 SUPPORTED_10baseT_Full |
275 SUPPORTED_100baseT_Half |
276 SUPPORTED_100baseT_Full);
31b619c5
SH		 277
278 else if (hw->chip_id == CHIP_ID_YUKON)
279 supported &= ~SUPPORTED_1000baseT_Half;
280 } else
67777f9b
JP		 281 supported = (SUPPORTED_1000baseT_Full |
282 SUPPORTED_1000baseT_Half |
283 SUPPORTED_FIBRE |
284 SUPPORTED_Autoneg);
31b619c5
SH		 285
286 return supported;
287}
baef58b1
SH		 288
289static int skge_get_settings(struct net_device *dev,
290 struct ethtool_cmd *ecmd)
291{
292 struct skge_port *skge = netdev_priv(dev);
293 struct skge_hw *hw = skge->hw;
294
295 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 296 ecmd->supported = skge_supported_modes(hw);
baef58b1 297
5e1705dd 298 if (hw->copper) {
baef58b1
SH		 299 ecmd->port = PORT_TP;
300 ecmd->phy_address = hw->phy_addr;
31b619c5 301 } else
baef58b1 302 ecmd->port = PORT_FIBRE;
baef58b1
SH		 303
304 ecmd->advertising = skge->advertising;
305 ecmd->autoneg = skge->autoneg;
70739497 306 ethtool_cmd_speed_set(ecmd, skge->speed);
baef58b1
SH		 307 ecmd->duplex = skge->duplex;
308 return 0;
309}
310
baef58b1
SH		 311static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
312{
313 struct skge_port *skge = netdev_priv(dev);
314 const struct skge_hw *hw = skge->hw;
31b619c5 315 u32 supported = skge_supported_modes(hw);
9ac1353f 316 int err = 0;
baef58b1
SH		 317
318 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 319 ecmd->advertising = supported;
320 skge->duplex = -1;
321 skge->speed = -1;
baef58b1 322 } else {
31b619c5 323 u32 setting;
25db0338 324 u32 speed = ethtool_cmd_speed(ecmd);
31b619c5 325
25db0338 326 switch (speed) {
baef58b1 327 case SPEED_1000:
31b619c5
SH		 328 if (ecmd->duplex == DUPLEX_FULL)
329 setting = SUPPORTED_1000baseT_Full;
330 else if (ecmd->duplex == DUPLEX_HALF)
331 setting = SUPPORTED_1000baseT_Half;
332 else
333 return -EINVAL;
baef58b1
SH		 334 break;
335 case SPEED_100:
31b619c5
SH		 336 if (ecmd->duplex == DUPLEX_FULL)
337 setting = SUPPORTED_100baseT_Full;
338 else if (ecmd->duplex == DUPLEX_HALF)
339 setting = SUPPORTED_100baseT_Half;
340 else
341 return -EINVAL;
342 break;
343
baef58b1 344 case SPEED_10:
31b619c5
SH		 345 if (ecmd->duplex == DUPLEX_FULL)
346 setting = SUPPORTED_10baseT_Full;
347 else if (ecmd->duplex == DUPLEX_HALF)
348 setting = SUPPORTED_10baseT_Half;
349 else
baef58b1
SH		 350 return -EINVAL;
351 break;
352 default:
353 return -EINVAL;
354 }
31b619c5
SH		 355
356 if ((setting & supported) == 0)
357 return -EINVAL;
358
25db0338 359 skge->speed = speed;
31b619c5 360 skge->duplex = ecmd->duplex;
baef58b1
SH		 361 }
362
363 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 364 skge->advertising = ecmd->advertising;
365
9ac1353f
XZ		 366 if (netif_running(dev)) {
367 skge_down(dev);
368 err = skge_up(dev);
369 if (err) {
370 dev_close(dev);
371 return err;
372 }
373 }
ee294dcd 374
67777f9b 375 return 0;
baef58b1
SH		 376}
377
378static void skge_get_drvinfo(struct net_device *dev,
379 struct ethtool_drvinfo *info)
380{
381 struct skge_port *skge = netdev_priv(dev);
382
383 strcpy(info->driver, DRV_NAME);
384 strcpy(info->version, DRV_VERSION);
385 strcpy(info->fw_version, "N/A");
386 strcpy(info->bus_info, pci_name(skge->hw->pdev));
387}
388
389static const struct skge_stat {
390 char name[ETH_GSTRING_LEN];
391 u16 xmac_offset;
392 u16 gma_offset;
393} skge_stats[] = {
394 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
395 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
396
397 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
398 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
399 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
400 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
401 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
402 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
403 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
404 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
405
406 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
407 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
408 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
409 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
410 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
411 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
412
413 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
414 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
415 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
416 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
417 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
418};
419
b9f2c044 420static int skge_get_sset_count(struct net_device *dev, int sset)
baef58b1 421{
b9f2c044
JG		 422 switch (sset) {
423 case ETH_SS_STATS:
424 return ARRAY_SIZE(skge_stats);
425 default:
426 return -EOPNOTSUPP;
427 }
baef58b1
SH		 428}
429
430static void skge_get_ethtool_stats(struct net_device *dev,
431 struct ethtool_stats *stats, u64 *data)
432{
433 struct skge_port *skge = netdev_priv(dev);
434
435 if (skge->hw->chip_id == CHIP_ID_GENESIS)
436 genesis_get_stats(skge, data);
437 else
438 yukon_get_stats(skge, data);
439}
440
441/* Use hardware MIB variables for critical path statistics and
442 * transmit feedback not reported at interrupt.
443 * Other errors are accounted for in interrupt handler.
444 */
445static struct net_device_stats *skge_get_stats(struct net_device *dev)
446{
447 struct skge_port *skge = netdev_priv(dev);
448 u64 data[ARRAY_SIZE(skge_stats)];
449
450 if (skge->hw->chip_id == CHIP_ID_GENESIS)
451 genesis_get_stats(skge, data);
452 else
453 yukon_get_stats(skge, data);
454
da00772f
SH		 455 dev->stats.tx_bytes = data[0];
456 dev->stats.rx_bytes = data[1];
457 dev->stats.tx_packets = data[2] + data[4] + data[6];
458 dev->stats.rx_packets = data[3] + data[5] + data[7];
459 dev->stats.multicast = data[3] + data[5];
460 dev->stats.collisions = data[10];
461 dev->stats.tx_aborted_errors = data[12];
baef58b1 462
da00772f 463 return &dev->stats;
baef58b1
SH		 464}
465
466static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
467{
468 int i;
469
95566065 470 switch (stringset) {
baef58b1
SH		 471 case ETH_SS_STATS:
472 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
473 memcpy(data + i * ETH_GSTRING_LEN,
474 skge_stats[i].name, ETH_GSTRING_LEN);
475 break;
476 }
477}
478
479static void skge_get_ring_param(struct net_device *dev,
480 struct ethtool_ringparam *p)
481{
482 struct skge_port *skge = netdev_priv(dev);
483
484 p->rx_max_pending = MAX_RX_RING_SIZE;
485 p->tx_max_pending = MAX_TX_RING_SIZE;
486 p->rx_mini_max_pending = 0;
487 p->rx_jumbo_max_pending = 0;
488
489 p->rx_pending = skge->rx_ring.count;
490 p->tx_pending = skge->tx_ring.count;
491 p->rx_mini_pending = 0;
492 p->rx_jumbo_pending = 0;
493}
494
495static int skge_set_ring_param(struct net_device *dev,
496 struct ethtool_ringparam *p)
497{
498 struct skge_port *skge = netdev_priv(dev);
e824b3eb 499 int err = 0;
baef58b1
SH		 500
501 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 502 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 503 return -EINVAL;
504
505 skge->rx_ring.count = p->rx_pending;
506 skge->tx_ring.count = p->tx_pending;
507
508 if (netif_running(dev)) {
509 skge_down(dev);
3b8bb472
SH		 510 err = skge_up(dev);
511 if (err)
512 dev_close(dev);
baef58b1
SH		 513 }
514
e824b3eb 515 return err;
baef58b1
SH		 516}
517
518static u32 skge_get_msglevel(struct net_device *netdev)
519{
520 struct skge_port *skge = netdev_priv(netdev);
521 return skge->msg_enable;
522}
523
524static void skge_set_msglevel(struct net_device *netdev, u32 value)
525{
526 struct skge_port *skge = netdev_priv(netdev);
527 skge->msg_enable = value;
528}
529
530static int skge_nway_reset(struct net_device *dev)
531{
532 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 533
534 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
535 return -EINVAL;
536
ee294dcd 537 skge_phy_reset(skge);
baef58b1
SH		 538 return 0;
539}
540
baef58b1
SH		 541static void skge_get_pauseparam(struct net_device *dev,
542 struct ethtool_pauseparam *ecmd)
543{
544 struct skge_port *skge = netdev_priv(dev);
545
8e95a202
JP		 546 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
547 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
548 ecmd->tx_pause = (ecmd->rx_pause ||
549 (skge->flow_control == FLOW_MODE_LOC_SEND));
baef58b1 550
5d5c8e03 551 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
baef58b1
SH		 552}
553
554static int skge_set_pauseparam(struct net_device *dev,
555 struct ethtool_pauseparam *ecmd)
556{
557 struct skge_port *skge = netdev_priv(dev);
5d5c8e03 558 struct ethtool_pauseparam old;
9ac1353f 559 int err = 0;
baef58b1 560
5d5c8e03
SH		 561 skge_get_pauseparam(dev, &old);
562
563 if (ecmd->autoneg != old.autoneg)
564 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
565 else {
566 if (ecmd->rx_pause && ecmd->tx_pause)
567 skge->flow_control = FLOW_MODE_SYMMETRIC;
568 else if (ecmd->rx_pause && !ecmd->tx_pause)
569 skge->flow_control = FLOW_MODE_SYM_OR_REM;
570 else if (!ecmd->rx_pause && ecmd->tx_pause)
571 skge->flow_control = FLOW_MODE_LOC_SEND;
572 else
573 skge->flow_control = FLOW_MODE_NONE;
574 }
baef58b1 575
9ac1353f
XZ		 576 if (netif_running(dev)) {
577 skge_down(dev);
578 err = skge_up(dev);
579 if (err) {
580 dev_close(dev);
581 return err;
582 }
583 }
5d5c8e03 584
baef58b1
SH		 585 return 0;
586}
587
588/* Chip internal frequency for clock calculations */
589static inline u32 hwkhz(const struct skge_hw *hw)
590{
187ff3b8 591 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
baef58b1
SH		 592}
593
8f3f8193 594/* Chip HZ to microseconds */
baef58b1
SH		 595static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
596{
597 return (ticks * 1000) / hwkhz(hw);
598}
599
8f3f8193 600/* Microseconds to chip HZ */
baef58b1
SH		 601static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
602{
603 return hwkhz(hw) * usec / 1000;
604}
605
606static int skge_get_coalesce(struct net_device *dev,
607 struct ethtool_coalesce *ecmd)
608{
609 struct skge_port *skge = netdev_priv(dev);
610 struct skge_hw *hw = skge->hw;
611 int port = skge->port;
612
613 ecmd->rx_coalesce_usecs = 0;
614 ecmd->tx_coalesce_usecs = 0;
615
616 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
617 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
618 u32 msk = skge_read32(hw, B2_IRQM_MSK);
619
620 if (msk & rxirqmask[port])
621 ecmd->rx_coalesce_usecs = delay;
622 if (msk & txirqmask[port])
623 ecmd->tx_coalesce_usecs = delay;
624 }
625
626 return 0;
627}
628
629/* Note: interrupt timer is per board, but can turn on/off per port */
630static int skge_set_coalesce(struct net_device *dev,
631 struct ethtool_coalesce *ecmd)
632{
633 struct skge_port *skge = netdev_priv(dev);
634 struct skge_hw *hw = skge->hw;
635 int port = skge->port;
636 u32 msk = skge_read32(hw, B2_IRQM_MSK);
637 u32 delay = 25;
638
639 if (ecmd->rx_coalesce_usecs == 0)
640 msk &= ~rxirqmask[port];
641 else if (ecmd->rx_coalesce_usecs < 25 ||
642 ecmd->rx_coalesce_usecs > 33333)
643 return -EINVAL;
644 else {
645 msk |= rxirqmask[port];
646 delay = ecmd->rx_coalesce_usecs;
647 }
648
649 if (ecmd->tx_coalesce_usecs == 0)
650 msk &= ~txirqmask[port];
651 else if (ecmd->tx_coalesce_usecs < 25 ||
652 ecmd->tx_coalesce_usecs > 33333)
653 return -EINVAL;
654 else {
655 msk |= txirqmask[port];
656 delay = min(delay, ecmd->rx_coalesce_usecs);
657 }
658
659 skge_write32(hw, B2_IRQM_MSK, msk);
660 if (msk == 0)
661 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
662 else {
663 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
664 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
665 }
666 return 0;
667}
668
6abebb53
SH		 669enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
670static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 671{
6abebb53
SH		 672 struct skge_hw *hw = skge->hw;
673 int port = skge->port;
674
9cbe330f 675 spin_lock_bh(&hw->phy_lock);
baef58b1 676 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 677 switch (mode) {
678 case LED_MODE_OFF:
64f6b64d
SH		 679 if (hw->phy_type == SK_PHY_BCOM)
680 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
681 else {
682 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
683 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
684 }
6abebb53
SH		 685 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
686 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
687 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
688 break;
baef58b1 689
6abebb53
SH		 690 case LED_MODE_ON:
691 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
692 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 693
6abebb53
SH		 694 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
695 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 696
6abebb53 697 break;
baef58b1 698
6abebb53
SH		 699 case LED_MODE_TST:
700 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
701 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
702 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 703
64f6b64d
SH		 704 if (hw->phy_type == SK_PHY_BCOM)
705 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
706 else {
707 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
708 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
709 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
710 }
711
6abebb53 712 }
baef58b1 713 } else {
6abebb53
SH		 714 switch (mode) {
715 case LED_MODE_OFF:
716 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
717 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
718 PHY_M_LED_MO_DUP(MO_LED_OFF) |
719 PHY_M_LED_MO_10(MO_LED_OFF) |
720 PHY_M_LED_MO_100(MO_LED_OFF) |
721 PHY_M_LED_MO_1000(MO_LED_OFF) |
722 PHY_M_LED_MO_RX(MO_LED_OFF));
723 break;
724 case LED_MODE_ON:
725 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
726 PHY_M_LED_PULS_DUR(PULS_170MS) |
727 PHY_M_LED_BLINK_RT(BLINK_84MS) |
728 PHY_M_LEDC_TX_CTRL |
729 PHY_M_LEDC_DP_CTRL);
46a60f2d 730
6abebb53
SH		 731 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
732 PHY_M_LED_MO_RX(MO_LED_OFF) |
733 (skge->speed == SPEED_100 ?
734 PHY_M_LED_MO_100(MO_LED_ON) : 0));
735 break;
736 case LED_MODE_TST:
737 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
738 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
739 PHY_M_LED_MO_DUP(MO_LED_ON) |
740 PHY_M_LED_MO_10(MO_LED_ON) |
741 PHY_M_LED_MO_100(MO_LED_ON) |
742 PHY_M_LED_MO_1000(MO_LED_ON) |
743 PHY_M_LED_MO_RX(MO_LED_ON));
744 }
baef58b1 745 }
9cbe330f 746 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 747}
748
749/* blink LED's for finding board */
a5b9f41c 750static int skge_set_phys_id(struct net_device *dev,
751 enum ethtool_phys_id_state state)
baef58b1
SH		 752{
753 struct skge_port *skge = netdev_priv(dev);
754
a5b9f41c 755 switch (state) {
756 case ETHTOOL_ID_ACTIVE:
fce55922 757 return 2; /* cycle on/off twice per second */
baef58b1 758
a5b9f41c 759 case ETHTOOL_ID_ON:
760 skge_led(skge, LED_MODE_TST);
761 break;
baef58b1 762
a5b9f41c 763 case ETHTOOL_ID_OFF:
764 skge_led(skge, LED_MODE_OFF);
765 break;
baef58b1 766
a5b9f41c 767 case ETHTOOL_ID_INACTIVE:
768 /* back to regular LED state */
769 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
770 }
baef58b1
SH		 771
772 return 0;
773}
774
afa151b9
SH		 775static int skge_get_eeprom_len(struct net_device *dev)
776{
777 struct skge_port *skge = netdev_priv(dev);
778 u32 reg2;
779
780 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
67777f9b 781 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
afa151b9
SH		 782}
783
784static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
785{
786 u32 val;
787
788 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
789
790 do {
791 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
792 } while (!(offset & PCI_VPD_ADDR_F));
793
794 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
795 return val;
796}
797
798static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
799{
800 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
801 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
802 offset | PCI_VPD_ADDR_F);
803
804 do {
805 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
806 } while (offset & PCI_VPD_ADDR_F);
807}
808
809static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
810 u8 *data)
811{
812 struct skge_port *skge = netdev_priv(dev);
813 struct pci_dev *pdev = skge->hw->pdev;
814 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
815 int length = eeprom->len;
816 u16 offset = eeprom->offset;
817
818 if (!cap)
819 return -EINVAL;
820
821 eeprom->magic = SKGE_EEPROM_MAGIC;
822
823 while (length > 0) {
824 u32 val = skge_vpd_read(pdev, cap, offset);
825 int n = min_t(int, length, sizeof(val));
826
827 memcpy(data, &val, n);
828 length -= n;
829 data += n;
830 offset += n;
831 }
832 return 0;
833}
834
835static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
836 u8 *data)
837{
838 struct skge_port *skge = netdev_priv(dev);
839 struct pci_dev *pdev = skge->hw->pdev;
840 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
841 int length = eeprom->len;
842 u16 offset = eeprom->offset;
843
844 if (!cap)
845 return -EINVAL;
846
847 if (eeprom->magic != SKGE_EEPROM_MAGIC)
848 return -EINVAL;
849
850 while (length > 0) {
851 u32 val;
852 int n = min_t(int, length, sizeof(val));
853
854 if (n < sizeof(val))
855 val = skge_vpd_read(pdev, cap, offset);
856 memcpy(&val, data, n);
857
858 skge_vpd_write(pdev, cap, offset, val);
859
860 length -= n;
861 data += n;
862 offset += n;
863 }
864 return 0;
865}
866
7282d491 867static const struct ethtool_ops skge_ethtool_ops = {
baef58b1
SH		 868 .get_settings = skge_get_settings,
869 .set_settings = skge_set_settings,
870 .get_drvinfo = skge_get_drvinfo,
871 .get_regs_len = skge_get_regs_len,
872 .get_regs = skge_get_regs,
873 .get_wol = skge_get_wol,
874 .set_wol = skge_set_wol,
875 .get_msglevel = skge_get_msglevel,
876 .set_msglevel = skge_set_msglevel,
877 .nway_reset = skge_nway_reset,
878 .get_link = ethtool_op_get_link,
afa151b9
SH		 879 .get_eeprom_len = skge_get_eeprom_len,
880 .get_eeprom = skge_get_eeprom,
881 .set_eeprom = skge_set_eeprom,
baef58b1
SH		 882 .get_ringparam = skge_get_ring_param,
883 .set_ringparam = skge_set_ring_param,
884 .get_pauseparam = skge_get_pauseparam,
885 .set_pauseparam = skge_set_pauseparam,
886 .get_coalesce = skge_get_coalesce,
887 .set_coalesce = skge_set_coalesce,
baef58b1 888 .get_strings = skge_get_strings,
a5b9f41c 889 .set_phys_id = skge_set_phys_id,
b9f2c044 890 .get_sset_count = skge_get_sset_count,
baef58b1
SH		 891 .get_ethtool_stats = skge_get_ethtool_stats,
892};
893
894/*
895 * Allocate ring elements and chain them together
896 * One-to-one association of board descriptors with ring elements
897 */
c3da1447 898static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 899{
900 struct skge_tx_desc *d;
901 struct skge_element *e;
902 int i;
903
cd861280 904 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
baef58b1
SH		 905 if (!ring->start)
906 return -ENOMEM;
907
908 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
909 e->desc = d;
910 if (i == ring->count - 1) {
911 e->next = ring->start;
912 d->next_offset = base;
913 } else {
914 e->next = e + 1;
915 d->next_offset = base + (i+1) * sizeof(*d);
916 }
917 }
918 ring->to_use = ring->to_clean = ring->start;
919
920 return 0;
921}
922
19a33d4e
SH		 923/* Allocate and setup a new buffer for receiving */
924static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
925 struct sk_buff *skb, unsigned int bufsize)
926{
927 struct skge_rx_desc *rd = e->desc;
928 u64 map;
baef58b1
SH		 929
930 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
931 PCI_DMA_FROMDEVICE);
932
933 rd->dma_lo = map;
934 rd->dma_hi = map >> 32;
935 e->skb = skb;
936 rd->csum1_start = ETH_HLEN;
937 rd->csum2_start = ETH_HLEN;
938 rd->csum1 = 0;
939 rd->csum2 = 0;
940
941 wmb();
942
943 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
10fc51b9
FT		 944 dma_unmap_addr_set(e, mapaddr, map);
945 dma_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 946}
947
19a33d4e
SH		 948/* Resume receiving using existing skb,
949 * Note: DMA address is not changed by chip.
950 * MTU not changed while receiver active.
951 */
5a011447 952static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 953{
954 struct skge_rx_desc *rd = e->desc;
955
956 rd->csum2 = 0;
957 rd->csum2_start = ETH_HLEN;
958
959 wmb();
960
961 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
962}
963
964
965/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 966static void skge_rx_clean(struct skge_port *skge)
967{
968 struct skge_hw *hw = skge->hw;
969 struct skge_ring *ring = &skge->rx_ring;
970 struct skge_element *e;
971
19a33d4e
SH		 972 e = ring->start;
973 do {
baef58b1
SH		 974 struct skge_rx_desc *rd = e->desc;
975 rd->control = 0;
19a33d4e
SH		 976 if (e->skb) {
977 pci_unmap_single(hw->pdev,
10fc51b9
FT		 978 dma_unmap_addr(e, mapaddr),
979 dma_unmap_len(e, maplen),
19a33d4e
SH		 980 PCI_DMA_FROMDEVICE);
981 dev_kfree_skb(e->skb);
982 e->skb = NULL;
983 }
984 } while ((e = e->next) != ring->start);
baef58b1
SH		 985}
986
19a33d4e 987
baef58b1 988/* Allocate buffers for receive ring
19a33d4e 989 * For receive: to_clean is next received frame.
baef58b1 990 */
c54f9765 991static int skge_rx_fill(struct net_device *dev)
baef58b1 992{
c54f9765 993 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 994 struct skge_ring *ring = &skge->rx_ring;
995 struct skge_element *e;
baef58b1 996
19a33d4e
SH		 997 e = ring->start;
998 do {
383181ac 999 struct sk_buff *skb;
baef58b1 1000
c54f9765
SH		 1001 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1002 GFP_KERNEL);
19a33d4e
SH		 1003 if (!skb)
1004 return -ENOMEM;
1005
383181ac
SH		 1006 skb_reserve(skb, NET_IP_ALIGN);
1007 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
67777f9b 1008 } while ((e = e->next) != ring->start);
baef58b1 1009
19a33d4e
SH		 1010 ring->to_clean = ring->start;
1011 return 0;
baef58b1
SH		 1012}
1013
5d5c8e03
SH		 1014static const char *skge_pause(enum pause_status status)
1015{
67777f9b 1016 switch (status) {
5d5c8e03
SH		 1017 case FLOW_STAT_NONE:
1018 return "none";
1019 case FLOW_STAT_REM_SEND:
1020 return "rx only";
1021 case FLOW_STAT_LOC_SEND:
1022 return "tx_only";
1023 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1024 return "both";
1025 default:
1026 return "indeterminated";
1027 }
1028}
1029
1030
baef58b1
SH		 1031static void skge_link_up(struct skge_port *skge)
1032{
46a60f2d 1033 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 1034 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1035
baef58b1 1036 netif_carrier_on(skge->netdev);
29b4e886 1037 netif_wake_queue(skge->netdev);
baef58b1 1038
d707204c
JP		 1039 netif_info(skge, link, skge->netdev,
1040 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1041 skge->speed,
1042 skge->duplex == DUPLEX_FULL ? "full" : "half",
1043 skge_pause(skge->flow_status));
baef58b1
SH		 1044}
1045
1046static void skge_link_down(struct skge_port *skge)
1047{
54cfb5aa 1048 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 1049 netif_carrier_off(skge->netdev);
1050 netif_stop_queue(skge->netdev);
1051
d707204c 1052 netif_info(skge, link, skge->netdev, "Link is down\n");
baef58b1
SH		 1053}
1054
a1bc9b87
SH		 1055
1056static void xm_link_down(struct skge_hw *hw, int port)
1057{
1058 struct net_device *dev = hw->dev[port];
1059 struct skge_port *skge = netdev_priv(dev);
a1bc9b87 1060
501fb72d 1061 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
a1bc9b87 1062
a1bc9b87
SH		 1063 if (netif_carrier_ok(dev))
1064 skge_link_down(skge);
1065}
1066
2cd8e5d3 1067static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 1068{
1069 int i;
baef58b1 1070
6b0c1480 1071 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 1072 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 1073
64f6b64d
SH		 1074 if (hw->phy_type == SK_PHY_XMAC)
1075 goto ready;
1076
89bf5f23 1077 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 1078 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 1079 goto ready;
0781191c 1080 udelay(1);
baef58b1
SH		 1081 }
1082
2cd8e5d3 1083 return -ETIMEDOUT;
89bf5f23 1084 ready:
2cd8e5d3 1085 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 1086
2cd8e5d3
SH		 1087 return 0;
1088}
1089
1090static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1091{
1092 u16 v = 0;
1093 if (__xm_phy_read(hw, port, reg, &v))
f15063cd 1094 pr_warning("%s: phy read timed out\n", hw->dev[port]->name);
baef58b1
SH		 1095 return v;
1096}
1097
2cd8e5d3 1098static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1099{
1100 int i;
1101
6b0c1480 1102 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 1103 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 1104 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 1105 goto ready;
89bf5f23 1106 udelay(1);
baef58b1 1107 }
2cd8e5d3 1108 return -EIO;
baef58b1
SH		 1109
1110 ready:
6b0c1480 1111 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 1112 for (i = 0; i < PHY_RETRIES; i++) {
1113 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1114 return 0;
1115 udelay(1);
1116 }
1117 return -ETIMEDOUT;
baef58b1
SH		 1118}
1119
1120static void genesis_init(struct skge_hw *hw)
1121{
1122 /* set blink source counter */
1123 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1124 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1125
1126 /* configure mac arbiter */
1127 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1128
1129 /* configure mac arbiter timeout values */
1130 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1131 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1132 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1133 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1134
1135 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1136 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1137 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1138 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1139
1140 /* configure packet arbiter timeout */
1141 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1142 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1143 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1144 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1145 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1146}
1147
1148static void genesis_reset(struct skge_hw *hw, int port)
1149{
b6bc7650 1150 static const u8 zero[8] = { 0 };
21d7f677 1151 u32 reg;
baef58b1 1152
46a60f2d
SH		 1153 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1154
baef58b1 1155 /* reset the statistics module */
6b0c1480 1156 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
501fb72d 1157 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
6b0c1480
SH		 1158 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1159 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1160 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 1161
89bf5f23 1162 /* disable Broadcom PHY IRQ */
64f6b64d
SH		 1163 if (hw->phy_type == SK_PHY_BCOM)
1164 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 1165
45bada65 1166 xm_outhash(hw, port, XM_HSM, zero);
21d7f677
SH		 1167
1168 /* Flush TX and RX fifo */
1169 reg = xm_read32(hw, port, XM_MODE);
1170 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1171 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
baef58b1
SH		 1172}
1173
1174
45bada65
SH		 1175/* Convert mode to MII values */
1176static const u16 phy_pause_map[] = {
1177 [FLOW_MODE_NONE] = 0,
1178 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1179 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
5d5c8e03 1180 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
45bada65
SH		 1181};
1182
4b67be99
SH		 1183/* special defines for FIBER (88E1011S only) */
1184static const u16 fiber_pause_map[] = {
1185 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1186 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1187 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
5d5c8e03 1188 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
4b67be99
SH		 1189};
1190
45bada65
SH		 1191
1192/* Check status of Broadcom phy link */
1193static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1194{
45bada65
SH		 1195 struct net_device *dev = hw->dev[port];
1196 struct skge_port *skge = netdev_priv(dev);
1197 u16 status;
1198
1199 /* read twice because of latch */
501fb72d 1200 xm_phy_read(hw, port, PHY_BCOM_STAT);
45bada65
SH		 1201 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1202
45bada65 1203 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1204 xm_link_down(hw, port);
64f6b64d
SH		 1205 return;
1206 }
45bada65 1207
64f6b64d
SH		 1208 if (skge->autoneg == AUTONEG_ENABLE) {
1209 u16 lpa, aux;
45bada65 1210
64f6b64d
SH		 1211 if (!(status & PHY_ST_AN_OVER))
1212 return;
45bada65 1213
64f6b64d
SH		 1214 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1215 if (lpa & PHY_B_AN_RF) {
f15063cd 1216 netdev_notice(dev, "remote fault\n");
64f6b64d
SH		 1217 return;
1218 }
45bada65 1219
64f6b64d
SH		 1220 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1221
1222 /* Check Duplex mismatch */
1223 switch (aux & PHY_B_AS_AN_RES_MSK) {
1224 case PHY_B_RES_1000FD:
1225 skge->duplex = DUPLEX_FULL;
1226 break;
1227 case PHY_B_RES_1000HD:
1228 skge->duplex = DUPLEX_HALF;
1229 break;
1230 default:
f15063cd 1231 netdev_notice(dev, "duplex mismatch\n");
64f6b64d 1232 return;
45bada65
SH		 1233 }
1234
64f6b64d
SH		 1235 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1236 switch (aux & PHY_B_AS_PAUSE_MSK) {
1237 case PHY_B_AS_PAUSE_MSK:
5d5c8e03 1238 skge->flow_status = FLOW_STAT_SYMMETRIC;
64f6b64d
SH		 1239 break;
1240 case PHY_B_AS_PRR:
5d5c8e03 1241 skge->flow_status = FLOW_STAT_REM_SEND;
64f6b64d
SH		 1242 break;
1243 case PHY_B_AS_PRT:
5d5c8e03 1244 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d
SH		 1245 break;
1246 default:
5d5c8e03 1247 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1248 }
1249 skge->speed = SPEED_1000;
45bada65 1250 }
64f6b64d
SH		 1251
1252 if (!netif_carrier_ok(dev))
1253 genesis_link_up(skge);
45bada65
SH		 1254}
1255
1256/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1257 * Phy on for 100 or 10Mbit operation
1258 */
64f6b64d 1259static void bcom_phy_init(struct skge_port *skge)
45bada65
SH		 1260{
1261 struct skge_hw *hw = skge->hw;
1262 int port = skge->port;
baef58b1 1263 int i;
45bada65 1264 u16 id1, r, ext, ctl;
baef58b1
SH		 1265
1266 /* magic workaround patterns for Broadcom */
1267 static const struct {
1268 u16 reg;
1269 u16 val;
1270 } A1hack[] = {
1271 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1272 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1273 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1274 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1275 }, C0hack[] = {
1276 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1277 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1278 };
1279
45bada65
SH		 1280 /* read Id from external PHY (all have the same address) */
1281 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1282
1283 /* Optimize MDIO transfer by suppressing preamble. */
1284 r = xm_read16(hw, port, XM_MMU_CMD);
1285 r |= XM_MMU_NO_PRE;
67777f9b 1286 xm_write16(hw, port, XM_MMU_CMD, r);
45bada65 1287
2c668514 1288 switch (id1) {
45bada65
SH		 1289 case PHY_BCOM_ID1_C0:
1290 /*
1291 * Workaround BCOM Errata for the C0 type.
1292 * Write magic patterns to reserved registers.
1293 */
1294 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1295 xm_phy_write(hw, port,
1296 C0hack[i].reg, C0hack[i].val);
1297
1298 break;
1299 case PHY_BCOM_ID1_A1:
1300 /*
1301 * Workaround BCOM Errata for the A1 type.
1302 * Write magic patterns to reserved registers.
1303 */
1304 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1305 xm_phy_write(hw, port,
1306 A1hack[i].reg, A1hack[i].val);
1307 break;
1308 }
1309
1310 /*
1311 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1312 * Disable Power Management after reset.
1313 */
1314 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1315 r |= PHY_B_AC_DIS_PM;
1316 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1317
1318 /* Dummy read */
1319 xm_read16(hw, port, XM_ISRC);
1320
1321 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1322 ctl = PHY_CT_SP1000; /* always 1000mbit */
1323
1324 if (skge->autoneg == AUTONEG_ENABLE) {
1325 /*
1326 * Workaround BCOM Errata #1 for the C5 type.
1327 * 1000Base-T Link Acquisition Failure in Slave Mode
1328 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1329 */
1330 u16 adv = PHY_B_1000C_RD;
1331 if (skge->advertising & ADVERTISED_1000baseT_Half)
1332 adv |= PHY_B_1000C_AHD;
1333 if (skge->advertising & ADVERTISED_1000baseT_Full)
1334 adv |= PHY_B_1000C_AFD;
1335 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1336
1337 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1338 } else {
1339 if (skge->duplex == DUPLEX_FULL)
1340 ctl |= PHY_CT_DUP_MD;
1341 /* Force to slave */
1342 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1343 }
1344
1345 /* Set autonegotiation pause parameters */
1346 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1347 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1348
1349 /* Handle Jumbo frames */
64f6b64d 1350 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
45bada65
SH		 1351 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1352 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1353
1354 ext |= PHY_B_PEC_HIGH_LA;
1355
1356 }
1357
1358 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1359 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1360
8f3f8193 1361 /* Use link status change interrupt */
45bada65 1362 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
64f6b64d 1363}
45bada65 1364
64f6b64d
SH		 1365static void xm_phy_init(struct skge_port *skge)
1366{
1367 struct skge_hw *hw = skge->hw;
1368 int port = skge->port;
1369 u16 ctrl = 0;
1370
1371 if (skge->autoneg == AUTONEG_ENABLE) {
1372 if (skge->advertising & ADVERTISED_1000baseT_Half)
1373 ctrl |= PHY_X_AN_HD;
1374 if (skge->advertising & ADVERTISED_1000baseT_Full)
1375 ctrl |= PHY_X_AN_FD;
1376
4b67be99 1377 ctrl |= fiber_pause_map[skge->flow_control];
64f6b64d
SH		 1378
1379 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1380
1381 /* Restart Auto-negotiation */
1382 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1383 } else {
1384 /* Set DuplexMode in Config register */
1385 if (skge->duplex == DUPLEX_FULL)
1386 ctrl |= PHY_CT_DUP_MD;
1387 /*
1388 * Do NOT enable Auto-negotiation here. This would hold
1389 * the link down because no IDLEs are transmitted
1390 */
1391 }
1392
1393 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1394
1395 /* Poll PHY for status changes */
9cbe330f 1396 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
64f6b64d
SH		 1397}
1398
501fb72d 1399static int xm_check_link(struct net_device *dev)
64f6b64d
SH		 1400{
1401 struct skge_port *skge = netdev_priv(dev);
1402 struct skge_hw *hw = skge->hw;
1403 int port = skge->port;
1404 u16 status;
1405
1406 /* read twice because of latch */
501fb72d 1407 xm_phy_read(hw, port, PHY_XMAC_STAT);
64f6b64d
SH		 1408 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1409
1410 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1411 xm_link_down(hw, port);
501fb72d 1412 return 0;
64f6b64d
SH		 1413 }
1414
1415 if (skge->autoneg == AUTONEG_ENABLE) {
1416 u16 lpa, res;
1417
1418 if (!(status & PHY_ST_AN_OVER))
501fb72d 1419 return 0;
64f6b64d
SH		 1420
1421 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1422 if (lpa & PHY_B_AN_RF) {
f15063cd 1423 netdev_notice(dev, "remote fault\n");
501fb72d 1424 return 0;
64f6b64d
SH		 1425 }
1426
1427 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1428
1429 /* Check Duplex mismatch */
1430 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1431 case PHY_X_RS_FD:
1432 skge->duplex = DUPLEX_FULL;
1433 break;
1434 case PHY_X_RS_HD:
1435 skge->duplex = DUPLEX_HALF;
1436 break;
1437 default:
f15063cd 1438 netdev_notice(dev, "duplex mismatch\n");
501fb72d 1439 return 0;
64f6b64d
SH		 1440 }
1441
1442 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
5d5c8e03
SH		 1443 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1444 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1445 (lpa & PHY_X_P_SYM_MD))
1446 skge->flow_status = FLOW_STAT_SYMMETRIC;
1447 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1448 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1449 /* Enable PAUSE receive, disable PAUSE transmit */
1450 skge->flow_status = FLOW_STAT_REM_SEND;
1451 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1452 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1453 /* Disable PAUSE receive, enable PAUSE transmit */
1454 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d 1455 else
5d5c8e03 1456 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1457
1458 skge->speed = SPEED_1000;
1459 }
1460
1461 if (!netif_carrier_ok(dev))
1462 genesis_link_up(skge);
501fb72d 1463 return 1;
64f6b64d
SH		 1464}
1465
1466/* Poll to check for link coming up.
501fb72d 1467 *
64f6b64d 1468 * Since internal PHY is wired to a level triggered pin, can't
501fb72d
SH		 1469 * get an interrupt when carrier is detected, need to poll for
1470 * link coming up.
64f6b64d 1471 */
9cbe330f 1472static void xm_link_timer(unsigned long arg)
64f6b64d 1473{
9cbe330f 1474 struct skge_port *skge = (struct skge_port *) arg;
c4028958 1475 struct net_device *dev = skge->netdev;
67777f9b 1476 struct skge_hw *hw = skge->hw;
64f6b64d 1477 int port = skge->port;
501fb72d
SH		 1478 int i;
1479 unsigned long flags;
64f6b64d
SH		 1480
1481 if (!netif_running(dev))
1482 return;
1483
501fb72d
SH		 1484 spin_lock_irqsave(&hw->phy_lock, flags);
1485
1486 /*
1487 * Verify that the link by checking GPIO register three times.
1488 * This pin has the signal from the link_sync pin connected to it.
1489 */
1490 for (i = 0; i < 3; i++) {
1491 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1492 goto link_down;
1493 }
1494
67777f9b 1495 /* Re-enable interrupt to detect link down */
501fb72d
SH		 1496 if (xm_check_link(dev)) {
1497 u16 msk = xm_read16(hw, port, XM_IMSK);
1498 msk &= ~XM_IS_INP_ASS;
1499 xm_write16(hw, port, XM_IMSK, msk);
64f6b64d 1500 xm_read16(hw, port, XM_ISRC);
64f6b64d 1501 } else {
501fb72d
SH		 1502link_down:
1503 mod_timer(&skge->link_timer,
1504 round_jiffies(jiffies + LINK_HZ));
64f6b64d 1505 }
501fb72d 1506 spin_unlock_irqrestore(&hw->phy_lock, flags);
45bada65
SH		 1507}
1508
1509static void genesis_mac_init(struct skge_hw *hw, int port)
1510{
1511 struct net_device *dev = hw->dev[port];
1512 struct skge_port *skge = netdev_priv(dev);
1513 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1514 int i;
1515 u32 r;
b6bc7650 1516 static const u8 zero[6] = { 0 };
45bada65 1517
0781191c
SH		 1518 for (i = 0; i < 10; i++) {
1519 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1520 MFF_SET_MAC_RST);
1521 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1522 goto reset_ok;
1523 udelay(1);
1524 }
baef58b1 1525
f15063cd 1526 netdev_warn(dev, "genesis reset failed\n");
0781191c
SH		 1527
1528 reset_ok:
baef58b1 1529 /* Unreset the XMAC. */
6b0c1480 1530 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1531
1532 /*
1533 * Perform additional initialization for external PHYs,
1534 * namely for the 1000baseTX cards that use the XMAC's
1535 * GMII mode.
1536 */
64f6b64d
SH		 1537 if (hw->phy_type != SK_PHY_XMAC) {
1538 /* Take external Phy out of reset */
1539 r = skge_read32(hw, B2_GP_IO);
1540 if (port == 0)
1541 r |= GP_DIR_0|GP_IO_0;
1542 else
1543 r |= GP_DIR_2|GP_IO_2;
89bf5f23 1544
64f6b64d 1545 skge_write32(hw, B2_GP_IO, r);
0781191c 1546
64f6b64d
SH		 1547 /* Enable GMII interface */
1548 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1549 }
89bf5f23 1550
89bf5f23 1551
67777f9b 1552 switch (hw->phy_type) {
64f6b64d
SH		 1553 case SK_PHY_XMAC:
1554 xm_phy_init(skge);
1555 break;
1556 case SK_PHY_BCOM:
1557 bcom_phy_init(skge);
1558 bcom_check_link(hw, port);
1559 }
89bf5f23 1560
45bada65
SH		 1561 /* Set Station Address */
1562 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1563
45bada65
SH		 1564 /* We don't use match addresses so clear */
1565 for (i = 1; i < 16; i++)
1566 xm_outaddr(hw, port, XM_EXM(i), zero);
1567
0781191c
SH		 1568 /* Clear MIB counters */
1569 xm_write16(hw, port, XM_STAT_CMD,
1570 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1571 /* Clear two times according to Errata #3 */
1572 xm_write16(hw, port, XM_STAT_CMD,
1573 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1574
45bada65
SH		 1575 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1576 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1577
1578 /* We don't need the FCS appended to the packet. */
1579 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1580 if (jumbo)
1581 r |= XM_RX_BIG_PK_OK;
89bf5f23 1582
45bada65 1583 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1584 /*
45bada65
SH		 1585 * If in manual half duplex mode the other side might be in
1586 * full duplex mode, so ignore if a carrier extension is not seen
1587 * on frames received
89bf5f23 1588 */
45bada65 1589 r |= XM_RX_DIS_CEXT;
baef58b1 1590 }
45bada65 1591 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1592
baef58b1 1593 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1594 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1595
485982a9
SH		 1596 /* Increase threshold for jumbo frames on dual port */
1597 if (hw->ports > 1 && jumbo)
1598 xm_write16(hw, port, XM_TX_THR, 1020);
1599 else
1600 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1601
1602 /*
1603 * Enable the reception of all error frames. This is is
1604 * a necessary evil due to the design of the XMAC. The
1605 * XMAC's receive FIFO is only 8K in size, however jumbo
1606 * frames can be up to 9000 bytes in length. When bad
1607 * frame filtering is enabled, the XMAC's RX FIFO operates
1608 * in 'store and forward' mode. For this to work, the
1609 * entire frame has to fit into the FIFO, but that means
1610 * that jumbo frames larger than 8192 bytes will be
1611 * truncated. Disabling all bad frame filtering causes
1612 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1613 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1614 * RX FIFO as soon as the FIFO threshold is reached.
1615 */
45bada65 1616 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1617
baef58b1
SH		 1618
1619 /*
45bada65
SH		 1620 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1621 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1622 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1623 */
45bada65
SH		 1624 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1625
1626 /*
1627 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1628 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1629 * and 'Octets Tx OK Hi Cnt Ov'.
1630 */
1631 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1632
1633 /* Configure MAC arbiter */
1634 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1635
1636 /* configure timeout values */
1637 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1638 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1639 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1640 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1641
1642 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1643 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1644 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1645 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1646
1647 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1648 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1649 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1650 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1651
1652 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1653 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1654 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1655 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1656
45bada65 1657 if (jumbo) {
baef58b1 1658 /* Enable frame flushing if jumbo frames used */
67777f9b 1659 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1660 } else {
1661 /* enable timeout timers if normal frames */
1662 skge_write16(hw, B3_PA_CTRL,
45bada65 1663 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1664 }
baef58b1
SH		 1665}
1666
1667static void genesis_stop(struct skge_port *skge)
1668{
1669 struct skge_hw *hw = skge->hw;
1670 int port = skge->port;
799b21d2 1671 unsigned retries = 1000;
21d7f677
SH		 1672 u16 cmd;
1673
67777f9b 1674 /* Disable Tx and Rx */
21d7f677
SH		 1675 cmd = xm_read16(hw, port, XM_MMU_CMD);
1676 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1677 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1678
46a60f2d
SH		 1679 genesis_reset(hw, port);
1680
baef58b1
SH		 1681 /* Clear Tx packet arbiter timeout IRQ */
1682 skge_write16(hw, B3_PA_CTRL,
1683 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1684
baef58b1 1685 /* Reset the MAC */
799b21d2
SH		 1686 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1687 do {
1688 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1689 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1690 break;
1691 } while (--retries > 0);
baef58b1
SH		 1692
1693 /* For external PHYs there must be special handling */
64f6b64d 1694 if (hw->phy_type != SK_PHY_XMAC) {
799b21d2 1695 u32 reg = skge_read32(hw, B2_GP_IO);
64f6b64d
SH		 1696 if (port == 0) {
1697 reg |= GP_DIR_0;
1698 reg &= ~GP_IO_0;
1699 } else {
1700 reg |= GP_DIR_2;
1701 reg &= ~GP_IO_2;
1702 }
1703 skge_write32(hw, B2_GP_IO, reg);
1704 skge_read32(hw, B2_GP_IO);
baef58b1
SH		 1705 }
1706
6b0c1480
SH		 1707 xm_write16(hw, port, XM_MMU_CMD,
1708 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1709 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1710
6b0c1480 1711 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1712}
1713
1714
1715static void genesis_get_stats(struct skge_port *skge, u64 *data)
1716{
1717 struct skge_hw *hw = skge->hw;
1718 int port = skge->port;
1719 int i;
1720 unsigned long timeout = jiffies + HZ;
1721
6b0c1480 1722 xm_write16(hw, port,
baef58b1
SH		 1723 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1724
1725 /* wait for update to complete */
6b0c1480 1726 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1727 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1728 if (time_after(jiffies, timeout))
1729 break;
1730 udelay(10);
1731 }
1732
1733 /* special case for 64 bit octet counter */
6b0c1480
SH		 1734 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1735 | xm_read32(hw, port, XM_TXO_OK_LO);
1736 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1737 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1738
1739 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1740 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1741}
1742
1743static void genesis_mac_intr(struct skge_hw *hw, int port)
1744{
da00772f
SH		 1745 struct net_device *dev = hw->dev[port];
1746 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1747 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1748
d707204c
JP		 1749 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1750 "mac interrupt status 0x%x\n", status);
baef58b1 1751
501fb72d 1752 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
67777f9b 1753 xm_link_down(hw, port);
501fb72d
SH		 1754 mod_timer(&skge->link_timer, jiffies + 1);
1755 }
a1bc9b87 1756
baef58b1 1757 if (status & XM_IS_TXF_UR) {
6b0c1480 1758 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
da00772f 1759 ++dev->stats.tx_fifo_errors;
baef58b1 1760 }
baef58b1
SH		 1761}
1762
baef58b1
SH		 1763static void genesis_link_up(struct skge_port *skge)
1764{
1765 struct skge_hw *hw = skge->hw;
1766 int port = skge->port;
a1bc9b87 1767 u16 cmd, msk;
64f6b64d 1768 u32 mode;
baef58b1 1769
6b0c1480 1770 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1771
1772 /*
1773 * enabling pause frame reception is required for 1000BT
1774 * because the XMAC is not reset if the link is going down
1775 */
5d5c8e03
SH		 1776 if (skge->flow_status == FLOW_STAT_NONE ||
1777 skge->flow_status == FLOW_STAT_LOC_SEND)
7e676d91 1778 /* Disable Pause Frame Reception */
baef58b1
SH		 1779 cmd |= XM_MMU_IGN_PF;
1780 else
1781 /* Enable Pause Frame Reception */
1782 cmd &= ~XM_MMU_IGN_PF;
1783
6b0c1480 1784 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1785
6b0c1480 1786 mode = xm_read32(hw, port, XM_MODE);
67777f9b 1787 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
5d5c8e03 1788 skge->flow_status == FLOW_STAT_LOC_SEND) {
baef58b1
SH		 1789 /*
1790 * Configure Pause Frame Generation
1791 * Use internal and external Pause Frame Generation.
1792 * Sending pause frames is edge triggered.
1793 * Send a Pause frame with the maximum pause time if
1794 * internal oder external FIFO full condition occurs.
1795 * Send a zero pause time frame to re-start transmission.
1796 */
1797 /* XM_PAUSE_DA = '010000C28001' (default) */
1798 /* XM_MAC_PTIME = 0xffff (maximum) */
1799 /* remember this value is defined in big endian (!) */
6b0c1480 1800 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1801
1802 mode |= XM_PAUSE_MODE;
6b0c1480 1803 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1804 } else {
1805 /*
1806 * disable pause frame generation is required for 1000BT
1807 * because the XMAC is not reset if the link is going down
1808 */
1809 /* Disable Pause Mode in Mode Register */
1810 mode &= ~XM_PAUSE_MODE;
1811
6b0c1480 1812 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1813 }
1814
6b0c1480 1815 xm_write32(hw, port, XM_MODE, mode);
a1bc9b87 1816
d08b9bdf 1817 /* Turn on detection of Tx underrun */
501fb72d 1818 msk = xm_read16(hw, port, XM_IMSK);
d08b9bdf 1819 msk &= ~XM_IS_TXF_UR;
a1bc9b87 1820 xm_write16(hw, port, XM_IMSK, msk);
501fb72d 1821
6b0c1480 1822 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1823
1824 /* get MMU Command Reg. */
6b0c1480 1825 cmd = xm_read16(hw, port, XM_MMU_CMD);
64f6b64d 1826 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1827 cmd |= XM_MMU_GMII_FD;
1828
89bf5f23
SH		 1829 /*
1830 * Workaround BCOM Errata (#10523) for all BCom Phys
1831 * Enable Power Management after link up
1832 */
64f6b64d
SH		 1833 if (hw->phy_type == SK_PHY_BCOM) {
1834 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1835 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1836 & ~PHY_B_AC_DIS_PM);
1837 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1838 }
baef58b1
SH		 1839
1840 /* enable Rx/Tx */
6b0c1480 1841 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1842 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1843 skge_link_up(skge);
1844}
1845
1846
45bada65 1847static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1848{
1849 struct skge_hw *hw = skge->hw;
1850 int port = skge->port;
45bada65
SH		 1851 u16 isrc;
1852
1853 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
d707204c
JP		 1854 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1855 "phy interrupt status 0x%x\n", isrc);
baef58b1 1856
45bada65 1857 if (isrc & PHY_B_IS_PSE)
f15063cd 1858 pr_err("%s: uncorrectable pair swap error\n",
45bada65 1859 hw->dev[port]->name);
baef58b1
SH		 1860
1861 /* Workaround BCom Errata:
1862 * enable and disable loopback mode if "NO HCD" occurs.
1863 */
45bada65 1864 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1865 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1866 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1867 ctrl | PHY_CT_LOOP);
6b0c1480 1868 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1869 ctrl & ~PHY_CT_LOOP);
1870 }
1871
45bada65
SH		 1872 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1873 bcom_check_link(hw, port);
baef58b1 1874
baef58b1
SH		 1875}
1876
2cd8e5d3
SH		 1877static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1878{
1879 int i;
1880
1881 gma_write16(hw, port, GM_SMI_DATA, val);
1882 gma_write16(hw, port, GM_SMI_CTRL,
1883 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1884 for (i = 0; i < PHY_RETRIES; i++) {
1885 udelay(1);
1886
1887 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1888 return 0;
1889 }
1890
f15063cd 1891 pr_warning("%s: phy write timeout\n", hw->dev[port]->name);
2cd8e5d3
SH		 1892 return -EIO;
1893}
1894
1895static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1896{
1897 int i;
1898
1899 gma_write16(hw, port, GM_SMI_CTRL,
1900 GM_SMI_CT_PHY_AD(hw->phy_addr)
1901 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1902
1903 for (i = 0; i < PHY_RETRIES; i++) {
1904 udelay(1);
1905 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1906 goto ready;
1907 }
1908
1909 return -ETIMEDOUT;
1910 ready:
1911 *val = gma_read16(hw, port, GM_SMI_DATA);
1912 return 0;
1913}
1914
1915static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1916{
1917 u16 v = 0;
1918 if (__gm_phy_read(hw, port, reg, &v))
f15063cd 1919 pr_warning("%s: phy read timeout\n", hw->dev[port]->name);
2cd8e5d3
SH		 1920 return v;
1921}
1922
8f3f8193 1923/* Marvell Phy Initialization */
baef58b1
SH		 1924static void yukon_init(struct skge_hw *hw, int port)
1925{
1926 struct skge_port *skge = netdev_priv(hw->dev[port]);
1927 u16 ctrl, ct1000, adv;
baef58b1 1928
baef58b1 1929 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1930 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1931
1932 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1933 PHY_M_EC_MAC_S_MSK);
1934 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1935
c506a509 1936 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1937
6b0c1480 1938 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1939 }
1940
6b0c1480 1941 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1942 if (skge->autoneg == AUTONEG_DISABLE)
1943 ctrl &= ~PHY_CT_ANE;
1944
1945 ctrl |= PHY_CT_RESET;
6b0c1480 1946 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1947
1948 ctrl = 0;
1949 ct1000 = 0;
b18f2091 1950 adv = PHY_AN_CSMA;
baef58b1
SH		 1951
1952 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1953 if (hw->copper) {
baef58b1
SH		 1954 if (skge->advertising & ADVERTISED_1000baseT_Full)
1955 ct1000 |= PHY_M_1000C_AFD;
1956 if (skge->advertising & ADVERTISED_1000baseT_Half)
1957 ct1000 |= PHY_M_1000C_AHD;
1958 if (skge->advertising & ADVERTISED_100baseT_Full)
1959 adv |= PHY_M_AN_100_FD;
1960 if (skge->advertising & ADVERTISED_100baseT_Half)
1961 adv |= PHY_M_AN_100_HD;
1962 if (skge->advertising & ADVERTISED_10baseT_Full)
1963 adv |= PHY_M_AN_10_FD;
1964 if (skge->advertising & ADVERTISED_10baseT_Half)
1965 adv |= PHY_M_AN_10_HD;
baef58b1 1966
4b67be99
SH		 1967 /* Set Flow-control capabilities */
1968 adv |= phy_pause_map[skge->flow_control];
1969 } else {
1970 if (skge->advertising & ADVERTISED_1000baseT_Full)
1971 adv |= PHY_M_AN_1000X_AFD;
1972 if (skge->advertising & ADVERTISED_1000baseT_Half)
1973 adv |= PHY_M_AN_1000X_AHD;
1974
1975 adv |= fiber_pause_map[skge->flow_control];
1976 }
45bada65 1977
baef58b1
SH		 1978 /* Restart Auto-negotiation */
1979 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1980 } else {
1981 /* forced speed/duplex settings */
1982 ct1000 = PHY_M_1000C_MSE;
1983
1984 if (skge->duplex == DUPLEX_FULL)
1985 ctrl |= PHY_CT_DUP_MD;
1986
1987 switch (skge->speed) {
1988 case SPEED_1000:
1989 ctrl |= PHY_CT_SP1000;
1990 break;
1991 case SPEED_100:
1992 ctrl |= PHY_CT_SP100;
1993 break;
1994 }
1995
1996 ctrl |= PHY_CT_RESET;
1997 }
1998
c506a509 1999 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 2000
6b0c1480
SH		 2001 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2002 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 2003
baef58b1
SH		 2004 /* Enable phy interrupt on autonegotiation complete (or link up) */
2005 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 2006 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 2007 else
4cde06ed 2008 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2009}
2010
2011static void yukon_reset(struct skge_hw *hw, int port)
2012{
6b0c1480
SH		 2013 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2014 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2015 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2016 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2017 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 2018
6b0c1480
SH		 2019 gma_write16(hw, port, GM_RX_CTRL,
2020 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 2021 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2022}
2023
c8868611
SH		 2024/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2025static int is_yukon_lite_a0(struct skge_hw *hw)
2026{
2027 u32 reg;
2028 int ret;
2029
2030 if (hw->chip_id != CHIP_ID_YUKON)
2031 return 0;
2032
2033 reg = skge_read32(hw, B2_FAR);
2034 skge_write8(hw, B2_FAR + 3, 0xff);
2035 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2036 skge_write32(hw, B2_FAR, reg);
2037 return ret;
2038}
2039
baef58b1
SH		 2040static void yukon_mac_init(struct skge_hw *hw, int port)
2041{
2042 struct skge_port *skge = netdev_priv(hw->dev[port]);
2043 int i;
2044 u32 reg;
2045 const u8 *addr = hw->dev[port]->dev_addr;
2046
2047 /* WA code for COMA mode -- set PHY reset */
2048 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2049 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2050 reg = skge_read32(hw, B2_GP_IO);
2051 reg |= GP_DIR_9 | GP_IO_9;
2052 skge_write32(hw, B2_GP_IO, reg);
2053 }
baef58b1
SH		 2054
2055 /* hard reset */
6b0c1480
SH		 2056 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2057 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2058
2059 /* WA code for COMA mode -- clear PHY reset */
2060 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2061 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2062 reg = skge_read32(hw, B2_GP_IO);
2063 reg |= GP_DIR_9;
2064 reg &= ~GP_IO_9;
2065 skge_write32(hw, B2_GP_IO, reg);
2066 }
baef58b1
SH		 2067
2068 /* Set hardware config mode */
2069 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2070 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 2071 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 2072
2073 /* Clear GMC reset */
6b0c1480
SH		 2074 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2075 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2076 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 2077
baef58b1
SH		 2078 if (skge->autoneg == AUTONEG_DISABLE) {
2079 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 2080 gma_write16(hw, port, GM_GP_CTRL,
2081 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 2082
2083 switch (skge->speed) {
2084 case SPEED_1000:
564f9abb 2085 reg &= ~GM_GPCR_SPEED_100;
baef58b1 2086 reg |= GM_GPCR_SPEED_1000;
564f9abb 2087 break;
baef58b1 2088 case SPEED_100:
564f9abb 2089 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 2090 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 2091 break;
2092 case SPEED_10:
2093 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2094 break;
baef58b1
SH		 2095 }
2096
2097 if (skge->duplex == DUPLEX_FULL)
2098 reg |= GM_GPCR_DUP_FULL;
2099 } else
2100 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 2101
baef58b1
SH		 2102 switch (skge->flow_control) {
2103 case FLOW_MODE_NONE:
6b0c1480 2104 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 2105 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2106 break;
2107 case FLOW_MODE_LOC_SEND:
2108 /* disable Rx flow-control */
2109 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
5d5c8e03
SH		 2110 break;
2111 case FLOW_MODE_SYMMETRIC:
2112 case FLOW_MODE_SYM_OR_REM:
2113 /* enable Tx & Rx flow-control */
2114 break;
baef58b1
SH		 2115 }
2116
6b0c1480 2117 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 2118 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2119
baef58b1 2120 yukon_init(hw, port);
baef58b1
SH		 2121
2122 /* MIB clear */
6b0c1480
SH		 2123 reg = gma_read16(hw, port, GM_PHY_ADDR);
2124 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 2125
2126 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 2127 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2128 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 2129
2130 /* transmit control */
6b0c1480 2131 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 2132
2133 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 2134 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 2135 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2136
2137 /* transmit flow control */
6b0c1480 2138 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 2139
2140 /* transmit parameter */
6b0c1480 2141 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 2142 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2143 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2144 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2145
44c7fcce
SH		 2146 /* configure the Serial Mode Register */
2147 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2148 | GM_SMOD_VLAN_ENA
2149 | IPG_DATA_VAL(IPG_DATA_DEF);
2150
2151 if (hw->dev[port]->mtu > ETH_DATA_LEN)
baef58b1
SH		 2152 reg |= GM_SMOD_JUMBO_ENA;
2153
6b0c1480 2154 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 2155
2156 /* physical address: used for pause frames */
6b0c1480 2157 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 2158 /* virtual address for data */
6b0c1480 2159 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 2160
2161 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 2162 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2163 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2164 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 2165
2166 /* Initialize Mac Fifo */
2167
2168 /* Configure Rx MAC FIFO */
6b0c1480 2169 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 2170 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 2171
2172 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2173 if (is_yukon_lite_a0(hw))
baef58b1 2174 reg &= ~GMF_RX_F_FL_ON;
c8868611 2175
6b0c1480
SH		 2176 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2177 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 2178 /*
2179 * because Pause Packet Truncation in GMAC is not working
2180 * we have to increase the Flush Threshold to 64 bytes
2181 * in order to flush pause packets in Rx FIFO on Yukon-1
2182 */
2183 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 2184
2185 /* Configure Tx MAC FIFO */
6b0c1480
SH		 2186 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2187 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 2188}
2189
355ec572
SH		 2190/* Go into power down mode */
2191static void yukon_suspend(struct skge_hw *hw, int port)
2192{
2193 u16 ctrl;
2194
2195 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2196 ctrl |= PHY_M_PC_POL_R_DIS;
2197 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2198
2199 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2200 ctrl |= PHY_CT_RESET;
2201 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2202
2203 /* switch IEEE compatible power down mode on */
2204 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2205 ctrl |= PHY_CT_PDOWN;
2206 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2207}
2208
baef58b1
SH		 2209static void yukon_stop(struct skge_port *skge)
2210{
2211 struct skge_hw *hw = skge->hw;
2212 int port = skge->port;
2213
46a60f2d
SH		 2214 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2215 yukon_reset(hw, port);
baef58b1 2216
6b0c1480
SH		 2217 gma_write16(hw, port, GM_GP_CTRL,
2218 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 2219 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 2220 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 2221
355ec572 2222 yukon_suspend(hw, port);
46a60f2d 2223
baef58b1 2224 /* set GPHY Control reset */
46a60f2d
SH		 2225 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2226 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2227}
2228
2229static void yukon_get_stats(struct skge_port *skge, u64 *data)
2230{
2231 struct skge_hw *hw = skge->hw;
2232 int port = skge->port;
2233 int i;
2234
6b0c1480
SH		 2235 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2236 | gma_read32(hw, port, GM_TXO_OK_LO);
2237 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2238 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 2239
2240 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 2241 data[i] = gma_read32(hw, port,
baef58b1
SH		 2242 skge_stats[i].gma_offset);
2243}
2244
2245static void yukon_mac_intr(struct skge_hw *hw, int port)
2246{
7e676d91
SH		 2247 struct net_device *dev = hw->dev[port];
2248 struct skge_port *skge = netdev_priv(dev);
6b0c1480 2249 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2250
d707204c
JP		 2251 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2252 "mac interrupt status 0x%x\n", status);
7e676d91 2253
baef58b1 2254 if (status & GM_IS_RX_FF_OR) {
da00772f 2255 ++dev->stats.rx_fifo_errors;
d8a09943 2256 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 2257 }
d8a09943 2258
baef58b1 2259 if (status & GM_IS_TX_FF_UR) {
da00772f 2260 ++dev->stats.tx_fifo_errors;
d8a09943 2261 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 2262 }
2263
2264}
2265
2266static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2267{
95566065 2268 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 2269 case PHY_M_PS_SPEED_1000:
2270 return SPEED_1000;
2271 case PHY_M_PS_SPEED_100:
2272 return SPEED_100;
2273 default:
2274 return SPEED_10;
2275 }
2276}
2277
2278static void yukon_link_up(struct skge_port *skge)
2279{
2280 struct skge_hw *hw = skge->hw;
2281 int port = skge->port;
2282 u16 reg;
2283
baef58b1 2284 /* Enable Transmit FIFO Underrun */
46a60f2d 2285 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 2286
6b0c1480 2287 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 2288 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2289 reg |= GM_GPCR_DUP_FULL;
2290
2291 /* enable Rx/Tx */
2292 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 2293 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 2294
4cde06ed 2295 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2296 skge_link_up(skge);
2297}
2298
2299static void yukon_link_down(struct skge_port *skge)
2300{
2301 struct skge_hw *hw = skge->hw;
2302 int port = skge->port;
d8a09943 2303 u16 ctrl;
baef58b1 2304
d8a09943
SH		 2305 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2306 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2307 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 2308
5d5c8e03
SH		 2309 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2310 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2311 ctrl |= PHY_M_AN_ASP;
baef58b1 2312 /* restore Asymmetric Pause bit */
5d5c8e03 2313 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
baef58b1
SH		 2314 }
2315
baef58b1
SH		 2316 skge_link_down(skge);
2317
2318 yukon_init(hw, port);
2319}
2320
2321static void yukon_phy_intr(struct skge_port *skge)
2322{
2323 struct skge_hw *hw = skge->hw;
2324 int port = skge->port;
2325 const char *reason = NULL;
2326 u16 istatus, phystat;
2327
6b0c1480
SH		 2328 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2329 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91 2330
d707204c
JP		 2331 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2332 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
baef58b1
SH		 2333
2334 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2335 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2336 & PHY_M_AN_RF) {
2337 reason = "remote fault";
2338 goto failed;
2339 }
2340
c506a509 2341 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 2342 reason = "master/slave fault";
2343 goto failed;
2344 }
2345
2346 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2347 reason = "speed/duplex";
2348 goto failed;
2349 }
2350
2351 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2352 ? DUPLEX_FULL : DUPLEX_HALF;
2353 skge->speed = yukon_speed(hw, phystat);
2354
baef58b1
SH		 2355 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2356 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2357 case PHY_M_PS_PAUSE_MSK:
5d5c8e03 2358 skge->flow_status = FLOW_STAT_SYMMETRIC;
baef58b1
SH		 2359 break;
2360 case PHY_M_PS_RX_P_EN:
5d5c8e03 2361 skge->flow_status = FLOW_STAT_REM_SEND;
baef58b1
SH		 2362 break;
2363 case PHY_M_PS_TX_P_EN:
5d5c8e03 2364 skge->flow_status = FLOW_STAT_LOC_SEND;
baef58b1
SH		 2365 break;
2366 default:
5d5c8e03 2367 skge->flow_status = FLOW_STAT_NONE;
baef58b1
SH		 2368 }
2369
5d5c8e03 2370 if (skge->flow_status == FLOW_STAT_NONE ||
baef58b1 2371 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2372 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2373 else
6b0c1480 2374 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2375 yukon_link_up(skge);
2376 return;
2377 }
2378
2379 if (istatus & PHY_M_IS_LSP_CHANGE)
2380 skge->speed = yukon_speed(hw, phystat);
2381
2382 if (istatus & PHY_M_IS_DUP_CHANGE)
2383 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2384 if (istatus & PHY_M_IS_LST_CHANGE) {
2385 if (phystat & PHY_M_PS_LINK_UP)
2386 yukon_link_up(skge);
2387 else
2388 yukon_link_down(skge);
2389 }
2390 return;
2391 failed:
f15063cd 2392 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
baef58b1
SH		 2393
2394 /* XXX restart autonegotiation? */
2395}
2396
ee294dcd
SH		 2397static void skge_phy_reset(struct skge_port *skge)
2398{
2399 struct skge_hw *hw = skge->hw;
2400 int port = skge->port;
aae343d4 2401 struct net_device *dev = hw->dev[port];
ee294dcd
SH		 2402
2403 netif_stop_queue(skge->netdev);
2404 netif_carrier_off(skge->netdev);
2405
9cbe330f 2406 spin_lock_bh(&hw->phy_lock);
ee294dcd
SH		 2407 if (hw->chip_id == CHIP_ID_GENESIS) {
2408 genesis_reset(hw, port);
2409 genesis_mac_init(hw, port);
2410 } else {
2411 yukon_reset(hw, port);
2412 yukon_init(hw, port);
2413 }
9cbe330f 2414 spin_unlock_bh(&hw->phy_lock);
75814090 2415
f80d032b 2416 skge_set_multicast(dev);
ee294dcd
SH		 2417}
2418
2cd8e5d3
SH		 2419/* Basic MII support */
2420static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2421{
2422 struct mii_ioctl_data *data = if_mii(ifr);
2423 struct skge_port *skge = netdev_priv(dev);
2424 struct skge_hw *hw = skge->hw;
2425 int err = -EOPNOTSUPP;
2426
2427 if (!netif_running(dev))
2428 return -ENODEV; /* Phy still in reset */
2429
67777f9b 2430 switch (cmd) {
2cd8e5d3
SH		 2431 case SIOCGMIIPHY:
2432 data->phy_id = hw->phy_addr;
2433
2434 /* fallthru */
2435 case SIOCGMIIREG: {
2436 u16 val = 0;
9cbe330f 2437 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2438 if (hw->chip_id == CHIP_ID_GENESIS)
2439 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2440 else
2441 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
9cbe330f 2442 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2443 data->val_out = val;
2444 break;
2445 }
2446
2447 case SIOCSMIIREG:
9cbe330f 2448 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2449 if (hw->chip_id == CHIP_ID_GENESIS)
2450 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2451 data->val_in);
2452 else
2453 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2454 data->val_in);
9cbe330f 2455 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2456 break;
2457 }
2458 return err;
2459}
2460
279e1dab 2461static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
baef58b1
SH		 2462{
2463 u32 end;
2464
279e1dab
LT		 2465 start /= 8;
2466 len /= 8;
2467 end = start + len - 1;
baef58b1
SH		 2468
2469 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2470 skge_write32(hw, RB_ADDR(q, RB_START), start);
2471 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2472 skge_write32(hw, RB_ADDR(q, RB_RP), start);
279e1dab 2473 skge_write32(hw, RB_ADDR(q, RB_END), end);
baef58b1
SH		 2474
2475 if (q == Q_R1 || q == Q_R2) {
2476 /* Set thresholds on receive queue's */
279e1dab
LT		 2477 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2478 start + (2*len)/3);
2479 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2480 start + (len/3));
2481 } else {
2482 /* Enable store & forward on Tx queue's because
2483 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2484 */
baef58b1 2485 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
279e1dab 2486 }
baef58b1
SH		 2487
2488 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2489}
2490
2491/* Setup Bus Memory Interface */
2492static void skge_qset(struct skge_port *skge, u16 q,
2493 const struct skge_element *e)
2494{
2495 struct skge_hw *hw = skge->hw;
2496 u32 watermark = 0x600;
2497 u64 base = skge->dma + (e->desc - skge->mem);
2498
2499 /* optimization to reduce window on 32bit/33mhz */
2500 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2501 watermark /= 2;
2502
2503 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2504 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2505 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2506 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2507}
2508
2509static int skge_up(struct net_device *dev)
2510{
2511 struct skge_port *skge = netdev_priv(dev);
2512 struct skge_hw *hw = skge->hw;
2513 int port = skge->port;
279e1dab 2514 u32 chunk, ram_addr;
baef58b1
SH		 2515 size_t rx_size, tx_size;
2516 int err;
2517
fae87592
SH		 2518 if (!is_valid_ether_addr(dev->dev_addr))
2519 return -EINVAL;
2520
d707204c 2521 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
baef58b1 2522
19a33d4e 2523 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2524 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2525 else
2526 skge->rx_buf_size = RX_BUF_SIZE;
2527
2528
baef58b1
SH		 2529 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2530 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2531 skge->mem_size = tx_size + rx_size;
2532 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2533 if (!skge->mem)
2534 return -ENOMEM;
2535
c3da1447
SH		 2536 BUG_ON(skge->dma & 7);
2537
2538 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
1479d13c 2539 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
c3da1447
SH		 2540 err = -EINVAL;
2541 goto free_pci_mem;
2542 }
2543
baef58b1
SH		 2544 memset(skge->mem, 0, skge->mem_size);
2545
203babb6
SH		 2546 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2547 if (err)
baef58b1
SH		 2548 goto free_pci_mem;
2549
c54f9765 2550 err = skge_rx_fill(dev);
19a33d4e 2551 if (err)
baef58b1
SH		 2552 goto free_rx_ring;
2553
203babb6
SH		 2554 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2555 skge->dma + rx_size);
2556 if (err)
baef58b1
SH		 2557 goto free_rx_ring;
2558
8f3f8193 2559 /* Initialize MAC */
9cbe330f 2560 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2561 if (hw->chip_id == CHIP_ID_GENESIS)
2562 genesis_mac_init(hw, port);
2563 else
2564 yukon_mac_init(hw, port);
9cbe330f 2565 spin_unlock_bh(&hw->phy_lock);
baef58b1 2566
29816d9a
SH		 2567 /* Configure RAMbuffers - equally between ports and tx/rx */
2568 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
279e1dab 2569 ram_addr = hw->ram_offset + 2 * chunk * port;
baef58b1 2570
279e1dab 2571 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
7fb7ac24 2572 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
279e1dab 2573
baef58b1 2574 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
279e1dab 2575 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
baef58b1
SH		 2576 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2577
2578 /* Start receiver BMU */
2579 wmb();
2580 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2581 skge_led(skge, LED_MODE_ON);
baef58b1 2582
4ebabfcb
SH		 2583 spin_lock_irq(&hw->hw_lock);
2584 hw->intr_mask |= portmask[port];
2585 skge_write32(hw, B0_IMSK, hw->intr_mask);
2586 spin_unlock_irq(&hw->hw_lock);
2587
bea3348e 2588 napi_enable(&skge->napi);
baef58b1
SH		 2589 return 0;
2590
2591 free_rx_ring:
2592 skge_rx_clean(skge);
2593 kfree(skge->rx_ring.start);
2594 free_pci_mem:
2595 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2596 skge->mem = NULL;
baef58b1
SH		 2597
2598 return err;
2599}
2600
60b24b51
SH		 2601/* stop receiver */
2602static void skge_rx_stop(struct skge_hw *hw, int port)
2603{
2604 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2605 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2606 RB_RST_SET|RB_DIS_OP_MD);
2607 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2608}
2609
baef58b1
SH		 2610static int skge_down(struct net_device *dev)
2611{
2612 struct skge_port *skge = netdev_priv(dev);
2613 struct skge_hw *hw = skge->hw;
2614 int port = skge->port;
2615
7731a4ea
SH		 2616 if (skge->mem == NULL)
2617 return 0;
2618
d707204c 2619 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
baef58b1 2620
d119b392 2621 netif_tx_disable(dev);
692412b3 2622
64f6b64d 2623 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
9cbe330f 2624 del_timer_sync(&skge->link_timer);
baef58b1 2625
bea3348e 2626 napi_disable(&skge->napi);
692412b3 2627 netif_carrier_off(dev);
4ebabfcb
SH		 2628
2629 spin_lock_irq(&hw->hw_lock);
2630 hw->intr_mask &= ~portmask[port];
2631 skge_write32(hw, B0_IMSK, hw->intr_mask);
2632 spin_unlock_irq(&hw->hw_lock);
2633
46a60f2d
SH		 2634 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2635 if (hw->chip_id == CHIP_ID_GENESIS)
2636 genesis_stop(skge);
2637 else
2638 yukon_stop(skge);
2639
baef58b1
SH		 2640 /* Stop transmitter */
2641 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2642 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2643 RB_RST_SET|RB_DIS_OP_MD);
2644
baef58b1
SH		 2645
2646 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2647 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2648 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2649
2650 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2651 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2652 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2653
2654 /* Reset PCI FIFO */
2655 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2656 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2657
2658 /* Reset the RAM Buffer async Tx queue */
2659 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
60b24b51
SH		 2660
2661 skge_rx_stop(hw, port);
baef58b1
SH		 2662
2663 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2664 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2665 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2666 } else {
6b0c1480
SH		 2667 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2668 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2669 }
2670
6abebb53 2671 skge_led(skge, LED_MODE_OFF);
baef58b1 2672
e3a1b99f 2673 netif_tx_lock_bh(dev);
513f533e 2674 skge_tx_clean(dev);
e3a1b99f
SH		 2675 netif_tx_unlock_bh(dev);
2676
baef58b1
SH		 2677 skge_rx_clean(skge);
2678
2679 kfree(skge->rx_ring.start);
2680 kfree(skge->tx_ring.start);
2681 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2682 skge->mem = NULL;
baef58b1
SH		 2683 return 0;
2684}
2685
29b4e886
SH		 2686static inline int skge_avail(const struct skge_ring *ring)
2687{
992c9623 2688 smp_mb();
29b4e886
SH		 2689 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2690 + (ring->to_clean - ring->to_use) - 1;
2691}
2692
61357325
SH		 2693static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2694 struct net_device *dev)
baef58b1
SH		 2695{
2696 struct skge_port *skge = netdev_priv(dev);
2697 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2698 struct skge_element *e;
2699 struct skge_tx_desc *td;
2700 int i;
2701 u32 control, len;
2702 u64 map;
baef58b1 2703
5b057c6b 2704 if (skb_padto(skb, ETH_ZLEN))
baef58b1
SH		 2705 return NETDEV_TX_OK;
2706
513f533e 2707 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
baef58b1 2708 return NETDEV_TX_BUSY;
baef58b1 2709
7c442fa1 2710 e = skge->tx_ring.to_use;
baef58b1 2711 td = e->desc;
7c442fa1 2712 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2713 e->skb = skb;
2714 len = skb_headlen(skb);
2715 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
10fc51b9
FT		 2716 dma_unmap_addr_set(e, mapaddr, map);
2717 dma_unmap_len_set(e, maplen, len);
baef58b1
SH		 2718
2719 td->dma_lo = map;
2720 td->dma_hi = map >> 32;
2721
84fa7933 2722 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 2723 const int offset = skb_checksum_start_offset(skb);
baef58b1
SH		 2724
2725 /* This seems backwards, but it is what the sk98lin
2726 * does. Looks like hardware is wrong?
2727 */
8e95a202 2728 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
67777f9b 2729 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2730 control = BMU_TCP_CHECK;
2731 else
2732 control = BMU_UDP_CHECK;
2733
2734 td->csum_offs = 0;
2735 td->csum_start = offset;
ff1dcadb 2736 td->csum_write = offset + skb->csum_offset;
baef58b1
SH		 2737 } else
2738 control = BMU_CHECK;
2739
2740 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
67777f9b 2741 control |= BMU_EOF | BMU_IRQ_EOF;
baef58b1
SH		 2742 else {
2743 struct skge_tx_desc *tf = td;
2744
2745 control |= BMU_STFWD;
2746 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2747 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2748
2749 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2750 frag->size, PCI_DMA_TODEVICE);
2751
2752 e = e->next;
7c442fa1 2753 e->skb = skb;
baef58b1 2754 tf = e->desc;
7c442fa1
SH		 2755 BUG_ON(tf->control & BMU_OWN);
2756
baef58b1
SH		 2757 tf->dma_lo = map;
2758 tf->dma_hi = (u64) map >> 32;
10fc51b9
FT		 2759 dma_unmap_addr_set(e, mapaddr, map);
2760 dma_unmap_len_set(e, maplen, frag->size);
baef58b1
SH		 2761
2762 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2763 }
2764 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2765 }
2766 /* Make sure all the descriptors written */
2767 wmb();
2768 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2769 wmb();
2770
2771 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2772
d707204c
JP		 2773 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2774 "tx queued, slot %td, len %d\n",
2775 e - skge->tx_ring.start, skb->len);
baef58b1 2776
7c442fa1 2777 skge->tx_ring.to_use = e->next;
992c9623
SH		 2778 smp_wmb();
2779
9db96479 2780 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
f15063cd 2781 netdev_dbg(dev, "transmit queue full\n");
baef58b1
SH		 2782 netif_stop_queue(dev);
2783 }
2784
baef58b1
SH		 2785 return NETDEV_TX_OK;
2786}
2787
7c442fa1
SH		 2788
2789/* Free resources associated with this reing element */
2790static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2791 u32 control)
866b4f3e
SH		 2792{
2793 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2794
7c442fa1
SH		 2795 /* skb header vs. fragment */
2796 if (control & BMU_STF)
10fc51b9
FT		 2797 pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr),
2798 dma_unmap_len(e, maplen),
7c442fa1
SH		 2799 PCI_DMA_TODEVICE);
2800 else
10fc51b9
FT		 2801 pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr),
2802 dma_unmap_len(e, maplen),
7c442fa1 2803 PCI_DMA_TODEVICE);
866b4f3e 2804
7c442fa1 2805 if (control & BMU_EOF) {
d707204c
JP		 2806 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
2807 "tx done slot %td\n", e - skge->tx_ring.start);
866b4f3e 2808
513f533e 2809 dev_kfree_skb(e->skb);
baef58b1
SH		 2810 }
2811}
2812
7c442fa1 2813/* Free all buffers in transmit ring */
513f533e 2814static void skge_tx_clean(struct net_device *dev)
baef58b1 2815{
513f533e 2816 struct skge_port *skge = netdev_priv(dev);
7c442fa1 2817 struct skge_element *e;
baef58b1 2818
7c442fa1
SH		 2819 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2820 struct skge_tx_desc *td = e->desc;
2821 skge_tx_free(skge, e, td->control);
2822 td->control = 0;
2823 }
2824
2825 skge->tx_ring.to_clean = e;
baef58b1
SH		 2826}
2827
2828static void skge_tx_timeout(struct net_device *dev)
2829{
2830 struct skge_port *skge = netdev_priv(dev);
2831
d707204c 2832 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
baef58b1
SH		 2833
2834 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
513f533e 2835 skge_tx_clean(dev);
d119b392 2836 netif_wake_queue(dev);
baef58b1
SH		 2837}
2838
2839static int skge_change_mtu(struct net_device *dev, int new_mtu)
2840{
7731a4ea 2841 int err;
baef58b1 2842
95566065 2843 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2844 return -EINVAL;
2845
7731a4ea
SH		 2846 if (!netif_running(dev)) {
2847 dev->mtu = new_mtu;
2848 return 0;
2849 }
2850
1a8098be 2851 skge_down(dev);
baef58b1 2852
19a33d4e 2853 dev->mtu = new_mtu;
7731a4ea 2854
1a8098be 2855 err = skge_up(dev);
7731a4ea
SH		 2856 if (err)
2857 dev_close(dev);
baef58b1
SH		 2858
2859 return err;
2860}
2861
c4cd29d2
SH		 2862static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2863
2864static void genesis_add_filter(u8 filter[8], const u8 *addr)
2865{
2866 u32 crc, bit;
2867
2868 crc = ether_crc_le(ETH_ALEN, addr);
2869 bit = ~crc & 0x3f;
2870 filter[bit/8] |= 1 << (bit%8);
2871}
2872
baef58b1
SH		 2873static void genesis_set_multicast(struct net_device *dev)
2874{
2875 struct skge_port *skge = netdev_priv(dev);
2876 struct skge_hw *hw = skge->hw;
2877 int port = skge->port;
22bedad3 2878 struct netdev_hw_addr *ha;
baef58b1
SH		 2879 u32 mode;
2880 u8 filter[8];
2881
6b0c1480 2882 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2883 mode |= XM_MD_ENA_HASH;
2884 if (dev->flags & IFF_PROMISC)
2885 mode |= XM_MD_ENA_PROM;
2886 else
2887 mode &= ~XM_MD_ENA_PROM;
2888
2889 if (dev->flags & IFF_ALLMULTI)
2890 memset(filter, 0xff, sizeof(filter));
2891 else {
2892 memset(filter, 0, sizeof(filter));
c4cd29d2 2893
8e95a202
JP		 2894 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2895 skge->flow_status == FLOW_STAT_SYMMETRIC)
c4cd29d2
SH		 2896 genesis_add_filter(filter, pause_mc_addr);
2897
22bedad3
JP		 2898 netdev_for_each_mc_addr(ha, dev)
2899 genesis_add_filter(filter, ha->addr);
baef58b1
SH		 2900 }
2901
6b0c1480 2902 xm_write32(hw, port, XM_MODE, mode);
45bada65 2903 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2904}
2905
c4cd29d2
SH		 2906static void yukon_add_filter(u8 filter[8], const u8 *addr)
2907{
2908 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2909 filter[bit/8] |= 1 << (bit%8);
2910}
2911
baef58b1
SH		 2912static void yukon_set_multicast(struct net_device *dev)
2913{
2914 struct skge_port *skge = netdev_priv(dev);
2915 struct skge_hw *hw = skge->hw;
2916 int port = skge->port;
22bedad3 2917 struct netdev_hw_addr *ha;
8e95a202
JP		 2918 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2919 skge->flow_status == FLOW_STAT_SYMMETRIC);
baef58b1
SH		 2920 u16 reg;
2921 u8 filter[8];
2922
2923 memset(filter, 0, sizeof(filter));
2924
6b0c1480 2925 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2926 reg |= GM_RXCR_UCF_ENA;
2927
8f3f8193 2928 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2929 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2930 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2931 memset(filter, 0xff, sizeof(filter));
4cd24eaf 2932 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
baef58b1
SH		 2933 reg &= ~GM_RXCR_MCF_ENA;
2934 else {
baef58b1
SH		 2935 reg |= GM_RXCR_MCF_ENA;
2936
c4cd29d2
SH		 2937 if (rx_pause)
2938 yukon_add_filter(filter, pause_mc_addr);
2939
22bedad3
JP		 2940 netdev_for_each_mc_addr(ha, dev)
2941 yukon_add_filter(filter, ha->addr);
baef58b1
SH		 2942 }
2943
2944
6b0c1480 2945 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2946 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2947 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2948 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2949 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2950 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2951 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2952 (u16)filter[6] | ((u16)filter[7] << 8));
2953
6b0c1480 2954 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2955}
2956
383181ac
SH		 2957static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2958{
2959 if (hw->chip_id == CHIP_ID_GENESIS)
2960 return status >> XMR_FS_LEN_SHIFT;
2961 else
2962 return status >> GMR_FS_LEN_SHIFT;
2963}
2964
baef58b1
SH		 2965static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2966{
2967 if (hw->chip_id == CHIP_ID_GENESIS)
2968 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2969 else
2970 return (status & GMR_FS_ANY_ERR) ||
2971 (status & GMR_FS_RX_OK) == 0;
2972}
2973
f80d032b
SH		 2974static void skge_set_multicast(struct net_device *dev)
2975{
2976 struct skge_port *skge = netdev_priv(dev);
2977 struct skge_hw *hw = skge->hw;
2978
2979 if (hw->chip_id == CHIP_ID_GENESIS)
2980 genesis_set_multicast(dev);
2981 else
2982 yukon_set_multicast(dev);
2983
2984}
2985
19a33d4e
SH		 2986
2987/* Get receive buffer from descriptor.
2988 * Handles copy of small buffers and reallocation failures
2989 */
c54f9765
SH		 2990static struct sk_buff *skge_rx_get(struct net_device *dev,
2991 struct skge_element *e,
2992 u32 control, u32 status, u16 csum)
19a33d4e 2993{
c54f9765 2994 struct skge_port *skge = netdev_priv(dev);
383181ac
SH		 2995 struct sk_buff *skb;
2996 u16 len = control & BMU_BBC;
2997
d707204c
JP		 2998 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
2999 "rx slot %td status 0x%x len %d\n",
3000 e - skge->rx_ring.start, status, len);
383181ac
SH		 3001
3002 if (len > skge->rx_buf_size)
3003 goto error;
3004
3005 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3006 goto error;
3007
3008 if (bad_phy_status(skge->hw, status))
3009 goto error;
3010
3011 if (phy_length(skge->hw, status) != len)
3012 goto error;
19a33d4e
SH		 3013
3014 if (len < RX_COPY_THRESHOLD) {
89d71a66 3015 skb = netdev_alloc_skb_ip_align(dev, len);
383181ac
SH		 3016 if (!skb)
3017 goto resubmit;
19a33d4e
SH		 3018
3019 pci_dma_sync_single_for_cpu(skge->hw->pdev,
10fc51b9 3020 dma_unmap_addr(e, mapaddr),
19a33d4e 3021 len, PCI_DMA_FROMDEVICE);
d626f62b 3022 skb_copy_from_linear_data(e->skb, skb->data, len);
19a33d4e 3023 pci_dma_sync_single_for_device(skge->hw->pdev,
10fc51b9 3024 dma_unmap_addr(e, mapaddr),
19a33d4e 3025 len, PCI_DMA_FROMDEVICE);
19a33d4e 3026 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 3027 } else {
383181ac 3028 struct sk_buff *nskb;
89d71a66
ED		 3029
3030 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
383181ac
SH		 3031 if (!nskb)
3032 goto resubmit;
19a33d4e
SH		 3033
3034 pci_unmap_single(skge->hw->pdev,
10fc51b9
FT		 3035 dma_unmap_addr(e, mapaddr),
3036 dma_unmap_len(e, maplen),
19a33d4e
SH		 3037 PCI_DMA_FROMDEVICE);
3038 skb = e->skb;
67777f9b 3039 prefetch(skb->data);
19a33d4e 3040 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 3041 }
383181ac
SH		 3042
3043 skb_put(skb, len);
e92702b1
MM		 3044
3045 if (dev->features & NETIF_F_RXCSUM) {
383181ac 3046 skb->csum = csum;
84fa7933 3047 skb->ip_summed = CHECKSUM_COMPLETE;
383181ac
SH		 3048 }
3049
c54f9765 3050 skb->protocol = eth_type_trans(skb, dev);
383181ac
SH		 3051
3052 return skb;
3053error:
3054
d707204c
JP		 3055 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3056 "rx err, slot %td control 0x%x status 0x%x\n",
3057 e - skge->rx_ring.start, control, status);
383181ac
SH		 3058
3059 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3060 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
da00772f 3061 dev->stats.rx_length_errors++;
383181ac 3062 if (status & XMR_FS_FRA_ERR)
da00772f 3063 dev->stats.rx_frame_errors++;
383181ac 3064 if (status & XMR_FS_FCS_ERR)
da00772f 3065 dev->stats.rx_crc_errors++;
383181ac
SH		 3066 } else {
3067 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
da00772f 3068 dev->stats.rx_length_errors++;
383181ac 3069 if (status & GMR_FS_FRAGMENT)
da00772f 3070 dev->stats.rx_frame_errors++;
383181ac 3071 if (status & GMR_FS_CRC_ERR)
da00772f 3072 dev->stats.rx_crc_errors++;
383181ac
SH		 3073 }
3074
3075resubmit:
3076 skge_rx_reuse(e, skge->rx_buf_size);
3077 return NULL;
baef58b1
SH		 3078}
3079
7c442fa1 3080/* Free all buffers in Tx ring which are no longer owned by device */
513f533e 3081static void skge_tx_done(struct net_device *dev)
00a6cae2 3082{
7c442fa1 3083 struct skge_port *skge = netdev_priv(dev);
00a6cae2 3084 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 3085 struct skge_element *e;
3086
513f533e 3087 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
00a6cae2 3088
866b4f3e 3089 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
992c9623 3090 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
00a6cae2 3091
992c9623 3092 if (control & BMU_OWN)
00a6cae2
SH		 3093 break;
3094
992c9623 3095 skge_tx_free(skge, e, control);
00a6cae2 3096 }
7c442fa1 3097 skge->tx_ring.to_clean = e;
866b4f3e 3098
992c9623
SH		 3099 /* Can run lockless until we need to synchronize to restart queue. */
3100 smp_mb();
3101
3102 if (unlikely(netif_queue_stopped(dev) &&
3103 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3104 netif_tx_lock(dev);
3105 if (unlikely(netif_queue_stopped(dev) &&
3106 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3107 netif_wake_queue(dev);
00a6cae2 3108
992c9623
SH		 3109 }
3110 netif_tx_unlock(dev);
3111 }
00a6cae2 3112}
19a33d4e 3113
bea3348e 3114static int skge_poll(struct napi_struct *napi, int to_do)
baef58b1 3115{
bea3348e
SH		 3116 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3117 struct net_device *dev = skge->netdev;
baef58b1
SH		 3118 struct skge_hw *hw = skge->hw;
3119 struct skge_ring *ring = &skge->rx_ring;
3120 struct skge_element *e;
00a6cae2
SH		 3121 int work_done = 0;
3122
513f533e
SH		 3123 skge_tx_done(dev);
3124
3125 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3126
1631aef1 3127 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 3128 struct skge_rx_desc *rd = e->desc;
19a33d4e 3129 struct sk_buff *skb;
383181ac 3130 u32 control;
baef58b1
SH		 3131
3132 rmb();
3133 control = rd->control;
3134 if (control & BMU_OWN)
3135 break;
3136
c54f9765 3137 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
19a33d4e 3138 if (likely(skb)) {
86cac58b 3139 napi_gro_receive(napi, skb);
19a33d4e 3140 ++work_done;
5a011447 3141 }
baef58b1
SH		 3142 }
3143 ring->to_clean = e;
3144
baef58b1
SH		 3145 /* restart receiver */
3146 wmb();
a9cdab86 3147 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 3148
bea3348e 3149 if (work_done < to_do) {
6ef2977d 3150 unsigned long flags;
f0c88f9c 3151
86cac58b 3152 napi_gro_flush(napi);
6ef2977d 3153 spin_lock_irqsave(&hw->hw_lock, flags);
288379f0 3154 __napi_complete(napi);
bea3348e
SH		 3155 hw->intr_mask |= napimask[skge->port];
3156 skge_write32(hw, B0_IMSK, hw->intr_mask);
3157 skge_read32(hw, B0_IMSK);
6ef2977d 3158 spin_unlock_irqrestore(&hw->hw_lock, flags);
bea3348e 3159 }
1631aef1 3160
bea3348e 3161 return work_done;
baef58b1
SH		 3162}
3163
f6620cab
SH		 3164/* Parity errors seem to happen when Genesis is connected to a switch
3165 * with no other ports present. Heartbeat error??
3166 */
baef58b1
SH		 3167static void skge_mac_parity(struct skge_hw *hw, int port)
3168{
f6620cab
SH		 3169 struct net_device *dev = hw->dev[port];
3170
da00772f 3171 ++dev->stats.tx_heartbeat_errors;
baef58b1
SH		 3172
3173 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 3174 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 3175 MFF_CLR_PERR);
3176 else
3177 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 3178 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 3179 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 3180 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3181}
3182
baef58b1
SH		 3183static void skge_mac_intr(struct skge_hw *hw, int port)
3184{
95566065 3185 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 3186 genesis_mac_intr(hw, port);
3187 else
3188 yukon_mac_intr(hw, port);
3189}
3190
3191/* Handle device specific framing and timeout interrupts */
3192static void skge_error_irq(struct skge_hw *hw)
3193{
1479d13c 3194 struct pci_dev *pdev = hw->pdev;
baef58b1
SH		 3195 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3196
3197 if (hw->chip_id == CHIP_ID_GENESIS) {
3198 /* clear xmac errors */
3199 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 3200 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 3201 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 3202 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 3203 } else {
3204 /* Timestamp (unused) overflow */
3205 if (hwstatus & IS_IRQ_TIST_OV)
3206 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 3207 }
3208
3209 if (hwstatus & IS_RAM_RD_PAR) {
1479d13c 3210 dev_err(&pdev->dev, "Ram read data parity error\n");
baef58b1
SH		 3211 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3212 }
3213
3214 if (hwstatus & IS_RAM_WR_PAR) {
1479d13c 3215 dev_err(&pdev->dev, "Ram write data parity error\n");
baef58b1
SH		 3216 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3217 }
3218
3219 if (hwstatus & IS_M1_PAR_ERR)
3220 skge_mac_parity(hw, 0);
3221
3222 if (hwstatus & IS_M2_PAR_ERR)
3223 skge_mac_parity(hw, 1);
3224
b9d64acc 3225 if (hwstatus & IS_R1_PAR_ERR) {
1479d13c
SH		 3226 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3227 hw->dev[0]->name);
baef58b1 3228 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 3229 }
baef58b1 3230
b9d64acc 3231 if (hwstatus & IS_R2_PAR_ERR) {
1479d13c
SH		 3232 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3233 hw->dev[1]->name);
baef58b1 3234 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 3235 }
baef58b1
SH		 3236
3237 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 3238 u16 pci_status, pci_cmd;
3239
1479d13c
SH		 3240 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3241 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
baef58b1 3242
1479d13c
SH		 3243 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3244 pci_cmd, pci_status);
b9d64acc
SH		 3245
3246 /* Write the error bits back to clear them. */
3247 pci_status &= PCI_STATUS_ERROR_BITS;
3248 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1479d13c 3249 pci_write_config_word(pdev, PCI_COMMAND,
b9d64acc 3250 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
1479d13c 3251 pci_write_config_word(pdev, PCI_STATUS, pci_status);
b9d64acc 3252 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 3253
050ec18a 3254 /* if error still set then just ignore it */
baef58b1
SH		 3255 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3256 if (hwstatus & IS_IRQ_STAT) {
1479d13c 3257 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
baef58b1
SH		 3258 hw->intr_mask &= ~IS_HW_ERR;
3259 }
3260 }
3261}
3262
3263/*
9cbe330f 3264 * Interrupt from PHY are handled in tasklet (softirq)
baef58b1
SH		 3265 * because accessing phy registers requires spin wait which might
3266 * cause excess interrupt latency.
3267 */
9cbe330f 3268static void skge_extirq(unsigned long arg)
baef58b1 3269{
9cbe330f 3270 struct skge_hw *hw = (struct skge_hw *) arg;
baef58b1
SH		 3271 int port;
3272
cfc3ed79 3273 for (port = 0; port < hw->ports; port++) {
baef58b1
SH		 3274 struct net_device *dev = hw->dev[port];
3275
cfc3ed79 3276 if (netif_running(dev)) {
9cbe330f
SH		 3277 struct skge_port *skge = netdev_priv(dev);
3278
3279 spin_lock(&hw->phy_lock);
baef58b1
SH		 3280 if (hw->chip_id != CHIP_ID_GENESIS)
3281 yukon_phy_intr(skge);
64f6b64d 3282 else if (hw->phy_type == SK_PHY_BCOM)
45bada65 3283 bcom_phy_intr(skge);
9cbe330f 3284 spin_unlock(&hw->phy_lock);
baef58b1
SH		 3285 }
3286 }
baef58b1 3287
7c442fa1 3288 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 3289 hw->intr_mask |= IS_EXT_REG;
3290 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3291 skge_read32(hw, B0_IMSK);
7c442fa1 3292 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 3293}
3294
7d12e780 3295static irqreturn_t skge_intr(int irq, void *dev_id)
baef58b1
SH		 3296{
3297 struct skge_hw *hw = dev_id;
cfc3ed79 3298 u32 status;
29365c90 3299 int handled = 0;
baef58b1 3300
29365c90 3301 spin_lock(&hw->hw_lock);
cfc3ed79
SH		 3302 /* Reading this register masks IRQ */
3303 status = skge_read32(hw, B0_SP_ISRC);
0486a8c8 3304 if (status == 0 || status == ~0)
29365c90 3305 goto out;
baef58b1 3306
29365c90 3307 handled = 1;
7c442fa1 3308 status &= hw->intr_mask;
cfc3ed79
SH		 3309 if (status & IS_EXT_REG) {
3310 hw->intr_mask &= ~IS_EXT_REG;
9cbe330f 3311 tasklet_schedule(&hw->phy_task);
cfc3ed79
SH		 3312 }
3313
513f533e 3314 if (status & (IS_XA1_F|IS_R1_F)) {
bea3348e 3315 struct skge_port *skge = netdev_priv(hw->dev[0]);
513f533e 3316 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
288379f0 3317 napi_schedule(&skge->napi);
baef58b1
SH		 3318 }
3319
7c442fa1
SH		 3320 if (status & IS_PA_TO_TX1)
3321 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 3322
d25f5a67 3323 if (status & IS_PA_TO_RX1) {
da00772f 3324 ++hw->dev[0]->stats.rx_over_errors;
7c442fa1 3325 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 3326 }
3327
d25f5a67 3328
baef58b1
SH		 3329 if (status & IS_MAC1)
3330 skge_mac_intr(hw, 0);
95566065 3331
7c442fa1 3332 if (hw->dev[1]) {
bea3348e
SH		 3333 struct skge_port *skge = netdev_priv(hw->dev[1]);
3334
513f533e
SH		 3335 if (status & (IS_XA2_F|IS_R2_F)) {
3336 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
288379f0 3337 napi_schedule(&skge->napi);
7c442fa1
SH		 3338 }
3339
3340 if (status & IS_PA_TO_RX2) {
da00772f 3341 ++hw->dev[1]->stats.rx_over_errors;
7c442fa1
SH		 3342 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3343 }
3344
3345 if (status & IS_PA_TO_TX2)
3346 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3347
3348 if (status & IS_MAC2)
3349 skge_mac_intr(hw, 1);
3350 }
baef58b1
SH		 3351
3352 if (status & IS_HW_ERR)
3353 skge_error_irq(hw);
3354
7e676d91 3355 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3356 skge_read32(hw, B0_IMSK);
29365c90 3357out:
7c442fa1 3358 spin_unlock(&hw->hw_lock);
baef58b1 3359
29365c90 3360 return IRQ_RETVAL(handled);
baef58b1
SH		 3361}
3362
3363#ifdef CONFIG_NET_POLL_CONTROLLER
3364static void skge_netpoll(struct net_device *dev)
3365{
3366 struct skge_port *skge = netdev_priv(dev);
3367
3368 disable_irq(dev->irq);
7d12e780 3369 skge_intr(dev->irq, skge->hw);
baef58b1
SH		 3370 enable_irq(dev->irq);
3371}
3372#endif
3373
3374static int skge_set_mac_address(struct net_device *dev, void *p)
3375{
3376 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 3377 struct skge_hw *hw = skge->hw;
3378 unsigned port = skge->port;
3379 const struct sockaddr *addr = p;
2eb3e621 3380 u16 ctrl;
baef58b1
SH		 3381
3382 if (!is_valid_ether_addr(addr->sa_data))
3383 return -EADDRNOTAVAIL;
3384
baef58b1 3385 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 3386
9cbe330f
SH		 3387 if (!netif_running(dev)) {
3388 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3389 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3390 } else {
3391 /* disable Rx */
3392 spin_lock_bh(&hw->phy_lock);
3393 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3394 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
2eb3e621 3395
9cbe330f
SH		 3396 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3397 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
2eb3e621 3398
2eb3e621
SH		 3399 if (hw->chip_id == CHIP_ID_GENESIS)
3400 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3401 else {
3402 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3403 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3404 }
2eb3e621 3405
9cbe330f
SH		 3406 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3407 spin_unlock_bh(&hw->phy_lock);
3408 }
c2681dd8
SH		 3409
3410 return 0;
baef58b1
SH		 3411}
3412
3413static const struct {
3414 u8 id;
3415 const char *name;
3416} skge_chips[] = {
3417 { CHIP_ID_GENESIS, "Genesis" },
3418 { CHIP_ID_YUKON, "Yukon" },
3419 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3420 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3421};
3422
3423static const char *skge_board_name(const struct skge_hw *hw)
3424{
3425 int i;
3426 static char buf[16];
3427
3428 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3429 if (skge_chips[i].id == hw->chip_id)
3430 return skge_chips[i].name;
3431
3432 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3433 return buf;
3434}
3435
3436
3437/*
3438 * Setup the board data structure, but don't bring up
3439 * the port(s)
3440 */
3441static int skge_reset(struct skge_hw *hw)
3442{
adba9e23 3443 u32 reg;
b9d64acc 3444 u16 ctst, pci_status;
64f6b64d 3445 u8 t8, mac_cfg, pmd_type;
981d0377 3446 int i;
baef58b1
SH		 3447
3448 ctst = skge_read16(hw, B0_CTST);
3449
3450 /* do a SW reset */
3451 skge_write8(hw, B0_CTST, CS_RST_SET);
3452 skge_write8(hw, B0_CTST, CS_RST_CLR);
3453
3454 /* clear PCI errors, if any */
b9d64acc
SH		 3455 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3456 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3457
b9d64acc
SH		 3458 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3459 pci_write_config_word(hw->pdev, PCI_STATUS,
3460 pci_status | PCI_STATUS_ERROR_BITS);
3461 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3462 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3463
3464 /* restore CLK_RUN bits (for Yukon-Lite) */
3465 skge_write16(hw, B0_CTST,
3466 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3467
3468 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
64f6b64d 3469 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
5e1705dd
SH		 3470 pmd_type = skge_read8(hw, B2_PMD_TYP);
3471 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3472
95566065 3473 switch (hw->chip_id) {
baef58b1 3474 case CHIP_ID_GENESIS:
64f6b64d
SH		 3475 switch (hw->phy_type) {
3476 case SK_PHY_XMAC:
3477 hw->phy_addr = PHY_ADDR_XMAC;
3478 break;
baef58b1
SH		 3479 case SK_PHY_BCOM:
3480 hw->phy_addr = PHY_ADDR_BCOM;
3481 break;
3482 default:
1479d13c
SH		 3483 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3484 hw->phy_type);
baef58b1
SH		 3485 return -EOPNOTSUPP;
3486 }
3487 break;
3488
3489 case CHIP_ID_YUKON:
3490 case CHIP_ID_YUKON_LITE:
3491 case CHIP_ID_YUKON_LP:
64f6b64d 3492 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
5e1705dd 3493 hw->copper = 1;
baef58b1
SH		 3494
3495 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3496 break;
3497
3498 default:
1479d13c
SH		 3499 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3500 hw->chip_id);
baef58b1
SH		 3501 return -EOPNOTSUPP;
3502 }
3503
981d0377
SH		 3504 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3505 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3506 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3507
3508 /* read the adapters RAM size */
3509 t8 = skge_read8(hw, B2_E_0);
3510 if (hw->chip_id == CHIP_ID_GENESIS) {
3511 if (t8 == 3) {
3512 /* special case: 4 x 64k x 36, offset = 0x80000 */
279e1dab
LT		 3513 hw->ram_size = 0x100000;
3514 hw->ram_offset = 0x80000;
baef58b1
SH		 3515 } else
3516 hw->ram_size = t8 * 512;
67777f9b 3517 } else if (t8 == 0)
279e1dab
LT		 3518 hw->ram_size = 0x20000;
3519 else
3520 hw->ram_size = t8 * 4096;
baef58b1 3521
4ebabfcb 3522 hw->intr_mask = IS_HW_ERR;
cfc3ed79 3523
4ebabfcb 3524 /* Use PHY IRQ for all but fiber based Genesis board */
64f6b64d
SH		 3525 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3526 hw->intr_mask |= IS_EXT_REG;
3527
baef58b1
SH		 3528 if (hw->chip_id == CHIP_ID_GENESIS)
3529 genesis_init(hw);
3530 else {
3531 /* switch power to VCC (WA for VAUX problem) */
3532 skge_write8(hw, B0_POWER_CTRL,
3533 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3534
050ec18a
SH		 3535 /* avoid boards with stuck Hardware error bits */
3536 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3537 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
1479d13c 3538 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
050ec18a
SH		 3539 hw->intr_mask &= ~IS_HW_ERR;
3540 }
3541
adba9e23
SH		 3542 /* Clear PHY COMA */
3543 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3544 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3545 reg &= ~PCI_PHY_COMA;
3546 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3547 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3548
3549
981d0377 3550 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3551 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3552 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3553 }
3554 }
3555
3556 /* turn off hardware timer (unused) */
3557 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3558 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3559 skge_write8(hw, B0_LED, LED_STAT_ON);
3560
3561 /* enable the Tx Arbiters */
981d0377 3562 for (i = 0; i < hw->ports; i++)
6b0c1480 3563 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3564
3565 /* Initialize ram interface */
3566 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3567
3568 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3569 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3570 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3571 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3572 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3573 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3574 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3575 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3576 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3577 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3578 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3579 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3580
3581 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3582
3583 /* Set interrupt moderation for Transmit only
3584 * Receive interrupts avoided by NAPI
3585 */
3586 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3587 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3588 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3589
baef58b1
SH		 3590 skge_write32(hw, B0_IMSK, hw->intr_mask);
3591
981d0377 3592 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3593 if (hw->chip_id == CHIP_ID_GENESIS)
3594 genesis_reset(hw, i);
3595 else
3596 yukon_reset(hw, i);
3597 }
baef58b1
SH		 3598
3599 return 0;
3600}
3601
678aa1f6
SH		 3602
3603#ifdef CONFIG_SKGE_DEBUG
3604
3605static struct dentry *skge_debug;
3606
3607static int skge_debug_show(struct seq_file *seq, void *v)
3608{
3609 struct net_device *dev = seq->private;
3610 const struct skge_port *skge = netdev_priv(dev);
3611 const struct skge_hw *hw = skge->hw;
3612 const struct skge_element *e;
3613
3614 if (!netif_running(dev))
3615 return -ENETDOWN;
3616
3617 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3618 skge_read32(hw, B0_IMSK));
3619
3620 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3621 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3622 const struct skge_tx_desc *t = e->desc;
3623 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3624 t->control, t->dma_hi, t->dma_lo, t->status,
3625 t->csum_offs, t->csum_write, t->csum_start);
3626 }
3627
2381a55c 3628 seq_printf(seq, "\nRx Ring:\n");
678aa1f6
SH		 3629 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3630 const struct skge_rx_desc *r = e->desc;
3631
3632 if (r->control & BMU_OWN)
3633 break;
3634
3635 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3636 r->control, r->dma_hi, r->dma_lo, r->status,
3637 r->timestamp, r->csum1, r->csum1_start);
3638 }
3639
3640 return 0;
3641}
3642
3643static int skge_debug_open(struct inode *inode, struct file *file)
3644{
3645 return single_open(file, skge_debug_show, inode->i_private);
3646}
3647
3648static const struct file_operations skge_debug_fops = {
3649 .owner = THIS_MODULE,
3650 .open = skge_debug_open,
3651 .read = seq_read,
3652 .llseek = seq_lseek,
3653 .release = single_release,
3654};
3655
3656/*
3657 * Use network device events to create/remove/rename
3658 * debugfs file entries
3659 */
3660static int skge_device_event(struct notifier_block *unused,
3661 unsigned long event, void *ptr)
3662{
3663 struct net_device *dev = ptr;
3664 struct skge_port *skge;
3665 struct dentry *d;
3666
f80d032b 3667 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
678aa1f6
SH		 3668 goto done;
3669
3670 skge = netdev_priv(dev);
67777f9b 3671 switch (event) {
678aa1f6
SH		 3672 case NETDEV_CHANGENAME:
3673 if (skge->debugfs) {
3674 d = debugfs_rename(skge_debug, skge->debugfs,
3675 skge_debug, dev->name);
3676 if (d)
3677 skge->debugfs = d;
3678 else {
f15063cd 3679 netdev_info(dev, "rename failed\n");
678aa1f6
SH		 3680 debugfs_remove(skge->debugfs);
3681 }
3682 }
3683 break;
3684
3685 case NETDEV_GOING_DOWN:
3686 if (skge->debugfs) {
3687 debugfs_remove(skge->debugfs);
3688 skge->debugfs = NULL;
3689 }
3690 break;
3691
3692 case NETDEV_UP:
3693 d = debugfs_create_file(dev->name, S_IRUGO,
3694 skge_debug, dev,
3695 &skge_debug_fops);
3696 if (!d || IS_ERR(d))
f15063cd 3697 netdev_info(dev, "debugfs create failed\n");
678aa1f6
SH		 3698 else
3699 skge->debugfs = d;
3700 break;
3701 }
3702
3703done:
3704 return NOTIFY_DONE;
3705}
3706
3707static struct notifier_block skge_notifier = {
3708 .notifier_call = skge_device_event,
3709};
3710
3711
3712static __init void skge_debug_init(void)
3713{
3714 struct dentry *ent;
3715
3716 ent = debugfs_create_dir("skge", NULL);
3717 if (!ent || IS_ERR(ent)) {
f15063cd 3718 pr_info("debugfs create directory failed\n");
678aa1f6
SH		 3719 return;
3720 }
3721
3722 skge_debug = ent;
3723 register_netdevice_notifier(&skge_notifier);
3724}
3725
3726static __exit void skge_debug_cleanup(void)
3727{
3728 if (skge_debug) {
3729 unregister_netdevice_notifier(&skge_notifier);
3730 debugfs_remove(skge_debug);
3731 skge_debug = NULL;
3732 }
3733}
3734
3735#else
3736#define skge_debug_init()
3737#define skge_debug_cleanup()
3738#endif
3739
f80d032b
SH		 3740static const struct net_device_ops skge_netdev_ops = {
3741 .ndo_open = skge_up,
3742 .ndo_stop = skge_down,
00829823 3743 .ndo_start_xmit = skge_xmit_frame,
f80d032b
SH		 3744 .ndo_do_ioctl = skge_ioctl,
3745 .ndo_get_stats = skge_get_stats,
3746 .ndo_tx_timeout = skge_tx_timeout,
3747 .ndo_change_mtu = skge_change_mtu,
3748 .ndo_validate_addr = eth_validate_addr,
3749 .ndo_set_multicast_list = skge_set_multicast,
3750 .ndo_set_mac_address = skge_set_mac_address,
3751#ifdef CONFIG_NET_POLL_CONTROLLER
3752 .ndo_poll_controller = skge_netpoll,
3753#endif
3754};
3755
3756
baef58b1 3757/* Initialize network device */
981d0377
SH		 3758static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3759 int highmem)
baef58b1
SH		 3760{
3761 struct skge_port *skge;
3762 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3763
3764 if (!dev) {
1479d13c 3765 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
baef58b1
SH		 3766 return NULL;
3767 }
3768
baef58b1 3769 SET_NETDEV_DEV(dev, &hw->pdev->dev);
f80d032b
SH		 3770 dev->netdev_ops = &skge_netdev_ops;
3771 dev->ethtool_ops = &skge_ethtool_ops;
baef58b1 3772 dev->watchdog_timeo = TX_WATCHDOG;
baef58b1 3773 dev->irq = hw->pdev->irq;
513f533e 3774
981d0377
SH		 3775 if (highmem)
3776 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3777
3778 skge = netdev_priv(dev);
bea3348e 3779 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
baef58b1
SH		 3780 skge->netdev = dev;
3781 skge->hw = hw;
3782 skge->msg_enable = netif_msg_init(debug, default_msg);
9cbe330f 3783
baef58b1
SH		 3784 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3785 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3786
3787 /* Auto speed and flow control */
3788 skge->autoneg = AUTONEG_ENABLE;
5d5c8e03 3789 skge->flow_control = FLOW_MODE_SYM_OR_REM;
baef58b1
SH		 3790 skge->duplex = -1;
3791 skge->speed = -1;
31b619c5 3792 skge->advertising = skge_supported_modes(hw);
5b982c5b 3793
7b55a4a3 3794 if (device_can_wakeup(&hw->pdev->dev)) {
5b982c5b 3795 skge->wol = wol_supported(hw) & WAKE_MAGIC;
7b55a4a3
RW		 3796 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3797 }
baef58b1
SH		 3798
3799 hw->dev[port] = dev;
3800
3801 skge->port = port;
3802
64f6b64d 3803 /* Only used for Genesis XMAC */
9cbe330f 3804 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
64f6b64d 3805
baef58b1 3806 if (hw->chip_id != CHIP_ID_GENESIS) {
e92702b1
MM		 3807 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3808 NETIF_F_RXCSUM;
3809 dev->features |= dev->hw_features;
baef58b1
SH		 3810 }
3811
3812 /* read the mac address */
3813 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3814 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1 3815
baef58b1
SH		 3816 return dev;
3817}
3818
3819static void __devinit skge_show_addr(struct net_device *dev)
3820{
3821 const struct skge_port *skge = netdev_priv(dev);
3822
d707204c 3823 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
baef58b1
SH		 3824}
3825
392bd0cb
SG		 3826static int only_32bit_dma;
3827
baef58b1
SH		 3828static int __devinit skge_probe(struct pci_dev *pdev,
3829 const struct pci_device_id *ent)
3830{
3831 struct net_device *dev, *dev1;
3832 struct skge_hw *hw;
3833 int err, using_dac = 0;
3834
203babb6
SH		 3835 err = pci_enable_device(pdev);
3836 if (err) {
1479d13c 3837 dev_err(&pdev->dev, "cannot enable PCI device\n");
baef58b1
SH		 3838 goto err_out;
3839 }
3840
203babb6
SH		 3841 err = pci_request_regions(pdev, DRV_NAME);
3842 if (err) {
1479d13c 3843 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
baef58b1
SH		 3844 goto err_out_disable_pdev;
3845 }
3846
3847 pci_set_master(pdev);
3848
392bd0cb 3849 if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
baef58b1 3850 using_dac = 1;
6a35528a 3851 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
284901a9 3852 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
93aea718 3853 using_dac = 0;
284901a9 3854 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
93aea718
SH		 3855 }
3856
3857 if (err) {
1479d13c 3858 dev_err(&pdev->dev, "no usable DMA configuration\n");
93aea718 3859 goto err_out_free_regions;
baef58b1
SH		 3860 }
3861
3862#ifdef __BIG_ENDIAN
8f3f8193 3863 /* byte swap descriptors in hardware */
baef58b1
SH		 3864 {
3865 u32 reg;
3866
3867 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3868 reg |= PCI_REV_DESC;
3869 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3870 }
3871#endif
3872
3873 err = -ENOMEM;
415e69e6 3874 /* space for skge@pci:0000:04:00.0 */
67777f9b 3875 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
415e69e6 3876 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
baef58b1 3877 if (!hw) {
1479d13c 3878 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
baef58b1
SH		 3879 goto err_out_free_regions;
3880 }
415e69e6 3881 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
baef58b1 3882
baef58b1 3883 hw->pdev = pdev;
d38efdd6 3884 spin_lock_init(&hw->hw_lock);
9cbe330f 3885 spin_lock_init(&hw->phy_lock);
164165da 3886 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
baef58b1
SH		 3887
3888 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3889 if (!hw->regs) {
1479d13c 3890 dev_err(&pdev->dev, "cannot map device registers\n");
baef58b1
SH		 3891 goto err_out_free_hw;
3892 }
3893
baef58b1
SH		 3894 err = skge_reset(hw);
3895 if (err)
ccdaa2a9 3896 goto err_out_iounmap;
baef58b1 3897
f15063cd
JP		 3898 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3899 DRV_VERSION,
3900 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3901 skge_board_name(hw), hw->chip_rev);
baef58b1 3902
ccdaa2a9
SH		 3903 dev = skge_devinit(hw, 0, using_dac);
3904 if (!dev)
baef58b1
SH		 3905 goto err_out_led_off;
3906
fae87592 3907 /* Some motherboards are broken and has zero in ROM. */
1479d13c
SH		 3908 if (!is_valid_ether_addr(dev->dev_addr))
3909 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
631ae320 3910
203babb6
SH		 3911 err = register_netdev(dev);
3912 if (err) {
1479d13c 3913 dev_err(&pdev->dev, "cannot register net device\n");
baef58b1
SH		 3914 goto err_out_free_netdev;
3915 }
3916
415e69e6 3917 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw);
ccdaa2a9 3918 if (err) {
1479d13c 3919 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
ccdaa2a9
SH		 3920 dev->name, pdev->irq);
3921 goto err_out_unregister;
3922 }
baef58b1
SH		 3923 skge_show_addr(dev);
3924
f1914226
MM		 3925 if (hw->ports > 1) {
3926 dev1 = skge_devinit(hw, 1, using_dac);
3927 if (dev1 && register_netdev(dev1) == 0)
baef58b1
SH		 3928 skge_show_addr(dev1);
3929 else {
3930 /* Failure to register second port need not be fatal */
1479d13c 3931 dev_warn(&pdev->dev, "register of second port failed\n");
baef58b1 3932 hw->dev[1] = NULL;
f1914226
MM		 3933 hw->ports = 1;
3934 if (dev1)
3935 free_netdev(dev1);
baef58b1
SH		 3936 }
3937 }
ccdaa2a9 3938 pci_set_drvdata(pdev, hw);
baef58b1
SH		 3939
3940 return 0;
3941
ccdaa2a9
SH		 3942err_out_unregister:
3943 unregister_netdev(dev);
baef58b1
SH		 3944err_out_free_netdev:
3945 free_netdev(dev);
3946err_out_led_off:
3947 skge_write16(hw, B0_LED, LED_STAT_OFF);
baef58b1
SH		 3948err_out_iounmap:
3949 iounmap(hw->regs);
3950err_out_free_hw:
3951 kfree(hw);
3952err_out_free_regions:
3953 pci_release_regions(pdev);
3954err_out_disable_pdev:
3955 pci_disable_device(pdev);
3956 pci_set_drvdata(pdev, NULL);
3957err_out:
3958 return err;
3959}
3960
3961static void __devexit skge_remove(struct pci_dev *pdev)
3962{
3963 struct skge_hw *hw = pci_get_drvdata(pdev);
3964 struct net_device *dev0, *dev1;
3965
95566065 3966 if (!hw)
baef58b1
SH		 3967 return;
3968
67777f9b
JP		 3969 dev1 = hw->dev[1];
3970 if (dev1)
baef58b1
SH		 3971 unregister_netdev(dev1);
3972 dev0 = hw->dev[0];
3973 unregister_netdev(dev0);
3974
9cbe330f
SH		 3975 tasklet_disable(&hw->phy_task);
3976
7c442fa1
SH		 3977 spin_lock_irq(&hw->hw_lock);
3978 hw->intr_mask = 0;
46a60f2d 3979 skge_write32(hw, B0_IMSK, 0);
78bc2186 3980 skge_read32(hw, B0_IMSK);
7c442fa1
SH		 3981 spin_unlock_irq(&hw->hw_lock);
3982
46a60f2d 3983 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 3984 skge_write8(hw, B0_CTST, CS_RST_SET);
3985
baef58b1
SH		 3986 free_irq(pdev->irq, hw);
3987 pci_release_regions(pdev);
3988 pci_disable_device(pdev);
3989 if (dev1)
3990 free_netdev(dev1);
3991 free_netdev(dev0);
46a60f2d 3992
baef58b1
SH		 3993 iounmap(hw->regs);
3994 kfree(hw);
3995 pci_set_drvdata(pdev, NULL);
3996}
3997
3998#ifdef CONFIG_PM
7dbf6acd 3999static int skge_suspend(struct device *dev)
baef58b1 4000{
7dbf6acd 4001 struct pci_dev *pdev = to_pci_dev(dev);
baef58b1 4002 struct skge_hw *hw = pci_get_drvdata(pdev);
7dbf6acd 4003 int i;
a504e64a 4004
e3b7df17
SH		 4005 if (!hw)
4006 return 0;
4007
d38efdd6 4008 for (i = 0; i < hw->ports; i++) {
baef58b1 4009 struct net_device *dev = hw->dev[i];
a504e64a 4010 struct skge_port *skge = netdev_priv(dev);
baef58b1 4011
a504e64a
SH		 4012 if (netif_running(dev))
4013 skge_down(dev);
7dbf6acd 4014
a504e64a
SH		 4015 if (skge->wol)
4016 skge_wol_init(skge);
baef58b1
SH		 4017 }
4018
d38efdd6 4019 skge_write32(hw, B0_IMSK, 0);
5177b324 4020
baef58b1
SH		 4021 return 0;
4022}
4023
7dbf6acd 4024static int skge_resume(struct device *dev)
baef58b1 4025{
7dbf6acd 4026 struct pci_dev *pdev = to_pci_dev(dev);
baef58b1 4027 struct skge_hw *hw = pci_get_drvdata(pdev);
d38efdd6 4028 int i, err;
baef58b1 4029
e3b7df17
SH		 4030 if (!hw)
4031 return 0;
4032
d38efdd6
SH		 4033 err = skge_reset(hw);
4034 if (err)
4035 goto out;
baef58b1 4036
d38efdd6 4037 for (i = 0; i < hw->ports; i++) {
baef58b1 4038 struct net_device *dev = hw->dev[i];
d38efdd6 4039
d38efdd6
SH		 4040 if (netif_running(dev)) {
4041 err = skge_up(dev);
4042
4043 if (err) {
f15063cd 4044 netdev_err(dev, "could not up: %d\n", err);
edd702e8 4045 dev_close(dev);
d38efdd6
SH		 4046 goto out;
4047 }
baef58b1
SH		 4048 }
4049 }
d38efdd6
SH		 4050out:
4051 return err;
baef58b1 4052}
7dbf6acd 4053
4054static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4055#define SKGE_PM_OPS (&skge_pm_ops)
4056
4057#else
4058
4059#define SKGE_PM_OPS NULL
baef58b1
SH		 4060#endif
4061
692412b3
SH		 4062static void skge_shutdown(struct pci_dev *pdev)
4063{
4064 struct skge_hw *hw = pci_get_drvdata(pdev);
7dbf6acd 4065 int i;
692412b3 4066
e3b7df17
SH		 4067 if (!hw)
4068 return;
4069
692412b3
SH		 4070 for (i = 0; i < hw->ports; i++) {
4071 struct net_device *dev = hw->dev[i];
4072 struct skge_port *skge = netdev_priv(dev);
4073
4074 if (skge->wol)
4075 skge_wol_init(skge);
692412b3
SH		 4076 }
4077
7dbf6acd 4078 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
692412b3 4079 pci_set_power_state(pdev, PCI_D3hot);
692412b3
SH		 4080}
4081
baef58b1
SH		 4082static struct pci_driver skge_driver = {
4083 .name = DRV_NAME,
4084 .id_table = skge_id_table,
4085 .probe = skge_probe,
4086 .remove = __devexit_p(skge_remove),
692412b3 4087 .shutdown = skge_shutdown,
7dbf6acd 4088 .driver.pm = SKGE_PM_OPS,
baef58b1
SH		 4089};
4090
392bd0cb
SG		 4091static struct dmi_system_id skge_32bit_dma_boards[] = {
4092 {
4093 .ident = "Gigabyte nForce boards",
4094 .matches = {
4095 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4096 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4097 },
4098 },
4099 {}
4100};
4101
baef58b1
SH		 4102static int __init skge_init_module(void)
4103{
392bd0cb
SG		 4104 if (dmi_check_system(skge_32bit_dma_boards))
4105 only_32bit_dma = 1;
678aa1f6 4106 skge_debug_init();
29917620 4107 return pci_register_driver(&skge_driver);
baef58b1
SH		 4108}
4109
4110static void __exit skge_cleanup_module(void)
4111{
4112 pci_unregister_driver(&skge_driver);
678aa1f6 4113 skge_debug_cleanup();
baef58b1
SH		 4114}
4115
4116module_init(skge_init_module);
4117module_exit(skge_cleanup_module);
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