projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| e3726fcf | 1 | /* |
| e0befb23 MP |
2 | * Copyright (C) STMicroelectronics 2009 |
| 3 | * Copyright (C) ST-Ericsson SA 2010 | |
| e3726fcf | 4 | * |
| e0befb23 MP |
5 | * Author: Kumar Sanghvi <[email protected]> |
| 6 | * Author: Sundar Iyer <[email protected]> | |
| 7 | * | |
| 8 | * License Terms: GNU General Public License v2 | |
| 9 | * | |
| 10 | * PRCM Unit registers | |
| e3726fcf | 11 | */ |
| c553b3ca | 12 | |
| 3df57bcf MN |
13 | #ifndef __DB8500_PRCMU_REGS_H |
| 14 | #define __DB8500_PRCMU_REGS_H | |
| e0befb23 | 15 | |
| 3df57bcf MN |
16 | #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end)) |
| 17 | ||
| b047d981 | 18 | #define PRCM_ACLK_MGT (0x004) |
| 7f8c5e14 LJ |
19 | #define PRCM_SVAMMCSPCLK_MGT (0x008) |
| 20 | #define PRCM_SIAMMDSPCLK_MGT (0x00C) | |
| b047d981 LW |
21 | #define PRCM_SGACLK_MGT (0x014) |
| 22 | #define PRCM_UARTCLK_MGT (0x018) | |
| 23 | #define PRCM_MSP02CLK_MGT (0x01C) | |
| 24 | #define PRCM_I2CCLK_MGT (0x020) | |
| 25 | #define PRCM_SDMMCCLK_MGT (0x024) | |
| 26 | #define PRCM_SLIMCLK_MGT (0x028) | |
| 27 | #define PRCM_PER1CLK_MGT (0x02C) | |
| 28 | #define PRCM_PER2CLK_MGT (0x030) | |
| 29 | #define PRCM_PER3CLK_MGT (0x034) | |
| 30 | #define PRCM_PER5CLK_MGT (0x038) | |
| 31 | #define PRCM_PER6CLK_MGT (0x03C) | |
| 32 | #define PRCM_PER7CLK_MGT (0x040) | |
| 33 | #define PRCM_LCDCLK_MGT (0x044) | |
| 34 | #define PRCM_BMLCLK_MGT (0x04C) | |
| 35 | #define PRCM_HSITXCLK_MGT (0x050) | |
| 36 | #define PRCM_HSIRXCLK_MGT (0x054) | |
| 37 | #define PRCM_HDMICLK_MGT (0x058) | |
| 38 | #define PRCM_APEATCLK_MGT (0x05C) | |
| 39 | #define PRCM_APETRACECLK_MGT (0x060) | |
| 40 | #define PRCM_MCDECLK_MGT (0x064) | |
| 41 | #define PRCM_IPI2CCLK_MGT (0x068) | |
| 42 | #define PRCM_DSIALTCLK_MGT (0x06C) | |
| 43 | #define PRCM_DMACLK_MGT (0x074) | |
| 44 | #define PRCM_B2R2CLK_MGT (0x078) | |
| 45 | #define PRCM_TVCLK_MGT (0x07C) | |
| 46 | #define PRCM_UNIPROCLK_MGT (0x278) | |
| 47 | #define PRCM_SSPCLK_MGT (0x280) | |
| 48 | #define PRCM_RNGCLK_MGT (0x284) | |
| 49 | #define PRCM_UICCCLK_MGT (0x27C) | |
| 50 | #define PRCM_MSP1CLK_MGT (0x288) | |
| 51 | ||
| 52 | #define PRCM_ARM_PLLDIVPS (prcmu_base + 0x118) | |
| c553b3ca MN |
53 | #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f |
| 54 | #define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf | |
| 55 | ||
| b047d981 | 56 | #define PRCM_PLLARM_LOCKP (prcmu_base + 0x0a8) |
| c553b3ca MN |
57 | #define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2 |
| 58 | ||
| b047d981 | 59 | #define PRCM_ARM_CHGCLKREQ (prcmu_base + 0x114) |
| 20aee5b6 MJ |
60 | #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0) |
| 61 | #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16) | |
| c553b3ca | 62 | |
| b047d981 | 63 | #define PRCM_PLLARM_ENABLE (prcmu_base + 0x98) |
| c553b3ca MN |
64 | #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1 |
| 65 | #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100 | |
| 66 | ||
| b047d981 LW |
67 | #define PRCM_ARMCLKFIX_MGT (prcmu_base + 0x0) |
| 68 | #define PRCM_A9PL_FORCE_CLKEN (prcmu_base + 0x19C) | |
| 69 | #define PRCM_A9_RESETN_CLR (prcmu_base + 0x1f4) | |
| 70 | #define PRCM_A9_RESETN_SET (prcmu_base + 0x1f0) | |
| 71 | #define PRCM_ARM_LS_CLAMP (prcmu_base + 0x30c) | |
| 72 | #define PRCM_SRAM_A9 (prcmu_base + 0x308) | |
| c553b3ca MN |
73 | |
| 74 | #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0) | |
| 75 | #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1) | |
| e3726fcf | 76 | |
| e3726fcf | 77 | /* CPU mailbox registers */ |
| b047d981 LW |
78 | #define PRCM_MBOX_CPU_VAL (prcmu_base + 0x0fc) |
| 79 | #define PRCM_MBOX_CPU_SET (prcmu_base + 0x100) | |
| 80 | #define PRCM_MBOX_CPU_CLR (prcmu_base + 0x104) | |
| e3726fcf | 81 | |
| b047d981 | 82 | #define PRCM_HOSTACCESS_REQ (prcmu_base + 0x334) |
| c553b3ca | 83 | #define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1 |
| 5261e101 | 84 | #define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16) |
| c553b3ca MN |
85 | #define ARM_WAKEUP_MODEM 0x1 |
| 86 | ||
| b047d981 LW |
87 | #define PRCM_ARM_IT1_CLR (prcmu_base + 0x48C) |
| 88 | #define PRCM_ARM_IT1_VAL (prcmu_base + 0x494) | |
| 89 | #define PRCM_HOLD_EVT (prcmu_base + 0x174) | |
| c553b3ca | 90 | |
| b047d981 | 91 | #define PRCM_MOD_AWAKE_STATUS (prcmu_base + 0x4A0) |
| c553b3ca MN |
92 | #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE BIT(0) |
| 93 | #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE BIT(1) | |
| 94 | #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO BIT(2) | |
| 95 | ||
| b047d981 LW |
96 | #define PRCM_ITSTATUS0 (prcmu_base + 0x148) |
| 97 | #define PRCM_ITSTATUS1 (prcmu_base + 0x150) | |
| 98 | #define PRCM_ITSTATUS2 (prcmu_base + 0x158) | |
| 99 | #define PRCM_ITSTATUS3 (prcmu_base + 0x160) | |
| 100 | #define PRCM_ITSTATUS4 (prcmu_base + 0x168) | |
| 101 | #define PRCM_ITSTATUS5 (prcmu_base + 0x484) | |
| 102 | #define PRCM_ITCLEAR5 (prcmu_base + 0x488) | |
| 103 | #define PRCM_ARMIT_MASKXP70_IT (prcmu_base + 0x1018) | |
| e3726fcf LW |
104 | |
| 105 | /* System reset register */ | |
| b047d981 | 106 | #define PRCM_APE_SOFTRST (prcmu_base + 0x228) |
| e3726fcf LW |
107 | |
| 108 | /* Level shifter and clamp control registers */ | |
| b047d981 LW |
109 | #define PRCM_MMIP_LS_CLAMP_SET (prcmu_base + 0x420) |
| 110 | #define PRCM_MMIP_LS_CLAMP_CLR (prcmu_base + 0x424) | |
| c553b3ca | 111 | |
| 6b6fae2b MN |
112 | #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP BIT(11) |
| 113 | #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI BIT(22) | |
| 114 | ||
| c553b3ca | 115 | /* PRCMU clock/PLL/reset registers */ |
| b047d981 LW |
116 | #define PRCM_PLLSOC0_FREQ (prcmu_base + 0x080) |
| 117 | #define PRCM_PLLSOC1_FREQ (prcmu_base + 0x084) | |
| 118 | #define PRCM_PLLARM_FREQ (prcmu_base + 0x088) | |
| 119 | #define PRCM_PLLDDR_FREQ (prcmu_base + 0x08C) | |
| 6b6fae2b MN |
120 | #define PRCM_PLL_FREQ_D_SHIFT 0 |
| 121 | #define PRCM_PLL_FREQ_D_MASK BITS(0, 7) | |
| 122 | #define PRCM_PLL_FREQ_N_SHIFT 8 | |
| 123 | #define PRCM_PLL_FREQ_N_MASK BITS(8, 13) | |
| 124 | #define PRCM_PLL_FREQ_R_SHIFT 16 | |
| 125 | #define PRCM_PLL_FREQ_R_MASK BITS(16, 18) | |
| 126 | #define PRCM_PLL_FREQ_SELDIV2 BIT(24) | |
| 127 | #define PRCM_PLL_FREQ_DIV2EN BIT(25) | |
| 128 | ||
| b047d981 LW |
129 | #define PRCM_PLLDSI_FREQ (prcmu_base + 0x500) |
| 130 | #define PRCM_PLLDSI_ENABLE (prcmu_base + 0x504) | |
| 131 | #define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508) | |
| 132 | #define PRCM_DSI_PLLOUT_SEL (prcmu_base + 0x530) | |
| 133 | #define PRCM_DSITVCLK_DIV (prcmu_base + 0x52C) | |
| 134 | #define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508) | |
| 135 | #define PRCM_APE_RESETN_SET (prcmu_base + 0x1E4) | |
| 136 | #define PRCM_APE_RESETN_CLR (prcmu_base + 0x1E8) | |
| c553b3ca | 137 | |
| 6b6fae2b MN |
138 | #define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0) |
| 139 | ||
| 140 | #define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 BIT(0) | |
| 141 | #define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3 BIT(1) | |
| 142 | ||
| 143 | #define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT 0 | |
| 144 | #define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK BITS(0, 2) | |
| 145 | #define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT 8 | |
| 146 | #define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK BITS(8, 10) | |
| 147 | ||
| 148 | #define PRCM_DSI_PLLOUT_SEL_OFF 0 | |
| 149 | #define PRCM_DSI_PLLOUT_SEL_PHI 1 | |
| 150 | #define PRCM_DSI_PLLOUT_SEL_PHI_2 2 | |
| 151 | #define PRCM_DSI_PLLOUT_SEL_PHI_4 3 | |
| 152 | ||
| 153 | #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT 0 | |
| 154 | #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK BITS(0, 7) | |
| 155 | #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT 8 | |
| 156 | #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK BITS(8, 15) | |
| 157 | #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT 16 | |
| 158 | #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK BITS(16, 23) | |
| 159 | #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN BIT(24) | |
| 160 | #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN BIT(25) | |
| 161 | #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN BIT(26) | |
| 162 | ||
| 163 | #define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14) | |
| 164 | ||
| b047d981 | 165 | #define PRCM_CLKOCR (prcmu_base + 0x1CC) |
| c553b3ca MN |
166 | #define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0) |
| 167 | #define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13) | |
| 168 | #define PRCM_CLKOCR_CLKOUT1_REF_CLK (1 << 16) | |
| 169 | #define PRCM_CLKOCR_CLKOUT1_MASK BITS(16, 29) | |
| 170 | ||
| 171 | /* ePOD and memory power signal control registers */ | |
| b047d981 LW |
172 | #define PRCM_EPOD_C_SET (prcmu_base + 0x410) |
| 173 | #define PRCM_SRAM_LS_SLEEP (prcmu_base + 0x304) | |
| c553b3ca MN |
174 | |
| 175 | /* Debug power control unit registers */ | |
| b047d981 | 176 | #define PRCM_POWER_STATE_SET (prcmu_base + 0x254) |
| c553b3ca MN |
177 | |
| 178 | /* Miscellaneous unit registers */ | |
| b047d981 LW |
179 | #define PRCM_DSI_SW_RESET (prcmu_base + 0x324) |
| 180 | #define PRCM_GPIOCR (prcmu_base + 0x138) | |
| c553b3ca MN |
181 | #define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800 |
| 182 | #define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1 | |
| 3df57bcf MN |
183 | |
| 184 | /* PRCMU HW semaphore */ | |
| b047d981 | 185 | #define PRCM_SEM (prcmu_base + 0x400) |
| 3df57bcf | 186 | #define PRCM_SEM_PRCM_SEM BIT(0) |
| e3726fcf | 187 | |
| b047d981 | 188 | #define PRCM_TCR (prcmu_base + 0x1C8) |
| c553b3ca MN |
189 | #define PRCM_TCR_TENSEL_MASK BITS(0, 7) |
| 190 | #define PRCM_TCR_STOP_TIMERS BIT(16) | |
| 191 | #define PRCM_TCR_DOZE_MODE BIT(17) | |
| 192 | ||
| 3df57bcf MN |
193 | #define PRCM_CLKOCR_CLKODIV0_SHIFT 0 |
| 194 | #define PRCM_CLKOCR_CLKODIV0_MASK BITS(0, 5) | |
| 195 | #define PRCM_CLKOCR_CLKOSEL0_SHIFT 6 | |
| 196 | #define PRCM_CLKOCR_CLKOSEL0_MASK BITS(6, 8) | |
| 197 | #define PRCM_CLKOCR_CLKODIV1_SHIFT 16 | |
| 198 | #define PRCM_CLKOCR_CLKODIV1_MASK BITS(16, 21) | |
| 199 | #define PRCM_CLKOCR_CLKOSEL1_SHIFT 22 | |
| 200 | #define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24) | |
| 201 | #define PRCM_CLKOCR_CLK1TYPE BIT(28) | |
| 202 | ||
| 6b6fae2b MN |
203 | #define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4) |
| 204 | #define PRCM_CLK_MGT_CLKPLLSW_SOC0 BIT(5) | |
| 205 | #define PRCM_CLK_MGT_CLKPLLSW_SOC1 BIT(6) | |
| 206 | #define PRCM_CLK_MGT_CLKPLLSW_DDR BIT(7) | |
| 207 | #define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7) | |
| 208 | #define PRCM_CLK_MGT_CLKEN BIT(8) | |
| 209 | #define PRCM_CLK_MGT_CLK38 BIT(9) | |
| 210 | #define PRCM_CLK_MGT_CLK38DIV BIT(11) | |
| 211 | #define PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN BIT(12) | |
| e3726fcf | 212 | |
| c553b3ca MN |
213 | /* GPIOCR register */ |
| 214 | #define PRCM_GPIOCR_SPI2_SELECT BIT(23) | |
| e3726fcf | 215 | |
| b047d981 LW |
216 | #define PRCM_DDR_SUBSYS_APE_MINBW (prcmu_base + 0x438) |
| 217 | #define PRCM_CGATING_BYPASS (prcmu_base + 0x134) | |
| c553b3ca | 218 | #define PRCM_CGATING_BYPASS_ICN2 BIT(6) |
| e3726fcf LW |
219 | |
| 220 | /* Miscellaneous unit registers */ | |
| b047d981 LW |
221 | #define PRCM_RESOUTN_SET (prcmu_base + 0x214) |
| 222 | #define PRCM_RESOUTN_CLR (prcmu_base + 0x218) | |
| 3df57bcf | 223 | |
| c553b3ca | 224 | /* System reset register */ |
| b047d981 | 225 | #define PRCM_APE_SOFTRST (prcmu_base + 0x228) |
| e3726fcf | 226 | |
| 3df57bcf | 227 | #endif /* __DB8500_PRCMU_REGS_H */ |