[linux.git] / drivers / irqchip / irq-sun4i.c

/*
 * Allwinner A1X SoCs IRQ chip driver.
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <[email protected]>
 *
 * Based on code from
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Benn Huang <[email protected]>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <asm/exception.h>

#define SUN4I_IRQ_VECTOR_REG		0x00
#define SUN4I_IRQ_PROTECTION_REG	0x08
#define SUN4I_IRQ_NMI_CTRL_REG		0x0c
#define SUN4I_IRQ_PENDING_REG(x)	(0x10 + 0x4 * x)
#define SUN4I_IRQ_FIQ_PENDING_REG(x)	(0x20 + 0x4 * x)
#define SUN4I_IRQ_ENABLE_REG(x)		(0x40 + 0x4 * x)
#define SUN4I_IRQ_MASK_REG(x)		(0x50 + 0x4 * x)

static void __iomem *sun4i_irq_base;
static struct irq_domain *sun4i_irq_domain;

static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);

static void sun4i_irq_ack(struct irq_data *irqd)
{
	unsigned int irq = irqd_to_hwirq(irqd);

	if (irq != 0)
		return; /* Only IRQ 0 / the ENMI needs to be acked */

	writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
}

static void sun4i_irq_mask(struct irq_data *irqd)
{
	unsigned int irq = irqd_to_hwirq(irqd);
	unsigned int irq_off = irq % 32;
	int reg = irq / 32;
	u32 val;

	val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
	writel(val & ~(1 << irq_off),
	       sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
}

static void sun4i_irq_unmask(struct irq_data *irqd)
{
	unsigned int irq = irqd_to_hwirq(irqd);
	unsigned int irq_off = irq % 32;
	int reg = irq / 32;
	u32 val;

	val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
	writel(val | (1 << irq_off),
	       sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
}

static struct irq_chip sun4i_irq_chip = {
	.name		= "sun4i_irq",
	.irq_eoi	= sun4i_irq_ack,
	.irq_mask	= sun4i_irq_mask,
	.irq_unmask	= sun4i_irq_unmask,
	.flags		= IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
};

static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
			 irq_hw_number_t hw)
{
	irq_set_chip_and_handler(virq, &sun4i_irq_chip, handle_fasteoi_irq);
	irq_set_probe(virq);

	return 0;
}

static const struct irq_domain_ops sun4i_irq_ops = {
	.map = sun4i_irq_map,
	.xlate = irq_domain_xlate_onecell,
};

static int __init sun4i_of_init(struct device_node *node,
				struct device_node *parent)
{
	sun4i_irq_base = of_iomap(node, 0);
	if (!sun4i_irq_base)
		panic("%s: unable to map IC registers\n",
			node->full_name);

	/* Disable all interrupts */
	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));

	/* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));

	/* Clear all the pending interrupts */
	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));

	/* Enable protection mode */
	writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);

	/* Configure the external interrupt source type */
	writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);

	sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
						 &sun4i_irq_ops, NULL);
	if (!sun4i_irq_domain)
		panic("%s: unable to create IRQ domain\n", node->full_name);

	set_handle_irq(sun4i_handle_irq);

	return 0;
}
IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init);

static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
{
	u32 hwirq;

	/*
	 * hwirq == 0 can mean one of 3 things:
	 * 1) no more irqs pending
	 * 2) irq 0 pending
	 * 3) spurious irq
	 * So if we immediately get a reading of 0, check the irq-pending reg
	 * to differentiate between 2 and 3. We only do this once to avoid
	 * the extra check in the common case of 1 hapening after having
	 * read the vector-reg once.
	 */
	hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
	if (hwirq == 0 &&
		  !(readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0)))
		return;

	do {
		handle_domain_irq(sun4i_irq_domain, hwirq, regs);
		hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
	} while (hwirq != 0);
}
Commit	Line	Data
d7fbc6ca MR	1	/*
	2	* Allwinner A1X SoCs IRQ chip driver.
	3	*
	4	* Copyright (C) 2012 Maxime Ripard
	5	*
	6	* Maxime Ripard <[email protected]>
	7	*
	8	* Based on code from
	9	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	10	* Benn Huang <[email protected]>
	11	*
	12	* This file is licensed under the terms of the GNU General Public
	13	* License version 2. This program is licensed "as is" without any
	14	* warranty of any kind, whether express or implied.
	15	*/
	16
	17	#include <linux/io.h>
	18	#include <linux/irq.h>
41a83e06	19	#include <linux/irqchip.h>
d7fbc6ca MR	20	#include <linux/of.h>
	21	#include <linux/of_address.h>
	22	#include <linux/of_irq.h>
	23
	24	#include <asm/exception.h>
d7fbc6ca	25
d7fbc6ca MR	26	#define SUN4I_IRQ_VECTOR_REG 0x00
	27	#define SUN4I_IRQ_PROTECTION_REG 0x08
	28	#define SUN4I_IRQ_NMI_CTRL_REG 0x0c
	29	#define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
	30	#define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
	31	#define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
	32	#define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
	33
	34	static void __iomem *sun4i_irq_base;
	35	static struct irq_domain *sun4i_irq_domain;
	36
8783dd3a	37	static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
d7fbc6ca	38
baaecfa7	39	static void sun4i_irq_ack(struct irq_data *irqd)
d7fbc6ca MR	40	{
d7fbc6ca MR	41	unsigned int irq = irqd_to_hwirq(irqd);
d7fbc6ca	42
915b78ce HG	43	if (irq != 0)
	44	return; /* Only IRQ 0 / the ENMI needs to be acked */
	45
cc3b68fe	46	writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
d7fbc6ca MR	47	}
	48
	49	static void sun4i_irq_mask(struct irq_data *irqd)
	50	{
	51	unsigned int irq = irqd_to_hwirq(irqd);
	52	unsigned int irq_off = irq % 32;
	53	int reg = irq / 32;
	54	u32 val;
	55
	56	val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
	57	writel(val & ~(1 << irq_off),
	58	sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
	59	}
	60
	61	static void sun4i_irq_unmask(struct irq_data *irqd)
	62	{
	63	unsigned int irq = irqd_to_hwirq(irqd);
	64	unsigned int irq_off = irq % 32;
	65	int reg = irq / 32;
	66	u32 val;
	67
	68	val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
	69	writel(val \| (1 << irq_off),
	70	sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
	71	}
	72
	73	static struct irq_chip sun4i_irq_chip = {
e9df9e22 HG	74	.name = "sun4i_irq",
	75	.irq_eoi = sun4i_irq_ack,
	76	.irq_mask = sun4i_irq_mask,
	77	.irq_unmask = sun4i_irq_unmask,
	78	.flags = IRQCHIP_EOI_THREADED \| IRQCHIP_EOI_IF_HANDLED,
	79	};
	80
d7fbc6ca MR	81	static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
	82	irq_hw_number_t hw)
	83	{
915b78ce	84	irq_set_chip_and_handler(virq, &sun4i_irq_chip, handle_fasteoi_irq);
d17cab44	85	irq_set_probe(virq);
d7fbc6ca MR	86
	87	return 0;
	88	}
	89
96009736	90	static const struct irq_domain_ops sun4i_irq_ops = {
d7fbc6ca MR	91	.map = sun4i_irq_map,
	92	.xlate = irq_domain_xlate_onecell,
	93	};
	94
	95	static int __init sun4i_of_init(struct device_node *node,
	96	struct device_node *parent)
	97	{
	98	sun4i_irq_base = of_iomap(node, 0);
	99	if (!sun4i_irq_base)
	100	panic("%s: unable to map IC registers\n",
	101	node->full_name);
	102
	103	/* Disable all interrupts */
	104	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
	105	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
	106	writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
	107
649ff46e	108	/* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
d7fbc6ca MR	109	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
	110	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
	111	writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
	112
	113	/* Clear all the pending interrupts */
	114	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
	115	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
	116	writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
	117
	118	/* Enable protection mode */
	119	writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
	120
	121	/* Configure the external interrupt source type */
	122	writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
	123
	124	sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
	125	&sun4i_irq_ops, NULL);
	126	if (!sun4i_irq_domain)
	127	panic("%s: unable to create IRQ domain\n", node->full_name);
	128
	129	set_handle_irq(sun4i_handle_irq);
	130
	131	return 0;
	132	}
a7e8b4b5	133	IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init);
d7fbc6ca	134
8783dd3a	135	static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
d7fbc6ca	136	{
21d06d91	137	u32 hwirq;
d7fbc6ca	138
56af0416 HG	139	/*
	140	* hwirq == 0 can mean one of 3 things:
	141	* 1) no more irqs pending
	142	* 2) irq 0 pending
	143	* 3) spurious irq
	144	* So if we immediately get a reading of 0, check the irq-pending reg
	145	* to differentiate between 2 and 3. We only do this once to avoid
	146	* the extra check in the common case of 1 hapening after having
	147	* read the vector-reg once.
	148	*/
d7fbc6ca	149	hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
56af0416 HG	150	if (hwirq == 0 &&
	151	!(readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0)))
	152	return;
	153
	154	do {
21d06d91	155	handle_domain_irq(sun4i_irq_domain, hwirq, regs);
d7fbc6ca	156	hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
56af0416	157	} while (hwirq != 0);
d7fbc6ca	158	}