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Merge git://git.kernel.org/pub/scm/linux/kernel/git/agk/linux-2.6-dm
[linux.git] / drivers / video / mx3fb.c
CommitLineData
86528da2
GL		 1/*
2 * Copyright (C) 2008
3 * Guennadi Liakhovetski, DENX Software Engineering, <[email protected]>
4 *
5 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/platform_device.h>
15#include <linux/sched.h>
16#include <linux/errno.h>
17#include <linux/string.h>
18#include <linux/interrupt.h>
19#include <linux/slab.h>
20#include <linux/fb.h>
21#include <linux/delay.h>
22#include <linux/init.h>
23#include <linux/ioport.h>
24#include <linux/dma-mapping.h>
25#include <linux/dmaengine.h>
26#include <linux/console.h>
27#include <linux/clk.h>
28#include <linux/mutex.h>
29
1b346af2 30#include <mach/dma.h>
86528da2
GL		 31#include <mach/hardware.h>
32#include <mach/ipu.h>
33#include <mach/mx3fb.h>
34
35#include <asm/io.h>
36#include <asm/uaccess.h>
37
6e1588cb 38#define MX3FB_NAME "mx3_sdc_fb"
86528da2 39
6e1588cb 40#define MX3FB_REG_OFFSET 0xB4
86528da2
GL		 41
42/* SDC Registers */
6e1588cb
GL		 43#define SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET)
44#define SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET)
45#define SDC_FG_POS (0xBC - MX3FB_REG_OFFSET)
46#define SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET)
47#define SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET)
48#define SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET)
49#define SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET)
50#define SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET)
51#define SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET)
52#define SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET)
53#define SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET)
86528da2
GL		 54
55/* Register bits */
6e1588cb
GL		 56#define SDC_COM_TFT_COLOR 0x00000001UL
57#define SDC_COM_FG_EN 0x00000010UL
58#define SDC_COM_GWSEL 0x00000020UL
59#define SDC_COM_GLB_A 0x00000040UL
60#define SDC_COM_KEY_COLOR_G 0x00000080UL
61#define SDC_COM_BG_EN 0x00000200UL
62#define SDC_COM_SHARP 0x00001000UL
86528da2 63
6e1588cb 64#define SDC_V_SYNC_WIDTH_L 0x00000001UL
86528da2
GL		 65
66/* Display Interface registers */
6e1588cb
GL		 67#define DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET)
68#define DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET)
69#define DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET)
70#define DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET)
71#define DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET)
72#define DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET)
73#define DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET)
74#define DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET)
75#define DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET)
76#define DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET)
77#define DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET)
78#define DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET)
79#define DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET)
80#define DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET)
81#define DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET)
82#define DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET)
83#define DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET)
84#define DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET)
85#define DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET)
86#define DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET)
87#define DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET)
88#define DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET)
89#define DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET)
90#define DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET)
91#define DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET)
92#define DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET)
93#define DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET)
94#define DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET)
95#define DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET)
96#define DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET)
97#define DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET)
98#define DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET)
99#define DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET)
100#define DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET)
101#define DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET)
102#define DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET)
103#define DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET)
104#define DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET)
105#define DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET)
86528da2
GL		 106
107/* DI_DISP_SIG_POL bits */
6e1588cb
GL		 108#define DI_D3_VSYNC_POL_SHIFT 28
109#define DI_D3_HSYNC_POL_SHIFT 27
110#define DI_D3_DRDY_SHARP_POL_SHIFT 26
111#define DI_D3_CLK_POL_SHIFT 25
112#define DI_D3_DATA_POL_SHIFT 24
86528da2
GL		 113
114/* DI_DISP_IF_CONF bits */
6e1588cb
GL		 115#define DI_D3_CLK_IDLE_SHIFT 26
116#define DI_D3_CLK_SEL_SHIFT 25
117#define DI_D3_DATAMSK_SHIFT 24
86528da2
GL		 118
119enum ipu_panel {
6e1588cb
GL		 120 IPU_PANEL_SHARP_TFT,
121 IPU_PANEL_TFT,
86528da2
GL		 122};
123
124struct ipu_di_signal_cfg {
6e1588cb
GL		 125 unsigned datamask_en:1;
126 unsigned clksel_en:1;
127 unsigned clkidle_en:1;
128 unsigned data_pol:1; /* true = inverted */
129 unsigned clk_pol:1; /* true = rising edge */
130 unsigned enable_pol:1;
131 unsigned Hsync_pol:1; /* true = active high */
132 unsigned Vsync_pol:1;
86528da2
GL		 133};
134
135static const struct fb_videomode mx3fb_modedb[] = {
6e1588cb
GL		 136 {
137 /* 240x320 @ 60 Hz */
138 .name = "Sharp-QVGA",
139 .refresh = 60,
140 .xres = 240,
141 .yres = 320,
142 .pixclock = 185925,
143 .left_margin = 9,
144 .right_margin = 16,
145 .upper_margin = 7,
146 .lower_margin = 9,
147 .hsync_len = 1,
148 .vsync_len = 1,
149 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
150 FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
151 FB_SYNC_CLK_IDLE_EN,
152 .vmode = FB_VMODE_NONINTERLACED,
153 .flag = 0,
154 }, {
155 /* 240x33 @ 60 Hz */
156 .name = "Sharp-CLI",
157 .refresh = 60,
158 .xres = 240,
159 .yres = 33,
160 .pixclock = 185925,
161 .left_margin = 9,
162 .right_margin = 16,
163 .upper_margin = 7,
164 .lower_margin = 9 + 287,
165 .hsync_len = 1,
166 .vsync_len = 1,
167 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
168 FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
169 FB_SYNC_CLK_IDLE_EN,
170 .vmode = FB_VMODE_NONINTERLACED,
171 .flag = 0,
172 }, {
173 /* 640x480 @ 60 Hz */
174 .name = "NEC-VGA",
175 .refresh = 60,
176 .xres = 640,
177 .yres = 480,
178 .pixclock = 38255,
179 .left_margin = 144,
180 .right_margin = 0,
181 .upper_margin = 34,
182 .lower_margin = 40,
183 .hsync_len = 1,
184 .vsync_len = 1,
185 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
186 .vmode = FB_VMODE_NONINTERLACED,
187 .flag = 0,
188 }, {
189 /* NTSC TV output */
190 .name = "TV-NTSC",
191 .refresh = 60,
192 .xres = 640,
193 .yres = 480,
194 .pixclock = 37538,
195 .left_margin = 38,
196 .right_margin = 858 - 640 - 38 - 3,
197 .upper_margin = 36,
198 .lower_margin = 518 - 480 - 36 - 1,
199 .hsync_len = 3,
200 .vsync_len = 1,
201 .sync = 0,
202 .vmode = FB_VMODE_NONINTERLACED,
203 .flag = 0,
204 }, {
205 /* PAL TV output */
206 .name = "TV-PAL",
207 .refresh = 50,
208 .xres = 640,
209 .yres = 480,
210 .pixclock = 37538,
211 .left_margin = 38,
212 .right_margin = 960 - 640 - 38 - 32,
213 .upper_margin = 32,
214 .lower_margin = 555 - 480 - 32 - 3,
215 .hsync_len = 32,
216 .vsync_len = 3,
217 .sync = 0,
218 .vmode = FB_VMODE_NONINTERLACED,
219 .flag = 0,
220 }, {
221 /* TV output VGA mode, 640x480 @ 65 Hz */
222 .name = "TV-VGA",
223 .refresh = 60,
224 .xres = 640,
225 .yres = 480,
226 .pixclock = 40574,
227 .left_margin = 35,
228 .right_margin = 45,
229 .upper_margin = 9,
230 .lower_margin = 1,
231 .hsync_len = 46,
232 .vsync_len = 5,
233 .sync = 0,
234 .vmode = FB_VMODE_NONINTERLACED,
235 .flag = 0,
236 },
86528da2
GL		 237};
238
239struct mx3fb_data {
6e1588cb
GL		 240 struct fb_info *fbi;
241 int backlight_level;
242 void __iomem *reg_base;
243 spinlock_t lock;
244 struct device *dev;
245
246 uint32_t h_start_width;
247 uint32_t v_start_width;
86528da2
GL		 248};
249
250struct dma_chan_request {
6e1588cb
GL		 251 struct mx3fb_data *mx3fb;
252 enum ipu_channel id;
86528da2
GL		 253};
254
255/* MX3 specific framebuffer information. */
256struct mx3fb_info {
6e1588cb
GL		 257 int blank;
258 enum ipu_channel ipu_ch;
259 uint32_t cur_ipu_buf;
86528da2 260
6e1588cb 261 u32 pseudo_palette[16];
86528da2 262
6e1588cb
GL		 263 struct completion flip_cmpl;
264 struct mutex mutex; /* Protects fb-ops */
265 struct mx3fb_data *mx3fb;
266 struct idmac_channel *idmac_channel;
267 struct dma_async_tx_descriptor *txd;
268 dma_cookie_t cookie;
269 struct scatterlist sg[2];
86528da2 270
6e1588cb 271 u32 sync; /* preserve var->sync flags */
86528da2
GL		 272};
273
274static void mx3fb_dma_done(void *);
275
276/* Used fb-mode and bpp. Can be set on kernel command line, therefore file-static. */
277static const char *fb_mode;
278static unsigned long default_bpp = 16;
279
280static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg)
281{
6e1588cb 282 return __raw_readl(mx3fb->reg_base + reg);
86528da2
GL		 283}
284
285static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg)
286{
6e1588cb 287 __raw_writel(value, mx3fb->reg_base + reg);
86528da2
GL		 288}
289
290static const uint32_t di_mappings[] = {
6e1588cb
GL		 291 0x1600AAAA, 0x00E05555, 0x00070000, 3, /* RGB888 */
292 0x0005000F, 0x000B000F, 0x0011000F, 1, /* RGB666 */
293 0x0011000F, 0x000B000F, 0x0005000F, 1, /* BGR666 */
294 0x0004003F, 0x000A000F, 0x000F003F, 1 /* RGB565 */
86528da2
GL		 295};
296
297static void sdc_fb_init(struct mx3fb_info *fbi)
298{
6e1588cb
GL		 299 struct mx3fb_data *mx3fb = fbi->mx3fb;
300 uint32_t reg;
86528da2 301
6e1588cb 302 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
86528da2 303
6e1588cb 304 mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF);
86528da2
GL		 305}
306
307/* Returns enabled flag before uninit */
308static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi)
309{
6e1588cb
GL		 310 struct mx3fb_data *mx3fb = fbi->mx3fb;
311 uint32_t reg;
86528da2 312
6e1588cb 313 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
86528da2 314
6e1588cb 315 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF);
86528da2 316
6e1588cb 317 return reg & SDC_COM_BG_EN;
86528da2
GL		 318}
319
320static void sdc_enable_channel(struct mx3fb_info *mx3_fbi)
321{
6e1588cb
GL		 322 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
323 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
324 struct dma_chan *dma_chan = &ichan->dma_chan;
325 unsigned long flags;
326 dma_cookie_t cookie;
327
b3cb5372
AP		 328 if (mx3_fbi->txd)
329 dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi,
330 to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg);
331 else
332 dev_dbg(mx3fb->dev, "mx3fbi %p, txd = NULL\n", mx3_fbi);
6e1588cb
GL		 333
334 /* This enables the channel */
335 if (mx3_fbi->cookie < 0) {
336 mx3_fbi->txd = dma_chan->device->device_prep_slave_sg(dma_chan,
337 &mx3_fbi->sg[0], 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT);
338 if (!mx3_fbi->txd) {
339 dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n",
340 dma_chan->chan_id);
341 return;
342 }
343
344 mx3_fbi->txd->callback_param = mx3_fbi->txd;
345 mx3_fbi->txd->callback = mx3fb_dma_done;
346
347 cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd);
348 dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__,
349 mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
350 } else {
351 if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) {
352 dev_err(mx3fb->dev, "Cannot enable channel %d\n",
353 dma_chan->chan_id);
354 return;
355 }
356
357 /* Just re-activate the same buffer */
358 dma_async_issue_pending(dma_chan);
359 cookie = mx3_fbi->cookie;
360 dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__,
361 mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
362 }
363
364 if (cookie >= 0) {
365 spin_lock_irqsave(&mx3fb->lock, flags);
366 sdc_fb_init(mx3_fbi);
367 mx3_fbi->cookie = cookie;
368 spin_unlock_irqrestore(&mx3fb->lock, flags);
369 }
370
371 /*
372 * Attention! Without this msleep the channel keeps generating
373 * interrupts. Next sdc_set_brightness() is going to be called
374 * from mx3fb_blank().
375 */
376 msleep(2);
86528da2
GL		 377}
378
379static void sdc_disable_channel(struct mx3fb_info *mx3_fbi)
380{
6e1588cb
GL		 381 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
382 uint32_t enabled;
383 unsigned long flags;
86528da2 384
6e1588cb 385 spin_lock_irqsave(&mx3fb->lock, flags);
86528da2 386
6e1588cb 387 enabled = sdc_fb_uninit(mx3_fbi);
86528da2 388
6e1588cb 389 spin_unlock_irqrestore(&mx3fb->lock, flags);
86528da2 390
c3635c78 391 mx3_fbi->txd->chan->device->device_control(mx3_fbi->txd->chan,
05827630 392 DMA_TERMINATE_ALL, 0);
6e1588cb
GL		 393 mx3_fbi->txd = NULL;
394 mx3_fbi->cookie = -EINVAL;
86528da2
GL		 395}
396
397/**
398 * sdc_set_window_pos() - set window position of the respective plane.
6e1588cb
GL		 399 * @mx3fb: mx3fb context.
400 * @channel: IPU DMAC channel ID.
401 * @x_pos: X coordinate relative to the top left corner to place window at.
402 * @y_pos: Y coordinate relative to the top left corner to place window at.
403 * @return: 0 on success or negative error code on failure.
86528da2
GL		 404 */
405static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel,
6e1588cb 406 int16_t x_pos, int16_t y_pos)
86528da2 407{
6e1588cb
GL		 408 if (channel != IDMAC_SDC_0)
409 return -EINVAL;
86528da2 410
d88ca815
GL		 411 x_pos += mx3fb->h_start_width;
412 y_pos += mx3fb->v_start_width;
413
6e1588cb
GL		 414 mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS);
415 return 0;
86528da2
GL		 416}
417
418/**
419 * sdc_init_panel() - initialize a synchronous LCD panel.
6e1588cb
GL		 420 * @mx3fb: mx3fb context.
421 * @panel: panel type.
422 * @pixel_clk: desired pixel clock frequency in Hz.
423 * @width: width of panel in pixels.
424 * @height: height of panel in pixels.
425 * @pixel_fmt: pixel format of buffer as FOURCC ASCII code.
426 * @h_start_width: number of pixel clocks between the HSYNC signal pulse
427 * and the start of valid data.
428 * @h_sync_width: width of the HSYNC signal in units of pixel clocks.
429 * @h_end_width: number of pixel clocks between the end of valid data
430 * and the HSYNC signal for next line.
431 * @v_start_width: number of lines between the VSYNC signal pulse and the
432 * start of valid data.
433 * @v_sync_width: width of the VSYNC signal in units of lines
434 * @v_end_width: number of lines between the end of valid data and the
435 * VSYNC signal for next frame.
436 * @sig: bitfield of signal polarities for LCD interface.
437 * @return: 0 on success or negative error code on failure.
86528da2
GL		 438 */
439static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel,
6e1588cb
GL		 440 uint32_t pixel_clk,
441 uint16_t width, uint16_t height,
442 enum pixel_fmt pixel_fmt,
443 uint16_t h_start_width, uint16_t h_sync_width,
444 uint16_t h_end_width, uint16_t v_start_width,
445 uint16_t v_sync_width, uint16_t v_end_width,
446 struct ipu_di_signal_cfg sig)
86528da2 447{
6e1588cb
GL		 448 unsigned long lock_flags;
449 uint32_t reg;
450 uint32_t old_conf;
451 uint32_t div;
452 struct clk *ipu_clk;
86528da2 453
6e1588cb 454 dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height);
86528da2 455
6e1588cb
GL		 456 if (v_sync_width == 0 || h_sync_width == 0)
457 return -EINVAL;
86528da2 458
6e1588cb
GL		 459 /* Init panel size and blanking periods */
460 reg = ((uint32_t) (h_sync_width - 1) << 26) |
461 ((uint32_t) (width + h_start_width + h_end_width - 1) << 16);
462 mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF);
86528da2
GL		 463
464#ifdef DEBUG
6e1588cb 465 printk(KERN_CONT " hor_conf %x,", reg);
86528da2
GL		 466#endif
467
6e1588cb
GL		 468 reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L |
469 ((uint32_t) (height + v_start_width + v_end_width - 1) << 16);
470 mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF);
86528da2
GL		 471
472#ifdef DEBUG
6e1588cb 473 printk(KERN_CONT " ver_conf %x\n", reg);
86528da2
GL		 474#endif
475
6e1588cb
GL		 476 mx3fb->h_start_width = h_start_width;
477 mx3fb->v_start_width = v_start_width;
478
479 switch (panel) {
480 case IPU_PANEL_SHARP_TFT:
481 mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1);
482 mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2);
483 mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
484 break;
485 case IPU_PANEL_TFT:
486 mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF);
487 break;
488 default:
489 return -EINVAL;
490 }
491
492 /* Init clocking */
493
494 /*
495 * Calculate divider: fractional part is 4 bits so simply multiple by
496 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
497 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
498 */
3879f5d6 499 ipu_clk = clk_get(mx3fb->dev, NULL);
d88ca815
GL		 500 if (!IS_ERR(ipu_clk)) {
501 div = clk_get_rate(ipu_clk) * 16 / pixel_clk;
502 clk_put(ipu_clk);
503 } else {
504 div = 0;
505 }
6e1588cb
GL		 506
507 if (div < 0x40) { /* Divider less than 4 */
508 dev_dbg(mx3fb->dev,
509 "InitPanel() - Pixel clock divider less than 4\n");
510 div = 0x40;
511 }
512
d88ca815
GL		 513 dev_dbg(mx3fb->dev, "pixel clk = %u, divider %u.%u\n",
514 pixel_clk, div >> 4, (div & 7) * 125);
515
6e1588cb
GL		 516 spin_lock_irqsave(&mx3fb->lock, lock_flags);
517
518 /*
519 * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits
520 * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing
521 * debug. DISP3_IF_CLK_UP_WR is 0
522 */
523 mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
524
525 /* DI settings */
526 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF;
527 old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT |
d88ca815
GL		 528 sig.clksel_en << DI_D3_CLK_SEL_SHIFT |
529 sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT;
6e1588cb
GL		 530 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF);
531
532 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF;
533 old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT |
d88ca815
GL		 534 sig.clk_pol << DI_D3_CLK_POL_SHIFT |
535 sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT |
536 sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT |
537 sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT;
6e1588cb
GL		 538 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL);
539
540 switch (pixel_fmt) {
541 case IPU_PIX_FMT_RGB24:
542 mx3fb_write_reg(mx3fb, di_mappings[0], DI_DISP3_B0_MAP);
543 mx3fb_write_reg(mx3fb, di_mappings[1], DI_DISP3_B1_MAP);
544 mx3fb_write_reg(mx3fb, di_mappings[2], DI_DISP3_B2_MAP);
545 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
546 ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC);
547 break;
548 case IPU_PIX_FMT_RGB666:
549 mx3fb_write_reg(mx3fb, di_mappings[4], DI_DISP3_B0_MAP);
550 mx3fb_write_reg(mx3fb, di_mappings[5], DI_DISP3_B1_MAP);
551 mx3fb_write_reg(mx3fb, di_mappings[6], DI_DISP3_B2_MAP);
552 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
553 ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC);
554 break;
555 case IPU_PIX_FMT_BGR666:
556 mx3fb_write_reg(mx3fb, di_mappings[8], DI_DISP3_B0_MAP);
557 mx3fb_write_reg(mx3fb, di_mappings[9], DI_DISP3_B1_MAP);
558 mx3fb_write_reg(mx3fb, di_mappings[10], DI_DISP3_B2_MAP);
559 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
560 ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC);
561 break;
562 default:
563 mx3fb_write_reg(mx3fb, di_mappings[12], DI_DISP3_B0_MAP);
564 mx3fb_write_reg(mx3fb, di_mappings[13], DI_DISP3_B1_MAP);
565 mx3fb_write_reg(mx3fb, di_mappings[14], DI_DISP3_B2_MAP);
566 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
567 ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC);
568 break;
569 }
570
571 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
572
573 dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n",
574 mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF));
575 dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n",
576 mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL));
577 dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n",
578 mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF));
579
580 return 0;
86528da2
GL		 581}
582
583/**
584 * sdc_set_color_key() - set the transparent color key for SDC graphic plane.
6e1588cb
GL		 585 * @mx3fb: mx3fb context.
586 * @channel: IPU DMAC channel ID.
587 * @enable: boolean to enable or disable color keyl.
588 * @color_key: 24-bit RGB color to use as transparent color key.
589 * @return: 0 on success or negative error code on failure.
86528da2
GL		 590 */
591static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel,
6e1588cb 592 bool enable, uint32_t color_key)
86528da2 593{
6e1588cb
GL		 594 uint32_t reg, sdc_conf;
595 unsigned long lock_flags;
86528da2 596
6e1588cb 597 spin_lock_irqsave(&mx3fb->lock, lock_flags);
86528da2 598
6e1588cb
GL		 599 sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
600 if (channel == IDMAC_SDC_0)
601 sdc_conf &= ~SDC_COM_GWSEL;
602 else
603 sdc_conf |= SDC_COM_GWSEL;
86528da2 604
6e1588cb
GL		 605 if (enable) {
606 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L;
607 mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL),
608 SDC_GW_CTRL);
86528da2 609
6e1588cb
GL		 610 sdc_conf |= SDC_COM_KEY_COLOR_G;
611 } else {
612 sdc_conf &= ~SDC_COM_KEY_COLOR_G;
613 }
614 mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF);
86528da2 615
6e1588cb 616 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
86528da2 617
6e1588cb 618 return 0;
86528da2
GL		 619}
620
621/**
622 * sdc_set_global_alpha() - set global alpha blending modes.
6e1588cb
GL		 623 * @mx3fb: mx3fb context.
624 * @enable: boolean to enable or disable global alpha blending. If disabled,
625 * per pixel blending is used.
626 * @alpha: global alpha value.
627 * @return: 0 on success or negative error code on failure.
86528da2
GL		 628 */
629static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha)
630{
6e1588cb
GL		 631 uint32_t reg;
632 unsigned long lock_flags;
86528da2 633
6e1588cb 634 spin_lock_irqsave(&mx3fb->lock, lock_flags);
86528da2 635
6e1588cb
GL		 636 if (enable) {
637 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL;
638 mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL);
86528da2 639
6e1588cb
GL		 640 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
641 mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF);
642 } else {
643 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
644 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF);
645 }
86528da2 646
6e1588cb 647 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
86528da2 648
6e1588cb 649 return 0;
86528da2
GL		 650}
651
652static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value)
653{
b3cb5372 654 dev_dbg(mx3fb->dev, "%s: value = %d\n", __func__, value);
6e1588cb
GL		 655 /* This might be board-specific */
656 mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL);
657 return;
86528da2
GL		 658}
659
660static uint32_t bpp_to_pixfmt(int bpp)
661{
6e1588cb
GL		 662 uint32_t pixfmt = 0;
663 switch (bpp) {
664 case 24:
665 pixfmt = IPU_PIX_FMT_BGR24;
666 break;
667 case 32:
668 pixfmt = IPU_PIX_FMT_BGR32;
669 break;
670 case 16:
671 pixfmt = IPU_PIX_FMT_RGB565;
672 break;
673 }
674 return pixfmt;
86528da2
GL		 675}
676
677static int mx3fb_blank(int blank, struct fb_info *fbi);
20de03da
GL		 678static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
679 bool lock);
86528da2
GL		 680static int mx3fb_unmap_video_memory(struct fb_info *fbi);
681
682/**
683 * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings.
6e1588cb
GL		 684 * @info: framebuffer information pointer
685 * @return: 0 on success or negative error code on failure.
86528da2
GL		 686 */
687static int mx3fb_set_fix(struct fb_info *fbi)
688{
6e1588cb
GL		 689 struct fb_fix_screeninfo *fix = &fbi->fix;
690 struct fb_var_screeninfo *var = &fbi->var;
86528da2 691
6e1588cb 692 strncpy(fix->id, "DISP3 BG", 8);
86528da2 693
6e1588cb 694 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
86528da2 695
6e1588cb
GL		 696 fix->type = FB_TYPE_PACKED_PIXELS;
697 fix->accel = FB_ACCEL_NONE;
698 fix->visual = FB_VISUAL_TRUECOLOR;
699 fix->xpanstep = 1;
700 fix->ypanstep = 1;
86528da2 701
6e1588cb 702 return 0;
86528da2
GL		 703}
704
705static void mx3fb_dma_done(void *arg)
706{
6e1588cb
GL		 707 struct idmac_tx_desc *tx_desc = to_tx_desc(arg);
708 struct dma_chan *chan = tx_desc->txd.chan;
709 struct idmac_channel *ichannel = to_idmac_chan(chan);
710 struct mx3fb_data *mx3fb = ichannel->client;
711 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
86528da2 712
6e1588cb 713 dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq);
86528da2 714
6e1588cb 715 /* We only need one interrupt, it will be re-enabled as needed */
c8a4fb47 716 disable_irq_nosync(ichannel->eof_irq);
86528da2 717
6e1588cb 718 complete(&mx3_fbi->flip_cmpl);
86528da2
GL		 719}
720
20de03da 721static int __set_par(struct fb_info *fbi, bool lock)
86528da2 722{
6e1588cb
GL		 723 u32 mem_len;
724 struct ipu_di_signal_cfg sig_cfg;
725 enum ipu_panel mode = IPU_PANEL_TFT;
726 struct mx3fb_info *mx3_fbi = fbi->par;
727 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
728 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
729 struct idmac_video_param *video = &ichan->params.video;
730 struct scatterlist *sg = mx3_fbi->sg;
6e1588cb 731
6e1588cb
GL		 732 /* Total cleanup */
733 if (mx3_fbi->txd)
734 sdc_disable_channel(mx3_fbi);
735
736 mx3fb_set_fix(fbi);
737
738 mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
739 if (mem_len > fbi->fix.smem_len) {
740 if (fbi->fix.smem_start)
741 mx3fb_unmap_video_memory(fbi);
742
20de03da 743 if (mx3fb_map_video_memory(fbi, mem_len, lock) < 0)
6e1588cb 744 return -ENOMEM;
6e1588cb
GL		 745 }
746
6e1588cb
GL		 747 sg_init_table(&sg[0], 1);
748 sg_init_table(&sg[1], 1);
749
d88ca815 750 sg_dma_address(&sg[0]) = fbi->fix.smem_start;
6e1588cb
GL		 751 sg_set_page(&sg[0], virt_to_page(fbi->screen_base),
752 fbi->fix.smem_len,
753 offset_in_page(fbi->screen_base));
754
755 if (mx3_fbi->ipu_ch == IDMAC_SDC_0) {
756 memset(&sig_cfg, 0, sizeof(sig_cfg));
757 if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
758 sig_cfg.Hsync_pol = true;
759 if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
760 sig_cfg.Vsync_pol = true;
761 if (fbi->var.sync & FB_SYNC_CLK_INVERT)
762 sig_cfg.clk_pol = true;
763 if (fbi->var.sync & FB_SYNC_DATA_INVERT)
764 sig_cfg.data_pol = true;
765 if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH)
766 sig_cfg.enable_pol = true;
767 if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
768 sig_cfg.clkidle_en = true;
769 if (fbi->var.sync & FB_SYNC_CLK_SEL_EN)
770 sig_cfg.clksel_en = true;
771 if (fbi->var.sync & FB_SYNC_SHARP_MODE)
772 mode = IPU_PANEL_SHARP_TFT;
773
774 dev_dbg(fbi->device, "pixclock = %ul Hz\n",
775 (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
776
777 if (sdc_init_panel(mx3fb, mode,
778 (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
779 fbi->var.xres, fbi->var.yres,
780 (fbi->var.sync & FB_SYNC_SWAP_RGB) ?
781 IPU_PIX_FMT_BGR666 : IPU_PIX_FMT_RGB666,
782 fbi->var.left_margin,
783 fbi->var.hsync_len,
784 fbi->var.right_margin +
785 fbi->var.hsync_len,
786 fbi->var.upper_margin,
787 fbi->var.vsync_len,
788 fbi->var.lower_margin +
789 fbi->var.vsync_len, sig_cfg) != 0) {
6e1588cb
GL		 790 dev_err(fbi->device,
791 "mx3fb: Error initializing panel.\n");
792 return -EINVAL;
793 }
794 }
795
796 sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0);
797
798 mx3_fbi->cur_ipu_buf = 0;
799
800 video->out_pixel_fmt = bpp_to_pixfmt(fbi->var.bits_per_pixel);
801 video->out_width = fbi->var.xres;
802 video->out_height = fbi->var.yres;
803 video->out_stride = fbi->var.xres_virtual;
804
805 if (mx3_fbi->blank == FB_BLANK_UNBLANK)
806 sdc_enable_channel(mx3_fbi);
807
20de03da
GL		 808 return 0;
809}
810
811/**
812 * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
813 * @fbi: framebuffer information pointer.
814 * @return: 0 on success or negative error code on failure.
815 */
816static int mx3fb_set_par(struct fb_info *fbi)
817{
818 struct mx3fb_info *mx3_fbi = fbi->par;
819 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
820 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
821 int ret;
822
823 dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+');
824
825 mutex_lock(&mx3_fbi->mutex);
826
827 ret = __set_par(fbi, true);
828
6e1588cb
GL		 829 mutex_unlock(&mx3_fbi->mutex);
830
20de03da 831 return ret;
86528da2
GL		 832}
833
834/**
835 * mx3fb_check_var() - check and adjust framebuffer variable parameters.
6e1588cb
GL		 836 * @var: framebuffer variable parameters
837 * @fbi: framebuffer information pointer
86528da2
GL		 838 */
839static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
840{
6e1588cb
GL		 841 struct mx3fb_info *mx3_fbi = fbi->par;
842 u32 vtotal;
843 u32 htotal;
844
845 dev_dbg(fbi->device, "%s\n", __func__);
846
847 if (var->xres_virtual < var->xres)
848 var->xres_virtual = var->xres;
849 if (var->yres_virtual < var->yres)
850 var->yres_virtual = var->yres;
851
852 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
853 (var->bits_per_pixel != 16))
854 var->bits_per_pixel = default_bpp;
855
856 switch (var->bits_per_pixel) {
857 case 16:
858 var->red.length = 5;
859 var->red.offset = 11;
860 var->red.msb_right = 0;
861
862 var->green.length = 6;
863 var->green.offset = 5;
864 var->green.msb_right = 0;
865
866 var->blue.length = 5;
867 var->blue.offset = 0;
868 var->blue.msb_right = 0;
869
870 var->transp.length = 0;
871 var->transp.offset = 0;
872 var->transp.msb_right = 0;
873 break;
874 case 24:
875 var->red.length = 8;
876 var->red.offset = 16;
877 var->red.msb_right = 0;
878
879 var->green.length = 8;
880 var->green.offset = 8;
881 var->green.msb_right = 0;
882
883 var->blue.length = 8;
884 var->blue.offset = 0;
885 var->blue.msb_right = 0;
886
887 var->transp.length = 0;
888 var->transp.offset = 0;
889 var->transp.msb_right = 0;
890 break;
891 case 32:
892 var->red.length = 8;
893 var->red.offset = 16;
894 var->red.msb_right = 0;
895
896 var->green.length = 8;
897 var->green.offset = 8;
898 var->green.msb_right = 0;
899
900 var->blue.length = 8;
901 var->blue.offset = 0;
902 var->blue.msb_right = 0;
903
904 var->transp.length = 8;
905 var->transp.offset = 24;
906 var->transp.msb_right = 0;
907 break;
908 }
909
910 if (var->pixclock < 1000) {
911 htotal = var->xres + var->right_margin + var->hsync_len +
912 var->left_margin;
913 vtotal = var->yres + var->lower_margin + var->vsync_len +
914 var->upper_margin;
915 var->pixclock = (vtotal * htotal * 6UL) / 100UL;
916 var->pixclock = KHZ2PICOS(var->pixclock);
917 dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n",
918 var->pixclock);
919 }
920
921 var->height = -1;
922 var->width = -1;
923 var->grayscale = 0;
924
925 /* Preserve sync flags */
926 var->sync |= mx3_fbi->sync;
927 mx3_fbi->sync |= var->sync;
928
929 return 0;
86528da2
GL		 930}
931
932static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf)
933{
6e1588cb
GL		 934 chan &= 0xffff;
935 chan >>= 16 - bf->length;
936 return chan << bf->offset;
86528da2
GL		 937}
938
939static int mx3fb_setcolreg(unsigned int regno, unsigned int red,
6e1588cb
GL		 940 unsigned int green, unsigned int blue,
941 unsigned int trans, struct fb_info *fbi)
86528da2 942{
6e1588cb
GL		 943 struct mx3fb_info *mx3_fbi = fbi->par;
944 u32 val;
945 int ret = 1;
946
d88ca815 947 dev_dbg(fbi->device, "%s, regno = %u\n", __func__, regno);
6e1588cb
GL		 948
949 mutex_lock(&mx3_fbi->mutex);
950 /*
951 * If greyscale is true, then we convert the RGB value
952 * to greyscale no matter what visual we are using.
953 */
954 if (fbi->var.grayscale)
955 red = green = blue = (19595 * red + 38470 * green +
956 7471 * blue) >> 16;
957 switch (fbi->fix.visual) {
958 case FB_VISUAL_TRUECOLOR:
959 /*
960 * 16-bit True Colour. We encode the RGB value
961 * according to the RGB bitfield information.
962 */
963 if (regno < 16) {
964 u32 *pal = fbi->pseudo_palette;
965
966 val = chan_to_field(red, &fbi->var.red);
967 val |= chan_to_field(green, &fbi->var.green);
968 val |= chan_to_field(blue, &fbi->var.blue);
969
970 pal[regno] = val;
971
972 ret = 0;
973 }
974 break;
975
976 case FB_VISUAL_STATIC_PSEUDOCOLOR:
977 case FB_VISUAL_PSEUDOCOLOR:
978 break;
979 }
980 mutex_unlock(&mx3_fbi->mutex);
981
982 return ret;
86528da2
GL		 983}
984
20de03da 985static void __blank(int blank, struct fb_info *fbi)
86528da2 986{
6e1588cb
GL		 987 struct mx3fb_info *mx3_fbi = fbi->par;
988 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
989
6e1588cb
GL		 990 mx3_fbi->blank = blank;
991
992 switch (blank) {
993 case FB_BLANK_POWERDOWN:
994 case FB_BLANK_VSYNC_SUSPEND:
995 case FB_BLANK_HSYNC_SUSPEND:
996 case FB_BLANK_NORMAL:
6e1588cb 997 sdc_set_brightness(mx3fb, 0);
d88ca815
GL		 998 memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
999 /* Give LCD time to update - enough for 50 and 60 Hz */
1000 msleep(25);
1001 sdc_disable_channel(mx3_fbi);
6e1588cb
GL		 1002 break;
1003 case FB_BLANK_UNBLANK:
1004 sdc_enable_channel(mx3_fbi);
1005 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1006 break;
1007 }
20de03da
GL		 1008}
1009
1010/**
1011 * mx3fb_blank() - blank the display.
1012 */
1013static int mx3fb_blank(int blank, struct fb_info *fbi)
1014{
1015 struct mx3fb_info *mx3_fbi = fbi->par;
1016
1017 dev_dbg(fbi->device, "%s, blank = %d, base %p, len %u\n", __func__,
1018 blank, fbi->screen_base, fbi->fix.smem_len);
1019
1020 if (mx3_fbi->blank == blank)
1021 return 0;
1022
1023 mutex_lock(&mx3_fbi->mutex);
1024 __blank(blank, fbi);
6e1588cb
GL		 1025 mutex_unlock(&mx3_fbi->mutex);
1026
1027 return 0;
86528da2
GL		 1028}
1029
1030/**
1031 * mx3fb_pan_display() - pan or wrap the display
6e1588cb
GL		 1032 * @var: variable screen buffer information.
1033 * @info: framebuffer information pointer.
86528da2
GL		 1034 *
1035 * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1036 */
1037static int mx3fb_pan_display(struct fb_var_screeninfo *var,
6e1588cb 1038 struct fb_info *fbi)
86528da2 1039{
6e1588cb
GL		 1040 struct mx3fb_info *mx3_fbi = fbi->par;
1041 u32 y_bottom;
1042 unsigned long base;
1043 off_t offset;
1044 dma_cookie_t cookie;
1045 struct scatterlist *sg = mx3_fbi->sg;
1046 struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan;
1047 struct dma_async_tx_descriptor *txd;
1048 int ret;
1049
1050 dev_dbg(fbi->device, "%s [%c]\n", __func__,
1051 list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+');
1052
1053 if (var->xoffset > 0) {
1054 dev_dbg(fbi->device, "x panning not supported\n");
1055 return -EINVAL;
1056 }
1057
1058 if (fbi->var.xoffset == var->xoffset &&
1059 fbi->var.yoffset == var->yoffset)
1060 return 0; /* No change, do nothing */
1061
1062 y_bottom = var->yoffset;
1063
1064 if (!(var->vmode & FB_VMODE_YWRAP))
1065 y_bottom += var->yres;
1066
1067 if (y_bottom > fbi->var.yres_virtual)
1068 return -EINVAL;
1069
1070 mutex_lock(&mx3_fbi->mutex);
1071
1072 offset = (var->yoffset * var->xres_virtual + var->xoffset) *
1073 (var->bits_per_pixel / 8);
1074 base = fbi->fix.smem_start + offset;
1075
1076 dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n",
1077 mx3_fbi->cur_ipu_buf, base);
1078
1079 /*
1080 * We enable the End of Frame interrupt, which will free a tx-descriptor,
1081 * which we will need for the next device_prep_slave_sg(). The
1082 * IRQ-handler will disable the IRQ again.
1083 */
1084 init_completion(&mx3_fbi->flip_cmpl);
1085 enable_irq(mx3_fbi->idmac_channel->eof_irq);
1086
1087 ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10);
1088 if (ret <= 0) {
1089 mutex_unlock(&mx3_fbi->mutex);
1090 dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ?
1091 "user interrupt" : "timeout");
d88ca815 1092 disable_irq(mx3_fbi->idmac_channel->eof_irq);
6e1588cb
GL		 1093 return ret ? : -ETIMEDOUT;
1094 }
1095
1096 mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf;
1097
1098 sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base;
1099 sg_set_page(&sg[mx3_fbi->cur_ipu_buf],
1100 virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len,
1101 offset_in_page(fbi->screen_base + offset));
1102
d88ca815
GL		 1103 if (mx3_fbi->txd)
1104 async_tx_ack(mx3_fbi->txd);
1105
6e1588cb
GL		 1106 txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg +
1107 mx3_fbi->cur_ipu_buf, 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT);
1108 if (!txd) {
1109 dev_err(fbi->device,
1110 "Error preparing a DMA transaction descriptor.\n");
1111 mutex_unlock(&mx3_fbi->mutex);
1112 return -EIO;
1113 }
1114
1115 txd->callback_param = txd;
1116 txd->callback = mx3fb_dma_done;
1117
1118 /*
1119 * Emulate original mx3fb behaviour: each new call to idmac_tx_submit()
1120 * should switch to another buffer
1121 */
1122 cookie = txd->tx_submit(txd);
1123 dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie);
1124 if (cookie < 0) {
1125 dev_err(fbi->device,
1126 "Error updating SDC buf %d to address=0x%08lX\n",
1127 mx3_fbi->cur_ipu_buf, base);
1128 mutex_unlock(&mx3_fbi->mutex);
1129 return -EIO;
1130 }
1131
6e1588cb
GL		 1132 mx3_fbi->txd = txd;
1133
1134 fbi->var.xoffset = var->xoffset;
1135 fbi->var.yoffset = var->yoffset;
1136
1137 if (var->vmode & FB_VMODE_YWRAP)
1138 fbi->var.vmode |= FB_VMODE_YWRAP;
1139 else
1140 fbi->var.vmode &= ~FB_VMODE_YWRAP;
1141
1142 mutex_unlock(&mx3_fbi->mutex);
1143
1144 dev_dbg(fbi->device, "Update complete\n");
1145
1146 return 0;
86528da2
GL		 1147}
1148
1149/*
1150 * This structure contains the pointers to the control functions that are
1151 * invoked by the core framebuffer driver to perform operations like
1152 * blitting, rectangle filling, copy regions and cursor definition.
1153 */
1154static struct fb_ops mx3fb_ops = {
6e1588cb
GL		 1155 .owner = THIS_MODULE,
1156 .fb_set_par = mx3fb_set_par,
1157 .fb_check_var = mx3fb_check_var,
1158 .fb_setcolreg = mx3fb_setcolreg,
1159 .fb_pan_display = mx3fb_pan_display,
1160 .fb_fillrect = cfb_fillrect,
1161 .fb_copyarea = cfb_copyarea,
1162 .fb_imageblit = cfb_imageblit,
1163 .fb_blank = mx3fb_blank,
86528da2
GL		 1164};
1165
1166#ifdef CONFIG_PM
1167/*
1168 * Power management hooks. Note that we won't be called from IRQ context,
1169 * unlike the blank functions above, so we may sleep.
1170 */
1171
1172/*
1173 * Suspends the framebuffer and blanks the screen. Power management support
1174 */
1175static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state)
1176{
b09de420
SH		 1177 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1178 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
86528da2 1179
ac751efa 1180 console_lock();
b09de420 1181 fb_set_suspend(mx3fb->fbi, 1);
ac751efa 1182 console_unlock();
86528da2 1183
6e1588cb
GL		 1184 if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1185 sdc_disable_channel(mx3_fbi);
1186 sdc_set_brightness(mx3fb, 0);
86528da2 1187
6e1588cb
GL		 1188 }
1189 return 0;
86528da2
GL		 1190}
1191
1192/*
1193 * Resumes the framebuffer and unblanks the screen. Power management support
1194 */
1195static int mx3fb_resume(struct platform_device *pdev)
1196{
b09de420
SH		 1197 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1198 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
86528da2 1199
6e1588cb
GL		 1200 if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1201 sdc_enable_channel(mx3_fbi);
b09de420 1202 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
6e1588cb 1203 }
86528da2 1204
ac751efa 1205 console_lock();
b09de420 1206 fb_set_suspend(mx3fb->fbi, 0);
ac751efa 1207 console_unlock();
86528da2 1208
6e1588cb 1209 return 0;
86528da2
GL		 1210}
1211#else
1212#define mx3fb_suspend NULL
1213#define mx3fb_resume NULL
1214#endif
1215
1216/*
1217 * Main framebuffer functions
1218 */
1219
1220/**
1221 * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer.
6e1588cb 1222 * @fbi: framebuffer information pointer
537a1bf0 1223 * @mem_len: length of mapped memory
20de03da 1224 * @lock: do not lock during initialisation
6e1588cb 1225 * @return: Error code indicating success or failure
86528da2
GL		 1226 *
1227 * This buffer is remapped into a non-cached, non-buffered, memory region to
1228 * allow palette and pixel writes to occur without flushing the cache. Once this
1229 * area is remapped, all virtual memory access to the video memory should occur
1230 * at the new region.
1231 */
20de03da
GL		 1232static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
1233 bool lock)
86528da2 1234{
6e1588cb
GL		 1235 int retval = 0;
1236 dma_addr_t addr;
86528da2 1237
6e1588cb 1238 fbi->screen_base = dma_alloc_writecombine(fbi->device,
537a1bf0 1239 mem_len,
6e1588cb 1240 &addr, GFP_DMA);
86528da2 1241
6e1588cb
GL		 1242 if (!fbi->screen_base) {
1243 dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n",
537a1bf0 1244 mem_len);
6e1588cb
GL		 1245 retval = -EBUSY;
1246 goto err0;
1247 }
86528da2 1248
20de03da
GL		 1249 if (lock)
1250 mutex_lock(&fbi->mm_lock);
6e1588cb 1251 fbi->fix.smem_start = addr;
537a1bf0 1252 fbi->fix.smem_len = mem_len;
20de03da
GL		 1253 if (lock)
1254 mutex_unlock(&fbi->mm_lock);
86528da2 1255
6e1588cb
GL		 1256 dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n",
1257 (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len);
86528da2 1258
6e1588cb 1259 fbi->screen_size = fbi->fix.smem_len;
86528da2 1260
6e1588cb
GL		 1261 /* Clear the screen */
1262 memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
86528da2 1263
6e1588cb 1264 return 0;
86528da2
GL		 1265
1266err0:
6e1588cb
GL		 1267 fbi->fix.smem_len = 0;
1268 fbi->fix.smem_start = 0;
1269 fbi->screen_base = NULL;
1270 return retval;
86528da2
GL		 1271}
1272
1273/**
1274 * mx3fb_unmap_video_memory() - de-allocate frame buffer memory.
6e1588cb
GL		 1275 * @fbi: framebuffer information pointer
1276 * @return: error code indicating success or failure
86528da2
GL		 1277 */
1278static int mx3fb_unmap_video_memory(struct fb_info *fbi)
1279{
6e1588cb
GL		 1280 dma_free_writecombine(fbi->device, fbi->fix.smem_len,
1281 fbi->screen_base, fbi->fix.smem_start);
86528da2 1282
6e1588cb 1283 fbi->screen_base = 0;
537a1bf0 1284 mutex_lock(&fbi->mm_lock);
6e1588cb
GL		 1285 fbi->fix.smem_start = 0;
1286 fbi->fix.smem_len = 0;
537a1bf0 1287 mutex_unlock(&fbi->mm_lock);
6e1588cb 1288 return 0;
86528da2
GL		 1289}
1290
1291/**
1292 * mx3fb_init_fbinfo() - initialize framebuffer information object.
6e1588cb 1293 * @return: initialized framebuffer structure.
86528da2
GL		 1294 */
1295static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops)
1296{
6e1588cb
GL		 1297 struct fb_info *fbi;
1298 struct mx3fb_info *mx3fbi;
1299 int ret;
86528da2 1300
6e1588cb
GL		 1301 /* Allocate sufficient memory for the fb structure */
1302 fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev);
1303 if (!fbi)
1304 return NULL;
86528da2 1305
6e1588cb
GL		 1306 mx3fbi = fbi->par;
1307 mx3fbi->cookie = -EINVAL;
1308 mx3fbi->cur_ipu_buf = 0;
86528da2 1309
6e1588cb 1310 fbi->var.activate = FB_ACTIVATE_NOW;
86528da2 1311
6e1588cb
GL		 1312 fbi->fbops = ops;
1313 fbi->flags = FBINFO_FLAG_DEFAULT;
1314 fbi->pseudo_palette = mx3fbi->pseudo_palette;
86528da2 1315
6e1588cb 1316 mutex_init(&mx3fbi->mutex);
86528da2 1317
6e1588cb
GL		 1318 /* Allocate colormap */
1319 ret = fb_alloc_cmap(&fbi->cmap, 16, 0);
1320 if (ret < 0) {
1321 framebuffer_release(fbi);
1322 return NULL;
1323 }
86528da2 1324
6e1588cb 1325 return fbi;
86528da2
GL		 1326}
1327
1328static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan)
1329{
6e1588cb
GL		 1330 struct device *dev = mx3fb->dev;
1331 struct mx3fb_platform_data *mx3fb_pdata = dev->platform_data;
1332 const char *name = mx3fb_pdata->name;
1333 unsigned int irq;
1334 struct fb_info *fbi;
1335 struct mx3fb_info *mx3fbi;
1336 const struct fb_videomode *mode;
1337 int ret, num_modes;
86528da2 1338
6e1588cb
GL		 1339 ichan->client = mx3fb;
1340 irq = ichan->eof_irq;
86528da2 1341
6e1588cb
GL		 1342 if (ichan->dma_chan.chan_id != IDMAC_SDC_0)
1343 return -EINVAL;
86528da2 1344
6e1588cb
GL		 1345 fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops);
1346 if (!fbi)
1347 return -ENOMEM;
86528da2 1348
6e1588cb
GL		 1349 if (!fb_mode)
1350 fb_mode = name;
86528da2 1351
6e1588cb
GL		 1352 if (!fb_mode) {
1353 ret = -EINVAL;
1354 goto emode;
1355 }
86528da2 1356
6e1588cb
GL		 1357 if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) {
1358 mode = mx3fb_pdata->mode;
1359 num_modes = mx3fb_pdata->num_modes;
1360 } else {
1361 mode = mx3fb_modedb;
1362 num_modes = ARRAY_SIZE(mx3fb_modedb);
1363 }
86528da2 1364
6e1588cb
GL		 1365 if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode,
1366 num_modes, NULL, default_bpp)) {
1367 ret = -EBUSY;
1368 goto emode;
1369 }
86528da2 1370
6e1588cb 1371 fb_videomode_to_modelist(mode, num_modes, &fbi->modelist);
86528da2 1372
6e1588cb
GL		 1373 /* Default Y virtual size is 2x panel size */
1374 fbi->var.yres_virtual = fbi->var.yres * 2;
86528da2 1375
6e1588cb 1376 mx3fb->fbi = fbi;
86528da2 1377
6e1588cb
GL		 1378 /* set Display Interface clock period */
1379 mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER);
1380 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
86528da2 1381
6e1588cb
GL		 1382 sdc_set_brightness(mx3fb, 255);
1383 sdc_set_global_alpha(mx3fb, true, 0xFF);
1384 sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0);
86528da2 1385
6e1588cb
GL		 1386 mx3fbi = fbi->par;
1387 mx3fbi->idmac_channel = ichan;
1388 mx3fbi->ipu_ch = ichan->dma_chan.chan_id;
1389 mx3fbi->mx3fb = mx3fb;
1390 mx3fbi->blank = FB_BLANK_NORMAL;
86528da2 1391
6e1588cb
GL		 1392 init_completion(&mx3fbi->flip_cmpl);
1393 disable_irq(ichan->eof_irq);
1394 dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq);
20de03da
GL		 1395 ret = __set_par(fbi, false);
1396 if (ret < 0)
1397 goto esetpar;
1398
1399 __blank(FB_BLANK_UNBLANK, fbi);
86528da2 1400
2eec8c31 1401 dev_info(dev, "registered, using mode %s\n", fb_mode);
86528da2 1402
6e1588cb
GL		 1403 ret = register_framebuffer(fbi);
1404 if (ret < 0)
1405 goto erfb;
86528da2 1406
6e1588cb 1407 return 0;
86528da2
GL		 1408
1409erfb:
1410esetpar:
1411emode:
6e1588cb
GL		 1412 fb_dealloc_cmap(&fbi->cmap);
1413 framebuffer_release(fbi);
86528da2 1414
6e1588cb 1415 return ret;
86528da2
GL		 1416}
1417
1418static bool chan_filter(struct dma_chan *chan, void *arg)
1419{
6e1588cb
GL		 1420 struct dma_chan_request *rq = arg;
1421 struct device *dev;
1422 struct mx3fb_platform_data *mx3fb_pdata;
86528da2 1423
1b346af2
SH		 1424 if (!imx_dma_is_ipu(chan))
1425 return false;
1426
6e1588cb
GL		 1427 if (!rq)
1428 return false;
86528da2 1429
6e1588cb
GL		 1430 dev = rq->mx3fb->dev;
1431 mx3fb_pdata = dev->platform_data;
86528da2 1432
6e1588cb
GL		 1433 return rq->id == chan->chan_id &&
1434 mx3fb_pdata->dma_dev == chan->device->dev;
86528da2
GL		 1435}
1436
1437static void release_fbi(struct fb_info *fbi)
1438{
6e1588cb 1439 mx3fb_unmap_video_memory(fbi);
86528da2 1440
6e1588cb 1441 fb_dealloc_cmap(&fbi->cmap);
86528da2 1442
6e1588cb
GL		 1443 unregister_framebuffer(fbi);
1444 framebuffer_release(fbi);
86528da2
GL		 1445}
1446
1447static int mx3fb_probe(struct platform_device *pdev)
1448{
6e1588cb
GL		 1449 struct device *dev = &pdev->dev;
1450 int ret;
1451 struct resource *sdc_reg;
1452 struct mx3fb_data *mx3fb;
1453 dma_cap_mask_t mask;
1454 struct dma_chan *chan;
1455 struct dma_chan_request rq;
1456
1457 /*
1458 * Display Interface (DI) and Synchronous Display Controller (SDC)
1459 * registers
1460 */
1461 sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1462 if (!sdc_reg)
1463 return -EINVAL;
1464
1465 mx3fb = kzalloc(sizeof(*mx3fb), GFP_KERNEL);
1466 if (!mx3fb)
1467 return -ENOMEM;
1468
1469 spin_lock_init(&mx3fb->lock);
1470
1471 mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg));
1472 if (!mx3fb->reg_base) {
1473 ret = -ENOMEM;
1474 goto eremap;
1475 }
1476
3b80ffde 1477 pr_debug("Remapped %pR at %p\n", sdc_reg, mx3fb->reg_base);
6e1588cb
GL		 1478
1479 /* IDMAC interface */
1480 dmaengine_get();
1481
1482 mx3fb->dev = dev;
1483 platform_set_drvdata(pdev, mx3fb);
1484
1485 rq.mx3fb = mx3fb;
1486
1487 dma_cap_zero(mask);
1488 dma_cap_set(DMA_SLAVE, mask);
1489 dma_cap_set(DMA_PRIVATE, mask);
1490 rq.id = IDMAC_SDC_0;
1491 chan = dma_request_channel(mask, chan_filter, &rq);
1492 if (!chan) {
1493 ret = -EBUSY;
1494 goto ersdc0;
1495 }
1496
b3cb5372
AP		 1497 mx3fb->backlight_level = 255;
1498
6e1588cb
GL		 1499 ret = init_fb_chan(mx3fb, to_idmac_chan(chan));
1500 if (ret < 0)
1501 goto eisdc0;
1502
6e1588cb 1503 return 0;
86528da2
GL		 1504
1505eisdc0:
6e1588cb 1506 dma_release_channel(chan);
86528da2 1507ersdc0:
6e1588cb
GL		 1508 dmaengine_put();
1509 iounmap(mx3fb->reg_base);
86528da2 1510eremap:
6e1588cb
GL		 1511 kfree(mx3fb);
1512 dev_err(dev, "mx3fb: failed to register fb\n");
1513 return ret;
86528da2
GL		 1514}
1515
1516static int mx3fb_remove(struct platform_device *dev)
1517{
6e1588cb
GL		 1518 struct mx3fb_data *mx3fb = platform_get_drvdata(dev);
1519 struct fb_info *fbi = mx3fb->fbi;
1520 struct mx3fb_info *mx3_fbi = fbi->par;
1521 struct dma_chan *chan;
86528da2 1522
6e1588cb
GL		 1523 chan = &mx3_fbi->idmac_channel->dma_chan;
1524 release_fbi(fbi);
86528da2 1525
6e1588cb
GL		 1526 dma_release_channel(chan);
1527 dmaengine_put();
86528da2 1528
6e1588cb
GL		 1529 iounmap(mx3fb->reg_base);
1530 kfree(mx3fb);
1531 return 0;
86528da2
GL		 1532}
1533
1534static struct platform_driver mx3fb_driver = {
6e1588cb
GL		 1535 .driver = {
1536 .name = MX3FB_NAME,
1537 },
1538 .probe = mx3fb_probe,
1539 .remove = mx3fb_remove,
1540 .suspend = mx3fb_suspend,
1541 .resume = mx3fb_resume,
86528da2
GL		 1542};
1543
1544/*
1545 * Parse user specified options (`video=mx3fb:')
1546 * example:
6e1588cb 1547 * video=mx3fb:bpp=16
86528da2 1548 */
d88ca815 1549static int __init mx3fb_setup(void)
86528da2
GL		 1550{
1551#ifndef MODULE
6e1588cb
GL		 1552 char *opt, *options = NULL;
1553
1554 if (fb_get_options("mx3fb", &options))
1555 return -ENODEV;
1556
1557 if (!options || !*options)
1558 return 0;
1559
1560 while ((opt = strsep(&options, ",")) != NULL) {
1561 if (!*opt)
1562 continue;
1563 if (!strncmp(opt, "bpp=", 4))
1564 default_bpp = simple_strtoul(opt + 4, NULL, 0);
1565 else
1566 fb_mode = opt;
1567 }
86528da2
GL		 1568#endif
1569
6e1588cb 1570 return 0;
86528da2
GL		 1571}
1572
1573static int __init mx3fb_init(void)
1574{
6e1588cb 1575 int ret = mx3fb_setup();
86528da2 1576
6e1588cb
GL		 1577 if (ret < 0)
1578 return ret;
86528da2 1579
6e1588cb
GL		 1580 ret = platform_driver_register(&mx3fb_driver);
1581 return ret;
86528da2
GL		 1582}
1583
1584static void __exit mx3fb_exit(void)
1585{
6e1588cb 1586 platform_driver_unregister(&mx3fb_driver);
86528da2
GL		 1587}
1588
1589module_init(mx3fb_init);
1590module_exit(mx3fb_exit);
1591
1592MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1593MODULE_DESCRIPTION("MX3 framebuffer driver");
1594MODULE_ALIAS("platform:" MX3FB_NAME);
1595MODULE_LICENSE("GPL v2");
Empty description
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