[linux.git] / arch / sparc / lib / copy_page.S

/* clear_page.S: UltraSparc optimized copy page.
 *
 * Copyright (C) 1996, 1998, 1999, 2000, 2004 David S. Miller ([email protected])
 * Copyright (C) 1997 Jakub Jelinek ([email protected])
 */

#include <asm/visasm.h>
#include <asm/thread_info.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/spitfire.h>
#include <asm/head.h>

	/* What we used to do was lock a TLB entry into a specific
	 * TLB slot, clear the page with interrupts disabled, then
	 * restore the original TLB entry.  This was great for
	 * disturbing the TLB as little as possible, but it meant
	 * we had to keep interrupts disabled for a long time.
	 *
	 * Now, we simply use the normal TLB loading mechanism,
	 * and this makes the cpu choose a slot all by itself.
	 * Then we do a normal TLB flush on exit.  We need only
	 * disable preemption during the clear.
	 */

#define	DCACHE_SIZE	(PAGE_SIZE * 2)

#if (PAGE_SHIFT == 13)
#define PAGE_SIZE_REM	0x80
#elif (PAGE_SHIFT == 16)
#define PAGE_SIZE_REM	0x100
#else
#error Wrong PAGE_SHIFT specified
#endif

#define TOUCH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7)	\
	fsrc2	%reg0, %f48; 	fsrc2	%reg1, %f50;		\
	fsrc2	%reg2, %f52; 	fsrc2	%reg3, %f54;		\
	fsrc2	%reg4, %f56; 	fsrc2	%reg5, %f58;		\
	fsrc2	%reg6, %f60; 	fsrc2	%reg7, %f62;

	.text

	.align		32
	.globl		copy_user_page
	.type		copy_user_page,#function
copy_user_page:		/* %o0=dest, %o1=src, %o2=vaddr */
	lduw		[%g6 + TI_PRE_COUNT], %o4
	sethi		%hi(PAGE_OFFSET), %g2
	sethi		%hi(PAGE_SIZE), %o3

	ldx		[%g2 + %lo(PAGE_OFFSET)], %g2
	sethi		%hi(PAGE_KERNEL_LOCKED), %g3

	ldx		[%g3 + %lo(PAGE_KERNEL_LOCKED)], %g3
	sub		%o0, %g2, %g1		! dest paddr

	sub		%o1, %g2, %g2		! src paddr

	and		%o2, %o3, %o0		! vaddr D-cache alias bit
	or		%g1, %g3, %g1		! dest TTE data

	or		%g2, %g3, %g2		! src TTE data
	sethi		%hi(TLBTEMP_BASE), %o3

	sethi		%hi(DCACHE_SIZE), %o1
	add		%o0, %o3, %o0		! dest TTE vaddr

	add		%o4, 1, %o2
	add		%o0, %o1, %o1		! src TTE vaddr

	/* Disable preemption.  */
	mov		TLB_TAG_ACCESS, %g3
	stw		%o2, [%g6 + TI_PRE_COUNT]

	/* Load TLB entries.  */
	rdpr		%pstate, %o2
	wrpr		%o2, PSTATE_IE, %pstate
	stxa		%o0, [%g3] ASI_DMMU
	stxa		%g1, [%g0] ASI_DTLB_DATA_IN
	membar		#Sync
	stxa		%o1, [%g3] ASI_DMMU
	stxa		%g2, [%g0] ASI_DTLB_DATA_IN
	membar		#Sync
	wrpr		%o2, 0x0, %pstate

cheetah_copy_page_insn:
	ba,pt		%xcc, 9f
	 nop

1:
	VISEntryHalf
	membar		#StoreLoad | #StoreStore | #LoadStore
	sethi		%hi((PAGE_SIZE/64)-2), %o2
	mov		%o0, %g1
	prefetch	[%o1 + 0x000], #one_read
	or		%o2, %lo((PAGE_SIZE/64)-2), %o2
	prefetch	[%o1 + 0x040], #one_read
	prefetch	[%o1 + 0x080], #one_read
	prefetch	[%o1 + 0x0c0], #one_read
	ldd		[%o1 + 0x000], %f0
	prefetch	[%o1 + 0x100], #one_read
	ldd		[%o1 + 0x008], %f2
	prefetch	[%o1 + 0x140], #one_read
	ldd		[%o1 + 0x010], %f4
	prefetch	[%o1 + 0x180], #one_read
	fsrc2		%f0, %f16
	ldd		[%o1 + 0x018], %f6
	fsrc2		%f2, %f18
	ldd		[%o1 + 0x020], %f8
	fsrc2		%f4, %f20
	ldd		[%o1 + 0x028], %f10
	fsrc2		%f6, %f22
	ldd		[%o1 + 0x030], %f12
	fsrc2		%f8, %f24
	ldd		[%o1 + 0x038], %f14
	fsrc2		%f10, %f26
	ldd		[%o1 + 0x040], %f0
1:	ldd		[%o1 + 0x048], %f2
	fsrc2		%f12, %f28
	ldd		[%o1 + 0x050], %f4
	fsrc2		%f14, %f30
	stda		%f16, [%o0] ASI_BLK_P
	ldd		[%o1 + 0x058], %f6
	fsrc2		%f0, %f16
	ldd		[%o1 + 0x060], %f8
	fsrc2		%f2, %f18
	ldd		[%o1 + 0x068], %f10
	fsrc2		%f4, %f20
	ldd		[%o1 + 0x070], %f12
	fsrc2		%f6, %f22
	ldd		[%o1 + 0x078], %f14
	fsrc2		%f8, %f24
	ldd		[%o1 + 0x080], %f0
	prefetch	[%o1 + 0x180], #one_read
	fsrc2		%f10, %f26
	subcc		%o2, 1, %o2
	add		%o0, 0x40, %o0
	bne,pt		%xcc, 1b
	 add		%o1, 0x40, %o1

	ldd		[%o1 + 0x048], %f2
	fsrc2		%f12, %f28
	ldd		[%o1 + 0x050], %f4
	fsrc2		%f14, %f30
	stda		%f16, [%o0] ASI_BLK_P
	ldd		[%o1 + 0x058], %f6
	fsrc2		%f0, %f16
	ldd		[%o1 + 0x060], %f8
	fsrc2		%f2, %f18
	ldd		[%o1 + 0x068], %f10
	fsrc2		%f4, %f20
	ldd		[%o1 + 0x070], %f12
	fsrc2		%f6, %f22
	add		%o0, 0x40, %o0
	ldd		[%o1 + 0x078], %f14
	fsrc2		%f8, %f24
	fsrc2		%f10, %f26
	fsrc2		%f12, %f28
	fsrc2		%f14, %f30
	stda		%f16, [%o0] ASI_BLK_P
	membar		#Sync
	VISExitHalf
	ba,pt		%xcc, 5f
	 nop

9:
	VISEntry
	ldub		[%g6 + TI_FAULT_CODE], %g3
	mov		%o0, %g1
	cmp		%g3, 0
	rd		%asi, %g3
	be,a,pt		%icc, 1f
	 wr		%g0, ASI_BLK_P, %asi
	wr		%g0, ASI_BLK_COMMIT_P, %asi
1:	ldda		[%o1] ASI_BLK_P, %f0
	add		%o1, 0x40, %o1
	ldda		[%o1] ASI_BLK_P, %f16
	add		%o1, 0x40, %o1
	sethi		%hi(PAGE_SIZE), %o2
1:	TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
	ldda		[%o1] ASI_BLK_P, %f32
	stda		%f48, [%o0] %asi
	add		%o1, 0x40, %o1
	sub		%o2, 0x40, %o2
	add		%o0, 0x40, %o0
	TOUCH(f16, f18, f20, f22, f24, f26, f28, f30)
	ldda		[%o1] ASI_BLK_P, %f0
	stda		%f48, [%o0] %asi
	add		%o1, 0x40, %o1
	sub		%o2, 0x40, %o2
	add		%o0, 0x40, %o0
	TOUCH(f32, f34, f36, f38, f40, f42, f44, f46)
	ldda		[%o1] ASI_BLK_P, %f16
	stda		%f48, [%o0] %asi
	sub		%o2, 0x40, %o2
	add		%o1, 0x40, %o1
	cmp		%o2, PAGE_SIZE_REM
	bne,pt		%xcc, 1b
	 add		%o0, 0x40, %o0
#if (PAGE_SHIFT == 16)
	TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
	ldda		[%o1] ASI_BLK_P, %f32
	stda		%f48, [%o0] %asi
	add		%o1, 0x40, %o1
	sub		%o2, 0x40, %o2
	add		%o0, 0x40, %o0
	TOUCH(f16, f18, f20, f22, f24, f26, f28, f30)
	ldda		[%o1] ASI_BLK_P, %f0
	stda		%f48, [%o0] %asi
	add		%o1, 0x40, %o1
	sub		%o2, 0x40, %o2
	add		%o0, 0x40, %o0
	membar		#Sync
	stda		%f32, [%o0] %asi
	add		%o0, 0x40, %o0
	stda		%f0, [%o0] %asi
#else
	membar		#Sync
	stda		%f0, [%o0] %asi
	add		%o0, 0x40, %o0
	stda		%f16, [%o0] %asi
#endif
	membar		#Sync
	wr		%g3, 0x0, %asi
	VISExit

5:
	stxa		%g0, [%g1] ASI_DMMU_DEMAP
	membar		#Sync

	sethi		%hi(DCACHE_SIZE), %g2
	stxa		%g0, [%g1 + %g2] ASI_DMMU_DEMAP
	membar		#Sync

	retl
	 stw		%o4, [%g6 + TI_PRE_COUNT]

	.size		copy_user_page, .-copy_user_page

	.globl		cheetah_patch_copy_page
cheetah_patch_copy_page:
	sethi		%hi(0x01000000), %o1	! NOP
	sethi		%hi(cheetah_copy_page_insn), %o0
	or		%o0, %lo(cheetah_copy_page_insn), %o0
	stw		%o1, [%o0]
	membar		#StoreStore
	flush		%o0
	retl
	 nop
Commit	Line	Data
1da177e4 LT	1	/* clear_page.S: UltraSparc optimized copy page.
	2	*
	3	* Copyright (C) 1996, 1998, 1999, 2000, 2004 David S. Miller ([email protected])
	4	* Copyright (C) 1997 Jakub Jelinek ([email protected])
	5	*/
	6
	7	#include <asm/visasm.h>
	8	#include <asm/thread_info.h>
	9	#include <asm/page.h>
	10	#include <asm/pgtable.h>
	11	#include <asm/spitfire.h>
	12	#include <asm/head.h>
	13
	14	/* What we used to do was lock a TLB entry into a specific
	15	* TLB slot, clear the page with interrupts disabled, then
	16	* restore the original TLB entry. This was great for
	17	* disturbing the TLB as little as possible, but it meant
	18	* we had to keep interrupts disabled for a long time.
	19	*
	20	* Now, we simply use the normal TLB loading mechanism,
	21	* and this makes the cpu choose a slot all by itself.
	22	* Then we do a normal TLB flush on exit. We need only
	23	* disable preemption during the clear.
	24	*/
	25
1da177e4 LT	26	#define DCACHE_SIZE (PAGE_SIZE * 2)
1da177e4 LT	27
f7fe9334	28	#if (PAGE_SHIFT == 13)
1da177e4	29	#define PAGE_SIZE_REM 0x80
f7fe9334	30	#elif (PAGE_SHIFT == 16)
1da177e4 LT	31	#define PAGE_SIZE_REM 0x100
	32	#else
	33	#error Wrong PAGE_SHIFT specified
	34	#endif
	35
	36	#define TOUCH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7) \
6f1d827f DM	37	fsrc2 %reg0, %f48; fsrc2 %reg1, %f50; \
	38	fsrc2 %reg2, %f52; fsrc2 %reg3, %f54; \
	39	fsrc2 %reg4, %f56; fsrc2 %reg5, %f58; \
	40	fsrc2 %reg6, %f60; fsrc2 %reg7, %f62;
1da177e4 LT	41
	42	.text
	43
	44	.align 32
	45	.globl copy_user_page
	46	.type copy_user_page,#function
	47	copy_user_page: /* %o0=dest, %o1=src, %o2=vaddr */
	48	lduw [%g6 + TI_PRE_COUNT], %o4
b2d43834	49	sethi %hi(PAGE_OFFSET), %g2
1da177e4 LT	50	sethi %hi(PAGE_SIZE), %o3
1da177e4 LT	51
b2d43834	52	ldx [%g2 + %lo(PAGE_OFFSET)], %g2
c4bce90e	53	sethi %hi(PAGE_KERNEL_LOCKED), %g3
1da177e4	54
c4bce90e	55	ldx [%g3 + %lo(PAGE_KERNEL_LOCKED)], %g3
1da177e4 LT	56	sub %o0, %g2, %g1 ! dest paddr
	57
	58	sub %o1, %g2, %g2 ! src paddr
1da177e4 LT	59
	60	and %o2, %o3, %o0 ! vaddr D-cache alias bit
	61	or %g1, %g3, %g1 ! dest TTE data
	62
	63	or %g2, %g3, %g2 ! src TTE data
	64	sethi %hi(TLBTEMP_BASE), %o3
	65
	66	sethi %hi(DCACHE_SIZE), %o1
	67	add %o0, %o3, %o0 ! dest TTE vaddr
	68
	69	add %o4, 1, %o2
	70	add %o0, %o1, %o1 ! src TTE vaddr
	71
	72	/* Disable preemption. */
	73	mov TLB_TAG_ACCESS, %g3
	74	stw %o2, [%g6 + TI_PRE_COUNT]
	75
	76	/* Load TLB entries. */
	77	rdpr %pstate, %o2
	78	wrpr %o2, PSTATE_IE, %pstate
	79	stxa %o0, [%g3] ASI_DMMU
	80	stxa %g1, [%g0] ASI_DTLB_DATA_IN
	81	membar #Sync
	82	stxa %o1, [%g3] ASI_DMMU
	83	stxa %g2, [%g0] ASI_DTLB_DATA_IN
	84	membar #Sync
	85	wrpr %o2, 0x0, %pstate
	86
dbd2fdf5	87	cheetah_copy_page_insn:
1da177e4 LT	88	ba,pt %xcc, 9f
	89	nop
	90
	91	1:
	92	VISEntryHalf
	93	membar #StoreLoad \| #StoreStore \| #LoadStore
	94	sethi %hi((PAGE_SIZE/64)-2), %o2
	95	mov %o0, %g1
	96	prefetch [%o1 + 0x000], #one_read
	97	or %o2, %lo((PAGE_SIZE/64)-2), %o2
	98	prefetch [%o1 + 0x040], #one_read
	99	prefetch [%o1 + 0x080], #one_read
	100	prefetch [%o1 + 0x0c0], #one_read
	101	ldd [%o1 + 0x000], %f0
	102	prefetch [%o1 + 0x100], #one_read
	103	ldd [%o1 + 0x008], %f2
	104	prefetch [%o1 + 0x140], #one_read
	105	ldd [%o1 + 0x010], %f4
	106	prefetch [%o1 + 0x180], #one_read
6f1d827f	107	fsrc2 %f0, %f16
1da177e4	108	ldd [%o1 + 0x018], %f6
6f1d827f	109	fsrc2 %f2, %f18
1da177e4	110	ldd [%o1 + 0x020], %f8
6f1d827f	111	fsrc2 %f4, %f20
1da177e4	112	ldd [%o1 + 0x028], %f10
6f1d827f	113	fsrc2 %f6, %f22
1da177e4	114	ldd [%o1 + 0x030], %f12
6f1d827f	115	fsrc2 %f8, %f24
1da177e4	116	ldd [%o1 + 0x038], %f14
6f1d827f	117	fsrc2 %f10, %f26
1da177e4 LT	118	ldd [%o1 + 0x040], %f0
1da177e4 LT	119	1: ldd [%o1 + 0x048], %f2
6f1d827f	120	fsrc2 %f12, %f28
1da177e4	121	ldd [%o1 + 0x050], %f4
6f1d827f	122	fsrc2 %f14, %f30
1da177e4 LT	123	stda %f16, [%o0] ASI_BLK_P
1da177e4 LT	124	ldd [%o1 + 0x058], %f6
6f1d827f	125	fsrc2 %f0, %f16
1da177e4	126	ldd [%o1 + 0x060], %f8
6f1d827f	127	fsrc2 %f2, %f18
1da177e4	128	ldd [%o1 + 0x068], %f10
6f1d827f	129	fsrc2 %f4, %f20
1da177e4	130	ldd [%o1 + 0x070], %f12
6f1d827f	131	fsrc2 %f6, %f22
1da177e4	132	ldd [%o1 + 0x078], %f14
6f1d827f	133	fsrc2 %f8, %f24
1da177e4 LT	134	ldd [%o1 + 0x080], %f0
1da177e4 LT	135	prefetch [%o1 + 0x180], #one_read
6f1d827f	136	fsrc2 %f10, %f26
1da177e4 LT	137	subcc %o2, 1, %o2
	138	add %o0, 0x40, %o0
	139	bne,pt %xcc, 1b
	140	add %o1, 0x40, %o1
	141
	142	ldd [%o1 + 0x048], %f2
6f1d827f	143	fsrc2 %f12, %f28
1da177e4	144	ldd [%o1 + 0x050], %f4
6f1d827f	145	fsrc2 %f14, %f30
1da177e4 LT	146	stda %f16, [%o0] ASI_BLK_P
1da177e4 LT	147	ldd [%o1 + 0x058], %f6
6f1d827f	148	fsrc2 %f0, %f16
1da177e4	149	ldd [%o1 + 0x060], %f8
6f1d827f	150	fsrc2 %f2, %f18
1da177e4	151	ldd [%o1 + 0x068], %f10
6f1d827f	152	fsrc2 %f4, %f20
1da177e4	153	ldd [%o1 + 0x070], %f12
6f1d827f	154	fsrc2 %f6, %f22
1da177e4 LT	155	add %o0, 0x40, %o0
1da177e4 LT	156	ldd [%o1 + 0x078], %f14
6f1d827f DM	157	fsrc2 %f8, %f24
	158	fsrc2 %f10, %f26
	159	fsrc2 %f12, %f28
	160	fsrc2 %f14, %f30
1da177e4 LT	161	stda %f16, [%o0] ASI_BLK_P
	162	membar #Sync
	163	VISExitHalf
	164	ba,pt %xcc, 5f
	165	nop
	166
	167	9:
	168	VISEntry
	169	ldub [%g6 + TI_FAULT_CODE], %g3
	170	mov %o0, %g1
	171	cmp %g3, 0
	172	rd %asi, %g3
	173	be,a,pt %icc, 1f
	174	wr %g0, ASI_BLK_P, %asi
	175	wr %g0, ASI_BLK_COMMIT_P, %asi
	176	1: ldda [%o1] ASI_BLK_P, %f0
	177	add %o1, 0x40, %o1
	178	ldda [%o1] ASI_BLK_P, %f16
	179	add %o1, 0x40, %o1
	180	sethi %hi(PAGE_SIZE), %o2
	181	1: TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
	182	ldda [%o1] ASI_BLK_P, %f32
	183	stda %f48, [%o0] %asi
	184	add %o1, 0x40, %o1
	185	sub %o2, 0x40, %o2
	186	add %o0, 0x40, %o0
	187	TOUCH(f16, f18, f20, f22, f24, f26, f28, f30)
	188	ldda [%o1] ASI_BLK_P, %f0
	189	stda %f48, [%o0] %asi
	190	add %o1, 0x40, %o1
	191	sub %o2, 0x40, %o2
	192	add %o0, 0x40, %o0
	193	TOUCH(f32, f34, f36, f38, f40, f42, f44, f46)
	194	ldda [%o1] ASI_BLK_P, %f16
	195	stda %f48, [%o0] %asi
	196	sub %o2, 0x40, %o2
	197	add %o1, 0x40, %o1
	198	cmp %o2, PAGE_SIZE_REM
	199	bne,pt %xcc, 1b
	200	add %o0, 0x40, %o0
f7fe9334	201	#if (PAGE_SHIFT == 16)
1da177e4 LT	202	TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
	203	ldda [%o1] ASI_BLK_P, %f32
	204	stda %f48, [%o0] %asi
	205	add %o1, 0x40, %o1
	206	sub %o2, 0x40, %o2
	207	add %o0, 0x40, %o0
	208	TOUCH(f16, f18, f20, f22, f24, f26, f28, f30)
	209	ldda [%o1] ASI_BLK_P, %f0
	210	stda %f48, [%o0] %asi
	211	add %o1, 0x40, %o1
	212	sub %o2, 0x40, %o2
	213	add %o0, 0x40, %o0
	214	membar #Sync
	215	stda %f32, [%o0] %asi
	216	add %o0, 0x40, %o0
	217	stda %f0, [%o0] %asi
	218	#else
	219	membar #Sync
	220	stda %f0, [%o0] %asi
	221	add %o0, 0x40, %o0
	222	stda %f16, [%o0] %asi
	223	#endif
	224	membar #Sync
	225	wr %g3, 0x0, %asi
	226	VISExit
	227
	228	5:
	229	stxa %g0, [%g1] ASI_DMMU_DEMAP
	230	membar #Sync
	231
	232	sethi %hi(DCACHE_SIZE), %g2
	233	stxa %g0, [%g1 + %g2] ASI_DMMU_DEMAP
	234	membar #Sync
	235
	236	retl
	237	stw %o4, [%g6 + TI_PRE_COUNT]
	238
	239	.size copy_user_page, .-copy_user_page
dbd2fdf5 DM	240
	241	.globl cheetah_patch_copy_page
	242	cheetah_patch_copy_page:
	243	sethi %hi(0x01000000), %o1 ! NOP
	244	sethi %hi(cheetah_copy_page_insn), %o0
	245	or %o0, %lo(cheetah_copy_page_insn), %o0
	246	stw %o1, [%o0]
	247	membar #StoreStore
	248	flush %o0
	249	retl
	250	nop