[linux.git] / drivers / gpio / gpio-f7188x.c

/*
 * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866
 *
 * Copyright (C) 2010-2013 LaCie
 *
 * Author: Simon Guinot <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio/driver.h>
#include <linux/bitops.h>

#define DRVNAME "gpio-f7188x"

/*
 * Super-I/O registers
 */
#define SIO_LDSEL		0x07	/* Logical device select */
#define SIO_DEVID		0x20	/* Device ID (2 bytes) */
#define SIO_DEVREV		0x22	/* Device revision */
#define SIO_MANID		0x23	/* Fintek ID (2 bytes) */

#define SIO_LD_GPIO		0x06	/* GPIO logical device */
#define SIO_UNLOCK_KEY		0x87	/* Key to enable Super-I/O */
#define SIO_LOCK_KEY		0xAA	/* Key to disable Super-I/O */

#define SIO_FINTEK_ID		0x1934	/* Manufacturer ID */
#define SIO_F71869_ID		0x0814	/* F71869 chipset ID */
#define SIO_F71869A_ID		0x1007	/* F71869A chipset ID */
#define SIO_F71882_ID		0x0541	/* F71882 chipset ID */
#define SIO_F71889_ID		0x0909	/* F71889 chipset ID */
#define SIO_F81866_ID		0x1010	/* F81866 chipset ID */

enum chips { f71869, f71869a, f71882fg, f71889f, f81866 };

static const char * const f7188x_names[] = {
	"f71869",
	"f71869a",
	"f71882fg",
	"f71889f",
	"f81866",
};

struct f7188x_sio {
	int addr;
	enum chips type;
};

struct f7188x_gpio_bank {
	struct gpio_chip chip;
	unsigned int regbase;
	struct f7188x_gpio_data *data;
};

struct f7188x_gpio_data {
	struct f7188x_sio *sio;
	int nr_bank;
	struct f7188x_gpio_bank *bank;
};

/*
 * Super-I/O functions.
 */

static inline int superio_inb(int base, int reg)
{
	outb(reg, base);
	return inb(base + 1);
}

static int superio_inw(int base, int reg)
{
	int val;

	outb(reg++, base);
	val = inb(base + 1) << 8;
	outb(reg, base);
	val |= inb(base + 1);

	return val;
}

static inline void superio_outb(int base, int reg, int val)
{
	outb(reg, base);
	outb(val, base + 1);
}

static inline int superio_enter(int base)
{
	/* Don't step on other drivers' I/O space by accident. */
	if (!request_muxed_region(base, 2, DRVNAME)) {
		pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
		return -EBUSY;
	}

	/* According to the datasheet the key must be send twice. */
	outb(SIO_UNLOCK_KEY, base);
	outb(SIO_UNLOCK_KEY, base);

	return 0;
}

static inline void superio_select(int base, int ld)
{
	outb(SIO_LDSEL, base);
	outb(ld, base + 1);
}

static inline void superio_exit(int base)
{
	outb(SIO_LOCK_KEY, base);
	release_region(base, 2);
}

/*
 * GPIO chip.
 */

static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
static int f7188x_gpio_direction_out(struct gpio_chip *chip,
				     unsigned offset, int value);
static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
static int f7188x_gpio_set_single_ended(struct gpio_chip *gc,
					unsigned offset,
					enum single_ended_mode mode);

#define F7188X_GPIO_BANK(_base, _ngpio, _regbase)			\
	{								\
		.chip = {						\
			.label            = DRVNAME,			\
			.owner            = THIS_MODULE,		\
			.direction_input  = f7188x_gpio_direction_in,	\
			.get              = f7188x_gpio_get,		\
			.direction_output = f7188x_gpio_direction_out,	\
			.set              = f7188x_gpio_set,		\
			.set_single_ended = f7188x_gpio_set_single_ended, \
			.base             = _base,			\
			.ngpio            = _ngpio,			\
			.can_sleep        = true,			\
		},							\
		.regbase = _regbase,					\
	}

#define gpio_dir(base) (base + 0)
#define gpio_data_out(base) (base + 1)
#define gpio_data_in(base) (base + 2)
/* Output mode register (0:open drain 1:push-pull). */
#define gpio_out_mode(base) (base + 3)

static struct f7188x_gpio_bank f71869_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 6, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 5, 0xA0),
	F7188X_GPIO_BANK(60, 6, 0x90),
};

static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 6, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 5, 0xA0),
	F7188X_GPIO_BANK(60, 8, 0x90),
	F7188X_GPIO_BANK(70, 8, 0x80),
};

static struct f7188x_gpio_bank f71882_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 8, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 4, 0xC0),
	F7188X_GPIO_BANK(40, 4, 0xB0),
};

static struct f7188x_gpio_bank f71889_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 7, 0xF0),
	F7188X_GPIO_BANK(10, 7, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 5, 0xA0),
	F7188X_GPIO_BANK(60, 8, 0x90),
	F7188X_GPIO_BANK(70, 8, 0x80),
};

static struct f7188x_gpio_bank f81866_gpio_bank[] = {
	F7188X_GPIO_BANK(0, 8, 0xF0),
	F7188X_GPIO_BANK(10, 8, 0xE0),
	F7188X_GPIO_BANK(20, 8, 0xD0),
	F7188X_GPIO_BANK(30, 8, 0xC0),
	F7188X_GPIO_BANK(40, 8, 0xB0),
	F7188X_GPIO_BANK(50, 8, 0xA0),
	F7188X_GPIO_BANK(60, 8, 0x90),
	F7188X_GPIO_BANK(70, 8, 0x80),
	F7188X_GPIO_BANK(80, 8, 0x88),
};

static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	dir &= ~BIT(offset);
	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);

	superio_exit(sio->addr);

	return 0;
}

static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir, data;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	dir = !!(dir & BIT(offset));
	if (dir)
		data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	else
		data = superio_inb(sio->addr, gpio_data_in(bank->regbase));

	superio_exit(sio->addr);

	return !!(data & BIT(offset));
}

static int f7188x_gpio_direction_out(struct gpio_chip *chip,
				     unsigned offset, int value)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 dir, data_out;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	if (value)
		data_out |= BIT(offset);
	else
		data_out &= ~BIT(offset);
	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);

	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
	dir |= BIT(offset);
	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);

	superio_exit(sio->addr);

	return 0;
}

static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 data_out;

	err = superio_enter(sio->addr);
	if (err)
		return;
	superio_select(sio->addr, SIO_LD_GPIO);

	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	if (value)
		data_out |= BIT(offset);
	else
		data_out &= ~BIT(offset);
	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);

	superio_exit(sio->addr);
}

static int f7188x_gpio_set_single_ended(struct gpio_chip *chip,
					unsigned offset,
					enum single_ended_mode mode)
{
	int err;
	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	struct f7188x_sio *sio = bank->data->sio;
	u8 data;

	if (mode != LINE_MODE_OPEN_DRAIN &&
	    mode != LINE_MODE_PUSH_PULL)
		return -ENOTSUPP;

	err = superio_enter(sio->addr);
	if (err)
		return err;
	superio_select(sio->addr, SIO_LD_GPIO);

	data = superio_inb(sio->addr, gpio_out_mode(bank->regbase));
	if (mode == LINE_MODE_OPEN_DRAIN)
		data &= ~BIT(offset);
	else
		data |= BIT(offset);
	superio_outb(sio->addr, gpio_out_mode(bank->regbase), data);

	superio_exit(sio->addr);
	return 0;
}

/*
 * Platform device and driver.
 */

static int f7188x_gpio_probe(struct platform_device *pdev)
{
	int err;
	int i;
	struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
	struct f7188x_gpio_data *data;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	switch (sio->type) {
	case f71869:
		data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
		data->bank = f71869_gpio_bank;
		break;
	case f71869a:
		data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
		data->bank = f71869a_gpio_bank;
		break;
	case f71882fg:
		data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
		data->bank = f71882_gpio_bank;
		break;
	case f71889f:
		data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
		data->bank = f71889_gpio_bank;
		break;
	case f81866:
		data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
		data->bank = f81866_gpio_bank;
		break;
	default:
		return -ENODEV;
	}
	data->sio = sio;

	platform_set_drvdata(pdev, data);

	/* For each GPIO bank, register a GPIO chip. */
	for (i = 0; i < data->nr_bank; i++) {
		struct f7188x_gpio_bank *bank = &data->bank[i];

		bank->chip.parent = &pdev->dev;
		bank->data = data;

		err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
		if (err) {
			dev_err(&pdev->dev,
				"Failed to register gpiochip %d: %d\n",
				i, err);
			return err;
		}
	}

	return 0;
}

static int __init f7188x_find(int addr, struct f7188x_sio *sio)
{
	int err;
	u16 devid;

	err = superio_enter(addr);
	if (err)
		return err;

	err = -ENODEV;
	devid = superio_inw(addr, SIO_MANID);
	if (devid != SIO_FINTEK_ID) {
		pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
		goto err;
	}

	devid = superio_inw(addr, SIO_DEVID);
	switch (devid) {
	case SIO_F71869_ID:
		sio->type = f71869;
		break;
	case SIO_F71869A_ID:
		sio->type = f71869a;
		break;
	case SIO_F71882_ID:
		sio->type = f71882fg;
		break;
	case SIO_F71889_ID:
		sio->type = f71889f;
		break;
	case SIO_F81866_ID:
		sio->type = f81866;
		break;
	default:
		pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
		goto err;
	}
	sio->addr = addr;
	err = 0;

	pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
		f7188x_names[sio->type],
		(unsigned int) addr,
		(int) superio_inb(addr, SIO_DEVREV));

err:
	superio_exit(addr);
	return err;
}

static struct platform_device *f7188x_gpio_pdev;

static int __init
f7188x_gpio_device_add(const struct f7188x_sio *sio)
{
	int err;

	f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
	if (!f7188x_gpio_pdev)
		return -ENOMEM;

	err = platform_device_add_data(f7188x_gpio_pdev,
				       sio, sizeof(*sio));
	if (err) {
		pr_err(DRVNAME "Platform data allocation failed\n");
		goto err;
	}

	err = platform_device_add(f7188x_gpio_pdev);
	if (err) {
		pr_err(DRVNAME "Device addition failed\n");
		goto err;
	}

	return 0;

err:
	platform_device_put(f7188x_gpio_pdev);

	return err;
}

/*
 * Try to match a supported Fintek device by reading the (hard-wired)
 * configuration I/O ports. If available, then register both the platform
 * device and driver to support the GPIOs.
 */

static struct platform_driver f7188x_gpio_driver = {
	.driver = {
		.name	= DRVNAME,
	},
	.probe		= f7188x_gpio_probe,
};

static int __init f7188x_gpio_init(void)
{
	int err;
	struct f7188x_sio sio;

	if (f7188x_find(0x2e, &sio) &&
	    f7188x_find(0x4e, &sio))
		return -ENODEV;

	err = platform_driver_register(&f7188x_gpio_driver);
	if (!err) {
		err = f7188x_gpio_device_add(&sio);
		if (err)
			platform_driver_unregister(&f7188x_gpio_driver);
	}

	return err;
}
subsys_initcall(f7188x_gpio_init);

static void __exit f7188x_gpio_exit(void)
{
	platform_device_unregister(f7188x_gpio_pdev);
	platform_driver_unregister(&f7188x_gpio_driver);
}
module_exit(f7188x_gpio_exit);

MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889F and F81866");
MODULE_AUTHOR("Simon Guinot <[email protected]>");
MODULE_LICENSE("GPL");
Commit	Line	Data
6c17aa01	1	/*
1920906f	2	* GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866
6c17aa01 SG	3	*
	4	* Copyright (C) 2010-2013 LaCie
	5	*
	6	* Author: Simon Guinot <[email protected]>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#include <linux/module.h>
	15	#include <linux/init.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/io.h>
148c8642 LW	18	#include <linux/gpio/driver.h>
148c8642 LW	19	#include <linux/bitops.h>
6c17aa01 SG	20
	21	#define DRVNAME "gpio-f7188x"
	22
	23	/*
	24	* Super-I/O registers
	25	*/
	26	#define SIO_LDSEL 0x07 /* Logical device select */
	27	#define SIO_DEVID 0x20 /* Device ID (2 bytes) */
	28	#define SIO_DEVREV 0x22 /* Device revision */
	29	#define SIO_MANID 0x23 /* Fintek ID (2 bytes) */
	30
	31	#define SIO_LD_GPIO 0x06 /* GPIO logical device */
	32	#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
	33	#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
	34
	35	#define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
24ccef35	36	#define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
7e960363	37	#define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
6c17aa01 SG	38	#define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
6c17aa01 SG	39	#define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
1920906f	40	#define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
6c17aa01	41
1920906f	42	enum chips { f71869, f71869a, f71882fg, f71889f, f81866 };
6c17aa01 SG	43
6c17aa01 SG	44	static const char * const f7188x_names[] = {
24ccef35	45	"f71869",
7e960363	46	"f71869a",
6c17aa01 SG	47	"f71882fg",
6c17aa01 SG	48	"f71889f",
1920906f	49	"f81866",
6c17aa01 SG	50	};
	51
	52	struct f7188x_sio {
	53	int addr;
	54	enum chips type;
	55	};
	56
	57	struct f7188x_gpio_bank {
	58	struct gpio_chip chip;
	59	unsigned int regbase;
	60	struct f7188x_gpio_data *data;
	61	};
	62
	63	struct f7188x_gpio_data {
	64	struct f7188x_sio *sio;
	65	int nr_bank;
	66	struct f7188x_gpio_bank *bank;
	67	};
	68
	69	/*
	70	* Super-I/O functions.
	71	*/
	72
	73	static inline int superio_inb(int base, int reg)
	74	{
	75	outb(reg, base);
	76	return inb(base + 1);
	77	}
	78
	79	static int superio_inw(int base, int reg)
	80	{
	81	int val;
	82
	83	outb(reg++, base);
	84	val = inb(base + 1) << 8;
	85	outb(reg, base);
	86	val \|= inb(base + 1);
	87
	88	return val;
	89	}
	90
	91	static inline void superio_outb(int base, int reg, int val)
	92	{
	93	outb(reg, base);
	94	outb(val, base + 1);
	95	}
	96
	97	static inline int superio_enter(int base)
	98	{
	99	/* Don't step on other drivers' I/O space by accident. */
	100	if (!request_muxed_region(base, 2, DRVNAME)) {
	101	pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
	102	return -EBUSY;
	103	}
	104
	105	/* According to the datasheet the key must be send twice. */
	106	outb(SIO_UNLOCK_KEY, base);
	107	outb(SIO_UNLOCK_KEY, base);
	108
	109	return 0;
	110	}
	111
	112	static inline void superio_select(int base, int ld)
	113	{
114	outb(SIO_LDSEL, base);
115	outb(ld, base + 1);
116	}
117
118	static inline void superio_exit(int base)
119	{
120	outb(SIO_LOCK_KEY, base);
121	release_region(base, 2);
122	}
123
124	/*
125	* GPIO chip.
126	*/
127
128	static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
129	static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
130	static int f7188x_gpio_direction_out(struct gpio_chip *chip,
131	unsigned offset, int value);
132	static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
f90c6bdb LW	133	static int f7188x_gpio_set_single_ended(struct gpio_chip *gc,
	134	unsigned offset,
	135	enum single_ended_mode mode);
6c17aa01 SG	136
	137	#define F7188X_GPIO_BANK(_base, _ngpio, _regbase) \
	138	{ \
	139	.chip = { \
	140	.label = DRVNAME, \
	141	.owner = THIS_MODULE, \
	142	.direction_input = f7188x_gpio_direction_in, \
	143	.get = f7188x_gpio_get, \
	144	.direction_output = f7188x_gpio_direction_out, \
	145	.set = f7188x_gpio_set, \
f90c6bdb	146	.set_single_ended = f7188x_gpio_set_single_ended, \
6c17aa01 SG	147	.base = _base, \
6c17aa01 SG	148	.ngpio = _ngpio, \
aeccc1b4	149	.can_sleep = true, \
6c17aa01 SG	150	}, \
	151	.regbase = _regbase, \
	152	}
	153
	154	#define gpio_dir(base) (base + 0)
	155	#define gpio_data_out(base) (base + 1)
	156	#define gpio_data_in(base) (base + 2)
	157	/* Output mode register (0:open drain 1:push-pull). */
	158	#define gpio_out_mode(base) (base + 3)
	159
24ccef35 AB	160	static struct f7188x_gpio_bank f71869_gpio_bank[] = {
	161	F7188X_GPIO_BANK(0, 6, 0xF0),
	162	F7188X_GPIO_BANK(10, 8, 0xE0),
	163	F7188X_GPIO_BANK(20, 8, 0xD0),
	164	F7188X_GPIO_BANK(30, 8, 0xC0),
	165	F7188X_GPIO_BANK(40, 8, 0xB0),
	166	F7188X_GPIO_BANK(50, 5, 0xA0),
	167	F7188X_GPIO_BANK(60, 6, 0x90),
	168	};
	169
7e960363 AB	170	static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
	171	F7188X_GPIO_BANK(0, 6, 0xF0),
	172	F7188X_GPIO_BANK(10, 8, 0xE0),
	173	F7188X_GPIO_BANK(20, 8, 0xD0),
	174	F7188X_GPIO_BANK(30, 8, 0xC0),
	175	F7188X_GPIO_BANK(40, 8, 0xB0),
	176	F7188X_GPIO_BANK(50, 5, 0xA0),
	177	F7188X_GPIO_BANK(60, 8, 0x90),
	178	F7188X_GPIO_BANK(70, 8, 0x80),
	179	};
	180
6c17aa01	181	static struct f7188x_gpio_bank f71882_gpio_bank[] = {
38e003f4	182	F7188X_GPIO_BANK(0, 8, 0xF0),
6c17aa01 SG	183	F7188X_GPIO_BANK(10, 8, 0xE0),
	184	F7188X_GPIO_BANK(20, 8, 0xD0),
	185	F7188X_GPIO_BANK(30, 4, 0xC0),
	186	F7188X_GPIO_BANK(40, 4, 0xB0),
	187	};
	188
	189	static struct f7188x_gpio_bank f71889_gpio_bank[] = {
38e003f4	190	F7188X_GPIO_BANK(0, 7, 0xF0),
6c17aa01 SG	191	F7188X_GPIO_BANK(10, 7, 0xE0),
	192	F7188X_GPIO_BANK(20, 8, 0xD0),
	193	F7188X_GPIO_BANK(30, 8, 0xC0),
	194	F7188X_GPIO_BANK(40, 8, 0xB0),
	195	F7188X_GPIO_BANK(50, 5, 0xA0),
	196	F7188X_GPIO_BANK(60, 8, 0x90),
	197	F7188X_GPIO_BANK(70, 8, 0x80),
	198	};
	199
1920906f PH	200	static struct f7188x_gpio_bank f81866_gpio_bank[] = {
	201	F7188X_GPIO_BANK(0, 8, 0xF0),
	202	F7188X_GPIO_BANK(10, 8, 0xE0),
	203	F7188X_GPIO_BANK(20, 8, 0xD0),
	204	F7188X_GPIO_BANK(30, 8, 0xC0),
	205	F7188X_GPIO_BANK(40, 8, 0xB0),
	206	F7188X_GPIO_BANK(50, 8, 0xA0),
	207	F7188X_GPIO_BANK(60, 8, 0x90),
	208	F7188X_GPIO_BANK(70, 8, 0x80),
	209	F7188X_GPIO_BANK(80, 8, 0x88),
	210	};
	211
6c17aa01 SG	212	static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
	213	{
	214	int err;
f372d5f5	215	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	216	struct f7188x_sio *sio = bank->data->sio;
	217	u8 dir;
	218
	219	err = superio_enter(sio->addr);
	220	if (err)
	221	return err;
	222	superio_select(sio->addr, SIO_LD_GPIO);
	223
	224	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
148c8642	225	dir &= ~BIT(offset);
6c17aa01 SG	226	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
	227
	228	superio_exit(sio->addr);
	229
	230	return 0;
	231	}
	232
	233	static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
	234	{
	235	int err;
f372d5f5	236	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	237	struct f7188x_sio *sio = bank->data->sio;
	238	u8 dir, data;
	239
	240	err = superio_enter(sio->addr);
	241	if (err)
	242	return err;
	243	superio_select(sio->addr, SIO_LD_GPIO);
	244
	245	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
148c8642	246	dir = !!(dir & BIT(offset));
6c17aa01 SG	247	if (dir)
	248	data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	249	else
	250	data = superio_inb(sio->addr, gpio_data_in(bank->regbase));
	251
	252	superio_exit(sio->addr);
	253
148c8642	254	return !!(data & BIT(offset));
6c17aa01 SG	255	}
	256
	257	static int f7188x_gpio_direction_out(struct gpio_chip *chip,
	258	unsigned offset, int value)
	259	{
	260	int err;
f372d5f5	261	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	262	struct f7188x_sio *sio = bank->data->sio;
	263	u8 dir, data_out;
	264
	265	err = superio_enter(sio->addr);
	266	if (err)
	267	return err;
	268	superio_select(sio->addr, SIO_LD_GPIO);
	269
	270	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	271	if (value)
148c8642	272	data_out \|= BIT(offset);
6c17aa01	273	else
148c8642	274	data_out &= ~BIT(offset);
6c17aa01 SG	275	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
	276
	277	dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
148c8642	278	dir \|= BIT(offset);
6c17aa01 SG	279	superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
	280
	281	superio_exit(sio->addr);
	282
	283	return 0;
	284	}
	285
	286	static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	287	{
	288	int err;
f372d5f5	289	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
6c17aa01 SG	290	struct f7188x_sio *sio = bank->data->sio;
	291	u8 data_out;
	292
	293	err = superio_enter(sio->addr);
	294	if (err)
	295	return;
	296	superio_select(sio->addr, SIO_LD_GPIO);
	297
	298	data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
	299	if (value)
148c8642	300	data_out \|= BIT(offset);
6c17aa01	301	else
148c8642	302	data_out &= ~BIT(offset);
6c17aa01 SG	303	superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
	304
	305	superio_exit(sio->addr);
	306	}
	307
f90c6bdb LW	308	static int f7188x_gpio_set_single_ended(struct gpio_chip *chip,
	309	unsigned offset,
	310	enum single_ended_mode mode)
	311	{
	312	int err;
	313	struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
	314	struct f7188x_sio *sio = bank->data->sio;
	315	u8 data;
	316
	317	if (mode != LINE_MODE_OPEN_DRAIN &&
	318	mode != LINE_MODE_PUSH_PULL)
	319	return -ENOTSUPP;
	320
	321	err = superio_enter(sio->addr);
	322	if (err)
	323	return err;
	324	superio_select(sio->addr, SIO_LD_GPIO);
	325
	326	data = superio_inb(sio->addr, gpio_out_mode(bank->regbase));
	327	if (mode == LINE_MODE_OPEN_DRAIN)
	328	data &= ~BIT(offset);
	329	else
	330	data \|= BIT(offset);
327819d1	331	superio_outb(sio->addr, gpio_out_mode(bank->regbase), data);
f90c6bdb LW	332
	333	superio_exit(sio->addr);
	334	return 0;
	335	}
	336
6c17aa01 SG	337	/*
	338	* Platform device and driver.
	339	*/
	340
	341	static int f7188x_gpio_probe(struct platform_device *pdev)
	342	{
	343	int err;
	344	int i;
ab128afc	345	struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
6c17aa01 SG	346	struct f7188x_gpio_data *data;
	347
	348	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	349	if (!data)
	350	return -ENOMEM;
	351
	352	switch (sio->type) {
24ccef35 AB	353	case f71869:
	354	data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
	355	data->bank = f71869_gpio_bank;
	356	break;
7e960363 AB	357	case f71869a:
	358	data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
	359	data->bank = f71869a_gpio_bank;
	360	break;
6c17aa01 SG	361	case f71882fg:
	362	data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
	363	data->bank = f71882_gpio_bank;
	364	break;
	365	case f71889f:
	366	data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
	367	data->bank = f71889_gpio_bank;
	368	break;
1920906f PH	369	case f81866:
	370	data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
	371	data->bank = f81866_gpio_bank;
	372	break;
6c17aa01 SG	373	default:
	374	return -ENODEV;
	375	}
	376	data->sio = sio;
	377
	378	platform_set_drvdata(pdev, data);
	379
	380	/* For each GPIO bank, register a GPIO chip. */
	381	for (i = 0; i < data->nr_bank; i++) {
	382	struct f7188x_gpio_bank *bank = &data->bank[i];
	383
58383c78	384	bank->chip.parent = &pdev->dev;
6c17aa01 SG	385	bank->data = data;
6c17aa01 SG	386
330f4e56	387	err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
6c17aa01 SG	388	if (err) {
	389	dev_err(&pdev->dev,
	390	"Failed to register gpiochip %d: %d\n",
	391	i, err);
330f4e56	392	return err;
6c17aa01 SG	393	}
	394	}
	395
6c17aa01 SG	396	return 0;
	397	}
	398
	399	static int __init f7188x_find(int addr, struct f7188x_sio *sio)
	400	{
	401	int err;
	402	u16 devid;
	403
	404	err = superio_enter(addr);
	405	if (err)
	406	return err;
	407
	408	err = -ENODEV;
	409	devid = superio_inw(addr, SIO_MANID);
	410	if (devid != SIO_FINTEK_ID) {
	411	pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
	412	goto err;
	413	}
	414
	415	devid = superio_inw(addr, SIO_DEVID);
	416	switch (devid) {
24ccef35 AB	417	case SIO_F71869_ID:
	418	sio->type = f71869;
	419	break;
7e960363 AB	420	case SIO_F71869A_ID:
	421	sio->type = f71869a;
	422	break;
6c17aa01 SG	423	case SIO_F71882_ID:
	424	sio->type = f71882fg;
	425	break;
	426	case SIO_F71889_ID:
	427	sio->type = f71889f;
	428	break;
1920906f PH	429	case SIO_F81866_ID:
	430	sio->type = f81866;
	431	break;
6c17aa01 SG	432	default:
	433	pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
	434	goto err;
	435	}
	436	sio->addr = addr;
	437	err = 0;
	438
	439	pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
	440	f7188x_names[sio->type],
	441	(unsigned int) addr,
	442	(int) superio_inb(addr, SIO_DEVREV));
	443
	444	err:
	445	superio_exit(addr);
	446	return err;
	447	}
	448
	449	static struct platform_device *f7188x_gpio_pdev;
	450
	451	static int __init
	452	f7188x_gpio_device_add(const struct f7188x_sio *sio)
	453	{
	454	int err;
	455
	456	f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
	457	if (!f7188x_gpio_pdev)
	458	return -ENOMEM;
	459
	460	err = platform_device_add_data(f7188x_gpio_pdev,
	461	sio, sizeof(*sio));
	462	if (err) {
	463	pr_err(DRVNAME "Platform data allocation failed\n");
	464	goto err;
	465	}
	466
	467	err = platform_device_add(f7188x_gpio_pdev);
	468	if (err) {
	469	pr_err(DRVNAME "Device addition failed\n");
	470	goto err;
	471	}
	472
	473	return 0;
	474
	475	err:
	476	platform_device_put(f7188x_gpio_pdev);
	477
	478	return err;
	479	}
	480
	481	/*
3f8f4f19	482	* Try to match a supported Fintek device by reading the (hard-wired)
6c17aa01 SG	483	* configuration I/O ports. If available, then register both the platform
	484	* device and driver to support the GPIOs.
	485	*/
	486
	487	static struct platform_driver f7188x_gpio_driver = {
	488	.driver = {
6c17aa01 SG	489	.name = DRVNAME,
	490	},
	491	.probe = f7188x_gpio_probe,
6c17aa01 SG	492	};
	493
	494	static int __init f7188x_gpio_init(void)
	495	{
	496	int err;
	497	struct f7188x_sio sio;
	498
	499	if (f7188x_find(0x2e, &sio) &&
	500	f7188x_find(0x4e, &sio))
	501	return -ENODEV;
	502
	503	err = platform_driver_register(&f7188x_gpio_driver);
	504	if (!err) {
	505	err = f7188x_gpio_device_add(&sio);
	506	if (err)
	507	platform_driver_unregister(&f7188x_gpio_driver);
	508	}
	509
	510	return err;
	511	}
	512	subsys_initcall(f7188x_gpio_init);
	513
	514	static void __exit f7188x_gpio_exit(void)
	515	{
	516	platform_device_unregister(f7188x_gpio_pdev);
	517	platform_driver_unregister(&f7188x_gpio_driver);
	518	}
	519	module_exit(f7188x_gpio_exit);
	520
1920906f	521	MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889F and F81866");
6c17aa01 SG	522	MODULE_AUTHOR("Simon Guinot <[email protected]>");
6c17aa01 SG	523	MODULE_LICENSE("GPL");