[linux.git] / drivers / gpio / gpio-em.c

/*
 * Emma Mobile GPIO Support - GIO
 *
 *  Copyright (C) 2012 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>

struct em_gio_priv {
	void __iomem *base0;
	void __iomem *base1;
	spinlock_t sense_lock;
	struct platform_device *pdev;
	struct gpio_chip gpio_chip;
	struct irq_chip irq_chip;
	struct irq_domain *irq_domain;
};

#define GIO_E1 0x00
#define GIO_E0 0x04
#define GIO_EM 0x04
#define GIO_OL 0x08
#define GIO_OH 0x0c
#define GIO_I 0x10
#define GIO_IIA 0x14
#define GIO_IEN 0x18
#define GIO_IDS 0x1c
#define GIO_IIM 0x1c
#define GIO_RAW 0x20
#define GIO_MST 0x24
#define GIO_IIR 0x28

#define GIO_IDT0 0x40
#define GIO_IDT1 0x44
#define GIO_IDT2 0x48
#define GIO_IDT3 0x4c
#define GIO_RAWBL 0x50
#define GIO_RAWBH 0x54
#define GIO_IRBL 0x58
#define GIO_IRBH 0x5c

#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))

static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
{
	if (offs < GIO_IDT0)
		return ioread32(p->base0 + offs);
	else
		return ioread32(p->base1 + (offs - GIO_IDT0));
}

static inline void em_gio_write(struct em_gio_priv *p, int offs,
				unsigned long value)
{
	if (offs < GIO_IDT0)
		iowrite32(value, p->base0 + offs);
	else
		iowrite32(value, p->base1 + (offs - GIO_IDT0));
}

static void em_gio_irq_disable(struct irq_data *d)
{
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);

	em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
}

static void em_gio_irq_enable(struct irq_data *d)
{
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);

	em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
}

static int em_gio_irq_reqres(struct irq_data *d)
{
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);

	if (gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) {
		dev_err(p->gpio_chip.parent,
			"unable to lock HW IRQ %lu for IRQ\n",
			irqd_to_hwirq(d));
		return -EINVAL;
	}
	return 0;
}

static void em_gio_irq_relres(struct irq_data *d)
{
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);

	gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
}


#define GIO_ASYNC(x) (x + 8)

static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
	[IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
	[IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
	[IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
	[IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
	[IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
};

static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
{
	unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
	unsigned int reg, offset, shift;
	unsigned long flags;
	unsigned long tmp;

	if (!value)
		return -EINVAL;

	offset = irqd_to_hwirq(d);

	pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);

	/* 8 x 4 bit fields in 4 IDT registers */
	reg = GIO_IDT(offset >> 3);
	shift = (offset & 0x07) << 4;

	spin_lock_irqsave(&p->sense_lock, flags);

	/* disable the interrupt in IIA */
	tmp = em_gio_read(p, GIO_IIA);
	tmp &= ~BIT(offset);
	em_gio_write(p, GIO_IIA, tmp);

	/* change the sense setting in IDT */
	tmp = em_gio_read(p, reg);
	tmp &= ~(0xf << shift);
	tmp |= value << shift;
	em_gio_write(p, reg, tmp);

	/* clear pending interrupts */
	em_gio_write(p, GIO_IIR, BIT(offset));

	/* enable the interrupt in IIA */
	tmp = em_gio_read(p, GIO_IIA);
	tmp |= BIT(offset);
	em_gio_write(p, GIO_IIA, tmp);

	spin_unlock_irqrestore(&p->sense_lock, flags);

	return 0;
}

static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
{
	struct em_gio_priv *p = dev_id;
	unsigned long pending;
	unsigned int offset, irqs_handled = 0;

	while ((pending = em_gio_read(p, GIO_MST))) {
		offset = __ffs(pending);
		em_gio_write(p, GIO_IIR, BIT(offset));
		generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
		irqs_handled++;
	}

	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
}

static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
{
	return gpiochip_get_data(chip);
}

static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
	return 0;
}

static int em_gio_get(struct gpio_chip *chip, unsigned offset)
{
	return !!(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
}

static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
			 unsigned shift, int value)
{
	/* upper 16 bits contains mask and lower 16 actual value */
	em_gio_write(gpio_to_priv(chip), reg,
		     (BIT(shift + 16)) | (value << shift));
}

static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	/* output is split into two registers */
	if (offset < 16)
		__em_gio_set(chip, GIO_OL, offset, value);
	else
		__em_gio_set(chip, GIO_OH, offset - 16, value);
}

static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
				   int value)
{
	/* write GPIO value to output before selecting output mode of pin */
	em_gio_set(chip, offset, value);
	em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
	return 0;
}

static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
}

static int em_gio_request(struct gpio_chip *chip, unsigned offset)
{
	return pinctrl_request_gpio(chip->base + offset);
}

static void em_gio_free(struct gpio_chip *chip, unsigned offset)
{
	pinctrl_free_gpio(chip->base + offset);

	/* Set the GPIO as an input to ensure that the next GPIO request won't
	* drive the GPIO pin as an output.
	*/
	em_gio_direction_input(chip, offset);
}

static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
				 irq_hw_number_t hwirq)
{
	struct em_gio_priv *p = h->host_data;

	pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);

	irq_set_chip_data(irq, h->host_data);
	irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
	return 0;
}

static const struct irq_domain_ops em_gio_irq_domain_ops = {
	.map	= em_gio_irq_domain_map,
	.xlate	= irq_domain_xlate_twocell,
};

static int em_gio_probe(struct platform_device *pdev)
{
	struct em_gio_priv *p;
	struct resource *io[2], *irq[2];
	struct gpio_chip *gpio_chip;
	struct irq_chip *irq_chip;
	const char *name = dev_name(&pdev->dev);
	unsigned int ngpios;
	int ret;

	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
	if (!p) {
		ret = -ENOMEM;
		goto err0;
	}

	p->pdev = pdev;
	platform_set_drvdata(pdev, p);
	spin_lock_init(&p->sense_lock);

	io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);

	if (!io[0] || !io[1] || !irq[0] || !irq[1]) {
		dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
		ret = -EINVAL;
		goto err0;
	}

	p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start,
					resource_size(io[0]));
	if (!p->base0) {
		dev_err(&pdev->dev, "failed to remap low I/O memory\n");
		ret = -ENXIO;
		goto err0;
	}

	p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start,
				   resource_size(io[1]));
	if (!p->base1) {
		dev_err(&pdev->dev, "failed to remap high I/O memory\n");
		ret = -ENXIO;
		goto err0;
	}

	if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
		dev_err(&pdev->dev, "Missing ngpios OF property\n");
		ret = -EINVAL;
		goto err0;
	}

	gpio_chip = &p->gpio_chip;
	gpio_chip->of_node = pdev->dev.of_node;
	gpio_chip->direction_input = em_gio_direction_input;
	gpio_chip->get = em_gio_get;
	gpio_chip->direction_output = em_gio_direction_output;
	gpio_chip->set = em_gio_set;
	gpio_chip->to_irq = em_gio_to_irq;
	gpio_chip->request = em_gio_request;
	gpio_chip->free = em_gio_free;
	gpio_chip->label = name;
	gpio_chip->parent = &pdev->dev;
	gpio_chip->owner = THIS_MODULE;
	gpio_chip->base = -1;
	gpio_chip->ngpio = ngpios;

	irq_chip = &p->irq_chip;
	irq_chip->name = name;
	irq_chip->irq_mask = em_gio_irq_disable;
	irq_chip->irq_unmask = em_gio_irq_enable;
	irq_chip->irq_set_type = em_gio_irq_set_type;
	irq_chip->irq_request_resources = em_gio_irq_reqres;
	irq_chip->irq_release_resources = em_gio_irq_relres;
	irq_chip->flags	= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;

	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, ngpios, 0,
					      &em_gio_irq_domain_ops, p);
	if (!p->irq_domain) {
		ret = -ENXIO;
		dev_err(&pdev->dev, "cannot initialize irq domain\n");
		goto err0;
	}

	if (devm_request_irq(&pdev->dev, irq[0]->start,
			     em_gio_irq_handler, 0, name, p)) {
		dev_err(&pdev->dev, "failed to request low IRQ\n");
		ret = -ENOENT;
		goto err1;
	}

	if (devm_request_irq(&pdev->dev, irq[1]->start,
			     em_gio_irq_handler, 0, name, p)) {
		dev_err(&pdev->dev, "failed to request high IRQ\n");
		ret = -ENOENT;
		goto err1;
	}

	ret = gpiochip_add_data(gpio_chip, p);
	if (ret) {
		dev_err(&pdev->dev, "failed to add GPIO controller\n");
		goto err1;
	}

	return 0;

err1:
	irq_domain_remove(p->irq_domain);
err0:
	return ret;
}

static int em_gio_remove(struct platform_device *pdev)
{
	struct em_gio_priv *p = platform_get_drvdata(pdev);

	gpiochip_remove(&p->gpio_chip);

	irq_domain_remove(p->irq_domain);
	return 0;
}

static const struct of_device_id em_gio_dt_ids[] = {
	{ .compatible = "renesas,em-gio", },
	{},
};
MODULE_DEVICE_TABLE(of, em_gio_dt_ids);

static struct platform_driver em_gio_device_driver = {
	.probe		= em_gio_probe,
	.remove		= em_gio_remove,
	.driver		= {
		.name	= "em_gio",
		.of_match_table = em_gio_dt_ids,
	}
};

static int __init em_gio_init(void)
{
	return platform_driver_register(&em_gio_device_driver);
}
postcore_initcall(em_gio_init);

static void __exit em_gio_exit(void)
{
	platform_driver_unregister(&em_gio_device_driver);
}
module_exit(em_gio_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a07e103e MD	1	/*
	2	* Emma Mobile GPIO Support - GIO
	3	*
	4	* Copyright (C) 2012 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/ioport.h>
	25	#include <linux/io.h>
	26	#include <linux/irq.h>
	27	#include <linux/irqdomain.h>
	28	#include <linux/bitops.h>
	29	#include <linux/err.h>
	30	#include <linux/gpio.h>
	31	#include <linux/slab.h>
	32	#include <linux/module.h>
640efa08	33	#include <linux/pinctrl/consumer.h>
a07e103e MD	34
	35	struct em_gio_priv {
	36	void __iomem *base0;
	37	void __iomem *base1;
a07e103e MD	38	spinlock_t sense_lock;
	39	struct platform_device *pdev;
	40	struct gpio_chip gpio_chip;
	41	struct irq_chip irq_chip;
	42	struct irq_domain *irq_domain;
	43	};
	44
	45	#define GIO_E1 0x00
	46	#define GIO_E0 0x04
	47	#define GIO_EM 0x04
	48	#define GIO_OL 0x08
	49	#define GIO_OH 0x0c
	50	#define GIO_I 0x10
	51	#define GIO_IIA 0x14
	52	#define GIO_IEN 0x18
	53	#define GIO_IDS 0x1c
	54	#define GIO_IIM 0x1c
	55	#define GIO_RAW 0x20
	56	#define GIO_MST 0x24
	57	#define GIO_IIR 0x28
	58
	59	#define GIO_IDT0 0x40
	60	#define GIO_IDT1 0x44
	61	#define GIO_IDT2 0x48
	62	#define GIO_IDT3 0x4c
	63	#define GIO_RAWBL 0x50
	64	#define GIO_RAWBH 0x54
	65	#define GIO_IRBL 0x58
	66	#define GIO_IRBH 0x5c
	67
	68	#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
	69
	70	static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
	71	{
	72	if (offs < GIO_IDT0)
	73	return ioread32(p->base0 + offs);
	74	else
	75	return ioread32(p->base1 + (offs - GIO_IDT0));
	76	}
	77
	78	static inline void em_gio_write(struct em_gio_priv *p, int offs,
	79	unsigned long value)
	80	{
	81	if (offs < GIO_IDT0)
	82	iowrite32(value, p->base0 + offs);
	83	else
	84	iowrite32(value, p->base1 + (offs - GIO_IDT0));
	85	}
	86
a07e103e MD	87	static void em_gio_irq_disable(struct irq_data *d)
a07e103e MD	88	{
a9f77c93	89	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
a07e103e MD	90
	91	em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
	92	}
	93
	94	static void em_gio_irq_enable(struct irq_data *d)
	95	{
a9f77c93	96	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
a07e103e MD	97
	98	em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
	99	}
	100
57ef0428	101	static int em_gio_irq_reqres(struct irq_data *d)
0dc61623 LW	102	{
	103	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
	104
e3a2e878	105	if (gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) {
58383c78	106	dev_err(p->gpio_chip.parent,
0dc61623 LW	107	"unable to lock HW IRQ %lu for IRQ\n",
0dc61623 LW	108	irqd_to_hwirq(d));
57ef0428 LW	109	return -EINVAL;
57ef0428 LW	110	}
0dc61623 LW	111	return 0;
	112	}
	113
57ef0428	114	static void em_gio_irq_relres(struct irq_data *d)
0dc61623 LW	115	{
	116	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
	117
e3a2e878	118	gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
0dc61623 LW	119	}
	120
	121
a07e103e MD	122	#define GIO_ASYNC(x) (x + 8)
	123
	124	static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
	125	[IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
	126	[IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
	127	[IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
	128	[IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
	129	[IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
	130	};
	131
	132	static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
	133	{
	134	unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
a9f77c93	135	struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
a07e103e MD	136	unsigned int reg, offset, shift;
	137	unsigned long flags;
	138	unsigned long tmp;
	139
	140	if (!value)
	141	return -EINVAL;
	142
	143	offset = irqd_to_hwirq(d);
	144
	145	pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
	146
	147	/* 8 x 4 bit fields in 4 IDT registers */
	148	reg = GIO_IDT(offset >> 3);
	149	shift = (offset & 0x07) << 4;
	150
	151	spin_lock_irqsave(&p->sense_lock, flags);
	152
	153	/* disable the interrupt in IIA */
	154	tmp = em_gio_read(p, GIO_IIA);
	155	tmp &= ~BIT(offset);
	156	em_gio_write(p, GIO_IIA, tmp);
	157
	158	/* change the sense setting in IDT */
	159	tmp = em_gio_read(p, reg);
	160	tmp &= ~(0xf << shift);
	161	tmp \|= value << shift;
	162	em_gio_write(p, reg, tmp);
	163
	164	/* clear pending interrupts */
	165	em_gio_write(p, GIO_IIR, BIT(offset));
	166
	167	/* enable the interrupt in IIA */
	168	tmp = em_gio_read(p, GIO_IIA);
	169	tmp \|= BIT(offset);
	170	em_gio_write(p, GIO_IIA, tmp);
	171
	172	spin_unlock_irqrestore(&p->sense_lock, flags);
	173
	174	return 0;
	175	}
	176
	177	static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
	178	{
	179	struct em_gio_priv *p = dev_id;
	180	unsigned long pending;
	181	unsigned int offset, irqs_handled = 0;
	182
	183	while ((pending = em_gio_read(p, GIO_MST))) {
	184	offset = __ffs(pending);
	185	em_gio_write(p, GIO_IIR, BIT(offset));
	186	generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
	187	irqs_handled++;
	188	}
	189
	190	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
	191	}
	192
	193	static inline struct em_gio_priv gpio_to_priv(struct gpio_chip chip)
	194	{
6219e7bb	195	return gpiochip_get_data(chip);
a07e103e MD	196	}
	197
	198	static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
	199	{
	200	em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
	201	return 0;
	202	}
	203
	204	static int em_gio_get(struct gpio_chip *chip, unsigned offset)
	205	{
8388f290	206	return !!(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
a07e103e MD	207	}
	208
	209	static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
	210	unsigned shift, int value)
	211	{
	212	/* upper 16 bits contains mask and lower 16 actual value */
	213	em_gio_write(gpio_to_priv(chip), reg,
5f077644	214	(BIT(shift + 16)) \| (value << shift));
a07e103e MD	215	}
	216
	217	static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
	218	{
	219	/* output is split into two registers */
	220	if (offset < 16)
	221	__em_gio_set(chip, GIO_OL, offset, value);
	222	else
	223	__em_gio_set(chip, GIO_OH, offset - 16, value);
	224	}
	225
	226	static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
	227	int value)
	228	{
	229	/* write GPIO value to output before selecting output mode of pin */
	230	em_gio_set(chip, offset, value);
	231	em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
	232	return 0;
	233	}
	234
	235	static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
	236	{
7385500a	237	return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
a07e103e MD	238	}
a07e103e MD	239
640efa08 MD	240	static int em_gio_request(struct gpio_chip *chip, unsigned offset)
	241	{
	242	return pinctrl_request_gpio(chip->base + offset);
	243	}
	244
	245	static void em_gio_free(struct gpio_chip *chip, unsigned offset)
	246	{
	247	pinctrl_free_gpio(chip->base + offset);
	248
	249	/* Set the GPIO as an input to ensure that the next GPIO request won't
	250	* drive the GPIO pin as an output.
	251	*/
	252	em_gio_direction_input(chip, offset);
	253	}
	254
2d61e3e9 LW	255	static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
2d61e3e9 LW	256	irq_hw_number_t hwirq)
a07e103e MD	257	{
	258	struct em_gio_priv *p = h->host_data;
	259
2d61e3e9	260	pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);
a07e103e	261
2d61e3e9 LW	262	irq_set_chip_data(irq, h->host_data);
2d61e3e9 LW	263	irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
a07e103e MD	264	return 0;
	265	}
	266
0b354dc4	267	static const struct irq_domain_ops em_gio_irq_domain_ops = {
a07e103e	268	.map = em_gio_irq_domain_map,
753c5983	269	.xlate = irq_domain_xlate_twocell,
a07e103e MD	270	};
a07e103e MD	271
3836309d	272	static int em_gio_probe(struct platform_device *pdev)
a07e103e	273	{
a07e103e MD	274	struct em_gio_priv *p;
	275	struct resource io[2], irq[2];
	276	struct gpio_chip *gpio_chip;
	277	struct irq_chip *irq_chip;
	278	const char *name = dev_name(&pdev->dev);
527b397a	279	unsigned int ngpios;
a07e103e MD	280	int ret;
a07e103e MD	281
1cfe6f8c	282	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
a07e103e	283	if (!p) {
a07e103e MD	284	ret = -ENOMEM;
	285	goto err0;
	286	}
	287
	288	p->pdev = pdev;
	289	platform_set_drvdata(pdev, p);
	290	spin_lock_init(&p->sense_lock);
	291
	292	io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	293	io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	294	irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	295	irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
	296
753c5983 MD	297	if (!io[0] \|\| !io[1] \|\| !irq[0] \|\| !irq[1]) {
753c5983 MD	298	dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
a07e103e	299	ret = -EINVAL;
1cfe6f8c	300	goto err0;
a07e103e MD	301	}
a07e103e MD	302
1cfe6f8c MD	303	p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start,
1cfe6f8c MD	304	resource_size(io[0]));
a07e103e MD	305	if (!p->base0) {
	306	dev_err(&pdev->dev, "failed to remap low I/O memory\n");
	307	ret = -ENXIO;
1cfe6f8c	308	goto err0;
a07e103e MD	309	}
a07e103e MD	310
1cfe6f8c MD	311	p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start,
1cfe6f8c MD	312	resource_size(io[1]));
a07e103e MD	313	if (!p->base1) {
	314	dev_err(&pdev->dev, "failed to remap high I/O memory\n");
	315	ret = -ENXIO;
1cfe6f8c	316	goto err0;
a07e103e MD	317	}
a07e103e MD	318
527b397a GU	319	if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
	320	dev_err(&pdev->dev, "Missing ngpios OF property\n");
	321	ret = -EINVAL;
	322	goto err0;
753c5983 MD	323	}
753c5983 MD	324
a07e103e	325	gpio_chip = &p->gpio_chip;
b5927854	326	gpio_chip->of_node = pdev->dev.of_node;
a07e103e MD	327	gpio_chip->direction_input = em_gio_direction_input;
	328	gpio_chip->get = em_gio_get;
	329	gpio_chip->direction_output = em_gio_direction_output;
	330	gpio_chip->set = em_gio_set;
	331	gpio_chip->to_irq = em_gio_to_irq;
640efa08 MD	332	gpio_chip->request = em_gio_request;
640efa08 MD	333	gpio_chip->free = em_gio_free;
a07e103e	334	gpio_chip->label = name;
58383c78	335	gpio_chip->parent = &pdev->dev;
a07e103e	336	gpio_chip->owner = THIS_MODULE;
527b397a GU	337	gpio_chip->base = -1;
527b397a GU	338	gpio_chip->ngpio = ngpios;
a07e103e MD	339
	340	irq_chip = &p->irq_chip;
	341	irq_chip->name = name;
	342	irq_chip->irq_mask = em_gio_irq_disable;
	343	irq_chip->irq_unmask = em_gio_irq_enable;
a07e103e	344	irq_chip->irq_set_type = em_gio_irq_set_type;
57ef0428 LW	345	irq_chip->irq_request_resources = em_gio_irq_reqres;
57ef0428 LW	346	irq_chip->irq_release_resources = em_gio_irq_relres;
03621b60	347	irq_chip->flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_MASK_ON_SUSPEND;
a07e103e	348
527b397a	349	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, ngpios, 0,
7385500a	350	&em_gio_irq_domain_ops, p);
16310819 AL	351	if (!p->irq_domain) {
16310819 AL	352	ret = -ENXIO;
a07e103e	353	dev_err(&pdev->dev, "cannot initialize irq domain\n");
1cfe6f8c	354	goto err0;
a07e103e MD	355	}
a07e103e MD	356
1cfe6f8c MD	357	if (devm_request_irq(&pdev->dev, irq[0]->start,
1cfe6f8c MD	358	em_gio_irq_handler, 0, name, p)) {
a07e103e MD	359	dev_err(&pdev->dev, "failed to request low IRQ\n");
a07e103e MD	360	ret = -ENOENT;
1cfe6f8c	361	goto err1;
a07e103e MD	362	}
a07e103e MD	363
1cfe6f8c MD	364	if (devm_request_irq(&pdev->dev, irq[1]->start,
1cfe6f8c MD	365	em_gio_irq_handler, 0, name, p)) {
a07e103e MD	366	dev_err(&pdev->dev, "failed to request high IRQ\n");
a07e103e MD	367	ret = -ENOENT;
1cfe6f8c	368	goto err1;
a07e103e MD	369	}
a07e103e MD	370
6219e7bb	371	ret = gpiochip_add_data(gpio_chip, p);
a07e103e MD	372	if (ret) {
a07e103e MD	373	dev_err(&pdev->dev, "failed to add GPIO controller\n");
1cfe6f8c	374	goto err1;
a07e103e	375	}
640efa08	376
a07e103e MD	377	return 0;
a07e103e MD	378
a07e103e	379	err1:
1cfe6f8c	380	irq_domain_remove(p->irq_domain);
a07e103e MD	381	err0:
	382	return ret;
	383	}
	384
206210ce	385	static int em_gio_remove(struct platform_device *pdev)
a07e103e MD	386	{
a07e103e MD	387	struct em_gio_priv *p = platform_get_drvdata(pdev);
a07e103e	388
9f5132ae	389	gpiochip_remove(&p->gpio_chip);
a07e103e	390
16310819	391	irq_domain_remove(p->irq_domain);
a07e103e MD	392	return 0;
	393	}
	394
753c5983 MD	395	static const struct of_device_id em_gio_dt_ids[] = {
	396	{ .compatible = "renesas,em-gio", },
	397	{},
	398	};
	399	MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
	400
a07e103e MD	401	static struct platform_driver em_gio_device_driver = {
a07e103e MD	402	.probe = em_gio_probe,
8283c4ff	403	.remove = em_gio_remove,
a07e103e MD	404	.driver = {
a07e103e MD	405	.name = "em_gio",
753c5983	406	.of_match_table = em_gio_dt_ids,
a07e103e MD	407	}
	408	};
	409
753c5983 MD	410	static int __init em_gio_init(void)
	411	{
	412	return platform_driver_register(&em_gio_device_driver);
	413	}
	414	postcore_initcall(em_gio_init);
	415
	416	static void __exit em_gio_exit(void)
	417	{
	418	platform_driver_unregister(&em_gio_device_driver);
	419	}
	420	module_exit(em_gio_exit);
a07e103e MD	421
	422	MODULE_AUTHOR("Magnus Damm");
	423	MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
	424	MODULE_LICENSE("GPL v2");