[linux.git] / drivers / cpufreq / qoriq-cpufreq.c

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * CPU Frequency Scaling driver for Freescale QorIQ SoCs.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/cpufreq.h>
#include <linux/cpu_cooling.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/smp.h>

/**
 * struct cpu_data
 * @pclk: the parent clock of cpu
 * @table: frequency table
 */
struct cpu_data {
	struct clk **pclk;
	struct cpufreq_frequency_table *table;
	struct thermal_cooling_device *cdev;
};

/*
 * Don't use cpufreq on this SoC -- used when the SoC would have otherwise
 * matched a more generic compatible.
 */
#define SOC_BLACKLIST		1

/**
 * struct soc_data - SoC specific data
 * @flags: SOC_xxx
 */
struct soc_data {
	u32 flags;
};

static u32 get_bus_freq(void)
{
	struct device_node *soc;
	u32 sysfreq;
	struct clk *pltclk;
	int ret;

	/* get platform freq by searching bus-frequency property */
	soc = of_find_node_by_type(NULL, "soc");
	if (soc) {
		ret = of_property_read_u32(soc, "bus-frequency", &sysfreq);
		of_node_put(soc);
		if (!ret)
			return sysfreq;
	}

	/* get platform freq by its clock name */
	pltclk = clk_get(NULL, "cg-pll0-div1");
	if (IS_ERR(pltclk)) {
		pr_err("%s: can't get bus frequency %ld\n",
		       __func__, PTR_ERR(pltclk));
		return PTR_ERR(pltclk);
	}

	return clk_get_rate(pltclk);
}

static struct clk *cpu_to_clk(int cpu)
{
	struct device_node *np;
	struct clk *clk;

	if (!cpu_present(cpu))
		return NULL;

	np = of_get_cpu_node(cpu, NULL);
	if (!np)
		return NULL;

	clk = of_clk_get(np, 0);
	of_node_put(np);
	return clk;
}

/* traverse cpu nodes to get cpu mask of sharing clock wire */
static void set_affected_cpus(struct cpufreq_policy *policy)
{
	struct cpumask *dstp = policy->cpus;
	struct clk *clk;
	int i;

	for_each_present_cpu(i) {
		clk = cpu_to_clk(i);
		if (IS_ERR(clk)) {
			pr_err("%s: no clock for cpu %d\n", __func__, i);
			continue;
		}

		if (clk_is_match(policy->clk, clk))
			cpumask_set_cpu(i, dstp);
	}
}

/* reduce the duplicated frequencies in frequency table */
static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
		int count)
{
	int i, j;

	for (i = 1; i < count; i++) {
		for (j = 0; j < i; j++) {
			if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID ||
					freq_table[j].frequency !=
					freq_table[i].frequency)
				continue;

			freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
			break;
		}
	}
}

/* sort the frequencies in frequency table in descenting order */
static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
		int count)
{
	int i, j, ind;
	unsigned int freq, max_freq;
	struct cpufreq_frequency_table table;

	for (i = 0; i < count - 1; i++) {
		max_freq = freq_table[i].frequency;
		ind = i;
		for (j = i + 1; j < count; j++) {
			freq = freq_table[j].frequency;
			if (freq == CPUFREQ_ENTRY_INVALID ||
					freq <= max_freq)
				continue;
			ind = j;
			max_freq = freq;
		}

		if (ind != i) {
			/* exchange the frequencies */
			table.driver_data = freq_table[i].driver_data;
			table.frequency = freq_table[i].frequency;
			freq_table[i].driver_data = freq_table[ind].driver_data;
			freq_table[i].frequency = freq_table[ind].frequency;
			freq_table[ind].driver_data = table.driver_data;
			freq_table[ind].frequency = table.frequency;
		}
	}
}

static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
	struct device_node *np;
	int i, count;
	u32 freq;
	struct clk *clk;
	const struct clk_hw *hwclk;
	struct cpufreq_frequency_table *table;
	struct cpu_data *data;
	unsigned int cpu = policy->cpu;
	u64 u64temp;

	np = of_get_cpu_node(cpu, NULL);
	if (!np)
		return -ENODEV;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		goto err_np;

	policy->clk = of_clk_get(np, 0);
	if (IS_ERR(policy->clk)) {
		pr_err("%s: no clock information\n", __func__);
		goto err_nomem2;
	}

	hwclk = __clk_get_hw(policy->clk);
	count = clk_hw_get_num_parents(hwclk);

	data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
	if (!data->pclk)
		goto err_nomem2;

	table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
	if (!table)
		goto err_pclk;

	for (i = 0; i < count; i++) {
		clk = clk_hw_get_parent_by_index(hwclk, i)->clk;
		data->pclk[i] = clk;
		freq = clk_get_rate(clk);
		table[i].frequency = freq / 1000;
		table[i].driver_data = i;
	}
	freq_table_redup(table, count);
	freq_table_sort(table, count);
	table[i].frequency = CPUFREQ_TABLE_END;
	policy->freq_table = table;
	data->table = table;

	/* update ->cpus if we have cluster, no harm if not */
	set_affected_cpus(policy);
	policy->driver_data = data;

	/* Minimum transition latency is 12 platform clocks */
	u64temp = 12ULL * NSEC_PER_SEC;
	do_div(u64temp, get_bus_freq());
	policy->cpuinfo.transition_latency = u64temp + 1;

	of_node_put(np);

	return 0;

err_pclk:
	kfree(data->pclk);
err_nomem2:
	kfree(data);
err_np:
	of_node_put(np);

	return -ENODEV;
}

static int qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
{
	struct cpu_data *data = policy->driver_data;

	cpufreq_cooling_unregister(data->cdev);
	kfree(data->pclk);
	kfree(data->table);
	kfree(data);
	policy->driver_data = NULL;

	return 0;
}

static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
		unsigned int index)
{
	struct clk *parent;
	struct cpu_data *data = policy->driver_data;

	parent = data->pclk[data->table[index].driver_data];
	return clk_set_parent(policy->clk, parent);
}


static void qoriq_cpufreq_ready(struct cpufreq_policy *policy)
{
	struct cpu_data *cpud = policy->driver_data;

	cpud->cdev = of_cpufreq_cooling_register(policy);
}

static struct cpufreq_driver qoriq_cpufreq_driver = {
	.name		= "qoriq_cpufreq",
	.flags		= CPUFREQ_CONST_LOOPS,
	.init		= qoriq_cpufreq_cpu_init,
	.exit		= qoriq_cpufreq_cpu_exit,
	.verify		= cpufreq_generic_frequency_table_verify,
	.target_index	= qoriq_cpufreq_target,
	.get		= cpufreq_generic_get,
	.ready		= qoriq_cpufreq_ready,
	.attr		= cpufreq_generic_attr,
};

static const struct soc_data blacklist = {
	.flags = SOC_BLACKLIST,
};

static const struct of_device_id node_matches[] __initconst = {
	/* e6500 cannot use cpufreq due to erratum A-008083 */
	{ .compatible = "fsl,b4420-clockgen", &blacklist },
	{ .compatible = "fsl,b4860-clockgen", &blacklist },
	{ .compatible = "fsl,t2080-clockgen", &blacklist },
	{ .compatible = "fsl,t4240-clockgen", &blacklist },

	{ .compatible = "fsl,ls1012a-clockgen", },
	{ .compatible = "fsl,ls1021a-clockgen", },
	{ .compatible = "fsl,ls1043a-clockgen", },
	{ .compatible = "fsl,ls1046a-clockgen", },
	{ .compatible = "fsl,ls1088a-clockgen", },
	{ .compatible = "fsl,ls2080a-clockgen", },
	{ .compatible = "fsl,p4080-clockgen", },
	{ .compatible = "fsl,qoriq-clockgen-1.0", },
	{ .compatible = "fsl,qoriq-clockgen-2.0", },
	{}
};

static int __init qoriq_cpufreq_init(void)
{
	int ret;
	struct device_node  *np;
	const struct of_device_id *match;
	const struct soc_data *data;

	np = of_find_matching_node(NULL, node_matches);
	if (!np)
		return -ENODEV;

	match = of_match_node(node_matches, np);
	data = match->data;

	of_node_put(np);

	if (data && data->flags & SOC_BLACKLIST)
		return -ENODEV;

	ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
	if (!ret)
		pr_info("Freescale QorIQ CPU frequency scaling driver\n");

	return ret;
}
module_init(qoriq_cpufreq_init);

static void __exit qoriq_cpufreq_exit(void)
{
	cpufreq_unregister_driver(&qoriq_cpufreq_driver);
}
module_exit(qoriq_cpufreq_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Tang Yuantian <[email protected]>");
MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");
Commit	Line	Data
defa4c73 TY	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
a4f20742	4	* CPU Frequency Scaling driver for Freescale QorIQ SoCs.
defa4c73 TY	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	12
	13	#include <linux/clk.h>
b1e9a649	14	#include <linux/clk-provider.h>
defa4c73	15	#include <linux/cpufreq.h>
8ae1702a	16	#include <linux/cpu_cooling.h>
defa4c73	17	#include <linux/errno.h>
defa4c73 TY	18	#include <linux/init.h>
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/mutex.h>
	22	#include <linux/of.h>
	23	#include <linux/slab.h>
	24	#include <linux/smp.h>
	25
	26	/**
a4f20742	27	* struct cpu_data
8a95c144	28	* @pclk: the parent clock of cpu
defa4c73 TY	29	* @table: frequency table
	30	*/
	31	struct cpu_data {
8a95c144	32	struct clk **pclk;
defa4c73	33	struct cpufreq_frequency_table *table;
8ae1702a	34	struct thermal_cooling_device *cdev;
defa4c73 TY	35	};
defa4c73 TY	36
b1e9a649 TY	37	/*
	38	* Don't use cpufreq on this SoC -- used when the SoC would have otherwise
	39	* matched a more generic compatible.
	40	*/
	41	#define SOC_BLACKLIST 1
	42
defa4c73 TY	43	/**
defa4c73 TY	44	* struct soc_data - SoC specific data
b1e9a649	45	* @flags: SOC_xxx
defa4c73 TY	46	*/
defa4c73 TY	47	struct soc_data {
b1e9a649	48	u32 flags;
defa4c73 TY	49	};
defa4c73 TY	50
a4f20742 TY	51	static u32 get_bus_freq(void)
	52	{
	53	struct device_node *soc;
	54	u32 sysfreq;
b51d3388 YT	55	struct clk *pltclk;
b51d3388 YT	56	int ret;
a4f20742	57
b51d3388	58	/* get platform freq by searching bus-frequency property */
a4f20742	59	soc = of_find_node_by_type(NULL, "soc");
b51d3388 YT	60	if (soc) {
	61	ret = of_property_read_u32(soc, "bus-frequency", &sysfreq);
	62	of_node_put(soc);
	63	if (!ret)
	64	return sysfreq;
	65	}
a4f20742	66
b51d3388 YT	67	/* get platform freq by its clock name */
	68	pltclk = clk_get(NULL, "cg-pll0-div1");
	69	if (IS_ERR(pltclk)) {
	70	pr_err("%s: can't get bus frequency %ld\n",
	71	__func__, PTR_ERR(pltclk));
	72	return PTR_ERR(pltclk);
	73	}
defa4c73	74
b51d3388	75	return clk_get_rate(pltclk);
a4f20742	76	}
defa4c73	77
b1e9a649	78	static struct clk *cpu_to_clk(int cpu)
defa4c73	79	{
b1e9a649 TY	80	struct device_node *np;
b1e9a649 TY	81	struct clk *clk;
a4f20742 TY	82
	83	if (!cpu_present(cpu))
	84	return NULL;
	85
	86	np = of_get_cpu_node(cpu, NULL);
	87	if (!np)
	88	return NULL;
	89
b1e9a649	90	clk = of_clk_get(np, 0);
a4f20742	91	of_node_put(np);
b1e9a649	92	return clk;
a4f20742 TY	93	}
	94
	95	/* traverse cpu nodes to get cpu mask of sharing clock wire */
	96	static void set_affected_cpus(struct cpufreq_policy *policy)
	97	{
a4f20742	98	struct cpumask *dstp = policy->cpus;
b1e9a649	99	struct clk *clk;
a4f20742 TY	100	int i;
a4f20742 TY	101
a4f20742	102	for_each_present_cpu(i) {
b1e9a649 TY	103	clk = cpu_to_clk(i);
	104	if (IS_ERR(clk)) {
	105	pr_err("%s: no clock for cpu %d\n", __func__, i);
a4f20742	106	continue;
b1e9a649	107	}
a4f20742	108
b1e9a649	109	if (clk_is_match(policy->clk, clk))
a4f20742	110	cpumask_set_cpu(i, dstp);
a4f20742	111	}
defa4c73	112	}
defa4c73	113
defa4c73 TY	114	/* reduce the duplicated frequencies in frequency table */
	115	static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
	116	int count)
	117	{
	118	int i, j;
	119
	120	for (i = 1; i < count; i++) {
	121	for (j = 0; j < i; j++) {
	122	if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID \|\|
	123	freq_table[j].frequency !=
	124	freq_table[i].frequency)
	125	continue;
	126
	127	freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
	128	break;
	129	}
	130	}
	131	}
	132
	133	/* sort the frequencies in frequency table in descenting order */
	134	static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
	135	int count)
	136	{
	137	int i, j, ind;
	138	unsigned int freq, max_freq;
	139	struct cpufreq_frequency_table table;
a4f20742	140
defa4c73 TY	141	for (i = 0; i < count - 1; i++) {
	142	max_freq = freq_table[i].frequency;
	143	ind = i;
	144	for (j = i + 1; j < count; j++) {
	145	freq = freq_table[j].frequency;
	146	if (freq == CPUFREQ_ENTRY_INVALID \|\|
	147	freq <= max_freq)
	148	continue;
	149	ind = j;
	150	max_freq = freq;
	151	}
	152
	153	if (ind != i) {
	154	/* exchange the frequencies */
	155	table.driver_data = freq_table[i].driver_data;
	156	table.frequency = freq_table[i].frequency;
	157	freq_table[i].driver_data = freq_table[ind].driver_data;
	158	freq_table[i].frequency = freq_table[ind].frequency;
	159	freq_table[ind].driver_data = table.driver_data;
	160	freq_table[ind].frequency = table.frequency;
	161	}
	162	}
	163	}
	164
a4f20742	165	static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
defa4c73	166	{
b1e9a649	167	struct device_node *np;
5ab508be	168	int i, count;
b1e9a649	169	u32 freq;
defa4c73	170	struct clk *clk;
b1e9a649	171	const struct clk_hw *hwclk;
defa4c73 TY	172	struct cpufreq_frequency_table *table;
	173	struct cpu_data *data;
	174	unsigned int cpu = policy->cpu;
906fe033	175	u64 u64temp;
defa4c73 TY	176
	177	np = of_get_cpu_node(cpu, NULL);
	178	if (!np)
	179	return -ENODEV;
	180
	181	data = kzalloc(sizeof(*data), GFP_KERNEL);
a4f20742	182	if (!data)
defa4c73	183	goto err_np;
defa4c73	184
652ed95d VK	185	policy->clk = of_clk_get(np, 0);
652ed95d VK	186	if (IS_ERR(policy->clk)) {
defa4c73 TY	187	pr_err("%s: no clock information\n", __func__);
	188	goto err_nomem2;
	189	}
	190
b1e9a649 TY	191	hwclk = __clk_get_hw(policy->clk);
b1e9a649 TY	192	count = clk_hw_get_num_parents(hwclk);
defa4c73	193
8a95c144	194	data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
d6b96e47	195	if (!data->pclk)
b1e9a649	196	goto err_nomem2;
8a95c144	197
defa4c73	198	table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
d6b96e47	199	if (!table)
8a95c144	200	goto err_pclk;
defa4c73	201
defa4c73	202	for (i = 0; i < count; i++) {
b1e9a649	203	clk = clk_hw_get_parent_by_index(hwclk, i)->clk;
8a95c144	204	data->pclk[i] = clk;
defa4c73	205	freq = clk_get_rate(clk);
b1e9a649	206	table[i].frequency = freq / 1000;
defa4c73 TY	207	table[i].driver_data = i;
	208	}
	209	freq_table_redup(table, count);
	210	freq_table_sort(table, count);
	211	table[i].frequency = CPUFREQ_TABLE_END;
5ab508be	212	policy->freq_table = table;
defa4c73	213	data->table = table;
defa4c73 TY	214
defa4c73 TY	215	/* update ->cpus if we have cluster, no harm if not */
a4f20742 TY	216	set_affected_cpus(policy);
a4f20742 TY	217	policy->driver_data = data;
defa4c73	218
906fe033 ES	219	/* Minimum transition latency is 12 platform clocks */
906fe033 ES	220	u64temp = 12ULL * NSEC_PER_SEC;
a4f20742	221	do_div(u64temp, get_bus_freq());
906fe033	222	policy->cpuinfo.transition_latency = u64temp + 1;
6712d293	223
defa4c73 TY	224	of_node_put(np);
	225
	226	return 0;
	227
8a95c144 TY	228	err_pclk:
8a95c144 TY	229	kfree(data->pclk);
defa4c73	230	err_nomem2:
defa4c73 TY	231	kfree(data);
	232	err_np:
	233	of_node_put(np);
	234
	235	return -ENODEV;
	236	}
	237
495c716f	238	static int qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
defa4c73	239	{
a4f20742	240	struct cpu_data *data = policy->driver_data;
defa4c73	241
394cb831	242	cpufreq_cooling_unregister(data->cdev);
8a95c144	243	kfree(data->pclk);
defa4c73 TY	244	kfree(data->table);
defa4c73 TY	245	kfree(data);
a4f20742	246	policy->driver_data = NULL;
defa4c73 TY	247
	248	return 0;
	249	}
	250
a4f20742	251	static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
9c0ebcf7	252	unsigned int index)
defa4c73	253	{
defa4c73	254	struct clk *parent;
a4f20742	255	struct cpu_data *data = policy->driver_data;
defa4c73	256
8a95c144	257	parent = data->pclk[data->table[index].driver_data];
652ed95d	258	return clk_set_parent(policy->clk, parent);
defa4c73 TY	259	}
defa4c73 TY	260
8ae1702a HJ	261
	262	static void qoriq_cpufreq_ready(struct cpufreq_policy *policy)
	263	{
	264	struct cpu_data *cpud = policy->driver_data;
8ae1702a	265
3ebb62ff	266	cpud->cdev = of_cpufreq_cooling_register(policy);
8ae1702a HJ	267	}
8ae1702a HJ	268
a4f20742 TY	269	static struct cpufreq_driver qoriq_cpufreq_driver = {
a4f20742 TY	270	.name = "qoriq_cpufreq",
defa4c73	271	.flags = CPUFREQ_CONST_LOOPS,
a4f20742	272	.init = qoriq_cpufreq_cpu_init,
495c716f	273	.exit = qoriq_cpufreq_cpu_exit,
dc2398d7	274	.verify = cpufreq_generic_frequency_table_verify,
a4f20742	275	.target_index = qoriq_cpufreq_target,
652ed95d	276	.get = cpufreq_generic_get,
8ae1702a	277	.ready = qoriq_cpufreq_ready,
dc2398d7	278	.attr = cpufreq_generic_attr,
defa4c73 TY	279	};
defa4c73 TY	280
b1e9a649 TY	281	static const struct soc_data blacklist = {
	282	.flags = SOC_BLACKLIST,
	283	};
	284
a4f20742	285	static const struct of_device_id node_matches[] __initconst = {
b1e9a649 TY	286	/* e6500 cannot use cpufreq due to erratum A-008083 */
	287	{ .compatible = "fsl,b4420-clockgen", &blacklist },
	288	{ .compatible = "fsl,b4860-clockgen", &blacklist },
	289	{ .compatible = "fsl,t2080-clockgen", &blacklist },
	290	{ .compatible = "fsl,t4240-clockgen", &blacklist },
	291
	292	{ .compatible = "fsl,ls1012a-clockgen", },
	293	{ .compatible = "fsl,ls1021a-clockgen", },
	294	{ .compatible = "fsl,ls1043a-clockgen", },
	295	{ .compatible = "fsl,ls1046a-clockgen", },
	296	{ .compatible = "fsl,ls1088a-clockgen", },
	297	{ .compatible = "fsl,ls2080a-clockgen", },
	298	{ .compatible = "fsl,p4080-clockgen", },
	299	{ .compatible = "fsl,qoriq-clockgen-1.0", },
defa4c73 TY	300	{ .compatible = "fsl,qoriq-clockgen-2.0", },
	301	{}
	302	};
	303
a4f20742	304	static int __init qoriq_cpufreq_init(void)
defa4c73 TY	305	{
	306	int ret;
	307	struct device_node *np;
	308	const struct of_device_id *match;
	309	const struct soc_data *data;
defa4c73 TY	310
	311	np = of_find_matching_node(NULL, node_matches);
	312	if (!np)
	313	return -ENODEV;
	314
defa4c73 TY	315	match = of_match_node(node_matches, np);
defa4c73 TY	316	data = match->data;
defa4c73 TY	317
	318	of_node_put(np);
	319
b1e9a649 TY	320	if (data && data->flags & SOC_BLACKLIST)
	321	return -ENODEV;
	322
a4f20742	323	ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
defa4c73	324	if (!ret)
a4f20742	325	pr_info("Freescale QorIQ CPU frequency scaling driver\n");
defa4c73 TY	326
defa4c73 TY	327	return ret;
defa4c73	328	}
a4f20742	329	module_init(qoriq_cpufreq_init);
defa4c73	330
a4f20742	331	static void __exit qoriq_cpufreq_exit(void)
defa4c73	332	{
a4f20742	333	cpufreq_unregister_driver(&qoriq_cpufreq_driver);
defa4c73	334	}
a4f20742	335	module_exit(qoriq_cpufreq_exit);
defa4c73 TY	336
	337	MODULE_LICENSE("GPL");
	338	MODULE_AUTHOR("Tang Yuantian <[email protected]>");
a4f20742	339	MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");