[linux.git] / drivers / gpu / drm / i915 / i915_pci.c

/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#include <linux/console.h>
#include <linux/vgaarb.h>
#include <linux/vga_switcheroo.h>

#include "i915_drv.h"
#include "i915_selftest.h"

#define GEN_DEFAULT_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }

#define GEN_CHV_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  CHV_PIPE_C_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   CHV_TRANSCODER_C_OFFSET, }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
			     CHV_PALETTE_C_OFFSET }

#define CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }

#define IVB_CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }

#define BDW_COLORS \
	.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
#define CHV_COLORS \
	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }

/* Keep in gen based order, and chronological order within a gen */
#define GEN2_FEATURES \
	.gen = 2, .num_pipes = 1, \
	.has_overlay = 1, .overlay_needs_physical = 1, \
	.has_gmch_display = 1, \
	.hws_needs_physical = 1, \
	.unfenced_needs_alignment = 1, \
	.ring_mask = RENDER_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_i830_info = {
	GEN2_FEATURES,
	.platform = INTEL_I830,
	.is_mobile = 1, .cursor_needs_physical = 1,
	.num_pipes = 2, /* legal, last one wins */
};

static const struct intel_device_info intel_i845g_info = {
	GEN2_FEATURES,
	.platform = INTEL_I845G,
};

static const struct intel_device_info intel_i85x_info = {
	GEN2_FEATURES,
	.platform = INTEL_I85X, .is_mobile = 1,
	.num_pipes = 2, /* legal, last one wins */
	.cursor_needs_physical = 1,
	.has_fbc = 1,
};

static const struct intel_device_info intel_i865g_info = {
	GEN2_FEATURES,
	.platform = INTEL_I865G,
};

#define GEN3_FEATURES \
	.gen = 3, .num_pipes = 2, \
	.has_gmch_display = 1, \
	.ring_mask = RENDER_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_i915g_info = {
	GEN3_FEATURES,
	.platform = INTEL_I915G, .cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.hws_needs_physical = 1,
	.unfenced_needs_alignment = 1,
};

static const struct intel_device_info intel_i915gm_info = {
	GEN3_FEATURES,
	.platform = INTEL_I915GM,
	.is_mobile = 1,
	.cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.supports_tv = 1,
	.has_fbc = 1,
	.hws_needs_physical = 1,
	.unfenced_needs_alignment = 1,
};

static const struct intel_device_info intel_i945g_info = {
	GEN3_FEATURES,
	.platform = INTEL_I945G,
	.has_hotplug = 1, .cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.hws_needs_physical = 1,
	.unfenced_needs_alignment = 1,
};

static const struct intel_device_info intel_i945gm_info = {
	GEN3_FEATURES,
	.platform = INTEL_I945GM, .is_mobile = 1,
	.has_hotplug = 1, .cursor_needs_physical = 1,
	.has_overlay = 1, .overlay_needs_physical = 1,
	.supports_tv = 1,
	.has_fbc = 1,
	.hws_needs_physical = 1,
	.unfenced_needs_alignment = 1,
};

static const struct intel_device_info intel_g33_info = {
	GEN3_FEATURES,
	.platform = INTEL_G33,
	.has_hotplug = 1,
	.has_overlay = 1,
};

static const struct intel_device_info intel_pineview_info = {
	GEN3_FEATURES,
	.platform = INTEL_PINEVIEW, .is_mobile = 1,
	.has_hotplug = 1,
	.has_overlay = 1,
};

#define GEN4_FEATURES \
	.gen = 4, .num_pipes = 2, \
	.has_hotplug = 1, \
	.has_gmch_display = 1, \
	.ring_mask = RENDER_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_i965g_info = {
	GEN4_FEATURES,
	.platform = INTEL_I965G,
	.has_overlay = 1,
	.hws_needs_physical = 1,
};

static const struct intel_device_info intel_i965gm_info = {
	GEN4_FEATURES,
	.platform = INTEL_I965GM,
	.is_mobile = 1, .has_fbc = 1,
	.has_overlay = 1,
	.supports_tv = 1,
	.hws_needs_physical = 1,
};

static const struct intel_device_info intel_g45_info = {
	GEN4_FEATURES,
	.platform = INTEL_G45,
	.has_pipe_cxsr = 1,
	.ring_mask = RENDER_RING | BSD_RING,
};

static const struct intel_device_info intel_gm45_info = {
	GEN4_FEATURES,
	.platform = INTEL_GM45,
	.is_mobile = 1, .has_fbc = 1,
	.has_pipe_cxsr = 1,
	.supports_tv = 1,
	.ring_mask = RENDER_RING | BSD_RING,
};

#define GEN5_FEATURES \
	.gen = 5, .num_pipes = 2, \
	.has_hotplug = 1, \
	.has_gmbus_irq = 1, \
	.ring_mask = RENDER_RING | BSD_RING, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_ironlake_d_info = {
	GEN5_FEATURES,
	.platform = INTEL_IRONLAKE,
};

static const struct intel_device_info intel_ironlake_m_info = {
	GEN5_FEATURES,
	.platform = INTEL_IRONLAKE,
	.is_mobile = 1, .has_fbc = 1,
};

#define GEN6_FEATURES \
	.gen = 6, .num_pipes = 2, \
	.has_hotplug = 1, \
	.has_fbc = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
	.has_llc = 1, \
	.has_rc6 = 1, \
	.has_rc6p = 1, \
	.has_gmbus_irq = 1, \
	.has_aliasing_ppgtt = 1, \
	GEN_DEFAULT_PIPEOFFSETS, \
	CURSOR_OFFSETS

static const struct intel_device_info intel_sandybridge_d_info = {
	GEN6_FEATURES,
	.platform = INTEL_SANDYBRIDGE,
};

static const struct intel_device_info intel_sandybridge_m_info = {
	GEN6_FEATURES,
	.platform = INTEL_SANDYBRIDGE,
	.is_mobile = 1,
};

#define GEN7_FEATURES  \
	.gen = 7, .num_pipes = 3, \
	.has_hotplug = 1, \
	.has_fbc = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
	.has_llc = 1, \
	.has_rc6 = 1, \
	.has_rc6p = 1, \
	.has_gmbus_irq = 1, \
	.has_aliasing_ppgtt = 1, \
	.has_full_ppgtt = 1, \
	GEN_DEFAULT_PIPEOFFSETS, \
	IVB_CURSOR_OFFSETS

static const struct intel_device_info intel_ivybridge_d_info = {
	GEN7_FEATURES,
	.platform = INTEL_IVYBRIDGE,
	.has_l3_dpf = 1,
};

static const struct intel_device_info intel_ivybridge_m_info = {
	GEN7_FEATURES,
	.platform = INTEL_IVYBRIDGE,
	.is_mobile = 1,
	.has_l3_dpf = 1,
};

static const struct intel_device_info intel_ivybridge_q_info = {
	GEN7_FEATURES,
	.platform = INTEL_IVYBRIDGE,
	.num_pipes = 0, /* legal, last one wins */
	.has_l3_dpf = 1,
};

static const struct intel_device_info intel_valleyview_info = {
	.platform = INTEL_VALLEYVIEW,
	.gen = 7,
	.is_lp = 1,
	.num_pipes = 2,
	.has_psr = 1,
	.has_runtime_pm = 1,
	.has_rc6 = 1,
	.has_gmbus_irq = 1,
	.has_gmch_display = 1,
	.has_hotplug = 1,
	.has_aliasing_ppgtt = 1,
	.has_full_ppgtt = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
	.display_mmio_offset = VLV_DISPLAY_BASE,
	GEN_DEFAULT_PIPEOFFSETS,
	CURSOR_OFFSETS
};

#define HSW_FEATURES  \
	GEN7_FEATURES, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
	.has_ddi = 1, \
	.has_fpga_dbg = 1, \
	.has_psr = 1, \
	.has_resource_streamer = 1, \
	.has_dp_mst = 1, \
	.has_rc6p = 0 /* RC6p removed-by HSW */, \
	.has_runtime_pm = 1

static const struct intel_device_info intel_haswell_info = {
	HSW_FEATURES,
	.platform = INTEL_HASWELL,
	.has_l3_dpf = 1,
};

#define BDW_FEATURES \
	HSW_FEATURES, \
	BDW_COLORS, \
	.has_logical_ring_contexts = 1, \
	.has_full_48bit_ppgtt = 1, \
	.has_64bit_reloc = 1

#define BDW_PLATFORM \
	BDW_FEATURES, \
	.gen = 8, \
	.platform = INTEL_BROADWELL

static const struct intel_device_info intel_broadwell_info = {
	BDW_PLATFORM,
};

static const struct intel_device_info intel_broadwell_gt3_info = {
	BDW_PLATFORM,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

static const struct intel_device_info intel_cherryview_info = {
	.gen = 8, .num_pipes = 3,
	.has_hotplug = 1,
	.is_lp = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.platform = INTEL_CHERRYVIEW,
	.has_64bit_reloc = 1,
	.has_psr = 1,
	.has_runtime_pm = 1,
	.has_resource_streamer = 1,
	.has_rc6 = 1,
	.has_gmbus_irq = 1,
	.has_logical_ring_contexts = 1,
	.has_gmch_display = 1,
	.has_aliasing_ppgtt = 1,
	.has_full_ppgtt = 1,
	.display_mmio_offset = VLV_DISPLAY_BASE,
	GEN_CHV_PIPEOFFSETS,
	CURSOR_OFFSETS,
	CHV_COLORS,
};

#define SKL_PLATFORM \
	BDW_FEATURES, \
	.gen = 9, \
	.platform = INTEL_SKYLAKE, \
	.has_csr = 1, \
	.has_guc = 1, \
	.ddb_size = 896

static const struct intel_device_info intel_skylake_info = {
	SKL_PLATFORM,
};

static const struct intel_device_info intel_skylake_gt3_info = {
	SKL_PLATFORM,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

#define GEN9_LP_FEATURES \
	.gen = 9, \
	.is_lp = 1, \
	.has_hotplug = 1, \
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
	.num_pipes = 3, \
	.has_64bit_reloc = 1, \
	.has_ddi = 1, \
	.has_fpga_dbg = 1, \
	.has_fbc = 1, \
	.has_runtime_pm = 1, \
	.has_pooled_eu = 0, \
	.has_csr = 1, \
	.has_resource_streamer = 1, \
	.has_rc6 = 1, \
	.has_dp_mst = 1, \
	.has_gmbus_irq = 1, \
	.has_logical_ring_contexts = 1, \
	.has_guc = 1, \
	.has_aliasing_ppgtt = 1, \
	.has_full_ppgtt = 1, \
	.has_full_48bit_ppgtt = 1, \
	GEN_DEFAULT_PIPEOFFSETS, \
	IVB_CURSOR_OFFSETS, \
	BDW_COLORS

static const struct intel_device_info intel_broxton_info = {
	GEN9_LP_FEATURES,
	.platform = INTEL_BROXTON,
	.ddb_size = 512,
};

static const struct intel_device_info intel_geminilake_info = {
	GEN9_LP_FEATURES,
	.platform = INTEL_GEMINILAKE,
	.ddb_size = 1024,
	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
};

#define KBL_PLATFORM \
	BDW_FEATURES, \
	.gen = 9, \
	.platform = INTEL_KABYLAKE, \
	.has_csr = 1, \
	.has_guc = 1, \
	.ddb_size = 896

static const struct intel_device_info intel_kabylake_info = {
	KBL_PLATFORM,
};

static const struct intel_device_info intel_kabylake_gt3_info = {
	KBL_PLATFORM,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

#define CFL_PLATFORM \
	.is_alpha_support = 1, \
	BDW_FEATURES, \
	.gen = 9, \
	.platform = INTEL_COFFEELAKE, \
	.has_csr = 1, \
	.has_guc = 1, \
	.ddb_size = 896

static const struct intel_device_info intel_coffeelake_info = {
	CFL_PLATFORM,
};

static const struct intel_device_info intel_coffeelake_gt3_info = {
	CFL_PLATFORM,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};

static const struct intel_device_info intel_cannonlake_info = {
	BDW_FEATURES,
	.is_alpha_support = 1,
	.platform = INTEL_CANNONLAKE,
	.gen = 10,
	.ddb_size = 1024,
	.has_csr = 1,
};

/*
 * Make sure any device matches here are from most specific to most
 * general.  For example, since the Quanta match is based on the subsystem
 * and subvendor IDs, we need it to come before the more general IVB
 * PCI ID matches, otherwise we'll use the wrong info struct above.
 */
static const struct pci_device_id pciidlist[] = {
	INTEL_I830_IDS(&intel_i830_info),
	INTEL_I845G_IDS(&intel_i845g_info),
	INTEL_I85X_IDS(&intel_i85x_info),
	INTEL_I865G_IDS(&intel_i865g_info),
	INTEL_I915G_IDS(&intel_i915g_info),
	INTEL_I915GM_IDS(&intel_i915gm_info),
	INTEL_I945G_IDS(&intel_i945g_info),
	INTEL_I945GM_IDS(&intel_i945gm_info),
	INTEL_I965G_IDS(&intel_i965g_info),
	INTEL_G33_IDS(&intel_g33_info),
	INTEL_I965GM_IDS(&intel_i965gm_info),
	INTEL_GM45_IDS(&intel_gm45_info),
	INTEL_G45_IDS(&intel_g45_info),
	INTEL_PINEVIEW_IDS(&intel_pineview_info),
	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
	INTEL_HSW_IDS(&intel_haswell_info),
	INTEL_VLV_IDS(&intel_valleyview_info),
	INTEL_BDW_GT12_IDS(&intel_broadwell_info),
	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
	INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
	INTEL_CHV_IDS(&intel_cherryview_info),
	INTEL_SKL_GT1_IDS(&intel_skylake_info),
	INTEL_SKL_GT2_IDS(&intel_skylake_info),
	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
	INTEL_BXT_IDS(&intel_broxton_info),
	INTEL_GLK_IDS(&intel_geminilake_info),
	INTEL_KBL_GT1_IDS(&intel_kabylake_info),
	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
	INTEL_CFL_S_IDS(&intel_coffeelake_info),
	INTEL_CFL_H_IDS(&intel_coffeelake_info),
	INTEL_CFL_U_IDS(&intel_coffeelake_gt3_info),
	INTEL_CNL_IDS(&intel_cannonlake_info),
	{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);

static void i915_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	i915_driver_unload(dev);
	drm_dev_unref(dev);
}

static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	struct intel_device_info *intel_info =
		(struct intel_device_info *) ent->driver_data;
	int err;

	if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
		DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
			 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
			 "to enable support in this kernel version, or check for kernel updates.\n");
		return -ENODEV;
	}

	/* Only bind to function 0 of the device. Early generations
	 * used function 1 as a placeholder for multi-head. This causes
	 * us confusion instead, especially on the systems where both
	 * functions have the same PCI-ID!
	 */
	if (PCI_FUNC(pdev->devfn))
		return -ENODEV;

	/*
	 * apple-gmux is needed on dual GPU MacBook Pro
	 * to probe the panel if we're the inactive GPU.
	 */
	if (vga_switcheroo_client_probe_defer(pdev))
		return -EPROBE_DEFER;

	err = i915_driver_load(pdev, ent);
	if (err)
		return err;

	err = i915_live_selftests(pdev);
	if (err) {
		i915_pci_remove(pdev);
		return err > 0 ? -ENOTTY : err;
	}

	return 0;
}

static struct pci_driver i915_pci_driver = {
	.name = DRIVER_NAME,
	.id_table = pciidlist,
	.probe = i915_pci_probe,
	.remove = i915_pci_remove,
	.driver.pm = &i915_pm_ops,
};

static int __init i915_init(void)
{
	bool use_kms = true;
	int err;

	err = i915_mock_selftests();
	if (err)
		return err > 0 ? 0 : err;

	/*
	 * Enable KMS by default, unless explicitly overriden by
	 * either the i915.modeset prarameter or by the
	 * vga_text_mode_force boot option.
	 */

	if (i915.modeset == 0)
		use_kms = false;

	if (vgacon_text_force() && i915.modeset == -1)
		use_kms = false;

	if (!use_kms) {
		/* Silently fail loading to not upset userspace. */
		DRM_DEBUG_DRIVER("KMS disabled.\n");
		return 0;
	}

	return pci_register_driver(&i915_pci_driver);
}

static void __exit i915_exit(void)
{
	if (!i915_pci_driver.driver.owner)
		return;

	pci_unregister_driver(&i915_pci_driver);
}

module_init(i915_init);
module_exit(i915_exit);

MODULE_AUTHOR("Tungsten Graphics, Inc.");
MODULE_AUTHOR("Intel Corporation");

MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
42f5551d CW	1	/*
	2	* Copyright © 2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
a09d0ba1	25	#include <linux/console.h>
42f5551d CW	26	#include <linux/vgaarb.h>
	27	#include <linux/vga_switcheroo.h>
	28
	29	#include "i915_drv.h"
953c7f82	30	#include "i915_selftest.h"
42f5551d CW	31
	32	#define GEN_DEFAULT_PIPEOFFSETS \
	33	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
	34	PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
	35	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
	36	TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
	37	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
	38
	39	#define GEN_CHV_PIPEOFFSETS \
	40	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
	41	CHV_PIPE_C_OFFSET }, \
	42	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
	43	CHV_TRANSCODER_C_OFFSET, }, \
	44	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
	45	CHV_PALETTE_C_OFFSET }
	46
	47	#define CURSOR_OFFSETS \
	48	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
	49
	50	#define IVB_CURSOR_OFFSETS \
	51	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
	52
	53	#define BDW_COLORS \
	54	.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
	55	#define CHV_COLORS \
	56	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
	57
a5ce929b	58	/* Keep in gen based order, and chronological order within a gen */
0eec8dc7 CS	59	#define GEN2_FEATURES \
	60	.gen = 2, .num_pipes = 1, \
	61	.has_overlay = 1, .overlay_needs_physical = 1, \
804b8712	62	.has_gmch_display = 1, \
3177659a	63	.hws_needs_physical = 1, \
f4ce766f	64	.unfenced_needs_alignment = 1, \
0eec8dc7 CS	65	.ring_mask = RENDER_RING, \
	66	GEN_DEFAULT_PIPEOFFSETS, \
	67	CURSOR_OFFSETS
	68
42f5551d	69	static const struct intel_device_info intel_i830_info = {
0eec8dc7	70	GEN2_FEATURES,
2e0d26f8	71	.platform = INTEL_I830,
0eec8dc7 CS	72	.is_mobile = 1, .cursor_needs_physical = 1,
0eec8dc7 CS	73	.num_pipes = 2, /* legal, last one wins */
42f5551d CW	74	};
42f5551d CW	75
2a307c2e	76	static const struct intel_device_info intel_i845g_info = {
0eec8dc7	77	GEN2_FEATURES,
2e0d26f8	78	.platform = INTEL_I845G,
42f5551d CW	79	};
	80
	81	static const struct intel_device_info intel_i85x_info = {
0eec8dc7	82	GEN2_FEATURES,
2e0d26f8	83	.platform = INTEL_I85X, .is_mobile = 1,
0eec8dc7	84	.num_pipes = 2, /* legal, last one wins */
42f5551d	85	.cursor_needs_physical = 1,
42f5551d	86	.has_fbc = 1,
42f5551d CW	87	};
	88
	89	static const struct intel_device_info intel_i865g_info = {
0eec8dc7	90	GEN2_FEATURES,
2e0d26f8	91	.platform = INTEL_I865G,
42f5551d CW	92	};
42f5551d CW	93
54d2a6a1 CS	94	#define GEN3_FEATURES \
54d2a6a1 CS	95	.gen = 3, .num_pipes = 2, \
804b8712	96	.has_gmch_display = 1, \
54d2a6a1 CS	97	.ring_mask = RENDER_RING, \
	98	GEN_DEFAULT_PIPEOFFSETS, \
	99	CURSOR_OFFSETS
	100
42f5551d	101	static const struct intel_device_info intel_i915g_info = {
54d2a6a1	102	GEN3_FEATURES,
2e0d26f8	103	.platform = INTEL_I915G, .cursor_needs_physical = 1,
42f5551d	104	.has_overlay = 1, .overlay_needs_physical = 1,
3177659a	105	.hws_needs_physical = 1,
f4ce766f	106	.unfenced_needs_alignment = 1,
42f5551d	107	};
a5ce929b	108
42f5551d	109	static const struct intel_device_info intel_i915gm_info = {
54d2a6a1	110	GEN3_FEATURES,
2e0d26f8	111	.platform = INTEL_I915GM,
54d2a6a1	112	.is_mobile = 1,
42f5551d CW	113	.cursor_needs_physical = 1,
	114	.has_overlay = 1, .overlay_needs_physical = 1,
	115	.supports_tv = 1,
	116	.has_fbc = 1,
3177659a	117	.hws_needs_physical = 1,
f4ce766f	118	.unfenced_needs_alignment = 1,
42f5551d	119	};
a5ce929b	120
42f5551d	121	static const struct intel_device_info intel_i945g_info = {
54d2a6a1	122	GEN3_FEATURES,
2e0d26f8	123	.platform = INTEL_I945G,
54d2a6a1	124	.has_hotplug = 1, .cursor_needs_physical = 1,
42f5551d	125	.has_overlay = 1, .overlay_needs_physical = 1,
3177659a	126	.hws_needs_physical = 1,
f4ce766f	127	.unfenced_needs_alignment = 1,
42f5551d	128	};
a5ce929b	129
42f5551d	130	static const struct intel_device_info intel_i945gm_info = {
54d2a6a1	131	GEN3_FEATURES,
2e0d26f8	132	.platform = INTEL_I945GM, .is_mobile = 1,
42f5551d CW	133	.has_hotplug = 1, .cursor_needs_physical = 1,
	134	.has_overlay = 1, .overlay_needs_physical = 1,
	135	.supports_tv = 1,
	136	.has_fbc = 1,
3177659a	137	.hws_needs_physical = 1,
f4ce766f	138	.unfenced_needs_alignment = 1,
42f5551d CW	139	};
42f5551d CW	140
a5ce929b JN	141	static const struct intel_device_info intel_g33_info = {
	142	GEN3_FEATURES,
	143	.platform = INTEL_G33,
	144	.has_hotplug = 1,
	145	.has_overlay = 1,
	146	};
	147
	148	static const struct intel_device_info intel_pineview_info = {
	149	GEN3_FEATURES,
73f67aa8	150	.platform = INTEL_PINEVIEW, .is_mobile = 1,
a5ce929b JN	151	.has_hotplug = 1,
	152	.has_overlay = 1,
	153	};
	154
4d495bea CS	155	#define GEN4_FEATURES \
	156	.gen = 4, .num_pipes = 2, \
	157	.has_hotplug = 1, \
804b8712	158	.has_gmch_display = 1, \
4d495bea CS	159	.ring_mask = RENDER_RING, \
	160	GEN_DEFAULT_PIPEOFFSETS, \
	161	CURSOR_OFFSETS
	162
42f5551d	163	static const struct intel_device_info intel_i965g_info = {
4d495bea	164	GEN4_FEATURES,
c0f86832	165	.platform = INTEL_I965G,
42f5551d	166	.has_overlay = 1,
3177659a	167	.hws_needs_physical = 1,
42f5551d CW	168	};
	169
	170	static const struct intel_device_info intel_i965gm_info = {
4d495bea	171	GEN4_FEATURES,
c0f86832	172	.platform = INTEL_I965GM,
4d495bea	173	.is_mobile = 1, .has_fbc = 1,
42f5551d CW	174	.has_overlay = 1,
42f5551d CW	175	.supports_tv = 1,
3177659a	176	.hws_needs_physical = 1,
42f5551d CW	177	};
42f5551d CW	178
42f5551d	179	static const struct intel_device_info intel_g45_info = {
4d495bea	180	GEN4_FEATURES,
f69c11ae	181	.platform = INTEL_G45,
4d495bea	182	.has_pipe_cxsr = 1,
42f5551d	183	.ring_mask = RENDER_RING \| BSD_RING,
42f5551d CW	184	};
	185
	186	static const struct intel_device_info intel_gm45_info = {
4d495bea	187	GEN4_FEATURES,
f69c11ae	188	.platform = INTEL_GM45,
3177659a	189	.is_mobile = 1, .has_fbc = 1,
4d495bea	190	.has_pipe_cxsr = 1,
42f5551d CW	191	.supports_tv = 1,
42f5551d CW	192	.ring_mask = RENDER_RING \| BSD_RING,
42f5551d CW	193	};
42f5551d CW	194
a1323380 CS	195	#define GEN5_FEATURES \
a1323380 CS	196	.gen = 5, .num_pipes = 2, \
3177659a	197	.has_hotplug = 1, \
b355f109	198	.has_gmbus_irq = 1, \
a1323380 CS	199	.ring_mask = RENDER_RING \| BSD_RING, \
	200	GEN_DEFAULT_PIPEOFFSETS, \
	201	CURSOR_OFFSETS
	202
42f5551d	203	static const struct intel_device_info intel_ironlake_d_info = {
a1323380	204	GEN5_FEATURES,
2e0d26f8	205	.platform = INTEL_IRONLAKE,
42f5551d CW	206	};
	207
	208	static const struct intel_device_info intel_ironlake_m_info = {
a1323380	209	GEN5_FEATURES,
2e0d26f8	210	.platform = INTEL_IRONLAKE,
c2d1a0ce	211	.is_mobile = 1, .has_fbc = 1,
42f5551d CW	212	};
42f5551d CW	213
07db6be7 CS	214	#define GEN6_FEATURES \
07db6be7 CS	215	.gen = 6, .num_pipes = 2, \
3177659a	216	.has_hotplug = 1, \
07db6be7 CS	217	.has_fbc = 1, \
	218	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING, \
	219	.has_llc = 1, \
86f3624b	220	.has_rc6 = 1, \
33b5bf82	221	.has_rc6p = 1, \
b355f109	222	.has_gmbus_irq = 1, \
9e1d0e60	223	.has_aliasing_ppgtt = 1, \
07db6be7 CS	224	GEN_DEFAULT_PIPEOFFSETS, \
	225	CURSOR_OFFSETS
	226
42f5551d	227	static const struct intel_device_info intel_sandybridge_d_info = {
07db6be7	228	GEN6_FEATURES,
2e0d26f8	229	.platform = INTEL_SANDYBRIDGE,
42f5551d CW	230	};
	231
	232	static const struct intel_device_info intel_sandybridge_m_info = {
07db6be7	233	GEN6_FEATURES,
2e0d26f8	234	.platform = INTEL_SANDYBRIDGE,
07db6be7	235	.is_mobile = 1,
42f5551d CW	236	};
	237
	238	#define GEN7_FEATURES \
	239	.gen = 7, .num_pipes = 3, \
3177659a	240	.has_hotplug = 1, \
42f5551d CW	241	.has_fbc = 1, \
	242	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING, \
	243	.has_llc = 1, \
86f3624b	244	.has_rc6 = 1, \
33b5bf82	245	.has_rc6p = 1, \
b355f109	246	.has_gmbus_irq = 1, \
9e1d0e60 MT	247	.has_aliasing_ppgtt = 1, \
9e1d0e60 MT	248	.has_full_ppgtt = 1, \
42f5551d CW	249	GEN_DEFAULT_PIPEOFFSETS, \
	250	IVB_CURSOR_OFFSETS
	251
	252	static const struct intel_device_info intel_ivybridge_d_info = {
	253	GEN7_FEATURES,
2e0d26f8	254	.platform = INTEL_IVYBRIDGE,
ca9c4523	255	.has_l3_dpf = 1,
42f5551d CW	256	};
	257
	258	static const struct intel_device_info intel_ivybridge_m_info = {
	259	GEN7_FEATURES,
2e0d26f8	260	.platform = INTEL_IVYBRIDGE,
42f5551d	261	.is_mobile = 1,
ca9c4523	262	.has_l3_dpf = 1,
42f5551d CW	263	};
	264
	265	static const struct intel_device_info intel_ivybridge_q_info = {
	266	GEN7_FEATURES,
2e0d26f8	267	.platform = INTEL_IVYBRIDGE,
42f5551d	268	.num_pipes = 0, /* legal, last one wins */
ca9c4523	269	.has_l3_dpf = 1,
42f5551d CW	270	};
42f5551d CW	271
8d9c20e1	272	static const struct intel_device_info intel_valleyview_info = {
2e0d26f8	273	.platform = INTEL_VALLEYVIEW,
eb6f771b RV	274	.gen = 7,
	275	.is_lp = 1,
	276	.num_pipes = 2,
	277	.has_psr = 1,
	278	.has_runtime_pm = 1,
	279	.has_rc6 = 1,
	280	.has_gmbus_irq = 1,
eb6f771b RV	281	.has_gmch_display = 1,
	282	.has_hotplug = 1,
	283	.has_aliasing_ppgtt = 1,
	284	.has_full_ppgtt = 1,
	285	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING,
	286	.display_mmio_offset = VLV_DISPLAY_BASE,
	287	GEN_DEFAULT_PIPEOFFSETS,
	288	CURSOR_OFFSETS
42f5551d CW	289	};
	290
	291	#define HSW_FEATURES \
	292	GEN7_FEATURES, \
	293	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING, \
	294	.has_ddi = 1, \
6e3b84d8	295	.has_fpga_dbg = 1, \
4aa4c23f	296	.has_psr = 1, \
53233f08	297	.has_resource_streamer = 1, \
1d3fe53b	298	.has_dp_mst = 1, \
33b5bf82	299	.has_rc6p = 0 /* RC6p removed-by HSW */, \
4aa4c23f	300	.has_runtime_pm = 1
42f5551d	301
8d9c20e1	302	static const struct intel_device_info intel_haswell_info = {
42f5551d	303	HSW_FEATURES,
2e0d26f8	304	.platform = INTEL_HASWELL,
ca9c4523	305	.has_l3_dpf = 1,
42f5551d CW	306	};
42f5551d CW	307
42f5551d CW	308	#define BDW_FEATURES \
42f5551d CW	309	HSW_FEATURES, \
4586f1d0	310	BDW_COLORS, \
dfc5148f	311	.has_logical_ring_contexts = 1, \
9e1d0e60	312	.has_full_48bit_ppgtt = 1, \
dfc5148f	313	.has_64bit_reloc = 1
42f5551d	314
94829de4 RV	315	#define BDW_PLATFORM \
	316	BDW_FEATURES, \
	317	.gen = 8, \
	318	.platform = INTEL_BROADWELL
	319
8d9c20e1	320	static const struct intel_device_info intel_broadwell_info = {
94829de4	321	BDW_PLATFORM,
42f5551d CW	322	};
42f5551d CW	323
8d9c20e1	324	static const struct intel_device_info intel_broadwell_gt3_info = {
94829de4	325	BDW_PLATFORM,
42f5551d CW	326	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
	327	};
	328
42f5551d CW	329	static const struct intel_device_info intel_cherryview_info = {
42f5551d CW	330	.gen = 8, .num_pipes = 3,
3177659a	331	.has_hotplug = 1,
8727dc09	332	.is_lp = 1,
42f5551d	333	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING,
2e0d26f8	334	.platform = INTEL_CHERRYVIEW,
dfc5148f	335	.has_64bit_reloc = 1,
6e3b84d8	336	.has_psr = 1,
4aa4c23f	337	.has_runtime_pm = 1,
53233f08	338	.has_resource_streamer = 1,
86f3624b	339	.has_rc6 = 1,
b355f109	340	.has_gmbus_irq = 1,
4586f1d0	341	.has_logical_ring_contexts = 1,
804b8712	342	.has_gmch_display = 1,
9e1d0e60 MT	343	.has_aliasing_ppgtt = 1,
9e1d0e60 MT	344	.has_full_ppgtt = 1,
42f5551d CW	345	.display_mmio_offset = VLV_DISPLAY_BASE,
	346	GEN_CHV_PIPEOFFSETS,
	347	CURSOR_OFFSETS,
	348	CHV_COLORS,
	349	};
	350
94829de4 RV	351	#define SKL_PLATFORM \
	352	BDW_FEATURES, \
	353	.gen = 9, \
	354	.platform = INTEL_SKYLAKE, \
	355	.has_csr = 1, \
	356	.has_guc = 1, \
	357	.ddb_size = 896
	358
42f5551d	359	static const struct intel_device_info intel_skylake_info = {
94829de4	360	SKL_PLATFORM,
42f5551d CW	361	};
	362
	363	static const struct intel_device_info intel_skylake_gt3_info = {
94829de4	364	SKL_PLATFORM,
42f5551d CW	365	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
	366	};
	367
80fa66b6 RV	368	#define GEN9_LP_FEATURES \
80fa66b6 RV	369	.gen = 9, \
3e4274f8	370	.is_lp = 1, \
80fa66b6 RV	371	.has_hotplug = 1, \
	372	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING, \
	373	.num_pipes = 3, \
	374	.has_64bit_reloc = 1, \
	375	.has_ddi = 1, \
	376	.has_fpga_dbg = 1, \
	377	.has_fbc = 1, \
	378	.has_runtime_pm = 1, \
	379	.has_pooled_eu = 0, \
	380	.has_csr = 1, \
	381	.has_resource_streamer = 1, \
	382	.has_rc6 = 1, \
	383	.has_dp_mst = 1, \
	384	.has_gmbus_irq = 1, \
80fa66b6 RV	385	.has_logical_ring_contexts = 1, \
80fa66b6 RV	386	.has_guc = 1, \
9e1d0e60 MT	387	.has_aliasing_ppgtt = 1, \
	388	.has_full_ppgtt = 1, \
	389	.has_full_48bit_ppgtt = 1, \
80fa66b6 RV	390	GEN_DEFAULT_PIPEOFFSETS, \
	391	IVB_CURSOR_OFFSETS, \
	392	BDW_COLORS
	393
42f5551d	394	static const struct intel_device_info intel_broxton_info = {
80fa66b6	395	GEN9_LP_FEATURES,
2e0d26f8	396	.platform = INTEL_BROXTON,
6f3fff60	397	.ddb_size = 512,
42f5551d CW	398	};
42f5551d CW	399
c22097fa	400	static const struct intel_device_info intel_geminilake_info = {
c22097fa	401	GEN9_LP_FEATURES,
2e0d26f8	402	.platform = INTEL_GEMINILAKE,
c22097fa	403	.ddb_size = 1024,
9751bafc	404	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
c22097fa ACO	405	};
c22097fa ACO	406
94829de4 RV	407	#define KBL_PLATFORM \
	408	BDW_FEATURES, \
	409	.gen = 9, \
	410	.platform = INTEL_KABYLAKE, \
	411	.has_csr = 1, \
	412	.has_guc = 1, \
	413	.ddb_size = 896
	414
42f5551d	415	static const struct intel_device_info intel_kabylake_info = {
94829de4	416	KBL_PLATFORM,
42f5551d CW	417	};
	418
	419	static const struct intel_device_info intel_kabylake_gt3_info = {
94829de4	420	KBL_PLATFORM,
42f5551d CW	421	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
	422	};
	423
71851fa8 RV	424	#define CFL_PLATFORM \
	425	.is_alpha_support = 1, \
	426	BDW_FEATURES, \
	427	.gen = 9, \
	428	.platform = INTEL_COFFEELAKE, \
84cd843e	429	.has_csr = 1, \
c0f82960	430	.has_guc = 1, \
71851fa8 RV	431	.ddb_size = 896
	432
	433	static const struct intel_device_info intel_coffeelake_info = {
	434	CFL_PLATFORM,
	435	};
	436
	437	static const struct intel_device_info intel_coffeelake_gt3_info = {
	438	CFL_PLATFORM,
	439	.ring_mask = RENDER_RING \| BSD_RING \| BLT_RING \| VEBOX_RING \| BSD2_RING,
	440	};
	441
413f3c19 RV	442	static const struct intel_device_info intel_cannonlake_info = {
	443	BDW_FEATURES,
	444	.is_alpha_support = 1,
	445	.platform = INTEL_CANNONLAKE,
	446	.gen = 10,
	447	.ddb_size = 1024,
cebfcead	448	.has_csr = 1,
413f3c19 RV	449	};
413f3c19 RV	450
42f5551d CW	451	/*
	452	* Make sure any device matches here are from most specific to most
	453	* general. For example, since the Quanta match is based on the subsystem
	454	* and subvendor IDs, we need it to come before the more general IVB
	455	* PCI ID matches, otherwise we'll use the wrong info struct above.
	456	*/
	457	static const struct pci_device_id pciidlist[] = {
	458	INTEL_I830_IDS(&intel_i830_info),
2a307c2e	459	INTEL_I845G_IDS(&intel_i845g_info),
42f5551d CW	460	INTEL_I85X_IDS(&intel_i85x_info),
	461	INTEL_I865G_IDS(&intel_i865g_info),
	462	INTEL_I915G_IDS(&intel_i915g_info),
	463	INTEL_I915GM_IDS(&intel_i915gm_info),
	464	INTEL_I945G_IDS(&intel_i945g_info),
	465	INTEL_I945GM_IDS(&intel_i945gm_info),
	466	INTEL_I965G_IDS(&intel_i965g_info),
	467	INTEL_G33_IDS(&intel_g33_info),
	468	INTEL_I965GM_IDS(&intel_i965gm_info),
	469	INTEL_GM45_IDS(&intel_gm45_info),
	470	INTEL_G45_IDS(&intel_g45_info),
	471	INTEL_PINEVIEW_IDS(&intel_pineview_info),
	472	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
	473	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
	474	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
	475	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
	476	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
	477	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
	478	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
8d9c20e1 CS	479	INTEL_HSW_IDS(&intel_haswell_info),
	480	INTEL_VLV_IDS(&intel_valleyview_info),
	481	INTEL_BDW_GT12_IDS(&intel_broadwell_info),
	482	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
98b2f01c	483	INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
42f5551d CW	484	INTEL_CHV_IDS(&intel_cherryview_info),
	485	INTEL_SKL_GT1_IDS(&intel_skylake_info),
	486	INTEL_SKL_GT2_IDS(&intel_skylake_info),
	487	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
	488	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
	489	INTEL_BXT_IDS(&intel_broxton_info),
8363e3c3	490	INTEL_GLK_IDS(&intel_geminilake_info),
42f5551d CW	491	INTEL_KBL_GT1_IDS(&intel_kabylake_info),
	492	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
	493	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
	494	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
b056f8f3	495	INTEL_CFL_S_IDS(&intel_coffeelake_info),
ccfd1321	496	INTEL_CFL_H_IDS(&intel_coffeelake_info),
d29fe702	497	INTEL_CFL_U_IDS(&intel_coffeelake_gt3_info),
e918d79a	498	INTEL_CNL_IDS(&intel_cannonlake_info),
42f5551d CW	499	{0, 0, 0}
	500	};
	501	MODULE_DEVICE_TABLE(pci, pciidlist);
	502
953c7f82 CW	503	static void i915_pci_remove(struct pci_dev *pdev)
	504	{
	505	struct drm_device *dev = pci_get_drvdata(pdev);
	506
	507	i915_driver_unload(dev);
	508	drm_dev_unref(dev);
	509	}
	510
42f5551d CW	511	static int i915_pci_probe(struct pci_dev pdev, const struct pci_device_id ent)
	512	{
	513	struct intel_device_info *intel_info =
	514	(struct intel_device_info *) ent->driver_data;
953c7f82	515	int err;
42f5551d	516
c007fb4a JN	517	if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
	518	DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
	519	"See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
	520	"to enable support in this kernel version, or check for kernel updates.\n");
42f5551d CW	521	return -ENODEV;
	522	}
	523
	524	/* Only bind to function 0 of the device. Early generations
	525	* used function 1 as a placeholder for multi-head. This causes
	526	* us confusion instead, especially on the systems where both
	527	* functions have the same PCI-ID!
	528	*/
	529	if (PCI_FUNC(pdev->devfn))
	530	return -ENODEV;
	531
	532	/*
	533	* apple-gmux is needed on dual GPU MacBook Pro
	534	* to probe the panel if we're the inactive GPU.
	535	*/
	536	if (vga_switcheroo_client_probe_defer(pdev))
	537	return -EPROBE_DEFER;
	538
953c7f82 CW	539	err = i915_driver_load(pdev, ent);
	540	if (err)
	541	return err;
42f5551d	542
953c7f82 CW	543	err = i915_live_selftests(pdev);
	544	if (err) {
	545	i915_pci_remove(pdev);
	546	return err > 0 ? -ENOTTY : err;
	547	}
42f5551d	548
953c7f82	549	return 0;
42f5551d CW	550	}
42f5551d CW	551
a09d0ba1	552	static struct pci_driver i915_pci_driver = {
42f5551d CW	553	.name = DRIVER_NAME,
	554	.id_table = pciidlist,
	555	.probe = i915_pci_probe,
	556	.remove = i915_pci_remove,
	557	.driver.pm = &i915_pm_ops,
	558	};
a09d0ba1 CW	559
	560	static int __init i915_init(void)
	561	{
	562	bool use_kms = true;
953c7f82 CW	563	int err;
	564
	565	err = i915_mock_selftests();
	566	if (err)
	567	return err > 0 ? 0 : err;
a09d0ba1 CW	568
	569	/*
	570	* Enable KMS by default, unless explicitly overriden by
	571	* either the i915.modeset prarameter or by the
	572	* vga_text_mode_force boot option.
	573	*/
	574
	575	if (i915.modeset == 0)
	576	use_kms = false;
	577
	578	if (vgacon_text_force() && i915.modeset == -1)
	579	use_kms = false;
	580
	581	if (!use_kms) {
	582	/* Silently fail loading to not upset userspace. */
	583	DRM_DEBUG_DRIVER("KMS disabled.\n");
	584	return 0;
	585	}
	586
	587	return pci_register_driver(&i915_pci_driver);
	588	}
	589
	590	static void __exit i915_exit(void)
	591	{
	592	if (!i915_pci_driver.driver.owner)
	593	return;
	594
	595	pci_unregister_driver(&i915_pci_driver);
	596	}
	597
	598	module_init(i915_init);
	599	module_exit(i915_exit);
	600
	601	MODULE_AUTHOR("Tungsten Graphics, Inc.");
	602	MODULE_AUTHOR("Intel Corporation");
	603
	604	MODULE_DESCRIPTION(DRIVER_DESC);
	605	MODULE_LICENSE("GPL and additional rights");