[linux.git] / arch / sh / mm / cache-sh2a.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * arch/sh/mm/cache-sh2a.c
 *
 * Copyright (C) 2008 Yoshinori Sato
 */

#include <linux/init.h>
#include <linux/mm.h>

#include <asm/cache.h>
#include <asm/addrspace.h>
#include <asm/processor.h>
#include <asm/cacheflush.h>
#include <asm/io.h>

/*
 * The maximum number of pages we support up to when doing ranged dcache
 * flushing. Anything exceeding this will simply flush the dcache in its
 * entirety.
 */
#define MAX_OCACHE_PAGES	32
#define MAX_ICACHE_PAGES	32

#ifdef CONFIG_CACHE_WRITEBACK
static void sh2a_flush_oc_line(unsigned long v, int way)
{
	unsigned long addr = (v & 0x000007f0) | (way << 11);
	unsigned long data;

	data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr);
	if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
		data &= ~SH_CACHE_UPDATED;
		__raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr);
	}
}
#endif

static void sh2a_invalidate_line(unsigned long cache_addr, unsigned long v)
{
	/* Set associative bit to hit all ways */
	unsigned long addr = (v & 0x000007f0) | SH_CACHE_ASSOC;
	__raw_writel((addr & CACHE_PHYSADDR_MASK), cache_addr | addr);
}

/*
 * Write back the dirty D-caches, but not invalidate them.
 */
static void sh2a__flush_wback_region(void *start, int size)
{
#ifdef CONFIG_CACHE_WRITEBACK
	unsigned long v;
	unsigned long begin, end;
	unsigned long flags;
	int nr_ways;

	begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
	end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
		& ~(L1_CACHE_BYTES-1);
	nr_ways = current_cpu_data.dcache.ways;

	local_irq_save(flags);
	jump_to_uncached();

	/* If there are too many pages then flush the entire cache */
	if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
		begin = CACHE_OC_ADDRESS_ARRAY;
		end = begin + (nr_ways * current_cpu_data.dcache.way_size);

		for (v = begin; v < end; v += L1_CACHE_BYTES) {
			unsigned long data = __raw_readl(v);
			if (data & SH_CACHE_UPDATED)
				__raw_writel(data & ~SH_CACHE_UPDATED, v);
		}
	} else {
		int way;
		for (way = 0; way < nr_ways; way++) {
			for (v = begin; v < end; v += L1_CACHE_BYTES)
				sh2a_flush_oc_line(v, way);
		}
	}

	back_to_cached();
	local_irq_restore(flags);
#endif
}

/*
 * Write back the dirty D-caches and invalidate them.
 */
static void sh2a__flush_purge_region(void *start, int size)
{
	unsigned long v;
	unsigned long begin, end;
	unsigned long flags;

	begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
	end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
		& ~(L1_CACHE_BYTES-1);

	local_irq_save(flags);
	jump_to_uncached();

	for (v = begin; v < end; v+=L1_CACHE_BYTES) {
#ifdef CONFIG_CACHE_WRITEBACK
		int way;
		int nr_ways = current_cpu_data.dcache.ways;
		for (way = 0; way < nr_ways; way++)
			sh2a_flush_oc_line(v, way);
#endif
		sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
	}

	back_to_cached();
	local_irq_restore(flags);
}

/*
 * Invalidate the D-caches, but no write back please
 */
static void sh2a__flush_invalidate_region(void *start, int size)
{
	unsigned long v;
	unsigned long begin, end;
	unsigned long flags;

	begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
	end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
		& ~(L1_CACHE_BYTES-1);

	local_irq_save(flags);
	jump_to_uncached();

	/* If there are too many pages then just blow the cache */
	if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
		__raw_writel(__raw_readl(SH_CCR) | CCR_OCACHE_INVALIDATE,
			     SH_CCR);
	} else {
		for (v = begin; v < end; v += L1_CACHE_BYTES)
			sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
	}

	back_to_cached();
	local_irq_restore(flags);
}

/*
 * Write back the range of D-cache, and purge the I-cache.
 */
static void sh2a_flush_icache_range(void *args)
{
	struct flusher_data *data = args;
	unsigned long start, end;
	unsigned long v;
	unsigned long flags;

	start = data->addr1 & ~(L1_CACHE_BYTES-1);
	end = (data->addr2 + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1);

#ifdef CONFIG_CACHE_WRITEBACK
	sh2a__flush_wback_region((void *)start, end-start);
#endif

	local_irq_save(flags);
	jump_to_uncached();

	/* I-Cache invalidate */
	/* If there are too many pages then just blow the cache */
	if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
		__raw_writel(__raw_readl(SH_CCR) | CCR_ICACHE_INVALIDATE,
			     SH_CCR);
	} else {
		for (v = start; v < end; v += L1_CACHE_BYTES)
			sh2a_invalidate_line(CACHE_IC_ADDRESS_ARRAY, v);
	}

	back_to_cached();
	local_irq_restore(flags);
}

void __init sh2a_cache_init(void)
{
	local_flush_icache_range	= sh2a_flush_icache_range;

	__flush_wback_region		= sh2a__flush_wback_region;
	__flush_purge_region		= sh2a__flush_purge_region;
	__flush_invalidate_region	= sh2a__flush_invalidate_region;
}
Commit	Line	Data
c456cfc2	1	// SPDX-License-Identifier: GPL-2.0-only
cce2d453 YS	2	/*
	3	* arch/sh/mm/cache-sh2a.c
	4	*
	5	* Copyright (C) 2008 Yoshinori Sato
cce2d453 YS	6	*/
	7
	8	#include <linux/init.h>
	9	#include <linux/mm.h>
	10
	11	#include <asm/cache.h>
	12	#include <asm/addrspace.h>
	13	#include <asm/processor.h>
	14	#include <asm/cacheflush.h>
	15	#include <asm/io.h>
	16
c1537b48 PE	17	/*
	18	* The maximum number of pages we support up to when doing ranged dcache
	19	* flushing. Anything exceeding this will simply flush the dcache in its
	20	* entirety.
	21	*/
	22	#define MAX_OCACHE_PAGES 32
	23	#define MAX_ICACHE_PAGES 32
	24
1ae911cb	25	#ifdef CONFIG_CACHE_WRITEBACK
c1537b48 PE	26	static void sh2a_flush_oc_line(unsigned long v, int way)
	27	{
	28	unsigned long addr = (v & 0x000007f0) \| (way << 11);
	29	unsigned long data;
	30
	31	data = __raw_readl(CACHE_OC_ADDRESS_ARRAY \| addr);
	32	if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
	33	data &= ~SH_CACHE_UPDATED;
	34	__raw_writel(data, CACHE_OC_ADDRESS_ARRAY \| addr);
	35	}
	36	}
1ae911cb	37	#endif
c1537b48 PE	38
	39	static void sh2a_invalidate_line(unsigned long cache_addr, unsigned long v)
	40	{
	41	/* Set associative bit to hit all ways */
	42	unsigned long addr = (v & 0x000007f0) \| SH_CACHE_ASSOC;
	43	__raw_writel((addr & CACHE_PHYSADDR_MASK), cache_addr \| addr);
	44	}
	45
	46	/*
	47	* Write back the dirty D-caches, but not invalidate them.
	48	*/
a58e1a2a	49	static void sh2a__flush_wback_region(void *start, int size)
cce2d453	50	{
c1537b48	51	#ifdef CONFIG_CACHE_WRITEBACK
cce2d453 YS	52	unsigned long v;
	53	unsigned long begin, end;
	54	unsigned long flags;
c1537b48	55	int nr_ways;
cce2d453 YS	56
	57	begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
	58	end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
	59	& ~(L1_CACHE_BYTES-1);
c1537b48	60	nr_ways = current_cpu_data.dcache.ways;
cce2d453 YS	61
	62	local_irq_save(flags);
	63	jump_to_uncached();
	64
c1537b48 PE	65	/* If there are too many pages then flush the entire cache */
	66	if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
	67	begin = CACHE_OC_ADDRESS_ARRAY;
	68	end = begin + (nr_ways * current_cpu_data.dcache.way_size);
	69
	70	for (v = begin; v < end; v += L1_CACHE_BYTES) {
	71	unsigned long data = __raw_readl(v);
	72	if (data & SH_CACHE_UPDATED)
	73	__raw_writel(data & ~SH_CACHE_UPDATED, v);
	74	}
	75	} else {
cce2d453	76	int way;
c1537b48 PE	77	for (way = 0; way < nr_ways; way++) {
	78	for (v = begin; v < end; v += L1_CACHE_BYTES)
	79	sh2a_flush_oc_line(v, way);
cce2d453 YS	80	}
	81	}
	82
	83	back_to_cached();
	84	local_irq_restore(flags);
c1537b48	85	#endif
cce2d453 YS	86	}
cce2d453 YS	87
c1537b48 PE	88	/*
	89	* Write back the dirty D-caches and invalidate them.
	90	*/
a58e1a2a	91	static void sh2a__flush_purge_region(void *start, int size)
cce2d453 YS	92	{
	93	unsigned long v;
	94	unsigned long begin, end;
	95	unsigned long flags;
	96
	97	begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
	98	end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
	99	& ~(L1_CACHE_BYTES-1);
	100
	101	local_irq_save(flags);
	102	jump_to_uncached();
	103
	104	for (v = begin; v < end; v+=L1_CACHE_BYTES) {
c1537b48 PE	105	#ifdef CONFIG_CACHE_WRITEBACK
	106	int way;
	107	int nr_ways = current_cpu_data.dcache.ways;
	108	for (way = 0; way < nr_ways; way++)
	109	sh2a_flush_oc_line(v, way);
	110	#endif
	111	sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
cce2d453	112	}
c1537b48	113
cce2d453 YS	114	back_to_cached();
	115	local_irq_restore(flags);
	116	}
	117
c1537b48 PE	118	/*
	119	* Invalidate the D-caches, but no write back please
	120	*/
a58e1a2a	121	static void sh2a__flush_invalidate_region(void *start, int size)
cce2d453 YS	122	{
	123	unsigned long v;
	124	unsigned long begin, end;
	125	unsigned long flags;
	126
	127	begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
	128	end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
	129	& ~(L1_CACHE_BYTES-1);
c1537b48	130
cce2d453 YS	131	local_irq_save(flags);
	132	jump_to_uncached();
	133
c1537b48 PE	134	/* If there are too many pages then just blow the cache */
c1537b48 PE	135	if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
a5f6ea29 GU	136	__raw_writel(__raw_readl(SH_CCR) \| CCR_OCACHE_INVALIDATE,
a5f6ea29 GU	137	SH_CCR);
c1537b48 PE	138	} else {
	139	for (v = begin; v < end; v += L1_CACHE_BYTES)
	140	sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
cce2d453	141	}
c1537b48	142
cce2d453 YS	143	back_to_cached();
	144	local_irq_restore(flags);
	145	}
	146
c1537b48 PE	147	/*
	148	* Write back the range of D-cache, and purge the I-cache.
	149	*/
f26b2a56	150	static void sh2a_flush_icache_range(void *args)
cce2d453	151	{
f26b2a56 PM	152	struct flusher_data *data = args;
f26b2a56 PM	153	unsigned long start, end;
cce2d453	154	unsigned long v;
983f4c51	155	unsigned long flags;
cce2d453	156
f26b2a56 PM	157	start = data->addr1 & ~(L1_CACHE_BYTES-1);
f26b2a56 PM	158	end = (data->addr2 + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1);
cce2d453	159
c1537b48 PE	160	#ifdef CONFIG_CACHE_WRITEBACK
	161	sh2a__flush_wback_region((void *)start, end-start);
	162	#endif
	163
983f4c51	164	local_irq_save(flags);
cce2d453 YS	165	jump_to_uncached();
cce2d453 YS	166
c1537b48 PE	167	/* I-Cache invalidate */
	168	/* If there are too many pages then just blow the cache */
	169	if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
a5f6ea29 GU	170	__raw_writel(__raw_readl(SH_CCR) \| CCR_ICACHE_INVALIDATE,
a5f6ea29 GU	171	SH_CCR);
c1537b48 PE	172	} else {
	173	for (v = start; v < end; v += L1_CACHE_BYTES)
	174	sh2a_invalidate_line(CACHE_IC_ADDRESS_ARRAY, v);
cce2d453 YS	175	}
	176
	177	back_to_cached();
983f4c51	178	local_irq_restore(flags);
cce2d453	179	}
a58e1a2a PM	180
	181	void __init sh2a_cache_init(void)
	182	{
f26b2a56	183	local_flush_icache_range = sh2a_flush_icache_range;
a58e1a2a PM	184
	185	__flush_wback_region = sh2a__flush_wback_region;
	186	__flush_purge_region = sh2a__flush_purge_region;
	187	__flush_invalidate_region = sh2a__flush_invalidate_region;
	188	}