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net: phy: fix phylib's dual eee_enabled
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2874c5fd 1/* SPDX-License-Identifier: GPL-2.0-or-later */
00db8189 2/*
00db8189 3 * Framework and drivers for configuring and reading different PHYs
d8de01b7 4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
00db8189
AF
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
00db8189
AF
9 */
10
11#ifndef __PHY_H
12#define __PHY_H
13
2220943a 14#include <linux/compiler.h>
00db8189 15#include <linux/spinlock.h>
13df29f6 16#include <linux/ethtool.h>
01e5b728 17#include <linux/leds.h>
b31cdffa 18#include <linux/linkmode.h>
a68a8138 19#include <linux/netlink.h>
bac83c65 20#include <linux/mdio.h>
13df29f6 21#include <linux/mii.h>
4715f65f 22#include <linux/mii_timestamper.h>
3e3aaf64 23#include <linux/module.h>
13df29f6
MR
24#include <linux/timer.h>
25#include <linux/workqueue.h>
8626d3b4 26#include <linux/mod_devicetable.h>
080bb352 27#include <linux/u64_stats_sync.h>
9010f9de 28#include <linux/irqreturn.h>
bd971ff0 29#include <linux/iopoll.h>
63490847 30#include <linux/refcount.h>
00db8189 31
60063497 32#include <linux/atomic.h>
fe0d4fd9 33#include <net/eee.h>
0ac49527 34
e9fbdf17 35#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \
00db8189
AF
36 SUPPORTED_TP | \
37 SUPPORTED_MII)
38
e9fbdf17
FF
39#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \
40 SUPPORTED_10baseT_Full)
41
42#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \
43 SUPPORTED_100baseT_Full)
44
45#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \
00db8189
AF
46 SUPPORTED_1000baseT_Full)
47
719655a1
AL
48extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init;
49extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;
16178c8e 50extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1s_p2mp_features) __ro_after_init;
719655a1
AL
51extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
52extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init;
53extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init;
54extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init;
9e857a40 55extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_fec_features) __ro_after_init;
719655a1 56extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init;
14e47d1f 57extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap1_features) __ro_after_init;
ef6ee3a3 58extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap2_features) __ro_after_init;
719655a1
AL
59
60#define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features)
61#define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features)
16178c8e 62#define PHY_BASIC_T1S_P2MP_FEATURES ((unsigned long *)&phy_basic_t1s_p2mp_features)
719655a1
AL
63#define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features)
64#define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features)
65#define PHY_GBIT_ALL_PORTS_FEATURES ((unsigned long *)&phy_gbit_all_ports_features)
66#define PHY_10GBIT_FEATURES ((unsigned long *)&phy_10gbit_features)
9e857a40 67#define PHY_10GBIT_FEC_FEATURES ((unsigned long *)&phy_10gbit_fec_features)
719655a1 68#define PHY_10GBIT_FULL_FEATURES ((unsigned long *)&phy_10gbit_full_features)
14e47d1f 69#define PHY_EEE_CAP1_FEATURES ((unsigned long *)&phy_eee_cap1_features)
ef6ee3a3 70#define PHY_EEE_CAP2_FEATURES ((unsigned long *)&phy_eee_cap2_features)
e9fbdf17 71
54638c6e
DE
72extern const int phy_basic_ports_array[3];
73extern const int phy_fibre_port_array[1];
74extern const int phy_all_ports_features_array[7];
3c1bcc86 75extern const int phy_10_100_features_array[4];
3254e0b9 76extern const int phy_basic_t1_features_array[3];
16178c8e 77extern const int phy_basic_t1s_p2mp_features_array[2];
3c1bcc86
AL
78extern const int phy_gbit_features_array[2];
79extern const int phy_10gbit_features_array[1];
80
c5e38a94
AF
81/*
82 * Set phydev->irq to PHY_POLL if interrupts are not supported,
93e8990c
HK
83 * or not desired for this PHY. Set to PHY_MAC_INTERRUPT if
84 * the attached MAC driver handles the interrupt
00db8189
AF
85 */
86#define PHY_POLL -1
93e8990c 87#define PHY_MAC_INTERRUPT -2
00db8189 88
a4307c0e
HK
89#define PHY_IS_INTERNAL 0x00000001
90#define PHY_RST_AFTER_CLK_EN 0x00000002
97c22438 91#define PHY_POLL_CABLE_TEST 0x00000004
a7e34480 92#define PHY_ALWAYS_CALL_SUSPEND 0x00000008
a9049e0c 93#define MDIO_DEVICE_IS_PHY 0x80000000
00db8189 94
4069a572
AL
95/**
96 * enum phy_interface_t - Interface Mode definitions
97 *
98 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch
99 * @PHY_INTERFACE_MODE_INTERNAL: No interface, MAC and PHY combined
26183cfe
CF
100 * @PHY_INTERFACE_MODE_MII: Media-independent interface
101 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface
4069a572
AL
102 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface
103 * @PHY_INTERFACE_MODE_TBI: Ten Bit Interface
104 * @PHY_INTERFACE_MODE_REVMII: Reverse Media Independent Interface
105 * @PHY_INTERFACE_MODE_RMII: Reduced Media Independent Interface
c858d436 106 * @PHY_INTERFACE_MODE_REVRMII: Reduced Media Independent Interface in PHY role
4069a572
AL
107 * @PHY_INTERFACE_MODE_RGMII: Reduced gigabit media-independent interface
108 * @PHY_INTERFACE_MODE_RGMII_ID: RGMII with Internal RX+TX delay
109 * @PHY_INTERFACE_MODE_RGMII_RXID: RGMII with Internal RX delay
110 * @PHY_INTERFACE_MODE_RGMII_TXID: RGMII with Internal RX delay
111 * @PHY_INTERFACE_MODE_RTBI: Reduced TBI
b9241f54 112 * @PHY_INTERFACE_MODE_SMII: Serial MII
4069a572
AL
113 * @PHY_INTERFACE_MODE_XGMII: 10 gigabit media-independent interface
114 * @PHY_INTERFACE_MODE_XLGMII:40 gigabit media-independent interface
115 * @PHY_INTERFACE_MODE_MOCA: Multimedia over Coax
83b5f025 116 * @PHY_INTERFACE_MODE_PSGMII: Penta SGMII
4069a572
AL
117 * @PHY_INTERFACE_MODE_QSGMII: Quad SGMII
118 * @PHY_INTERFACE_MODE_TRGMII: Turbo RGMII
b1ae3587 119 * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX
4069a572
AL
120 * @PHY_INTERFACE_MODE_1000BASEX: 1000 BaseX
121 * @PHY_INTERFACE_MODE_2500BASEX: 2500 BaseX
7331d1d4 122 * @PHY_INTERFACE_MODE_5GBASER: 5G BaseR
4069a572
AL
123 * @PHY_INTERFACE_MODE_RXAUI: Reduced XAUI
124 * @PHY_INTERFACE_MODE_XAUI: 10 Gigabit Attachment Unit Interface
125 * @PHY_INTERFACE_MODE_10GBASER: 10G BaseR
a56c2868 126 * @PHY_INTERFACE_MODE_25GBASER: 25G BaseR
4069a572
AL
127 * @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII
128 * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN
5e61fe15 129 * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII
05ad5d45 130 * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN
777b8afb 131 * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII
4069a572
AL
132 * @PHY_INTERFACE_MODE_MAX: Book keeping
133 *
134 * Describes the interface between the MAC and PHY.
135 */
e8a2b6a4 136typedef enum {
4157ef1b 137 PHY_INTERFACE_MODE_NA,
735d8a18 138 PHY_INTERFACE_MODE_INTERNAL,
e8a2b6a4
AF
139 PHY_INTERFACE_MODE_MII,
140 PHY_INTERFACE_MODE_GMII,
141 PHY_INTERFACE_MODE_SGMII,
142 PHY_INTERFACE_MODE_TBI,
2cc70ba4 143 PHY_INTERFACE_MODE_REVMII,
e8a2b6a4 144 PHY_INTERFACE_MODE_RMII,
c858d436 145 PHY_INTERFACE_MODE_REVRMII,
e8a2b6a4 146 PHY_INTERFACE_MODE_RGMII,
a999589c 147 PHY_INTERFACE_MODE_RGMII_ID,
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148 PHY_INTERFACE_MODE_RGMII_RXID,
149 PHY_INTERFACE_MODE_RGMII_TXID,
4157ef1b
SG
150 PHY_INTERFACE_MODE_RTBI,
151 PHY_INTERFACE_MODE_SMII,
898dd0bd 152 PHY_INTERFACE_MODE_XGMII,
58b05e58 153 PHY_INTERFACE_MODE_XLGMII,
fd70f72c 154 PHY_INTERFACE_MODE_MOCA,
83b5f025 155 PHY_INTERFACE_MODE_PSGMII,
b9d12085 156 PHY_INTERFACE_MODE_QSGMII,
572de608 157 PHY_INTERFACE_MODE_TRGMII,
b1ae3587 158 PHY_INTERFACE_MODE_100BASEX,
55601a88
AL
159 PHY_INTERFACE_MODE_1000BASEX,
160 PHY_INTERFACE_MODE_2500BASEX,
7331d1d4 161 PHY_INTERFACE_MODE_5GBASER,
55601a88 162 PHY_INTERFACE_MODE_RXAUI,
c125ca09 163 PHY_INTERFACE_MODE_XAUI,
c114574e
RK
164 /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */
165 PHY_INTERFACE_MODE_10GBASER,
a56c2868 166 PHY_INTERFACE_MODE_25GBASER,
4618d671 167 PHY_INTERFACE_MODE_USXGMII,
c114574e
RK
168 /* 10GBASE-KR - with Clause 73 AN */
169 PHY_INTERFACE_MODE_10GKR,
5e61fe15 170 PHY_INTERFACE_MODE_QUSGMII,
05ad5d45 171 PHY_INTERFACE_MODE_1000BASEKX,
777b8afb 172 PHY_INTERFACE_MODE_10G_QXGMII,
8a2fe56e 173 PHY_INTERFACE_MODE_MAX,
e8a2b6a4
AF
174} phy_interface_t;
175
8e20f591
RKO
176/* PHY interface mode bitmap handling */
177#define DECLARE_PHY_INTERFACE_MASK(name) \
178 DECLARE_BITMAP(name, PHY_INTERFACE_MODE_MAX)
179
180static inline void phy_interface_zero(unsigned long *intf)
181{
182 bitmap_zero(intf, PHY_INTERFACE_MODE_MAX);
183}
184
185static inline bool phy_interface_empty(const unsigned long *intf)
186{
187 return bitmap_empty(intf, PHY_INTERFACE_MODE_MAX);
188}
189
190static inline void phy_interface_and(unsigned long *dst, const unsigned long *a,
191 const unsigned long *b)
192{
193 bitmap_and(dst, a, b, PHY_INTERFACE_MODE_MAX);
194}
195
196static inline void phy_interface_or(unsigned long *dst, const unsigned long *a,
197 const unsigned long *b)
198{
199 bitmap_or(dst, a, b, PHY_INTERFACE_MODE_MAX);
200}
201
202static inline void phy_interface_set_rgmii(unsigned long *intf)
203{
204 __set_bit(PHY_INTERFACE_MODE_RGMII, intf);
205 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, intf);
206 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, intf);
207 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, intf);
208}
209
e86c6569 210/*
4069a572 211 * phy_supported_speeds - return all speeds currently supported by a PHY device
1f9127ca
ZB
212 */
213unsigned int phy_supported_speeds(struct phy_device *phy,
214 unsigned int *speeds,
215 unsigned int size);
216
8a2fe56e 217/**
d8de01b7
RD
218 * phy_modes - map phy_interface_t enum to device tree binding of phy-mode
219 * @interface: enum phy_interface_t value
220 *
4069a572 221 * Description: maps enum &phy_interface_t defined in this file
8a2fe56e 222 * into the device tree binding of 'phy-mode', so that Ethernet
4069a572 223 * device driver can get PHY interface from device tree.
8a2fe56e
FF
224 */
225static inline const char *phy_modes(phy_interface_t interface)
226{
227 switch (interface) {
228 case PHY_INTERFACE_MODE_NA:
229 return "";
735d8a18
FF
230 case PHY_INTERFACE_MODE_INTERNAL:
231 return "internal";
8a2fe56e
FF
232 case PHY_INTERFACE_MODE_MII:
233 return "mii";
234 case PHY_INTERFACE_MODE_GMII:
235 return "gmii";
236 case PHY_INTERFACE_MODE_SGMII:
237 return "sgmii";
238 case PHY_INTERFACE_MODE_TBI:
239 return "tbi";
240 case PHY_INTERFACE_MODE_REVMII:
241 return "rev-mii";
242 case PHY_INTERFACE_MODE_RMII:
243 return "rmii";
c858d436
VO
244 case PHY_INTERFACE_MODE_REVRMII:
245 return "rev-rmii";
8a2fe56e
FF
246 case PHY_INTERFACE_MODE_RGMII:
247 return "rgmii";
248 case PHY_INTERFACE_MODE_RGMII_ID:
249 return "rgmii-id";
250 case PHY_INTERFACE_MODE_RGMII_RXID:
251 return "rgmii-rxid";
252 case PHY_INTERFACE_MODE_RGMII_TXID:
253 return "rgmii-txid";
254 case PHY_INTERFACE_MODE_RTBI:
255 return "rtbi";
256 case PHY_INTERFACE_MODE_SMII:
257 return "smii";
258 case PHY_INTERFACE_MODE_XGMII:
259 return "xgmii";
58b05e58
JA
260 case PHY_INTERFACE_MODE_XLGMII:
261 return "xlgmii";
fd70f72c
FF
262 case PHY_INTERFACE_MODE_MOCA:
263 return "moca";
83b5f025
GJ
264 case PHY_INTERFACE_MODE_PSGMII:
265 return "psgmii";
b9d12085
TP
266 case PHY_INTERFACE_MODE_QSGMII:
267 return "qsgmii";
572de608
SW
268 case PHY_INTERFACE_MODE_TRGMII:
269 return "trgmii";
55601a88
AL
270 case PHY_INTERFACE_MODE_1000BASEX:
271 return "1000base-x";
05ad5d45
SA
272 case PHY_INTERFACE_MODE_1000BASEKX:
273 return "1000base-kx";
55601a88
AL
274 case PHY_INTERFACE_MODE_2500BASEX:
275 return "2500base-x";
7331d1d4
PS
276 case PHY_INTERFACE_MODE_5GBASER:
277 return "5gbase-r";
55601a88
AL
278 case PHY_INTERFACE_MODE_RXAUI:
279 return "rxaui";
c125ca09
RK
280 case PHY_INTERFACE_MODE_XAUI:
281 return "xaui";
c114574e
RK
282 case PHY_INTERFACE_MODE_10GBASER:
283 return "10gbase-r";
a56c2868
SH
284 case PHY_INTERFACE_MODE_25GBASER:
285 return "25gbase-r";
4618d671
HK
286 case PHY_INTERFACE_MODE_USXGMII:
287 return "usxgmii";
c114574e
RK
288 case PHY_INTERFACE_MODE_10GKR:
289 return "10gbase-kr";
b1ae3587
BJ
290 case PHY_INTERFACE_MODE_100BASEX:
291 return "100base-x";
5e61fe15
MC
292 case PHY_INTERFACE_MODE_QUSGMII:
293 return "qusgmii";
777b8afb
VO
294 case PHY_INTERFACE_MODE_10G_QXGMII:
295 return "10g-qxgmii";
8a2fe56e
FF
296 default:
297 return "unknown";
298 }
299}
300
e8a2b6a4 301#define PHY_INIT_TIMEOUT 100000
00db8189 302#define PHY_FORCE_TIMEOUT 10
00db8189 303
e8a2b6a4 304#define PHY_MAX_ADDR 32
00db8189 305
a4d00f17 306/* Used when trying to connect to a specific phy (mii bus id:phy device id) */
9d9326d3
AF
307#define PHY_ID_FMT "%s:%02x"
308
4567d686 309#define MII_BUS_ID_SIZE 61
a4d00f17 310
313162d0 311struct device;
60495b66 312struct kernel_hwtstamp_config;
9525ae83 313struct phylink;
298e54fa
RK
314struct sfp_bus;
315struct sfp_upstream_ops;
313162d0
PG
316struct sk_buff;
317
4069a572
AL
318/**
319 * struct mdio_bus_stats - Statistics counters for MDIO busses
320 * @transfers: Total number of transfers, i.e. @writes + @reads
321 * @errors: Number of MDIO transfers that returned an error
322 * @writes: Number of write transfers
323 * @reads: Number of read transfers
324 * @syncp: Synchronisation for incrementing statistics
325 */
080bb352
FF
326struct mdio_bus_stats {
327 u64_stats_t transfers;
328 u64_stats_t errors;
329 u64_stats_t writes;
330 u64_stats_t reads;
331 /* Must be last, add new statistics above */
332 struct u64_stats_sync syncp;
333};
334
4069a572
AL
335/**
336 * struct phy_package_shared - Shared information in PHY packages
9eea577e
CM
337 * @base_addr: Base PHY address of PHY package used to combine PHYs
338 * in one package and for offset calculation of phy_package_read/write
471e8fd3 339 * @np: Pointer to the Device Node if PHY package defined in DT
4069a572
AL
340 * @refcnt: Number of PHYs connected to this shared data
341 * @flags: Initialization of PHY package
342 * @priv_size: Size of the shared private data @priv
343 * @priv: Driver private data shared across a PHY package
344 *
345 * Represents a shared structure between different phydev's in the same
63490847
MW
346 * package, for example a quad PHY. See phy_package_join() and
347 * phy_package_leave().
348 */
349struct phy_package_shared {
9eea577e 350 u8 base_addr;
471e8fd3
CM
351 /* With PHY package defined in DT this points to the PHY package node */
352 struct device_node *np;
63490847
MW
353 refcount_t refcnt;
354 unsigned long flags;
355 size_t priv_size;
356
357 /* private data pointer */
358 /* note that this pointer is shared between different phydevs and
359 * the user has to take care of appropriate locking. It is allocated
360 * and freed automatically by phy_package_join() and
361 * phy_package_leave().
362 */
363 void *priv;
364};
365
366/* used as bit number in atomic bitops */
0ef44e5c
AT
367#define PHY_SHARED_F_INIT_DONE 0
368#define PHY_SHARED_F_PROBE_DONE 1
63490847 369
4069a572
AL
370/**
371 * struct mii_bus - Represents an MDIO bus
372 *
373 * @owner: Who owns this device
374 * @name: User friendly name for this MDIO device, or driver name
375 * @id: Unique identifier for this bus, typical from bus hierarchy
376 * @priv: Driver private data
377 *
c5e38a94
AF
378 * The Bus class for PHYs. Devices which provide access to
379 * PHYs should register using this structure
380 */
00db8189 381struct mii_bus {
3e3aaf64 382 struct module *owner;
00db8189 383 const char *name;
9d9326d3 384 char id[MII_BUS_ID_SIZE];
00db8189 385 void *priv;
4069a572 386 /** @read: Perform a read transfer on the bus */
ccaa953e 387 int (*read)(struct mii_bus *bus, int addr, int regnum);
4069a572 388 /** @write: Perform a write transfer on the bus */
ccaa953e 389 int (*write)(struct mii_bus *bus, int addr, int regnum, u16 val);
4e4aafcd
AL
390 /** @read_c45: Perform a C45 read transfer on the bus */
391 int (*read_c45)(struct mii_bus *bus, int addr, int devnum, int regnum);
392 /** @write_c45: Perform a C45 write transfer on the bus */
393 int (*write_c45)(struct mii_bus *bus, int addr, int devnum,
394 int regnum, u16 val);
4069a572 395 /** @reset: Perform a reset of the bus */
00db8189 396 int (*reset)(struct mii_bus *bus);
4069a572
AL
397
398 /** @stats: Statistic counters per device on the bus */
080bb352 399 struct mdio_bus_stats stats[PHY_MAX_ADDR];
00db8189 400
4069a572
AL
401 /**
402 * @mdio_lock: A lock to ensure that only one thing can read/write
c5e38a94
AF
403 * the MDIO bus at a time
404 */
35b5f6b1 405 struct mutex mdio_lock;
00db8189 406
4069a572 407 /** @parent: Parent device of this bus */
18ee49dd 408 struct device *parent;
4069a572 409 /** @state: State of bus structure */
46abc021
LB
410 enum {
411 MDIOBUS_ALLOCATED = 1,
412 MDIOBUS_REGISTERED,
413 MDIOBUS_UNREGISTERED,
414 MDIOBUS_RELEASED,
415 } state;
4069a572
AL
416
417 /** @dev: Kernel device representation */
46abc021 418 struct device dev;
00db8189 419
4069a572 420 /** @mdio_map: list of all MDIO devices on bus */
7f854420 421 struct mdio_device *mdio_map[PHY_MAX_ADDR];
00db8189 422
4069a572 423 /** @phy_mask: PHY addresses to be ignored when probing */
f896424c
MP
424 u32 phy_mask;
425
4069a572 426 /** @phy_ignore_ta_mask: PHY addresses to ignore the TA/read failure */
922f2dd1
FF
427 u32 phy_ignore_ta_mask;
428
4069a572
AL
429 /**
430 * @irq: An array of interrupts, each PHY's interrupt at the index
e7f4dc35 431 * matching its address
c5e38a94 432 */
e7f4dc35 433 int irq[PHY_MAX_ADDR];
69226896 434
4069a572 435 /** @reset_delay_us: GPIO reset pulse width in microseconds */
69226896 436 int reset_delay_us;
4069a572 437 /** @reset_post_delay_us: GPIO reset deassert delay in microseconds */
bb383129 438 int reset_post_delay_us;
4069a572 439 /** @reset_gpiod: Reset GPIO descriptor pointer */
d396e84c 440 struct gpio_desc *reset_gpiod;
63490847 441
4069a572 442 /** @shared_lock: protect access to the shared element */
63490847
MW
443 struct mutex shared_lock;
444
4069a572 445 /** @shared: shared state across different PHYs */
63490847 446 struct phy_package_shared *shared[PHY_MAX_ADDR];
00db8189 447};
46abc021 448#define to_mii_bus(d) container_of(d, struct mii_bus, dev)
00db8189 449
4069a572
AL
450struct mii_bus *mdiobus_alloc_size(size_t size);
451
452/**
453 * mdiobus_alloc - Allocate an MDIO bus structure
454 *
455 * The internal state of the MDIO bus will be set of MDIOBUS_ALLOCATED ready
456 * for the driver to register the bus.
457 */
eb8a54a7
TT
458static inline struct mii_bus *mdiobus_alloc(void)
459{
460 return mdiobus_alloc_size(0);
461}
462
3e3aaf64 463int __mdiobus_register(struct mii_bus *bus, struct module *owner);
ac3a68d5
BG
464int __devm_mdiobus_register(struct device *dev, struct mii_bus *bus,
465 struct module *owner);
3e3aaf64 466#define mdiobus_register(bus) __mdiobus_register(bus, THIS_MODULE)
ac3a68d5
BG
467#define devm_mdiobus_register(dev, bus) \
468 __devm_mdiobus_register(dev, bus, THIS_MODULE)
38f961e7 469
2e888103
LB
470void mdiobus_unregister(struct mii_bus *bus);
471void mdiobus_free(struct mii_bus *bus);
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472struct mii_bus *devm_mdiobus_alloc_size(struct device *dev, int sizeof_priv);
473static inline struct mii_bus *devm_mdiobus_alloc(struct device *dev)
474{
475 return devm_mdiobus_alloc_size(dev, 0);
476}
477
ce69e216 478struct mii_bus *mdio_find_bus(const char *mdio_name);
d41e1277 479struct phy_device *mdiobus_scan_c22(struct mii_bus *bus, int addr);
2e888103 480
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481#define PHY_INTERRUPT_DISABLED false
482#define PHY_INTERRUPT_ENABLED true
00db8189 483
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484/**
485 * enum phy_state - PHY state machine states:
00db8189 486 *
4069a572 487 * @PHY_DOWN: PHY device and driver are not ready for anything. probe
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488 * should be called if and only if the PHY is in this state,
489 * given that the PHY device exists.
4069a572 490 * - PHY driver probe function will set the state to @PHY_READY
00db8189 491 *
4069a572 492 * @PHY_READY: PHY is ready to send and receive packets, but the
00db8189 493 * controller is not. By default, PHYs which do not implement
899a3cbb 494 * probe will be set to this state by phy_probe().
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495 * - start will set the state to UP
496 *
4069a572 497 * @PHY_UP: The PHY and attached device are ready to do work.
00db8189 498 * Interrupts should be started here.
4069a572 499 * - timer moves to @PHY_NOLINK or @PHY_RUNNING
00db8189 500 *
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501 * @PHY_NOLINK: PHY is up, but not currently plugged in.
502 * - irq or timer will set @PHY_RUNNING if link comes back
503 * - phy_stop moves to @PHY_HALTED
00db8189 504 *
4069a572 505 * @PHY_RUNNING: PHY is currently up, running, and possibly sending
00db8189 506 * and/or receiving packets
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507 * - irq or timer will set @PHY_NOLINK if link goes down
508 * - phy_stop moves to @PHY_HALTED
00db8189 509 *
4069a572 510 * @PHY_CABLETEST: PHY is performing a cable test. Packet reception/sending
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511 * is not expected to work, carrier will be indicated as down. PHY will be
512 * poll once per second, or on interrupt for it current state.
513 * Once complete, move to UP to restart the PHY.
4069a572 514 * - phy_stop aborts the running test and moves to @PHY_HALTED
a68a8138 515 *
59088b5a 516 * @PHY_HALTED: PHY is up, but no polling or interrupts are done.
4069a572 517 * - phy_start moves to @PHY_UP
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518 *
519 * @PHY_ERROR: PHY is up, but is in an error state.
520 * - phy_stop moves to @PHY_HALTED
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521 */
522enum phy_state {
4017b4d3 523 PHY_DOWN = 0,
00db8189 524 PHY_READY,
2b3e88ea 525 PHY_HALTED,
59088b5a 526 PHY_ERROR,
00db8189 527 PHY_UP,
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528 PHY_RUNNING,
529 PHY_NOLINK,
a68a8138 530 PHY_CABLETEST,
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531};
532
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533#define MDIO_MMD_NUM 32
534
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535/**
536 * struct phy_c45_device_ids - 802.3-c45 Device Identifiers
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537 * @devices_in_package: IEEE 802.3 devices in package register value.
538 * @mmds_present: bit vector of MMDs present.
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539 * @device_ids: The device identifer for each present device.
540 */
541struct phy_c45_device_ids {
542 u32 devices_in_package;
320ed3bf 543 u32 mmds_present;
389a3389 544 u32 device_ids[MDIO_MMD_NUM];
ac28b9f8 545};
c1f19b51 546
76564261 547struct macsec_context;
2e181358 548struct macsec_ops;
76564261 549
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550/**
551 * struct phy_device - An instance of a PHY
00db8189 552 *
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553 * @mdio: MDIO bus this PHY is on
554 * @drv: Pointer to the driver for this PHY instance
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555 * @devlink: Create a link between phy dev and mac dev, if the external phy
556 * used by current mac interface is managed by another mac interface.
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557 * @phyindex: Unique id across the phy's parent tree of phys to address the PHY
558 * from userspace, similar to ifindex. A zero index means the PHY
559 * wasn't assigned an id yet.
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560 * @phy_id: UID for this device found during discovery
561 * @c45_ids: 802.3-c45 Device Identifiers if is_c45.
562 * @is_c45: Set to true if this PHY uses clause 45 addressing.
563 * @is_internal: Set to true if this PHY is internal to a MAC.
564 * @is_pseudo_fixed_link: Set to true if this PHY is an Ethernet switch, etc.
565 * @is_gigabit_capable: Set to true if PHY supports 1000Mbps
566 * @has_fixups: Set to true if this PHY has fixups/quirks.
567 * @suspended: Set to true if this PHY has been suspended successfully.
568 * @suspended_by_mdio_bus: Set to true if this PHY was suspended by MDIO bus.
569 * @sysfs_links: Internal boolean tracking sysfs symbolic links setup/removal.
570 * @loopback_enabled: Set true if this PHY has been loopbacked successfully.
571 * @downshifted_rate: Set true if link speed has been downshifted.
b834489b 572 * @is_on_sfp_module: Set true if PHY is located on an SFP module.
fba863b8 573 * @mac_managed_pm: Set true if MAC driver takes of suspending/resuming PHY
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574 * @wol_enabled: Set to true if the PHY or the attached MAC have Wake-on-LAN
575 * enabled.
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576 * @state: State of the PHY for management purposes
577 * @dev_flags: Device-specific flags used by the PHY driver.
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578 *
579 * - Bits [15:0] are free to use by the PHY driver to communicate
580 * driver specific behavior.
581 * - Bits [23:16] are currently reserved for future use.
582 * - Bits [31:24] are reserved for defining generic
583 * PHY driver behavior.
4069a572 584 * @irq: IRQ number of the PHY's interrupt (-1 if none)
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585 * @phylink: Pointer to phylink instance for this PHY
586 * @sfp_bus_attached: Flag indicating whether the SFP bus has been attached
587 * @sfp_bus: SFP bus attached to this PHY's fiber port
588 * @attached_dev: The attached enet driver's device instance ptr
589 * @adjust_link: Callback for the enet controller to respond to changes: in the
590 * link state.
591 * @phy_link_change: Callback for phylink for notification of link change
592 * @macsec_ops: MACsec offloading ops.
00db8189 593 *
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594 * @speed: Current link speed
595 * @duplex: Current duplex
4217a64e 596 * @port: Current port
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597 * @pause: Current pause
598 * @asym_pause: Current asymmetric pause
599 * @supported: Combined MAC/PHY supported linkmodes
600 * @advertising: Currently advertised linkmodes
601 * @adv_old: Saved advertised while power saving for WoL
14e47d1f 602 * @supported_eee: supported PHY EEE linkmodes
3eeca4e1 603 * @advertising_eee: Currently advertised EEE linkmodes
e3b6876a 604 * @enable_tx_lpi: When True, MAC should transmit LPI to PHY
fe0d4fd9 605 * @eee_cfg: User configuration of EEE
4069a572 606 * @lp_advertising: Current link partner advertised linkmodes
eca68a3c 607 * @host_interfaces: PHY interface modes supported by host
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608 * @eee_broken_modes: Energy efficient ethernet modes which should be prohibited
609 * @autoneg: Flag autoneg being used
0c3e10cb 610 * @rate_matching: Current rate matching mode
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611 * @link: Current link state
612 * @autoneg_complete: Flag auto negotiation of the link has completed
613 * @mdix: Current crossover
614 * @mdix_ctrl: User setting of crossover
3da8ffd8 615 * @pma_extable: Cached value of PMA/PMD Extended Abilities Register
4069a572 616 * @interrupts: Flag interrupts have been enabled
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617 * @irq_suspended: Flag indicating PHY is suspended and therefore interrupt
618 * handling shall be postponed until PHY has resumed
619 * @irq_rerun: Flag indicating interrupts occurred while PHY was suspended,
620 * requiring a rerun of the interrupt handler after resume
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621 * @default_timestamp: Flag indicating whether we are using the phy
622 * timestamp as the default one
4069a572 623 * @interface: enum phy_interface_t value
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624 * @possible_interfaces: bitmap if interface modes that the attached PHY
625 * will switch between depending on media speed.
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626 * @skb: Netlink message for cable diagnostics
627 * @nest: Netlink nest used for cable diagnostics
628 * @ehdr: nNtlink header for cable diagnostics
629 * @phy_led_triggers: Array of LED triggers
630 * @phy_num_led_triggers: Number of triggers in @phy_led_triggers
631 * @led_link_trigger: LED trigger for link up/down
632 * @last_triggered: last LED trigger for link speed
01e5b728 633 * @leds: list of PHY LED structures
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634 * @master_slave_set: User requested master/slave configuration
635 * @master_slave_get: Current master/slave advertisement
636 * @master_slave_state: Current master/slave configuration
637 * @mii_ts: Pointer to time stamper callbacks
5e82147d 638 * @psec: Pointer to Power Sourcing Equipment control struct
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639 * @lock: Mutex for serialization access to PHY
640 * @state_queue: Work queue for state machine
9a0f830f 641 * @link_down_events: Number of times link was lost
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642 * @shared: Pointer to private data shared by phys in one package
643 * @priv: Pointer to driver private data
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644 *
645 * interrupts currently only supports enabled or disabled,
646 * but could be changed in the future to support enabling
647 * and disabling specific interrupts
648 *
649 * Contains some infrastructure for polling and interrupt
650 * handling, as well as handling shifts in PHY hardware state
651 */
652struct phy_device {
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653 struct mdio_device mdio;
654
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655 /* Information about the PHY type */
656 /* And management functions */
0bd199fd 657 const struct phy_driver *drv;
00db8189 658
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659 struct device_link *devlink;
660
38496878 661 u32 phyindex;
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662 u32 phy_id;
663
ac28b9f8 664 struct phy_c45_device_ids c45_ids;
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665 unsigned is_c45:1;
666 unsigned is_internal:1;
667 unsigned is_pseudo_fixed_link:1;
3b8b11f9 668 unsigned is_gigabit_capable:1;
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669 unsigned has_fixups:1;
670 unsigned suspended:1;
611d779a 671 unsigned suspended_by_mdio_bus:1;
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672 unsigned sysfs_links:1;
673 unsigned loopback_enabled:1;
5eee3bb7 674 unsigned downshifted_rate:1;
b834489b 675 unsigned is_on_sfp_module:1;
fba863b8 676 unsigned mac_managed_pm:1;
a7e34480 677 unsigned wol_enabled:1;
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678
679 unsigned autoneg:1;
680 /* The most recently read link state */
681 unsigned link:1;
4950c2ba 682 unsigned autoneg_complete:1;
ac28b9f8 683
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684 /* Interrupts are enabled */
685 unsigned interrupts:1;
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686 unsigned irq_suspended:1;
687 unsigned irq_rerun:1;
695bce8f 688
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689 unsigned default_timestamp:1;
690
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691 int rate_matching;
692
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693 enum phy_state state;
694
695 u32 dev_flags;
696
e8a2b6a4 697 phy_interface_t interface;
243ad8df 698 DECLARE_PHY_INTERFACE_MASK(possible_interfaces);
e8a2b6a4 699
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700 /*
701 * forced speed & duplex (no autoneg)
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702 * partner speed & duplex & pause (autoneg)
703 */
704 int speed;
705 int duplex;
4217a64e 706 int port;
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707 int pause;
708 int asym_pause;
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709 u8 master_slave_get;
710 u8 master_slave_set;
711 u8 master_slave_state;
00db8189 712
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713 /* Union of PHY and Attached devices' supported link modes */
714 /* See ethtool.h for more info */
715 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
716 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
c0ec3c27 717 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising);
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718 /* used with phy_speed_down */
719 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv_old);
49168d19 720 /* used for eee validation and configuration*/
14e47d1f 721 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported_eee);
3eeca4e1 722 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising_eee);
00db8189 723
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724 /* Host supported PHY interface types. Should be ignored if empty. */
725 DECLARE_PHY_INTERFACE_MASK(host_interfaces);
726
d853d145 727 /* Energy efficient ethernet modes which should be prohibited */
728 u32 eee_broken_modes;
e3b6876a 729 bool enable_tx_lpi;
fe0d4fd9 730 struct eee_config eee_cfg;
d853d145 731
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ZB
732#ifdef CONFIG_LED_TRIGGER_PHY
733 struct phy_led_trigger *phy_led_triggers;
734 unsigned int phy_num_led_triggers;
735 struct phy_led_trigger *last_triggered;
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MS
736
737 struct phy_led_trigger *led_link_trigger;
2e0bc452 738#endif
01e5b728 739 struct list_head leds;
2e0bc452 740
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741 /*
742 * Interrupt number for this PHY
743 * -1 means no interrupt
744 */
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745 int irq;
746
747 /* private data pointer */
748 /* For use by PHYs to maintain extra state */
749 void *priv;
750
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751 /* shared data pointer */
752 /* For use by PHYs inside the same package that need a shared state. */
753 struct phy_package_shared *shared;
754
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755 /* Reporting cable test results */
756 struct sk_buff *skb;
757 void *ehdr;
758 struct nlattr *nest;
759
00db8189 760 /* Interrupt and Polling infrastructure */
a390d1f3 761 struct delayed_work state_queue;
00db8189 762
35b5f6b1 763 struct mutex lock;
00db8189 764
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765 /* This may be modified under the rtnl lock */
766 bool sfp_bus_attached;
767 struct sfp_bus *sfp_bus;
9525ae83 768 struct phylink *phylink;
00db8189 769 struct net_device *attached_dev;
4715f65f 770 struct mii_timestamper *mii_ts;
5e82147d 771 struct pse_control *psec;
00db8189 772
634ec36c 773 u8 mdix;
f4ed2fe3 774 u8 mdix_ctrl;
634ec36c 775
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AT
776 int pma_extable;
777
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778 unsigned int link_down_events;
779
a307593a 780 void (*phy_link_change)(struct phy_device *phydev, bool up);
00db8189 781 void (*adjust_link)(struct net_device *dev);
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782
783#if IS_ENABLED(CONFIG_MACSEC)
784 /* MACsec management functions */
785 const struct macsec_ops *macsec_ops;
786#endif
00db8189 787};
7eab14de 788
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789/* Generic phy_device::dev_flags */
790#define PHY_F_NO_IRQ 0x80000000
21d9ba5b 791#define PHY_F_RXC_ALWAYS_ON 0x40000000
7d885863 792
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793static inline struct phy_device *to_phy_device(const struct device *dev)
794{
795 return container_of(to_mdio_device(dev), struct phy_device, mdio);
796}
00db8189 797
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798/**
799 * struct phy_tdr_config - Configuration of a TDR raw test
800 *
801 * @first: Distance for first data collection point
802 * @last: Distance for last data collection point
803 * @step: Step between data collection points
804 * @pair: Bitmap of cable pairs to collect data for
805 *
806 * A structure containing possible configuration parameters
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807 * for a TDR cable test. The driver does not need to implement
808 * all the parameters, but should report what is actually used.
4069a572 809 * All distances are in centimeters.
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810 */
811struct phy_tdr_config {
812 u32 first;
813 u32 last;
814 u32 step;
815 s8 pair;
816};
817#define PHY_PAIR_ALL -1
818
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819/**
820 * struct phy_plca_cfg - Configuration of the PLCA (Physical Layer Collision
821 * Avoidance) Reconciliation Sublayer.
822 *
823 * @version: read-only PLCA register map version. -1 = not available. Ignored
824 * when setting the configuration. Format is the same as reported by the PLCA
825 * IDVER register (31.CA00). -1 = not available.
826 * @enabled: PLCA configured mode (enabled/disabled). -1 = not available / don't
827 * set. 0 = disabled, anything else = enabled.
828 * @node_id: the PLCA local node identifier. -1 = not available / don't set.
829 * Allowed values [0 .. 254]. 255 = node disabled.
830 * @node_cnt: the PLCA node count (maximum number of nodes having a TO). Only
831 * meaningful for the coordinator (node_id = 0). -1 = not available / don't
832 * set. Allowed values [1 .. 255].
833 * @to_tmr: The value of the PLCA to_timer in bit-times, which determines the
834 * PLCA transmit opportunity window opening. See IEEE802.3 Clause 148 for
835 * more details. The to_timer shall be set equal over all nodes.
836 * -1 = not available / don't set. Allowed values [0 .. 255].
837 * @burst_cnt: controls how many additional frames a node is allowed to send in
838 * single transmit opportunity (TO). The default value of 0 means that the
839 * node is allowed exactly one frame per TO. A value of 1 allows two frames
840 * per TO, and so on. -1 = not available / don't set.
841 * Allowed values [0 .. 255].
842 * @burst_tmr: controls how many bit times to wait for the MAC to send a new
843 * frame before interrupting the burst. This value should be set to a value
844 * greater than the MAC inter-packet gap (which is typically 96 bits).
845 * -1 = not available / don't set. Allowed values [0 .. 255].
846 *
847 * A structure containing configuration parameters for setting/getting the PLCA
848 * RS configuration. The driver does not need to implement all the parameters,
849 * but should report what is actually used.
850 */
851struct phy_plca_cfg {
852 int version;
853 int enabled;
854 int node_id;
855 int node_cnt;
856 int to_tmr;
857 int burst_cnt;
858 int burst_tmr;
859};
860
861/**
862 * struct phy_plca_status - Status of the PLCA (Physical Layer Collision
863 * Avoidance) Reconciliation Sublayer.
864 *
865 * @pst: The PLCA status as reported by the PST bit in the PLCA STATUS
866 * register(31.CA03), indicating BEACON activity.
867 *
868 * A structure containing status information of the PLCA RS configuration.
869 * The driver does not need to implement all the parameters, but should report
870 * what is actually used.
871 */
872struct phy_plca_status {
873 bool pst;
874};
875
7ae215ee
CM
876/* Modes for PHY LED configuration */
877enum phy_led_modes {
878 PHY_LED_ACTIVE_LOW = 0,
879 PHY_LED_INACTIVE_HIGH_IMPEDANCE = 1,
880
881 /* keep it last */
882 __PHY_LED_MODES_NUM,
883};
884
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885/**
886 * struct phy_led: An LED driven by the PHY
887 *
888 * @list: List of LEDs
68481818 889 * @phydev: PHY this LED is attached to
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890 * @led_cdev: Standard LED class structure
891 * @index: Number of the LED
892 */
893struct phy_led {
894 struct list_head list;
68481818 895 struct phy_device *phydev;
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896 struct led_classdev led_cdev;
897 u8 index;
898};
899
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900#define to_phy_led(d) container_of(d, struct phy_led, led_cdev)
901
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902/**
903 * struct phy_driver - Driver structure for a particular PHY type
00db8189 904 *
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905 * @mdiodrv: Data common to all MDIO devices
906 * @phy_id: The result of reading the UID registers of this PHY
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907 * type, and ANDing them with the phy_id_mask. This driver
908 * only works for PHYs with IDs which match this field
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909 * @name: The friendly name of this PHY type
910 * @phy_id_mask: Defines the important bits of the phy_id
911 * @features: A mandatory list of features (speed, duplex, etc)
3e64cf7a 912 * supported by this PHY
4069a572 913 * @flags: A bitfield defining certain other features this PHY
00db8189 914 * supports (like interrupts)
4069a572 915 * @driver_data: Static driver data
00db8189 916 *
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HK
917 * All functions are optional. If config_aneg or read_status
918 * are not implemented, the phy core uses the genphy versions.
919 * Note that none of these functions should be called from
920 * interrupt time. The goal is for the bus read/write functions
921 * to be able to block when the bus transaction is happening,
922 * and be freed up by an interrupt (The MPC85xx has this ability,
923 * though it is not currently supported in the driver).
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924 */
925struct phy_driver {
a9049e0c 926 struct mdio_driver_common mdiodrv;
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927 u32 phy_id;
928 char *name;
511e3036 929 u32 phy_id_mask;
719655a1 930 const unsigned long * const features;
00db8189 931 u32 flags;
860f6e9e 932 const void *driver_data;
00db8189 933
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934 /**
935 * @soft_reset: Called to issue a PHY software reset
9df81dd7
FF
936 */
937 int (*soft_reset)(struct phy_device *phydev);
938
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939 /**
940 * @config_init: Called to initialize the PHY,
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941 * including after a reset
942 */
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943 int (*config_init)(struct phy_device *phydev);
944
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945 /**
946 * @probe: Called during discovery. Used to set
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947 * up device-specific structures, if any
948 */
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949 int (*probe)(struct phy_device *phydev);
950
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951 /**
952 * @get_features: Probe the hardware to determine what
953 * abilities it has. Should only set phydev->supported.
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954 */
955 int (*get_features)(struct phy_device *phydev);
956
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957 /**
958 * @get_rate_matching: Get the supported type of rate matching for a
959 * particular phy interface. This is used by phy consumers to determine
960 * whether to advertise lower-speed modes for that interface. It is
961 * assumed that if a rate matching mode is supported on an interface,
962 * then that interface's rate can be adapted to all slower link speeds
6d4cfcf9 963 * supported by the phy. If the interface is not supported, this should
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964 * return %RATE_MATCH_NONE.
965 */
966 int (*get_rate_matching)(struct phy_device *phydev,
967 phy_interface_t iface);
968
00db8189 969 /* PHY Power Management */
4069a572 970 /** @suspend: Suspend the hardware, saving state if needed */
00db8189 971 int (*suspend)(struct phy_device *phydev);
4069a572 972 /** @resume: Resume the hardware, restoring state if needed */
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973 int (*resume)(struct phy_device *phydev);
974
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975 /**
976 * @config_aneg: Configures the advertisement and resets
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977 * autonegotiation if phydev->autoneg is on,
978 * forces the speed to the current settings in phydev
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979 * if phydev->autoneg is off
980 */
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981 int (*config_aneg)(struct phy_device *phydev);
982
4069a572 983 /** @aneg_done: Determines the auto negotiation result */
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984 int (*aneg_done)(struct phy_device *phydev);
985
4069a572 986 /** @read_status: Determines the negotiated speed and duplex */
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987 int (*read_status)(struct phy_device *phydev);
988
767143a1
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989 /**
990 * @config_intr: Enables or disables interrupts.
6527b938
IC
991 * It should also clear any pending interrupts prior to enabling the
992 * IRQs and after disabling them.
a8729eb3 993 */
6527b938 994 int (*config_intr)(struct phy_device *phydev);
a8729eb3 995
4069a572 996 /** @handle_interrupt: Override default interrupt handling */
9010f9de 997 irqreturn_t (*handle_interrupt)(struct phy_device *phydev);
49644e68 998
4069a572 999 /** @remove: Clears up any memory if needed */
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1000 void (*remove)(struct phy_device *phydev);
1001
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1002 /**
1003 * @match_phy_device: Returns true if this is a suitable
1004 * driver for the given phydev. If NULL, matching is based on
1005 * phy_id and phy_id_mask.
a30e2c18
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1006 */
1007 int (*match_phy_device)(struct phy_device *phydev);
1008
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1009 /**
1010 * @set_wol: Some devices (e.g. qnap TS-119P II) require PHY
1011 * register changes to enable Wake on LAN, so set_wol is
1012 * provided to be called in the ethernet driver's set_wol
1013 * function.
1014 */
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MS
1015 int (*set_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol);
1016
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1017 /**
1018 * @get_wol: See set_wol, but for checking whether Wake on LAN
1019 * is enabled.
1020 */
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1021 void (*get_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol);
1022
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1023 /**
1024 * @link_change_notify: Called to inform a PHY device driver
1025 * when the core is about to change the link state. This
1026 * callback is supposed to be used as fixup hook for drivers
1027 * that need to take action when the link state
1028 * changes. Drivers are by no means allowed to mess with the
2b8f2a28
DM
1029 * PHY device structure in their implementations.
1030 */
1031 void (*link_change_notify)(struct phy_device *dev);
1032
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1033 /**
1034 * @read_mmd: PHY specific driver override for reading a MMD
1035 * register. This function is optional for PHY specific
1036 * drivers. When not provided, the default MMD read function
1037 * will be used by phy_read_mmd(), which will use either a
1038 * direct read for Clause 45 PHYs or an indirect read for
1039 * Clause 22 PHYs. devnum is the MMD device number within the
1040 * PHY device, regnum is the register within the selected MMD
1041 * device.
1ee6b9bc
RK
1042 */
1043 int (*read_mmd)(struct phy_device *dev, int devnum, u16 regnum);
1044
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1045 /**
1046 * @write_mmd: PHY specific driver override for writing a MMD
1047 * register. This function is optional for PHY specific
1048 * drivers. When not provided, the default MMD write function
1049 * will be used by phy_write_mmd(), which will use either a
1050 * direct write for Clause 45 PHYs, or an indirect write for
1051 * Clause 22 PHYs. devnum is the MMD device number within the
1052 * PHY device, regnum is the register within the selected MMD
1053 * device. val is the value to be written.
1ee6b9bc
RK
1054 */
1055 int (*write_mmd)(struct phy_device *dev, int devnum, u16 regnum,
1056 u16 val);
1057
4069a572 1058 /** @read_page: Return the current PHY register page number */
78ffc4ac 1059 int (*read_page)(struct phy_device *dev);
4069a572 1060 /** @write_page: Set the current PHY register page number */
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RK
1061 int (*write_page)(struct phy_device *dev, int page);
1062
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1063 /**
1064 * @module_info: Get the size and type of the eeprom contained
1065 * within a plug-in module
1066 */
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ES
1067 int (*module_info)(struct phy_device *dev,
1068 struct ethtool_modinfo *modinfo);
1069
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1070 /**
1071 * @module_eeprom: Get the eeprom information from the plug-in
1072 * module
1073 */
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ES
1074 int (*module_eeprom)(struct phy_device *dev,
1075 struct ethtool_eeprom *ee, u8 *data);
1076
4069a572 1077 /** @cable_test_start: Start a cable test */
a68a8138 1078 int (*cable_test_start)(struct phy_device *dev);
1a644de2 1079
4069a572 1080 /** @cable_test_tdr_start: Start a raw TDR cable test */
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AL
1081 int (*cable_test_tdr_start)(struct phy_device *dev,
1082 const struct phy_tdr_config *config);
1a644de2 1083
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AL
1084 /**
1085 * @cable_test_get_status: Once per second, or on interrupt,
1086 * request the status of the test.
a68a8138
AL
1087 */
1088 int (*cable_test_get_status)(struct phy_device *dev, bool *finished);
1089
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AL
1090 /* Get statistics from the PHY using ethtool */
1091 /** @get_sset_count: Number of statistic counters */
f3a40945 1092 int (*get_sset_count)(struct phy_device *dev);
4069a572 1093 /** @get_strings: Names of the statistic counters */
f3a40945 1094 void (*get_strings)(struct phy_device *dev, u8 *data);
4069a572 1095 /** @get_stats: Return the statistic counter values */
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AL
1096 void (*get_stats)(struct phy_device *dev,
1097 struct ethtool_stats *stats, u64 *data);
968ad9da
RL
1098
1099 /* Get and Set PHY tunables */
4069a572 1100 /** @get_tunable: Return the value of a tunable */
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RL
1101 int (*get_tunable)(struct phy_device *dev,
1102 struct ethtool_tunable *tuna, void *data);
4069a572 1103 /** @set_tunable: Set the value of a tunable */
968ad9da
RL
1104 int (*set_tunable)(struct phy_device *dev,
1105 struct ethtool_tunable *tuna,
1106 const void *data);
4069a572 1107 /** @set_loopback: Set the loopback mood of the PHY */
f0f9b4ed 1108 int (*set_loopback)(struct phy_device *dev, bool enable);
4069a572 1109 /** @get_sqi: Get the signal quality indication */
80660219 1110 int (*get_sqi)(struct phy_device *dev);
4069a572 1111 /** @get_sqi_max: Get the maximum signal quality indication */
80660219 1112 int (*get_sqi_max)(struct phy_device *dev);
16178c8e
PB
1113
1114 /* PLCA RS interface */
1115 /** @get_plca_cfg: Return the current PLCA configuration */
1116 int (*get_plca_cfg)(struct phy_device *dev,
1117 struct phy_plca_cfg *plca_cfg);
1118 /** @set_plca_cfg: Set the PLCA configuration */
1119 int (*set_plca_cfg)(struct phy_device *dev,
1120 const struct phy_plca_cfg *plca_cfg);
1121 /** @get_plca_status: Return the current PLCA status info */
1122 int (*get_plca_status)(struct phy_device *dev,
1123 struct phy_plca_status *plca_st);
68481818
AL
1124
1125 /**
1126 * @led_brightness_set: Set a PHY LED brightness. Index
1127 * indicates which of the PHYs led should be set. Value
1128 * follows the standard LED class meaning, e.g. LED_OFF,
1129 * LED_HALF, LED_FULL.
1130 */
1131 int (*led_brightness_set)(struct phy_device *dev,
1132 u8 index, enum led_brightness value);
4e901018
AL
1133
1134 /**
d3dcb084 1135 * @led_blink_set: Set a PHY LED blinking. Index indicates
4e901018
AL
1136 * which of the PHYs led should be configured to blink. Delays
1137 * are in milliseconds and if both are zero then a sensible
1138 * default should be chosen. The call should adjust the
1139 * timings in that case and if it can't match the values
1140 * specified exactly.
1141 */
1142 int (*led_blink_set)(struct phy_device *dev, u8 index,
1143 unsigned long *delay_on,
1144 unsigned long *delay_off);
1dcc03c9
AL
1145 /**
1146 * @led_hw_is_supported: Can the HW support the given rules.
1147 * @dev: PHY device which has the LED
1148 * @index: Which LED of the PHY device
1149 * @rules The core is interested in these rules
1150 *
1151 * Return 0 if yes, -EOPNOTSUPP if not, or an error code.
1152 */
1153 int (*led_hw_is_supported)(struct phy_device *dev, u8 index,
1154 unsigned long rules);
1155 /**
1156 * @led_hw_control_set: Set the HW to control the LED
1157 * @dev: PHY device which has the LED
1158 * @index: Which LED of the PHY device
1159 * @rules The rules used to control the LED
1160 *
1161 * Returns 0, or a an error code.
1162 */
1163 int (*led_hw_control_set)(struct phy_device *dev, u8 index,
1164 unsigned long rules);
1165 /**
1166 * @led_hw_control_get: Get how the HW is controlling the LED
1167 * @dev: PHY device which has the LED
1168 * @index: Which LED of the PHY device
1169 * @rules Pointer to the rules used to control the LED
1170 *
1171 * Set *@rules to how the HW is currently blinking. Returns 0
1172 * on success, or a error code if the current blinking cannot
1173 * be represented in rules, or some other error happens.
1174 */
1175 int (*led_hw_control_get)(struct phy_device *dev, u8 index,
1176 unsigned long *rules);
1177
7ae215ee
CM
1178 /**
1179 * @led_polarity_set: Set the LED polarity modes
1180 * @dev: PHY device which has the LED
1181 * @index: Which LED of the PHY device
1182 * @modes: bitmap of LED polarity modes
1183 *
1184 * Configure LED with all the required polarity modes in @modes
1185 * to make it correctly turn ON or OFF.
1186 *
1187 * Returns 0, or an error code.
1188 */
1189 int (*led_polarity_set)(struct phy_device *dev, int index,
1190 unsigned long modes);
00db8189 1191};
d69d8048 1192#define to_phy_driver(d) container_of_const(to_mdio_common_driver(d), \
a9049e0c 1193 struct phy_driver, mdiodrv)
00db8189 1194
f62220d3
AF
1195#define PHY_ANY_ID "MATCH ANY PHY"
1196#define PHY_ANY_UID 0xffffffff
1197
aa2af2eb
HK
1198#define PHY_ID_MATCH_EXACT(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 0)
1199#define PHY_ID_MATCH_MODEL(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 4)
1200#define PHY_ID_MATCH_VENDOR(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 10)
1201
4b159f50
RK
1202/**
1203 * phy_id_compare - compare @id1 with @id2 taking account of @mask
1204 * @id1: first PHY ID
1205 * @id2: second PHY ID
1206 * @mask: the PHY ID mask, set bits are significant in matching
1207 *
1208 * Return true if the bits from @id1 and @id2 specified by @mask match.
1209 * This uses an equivalent test to (@id & @mask) == (@phy_id & @mask).
1210 */
1211static inline bool phy_id_compare(u32 id1, u32 id2, u32 mask)
1212{
1213 return !((id1 ^ id2) & mask);
1214}
1215
1216/**
1217 * phydev_id_compare - compare @id with the PHY's Clause 22 ID
1218 * @phydev: the PHY device
1219 * @id: the PHY ID to be matched
1220 *
1221 * Compare the @phydev clause 22 ID with the provided @id and return true or
1222 * false depending whether it matches, using the bound driver mask. The
1223 * @phydev must be bound to a driver.
1224 */
1225static inline bool phydev_id_compare(struct phy_device *phydev, u32 id)
1226{
1227 return phy_id_compare(id, phydev->phy_id, phydev->drv->phy_id_mask);
1228}
1229
f62220d3
AF
1230/* A Structure for boards to register fixups with the PHY Lib */
1231struct phy_fixup {
1232 struct list_head list;
4567d686 1233 char bus_id[MII_BUS_ID_SIZE + 3];
f62220d3
AF
1234 u32 phy_uid;
1235 u32 phy_uid_mask;
1236 int (*run)(struct phy_device *phydev);
1237};
1238
da4625ac
RK
1239const char *phy_speed_to_str(int speed);
1240const char *phy_duplex_to_str(unsigned int duplex);
0c3e10cb 1241const char *phy_rate_matching_to_str(int rate_matching);
da4625ac 1242
c04ade27
MC
1243int phy_interface_num_ports(phy_interface_t interface);
1244
0ccb4fc6
RK
1245/* A structure for mapping a particular speed and duplex
1246 * combination to a particular SUPPORTED and ADVERTISED value
1247 */
1248struct phy_setting {
1249 u32 speed;
1250 u8 duplex;
1251 u8 bit;
1252};
1253
1254const struct phy_setting *
1255phy_lookup_setting(int speed, int duplex, const unsigned long *mask,
3c1bcc86 1256 bool exact);
0ccb4fc6 1257size_t phy_speeds(unsigned int *speeds, size_t size,
3c1bcc86 1258 unsigned long *mask);
a4eaed9f 1259void of_set_phy_supported(struct phy_device *phydev);
3feb9b23 1260void of_set_phy_eee_broken(struct phy_device *phydev);
331c56ac 1261int phy_speed_down_core(struct phy_device *phydev);
0ccb4fc6 1262
2b3e88ea
HK
1263/**
1264 * phy_is_started - Convenience function to check whether PHY is started
1265 * @phydev: The phy_device struct
1266 */
1267static inline bool phy_is_started(struct phy_device *phydev)
1268{
a2fc9d7e 1269 return phydev->state >= PHY_UP;
2b3e88ea
HK
1270}
1271
2d880b87 1272void phy_resolve_aneg_pause(struct phy_device *phydev);
8c5e850c 1273void phy_resolve_aneg_linkmode(struct phy_device *phydev);
5eee3bb7 1274void phy_check_downshift(struct phy_device *phydev);
8c5e850c 1275
2e888103
LB
1276/**
1277 * phy_read - Convenience function for reading a given PHY register
1278 * @phydev: the phy_device struct
1279 * @regnum: register number to read
1280 *
1281 * NOTE: MUST NOT be called from interrupt context,
1282 * because the bus read/write functions may wait for an interrupt
1283 * to conclude the operation.
1284 */
abf35df2 1285static inline int phy_read(struct phy_device *phydev, u32 regnum)
2e888103 1286{
e5a03bfd 1287 return mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum);
2e888103
LB
1288}
1289
fcbd30d0
DZ
1290#define phy_read_poll_timeout(phydev, regnum, val, cond, sleep_us, \
1291 timeout_us, sleep_before_read) \
1292({ \
4ec73295
RKO
1293 int __ret, __val; \
1294 __ret = read_poll_timeout(__val = phy_read, val, \
1295 __val < 0 || (cond), \
fcbd30d0 1296 sleep_us, timeout_us, sleep_before_read, phydev, regnum); \
4ec73295
RKO
1297 if (__val < 0) \
1298 __ret = __val; \
fcbd30d0
DZ
1299 if (__ret) \
1300 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \
1301 __ret; \
1302})
1303
788f9933
RK
1304/**
1305 * __phy_read - convenience function for reading a given PHY register
1306 * @phydev: the phy_device struct
1307 * @regnum: register number to read
1308 *
1309 * The caller must have taken the MDIO bus lock.
1310 */
1311static inline int __phy_read(struct phy_device *phydev, u32 regnum)
1312{
1313 return __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum);
1314}
1315
2e888103
LB
1316/**
1317 * phy_write - Convenience function for writing a given PHY register
1318 * @phydev: the phy_device struct
1319 * @regnum: register number to write
1320 * @val: value to write to @regnum
1321 *
1322 * NOTE: MUST NOT be called from interrupt context,
1323 * because the bus read/write functions may wait for an interrupt
1324 * to conclude the operation.
1325 */
abf35df2 1326static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
2e888103 1327{
e5a03bfd 1328 return mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum, val);
2e888103
LB
1329}
1330
788f9933
RK
1331/**
1332 * __phy_write - Convenience function for writing a given PHY register
1333 * @phydev: the phy_device struct
1334 * @regnum: register number to write
1335 * @val: value to write to @regnum
1336 *
1337 * The caller must have taken the MDIO bus lock.
1338 */
1339static inline int __phy_write(struct phy_device *phydev, u32 regnum, u16 val)
1340{
1341 return __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum,
1342 val);
1343}
1344
6cc7cf81
RK
1345/**
1346 * __phy_modify_changed() - Convenience function for modifying a PHY register
1347 * @phydev: a pointer to a &struct phy_device
1348 * @regnum: register number
1349 * @mask: bit mask of bits to clear
1350 * @set: bit mask of bits to set
1351 *
1352 * Unlocked helper function which allows a PHY register to be modified as
1353 * new register value = (old register value & ~mask) | set
1354 *
1355 * Returns negative errno, 0 if there was no change, and 1 in case of change
1356 */
1357static inline int __phy_modify_changed(struct phy_device *phydev, u32 regnum,
1358 u16 mask, u16 set)
1359{
1360 return __mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr,
1361 regnum, mask, set);
1362}
1363
e86c6569 1364/*
1878f0dc
NY
1365 * phy_read_mmd - Convenience function for reading a register
1366 * from an MMD on a given PHY.
1878f0dc
NY
1367 */
1368int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
1369
4069a572
AL
1370/**
1371 * phy_read_mmd_poll_timeout - Periodically poll a PHY register until a
1372 * condition is met or a timeout occurs
1373 *
1374 * @phydev: The phy_device struct
1375 * @devaddr: The MMD to read from
1376 * @regnum: The register on the MMD to read
1377 * @val: Variable to read the register into
1378 * @cond: Break condition (usually involving @val)
1379 * @sleep_us: Maximum time to sleep between reads in us (0
1380 * tight-loops). Should be less than ~20ms since usleep_range
1381 * is used (see Documentation/timers/timers-howto.rst).
1382 * @timeout_us: Timeout in us, 0 means never timeout
1383 * @sleep_before_read: if it is true, sleep @sleep_us before read.
1384 * Returns 0 on success and -ETIMEDOUT upon a timeout. In either
1385 * case, the last read value at @args is stored in @val. Must not
1386 * be called from atomic context if sleep_us or timeout_us are used.
1387 */
bd971ff0
DZ
1388#define phy_read_mmd_poll_timeout(phydev, devaddr, regnum, val, cond, \
1389 sleep_us, timeout_us, sleep_before_read) \
1390({ \
4ec73295
RKO
1391 int __ret, __val; \
1392 __ret = read_poll_timeout(__val = phy_read_mmd, val, \
1393 __val < 0 || (cond), \
bd971ff0
DZ
1394 sleep_us, timeout_us, sleep_before_read, \
1395 phydev, devaddr, regnum); \
4ec73295
RKO
1396 if (__val < 0) \
1397 __ret = __val; \
bd971ff0
DZ
1398 if (__ret) \
1399 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \
1400 __ret; \
1401})
1402
e86c6569 1403/*
1878f0dc
NY
1404 * __phy_read_mmd - Convenience function for reading a register
1405 * from an MMD on a given PHY.
1878f0dc
NY
1406 */
1407int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
1408
e86c6569 1409/*
1878f0dc
NY
1410 * phy_write_mmd - Convenience function for writing a register
1411 * on an MMD on a given PHY.
1878f0dc
NY
1412 */
1413int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
1414
e86c6569 1415/*
1878f0dc
NY
1416 * __phy_write_mmd - Convenience function for writing a register
1417 * on an MMD on a given PHY.
1878f0dc
NY
1418 */
1419int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
1420
b8554d4f
HK
1421int __phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask,
1422 u16 set);
1423int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask,
1424 u16 set);
788f9933 1425int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
2b74e5be 1426int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
788f9933 1427
b8554d4f
HK
1428int __phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
1429 u16 mask, u16 set);
1430int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
1431 u16 mask, u16 set);
1878f0dc 1432int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
b8554d4f 1433 u16 mask, u16 set);
1878f0dc 1434int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
b8554d4f 1435 u16 mask, u16 set);
1878f0dc 1436
ac8322d8
HK
1437/**
1438 * __phy_set_bits - Convenience function for setting bits in a PHY register
1439 * @phydev: the phy_device struct
1440 * @regnum: register number to write
1441 * @val: bits to set
1442 *
1443 * The caller must have taken the MDIO bus lock.
1444 */
1445static inline int __phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val)
1446{
1447 return __phy_modify(phydev, regnum, 0, val);
1448}
1449
1450/**
1451 * __phy_clear_bits - Convenience function for clearing bits in a PHY register
1452 * @phydev: the phy_device struct
1453 * @regnum: register number to write
1454 * @val: bits to clear
1455 *
1456 * The caller must have taken the MDIO bus lock.
1457 */
1458static inline int __phy_clear_bits(struct phy_device *phydev, u32 regnum,
1459 u16 val)
1460{
1461 return __phy_modify(phydev, regnum, val, 0);
1462}
1463
1464/**
1465 * phy_set_bits - Convenience function for setting bits in a PHY register
1466 * @phydev: the phy_device struct
1467 * @regnum: register number to write
1468 * @val: bits to set
1469 */
1470static inline int phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val)
1471{
1472 return phy_modify(phydev, regnum, 0, val);
1473}
1474
1475/**
1476 * phy_clear_bits - Convenience function for clearing bits in a PHY register
1477 * @phydev: the phy_device struct
1478 * @regnum: register number to write
1479 * @val: bits to clear
1480 */
1481static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val)
1482{
1483 return phy_modify(phydev, regnum, val, 0);
1484}
1485
1878f0dc
NY
1486/**
1487 * __phy_set_bits_mmd - Convenience function for setting bits in a register
1488 * on MMD
1489 * @phydev: the phy_device struct
1490 * @devad: the MMD containing register to modify
1491 * @regnum: register number to modify
1492 * @val: bits to set
1493 *
1494 * The caller must have taken the MDIO bus lock.
1495 */
1496static inline int __phy_set_bits_mmd(struct phy_device *phydev, int devad,
1497 u32 regnum, u16 val)
1498{
1499 return __phy_modify_mmd(phydev, devad, regnum, 0, val);
1500}
1501
1502/**
1503 * __phy_clear_bits_mmd - Convenience function for clearing bits in a register
1504 * on MMD
1505 * @phydev: the phy_device struct
1506 * @devad: the MMD containing register to modify
1507 * @regnum: register number to modify
1508 * @val: bits to clear
1509 *
1510 * The caller must have taken the MDIO bus lock.
1511 */
1512static inline int __phy_clear_bits_mmd(struct phy_device *phydev, int devad,
1513 u32 regnum, u16 val)
1514{
1515 return __phy_modify_mmd(phydev, devad, regnum, val, 0);
1516}
1517
1518/**
1519 * phy_set_bits_mmd - Convenience function for setting bits in a register
1520 * on MMD
1521 * @phydev: the phy_device struct
1522 * @devad: the MMD containing register to modify
1523 * @regnum: register number to modify
1524 * @val: bits to set
1525 */
1526static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad,
1527 u32 regnum, u16 val)
1528{
1529 return phy_modify_mmd(phydev, devad, regnum, 0, val);
1530}
1531
1532/**
1533 * phy_clear_bits_mmd - Convenience function for clearing bits in a register
1534 * on MMD
1535 * @phydev: the phy_device struct
1536 * @devad: the MMD containing register to modify
1537 * @regnum: register number to modify
1538 * @val: bits to clear
1539 */
1540static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad,
1541 u32 regnum, u16 val)
1542{
1543 return phy_modify_mmd(phydev, devad, regnum, val, 0);
1544}
1545
2c7b4921
FF
1546/**
1547 * phy_interrupt_is_valid - Convenience function for testing a given PHY irq
1548 * @phydev: the phy_device struct
1549 *
1550 * NOTE: must be kept in sync with addition/removal of PHY_POLL and
93e8990c 1551 * PHY_MAC_INTERRUPT
2c7b4921
FF
1552 */
1553static inline bool phy_interrupt_is_valid(struct phy_device *phydev)
1554{
93e8990c 1555 return phydev->irq != PHY_POLL && phydev->irq != PHY_MAC_INTERRUPT;
2c7b4921
FF
1556}
1557
3c507b8a
HK
1558/**
1559 * phy_polling_mode - Convenience function for testing whether polling is
1560 * used to detect PHY status changes
1561 * @phydev: the phy_device struct
1562 */
1563static inline bool phy_polling_mode(struct phy_device *phydev)
1564{
97c22438
AL
1565 if (phydev->state == PHY_CABLETEST)
1566 if (phydev->drv->flags & PHY_POLL_CABLE_TEST)
1567 return true;
1568
3c507b8a
HK
1569 return phydev->irq == PHY_POLL;
1570}
1571
0e5dafc8
RC
1572/**
1573 * phy_has_hwtstamp - Tests whether a PHY time stamp configuration.
1574 * @phydev: the phy_device struct
1575 */
1576static inline bool phy_has_hwtstamp(struct phy_device *phydev)
1577{
4715f65f 1578 return phydev && phydev->mii_ts && phydev->mii_ts->hwtstamp;
0e5dafc8
RC
1579}
1580
1581/**
1582 * phy_has_rxtstamp - Tests whether a PHY supports receive time stamping.
1583 * @phydev: the phy_device struct
1584 */
1585static inline bool phy_has_rxtstamp(struct phy_device *phydev)
1586{
4715f65f 1587 return phydev && phydev->mii_ts && phydev->mii_ts->rxtstamp;
0e5dafc8
RC
1588}
1589
1590/**
1591 * phy_has_tsinfo - Tests whether a PHY reports time stamping and/or
1592 * PTP hardware clock capabilities.
1593 * @phydev: the phy_device struct
1594 */
1595static inline bool phy_has_tsinfo(struct phy_device *phydev)
1596{
4715f65f 1597 return phydev && phydev->mii_ts && phydev->mii_ts->ts_info;
0e5dafc8
RC
1598}
1599
1600/**
1601 * phy_has_txtstamp - Tests whether a PHY supports transmit time stamping.
1602 * @phydev: the phy_device struct
1603 */
1604static inline bool phy_has_txtstamp(struct phy_device *phydev)
1605{
4715f65f 1606 return phydev && phydev->mii_ts && phydev->mii_ts->txtstamp;
0e5dafc8
RC
1607}
1608
446e2305
KM
1609static inline int phy_hwtstamp(struct phy_device *phydev,
1610 struct kernel_hwtstamp_config *cfg,
1611 struct netlink_ext_ack *extack)
0e5dafc8 1612{
446e2305 1613 return phydev->mii_ts->hwtstamp(phydev->mii_ts, cfg, extack);
0e5dafc8
RC
1614}
1615
1616static inline bool phy_rxtstamp(struct phy_device *phydev, struct sk_buff *skb,
1617 int type)
1618{
4715f65f 1619 return phydev->mii_ts->rxtstamp(phydev->mii_ts, skb, type);
0e5dafc8
RC
1620}
1621
1622static inline int phy_ts_info(struct phy_device *phydev,
2111375b 1623 struct kernel_ethtool_ts_info *tsinfo)
0e5dafc8 1624{
4715f65f 1625 return phydev->mii_ts->ts_info(phydev->mii_ts, tsinfo);
0e5dafc8
RC
1626}
1627
1628static inline void phy_txtstamp(struct phy_device *phydev, struct sk_buff *skb,
1629 int type)
1630{
4715f65f 1631 phydev->mii_ts->txtstamp(phydev->mii_ts, skb, type);
0e5dafc8
RC
1632}
1633
2dd35600
KM
1634/**
1635 * phy_is_default_hwtstamp - Is the PHY hwtstamp the default timestamp
1636 * @phydev: Pointer to phy_device
1637 *
1638 * This is used to get default timestamping device taking into account
1639 * the new API choice, which is selecting the timestamping from MAC by
1640 * default if the phydev does not have default_timestamp flag enabled.
1641 *
1642 * Return: True if phy is the default hw timestamp, false otherwise.
1643 */
1644static inline bool phy_is_default_hwtstamp(struct phy_device *phydev)
1645{
1646 return phy_has_hwtstamp(phydev) && phydev->default_timestamp;
1647}
1648
4284b6a5
FF
1649/**
1650 * phy_is_internal - Convenience function for testing if a PHY is internal
1651 * @phydev: the phy_device struct
1652 */
1653static inline bool phy_is_internal(struct phy_device *phydev)
1654{
1655 return phydev->is_internal;
1656}
1657
b834489b
RH
1658/**
1659 * phy_on_sfp - Convenience function for testing if a PHY is on an SFP module
1660 * @phydev: the phy_device struct
1661 */
1662static inline bool phy_on_sfp(struct phy_device *phydev)
1663{
1664 return phydev->is_on_sfp_module;
1665}
1666
32d0f783
IS
1667/**
1668 * phy_interface_mode_is_rgmii - Convenience function for testing if a
1669 * PHY interface mode is RGMII (all variants)
4069a572 1670 * @mode: the &phy_interface_t enum
32d0f783
IS
1671 */
1672static inline bool phy_interface_mode_is_rgmii(phy_interface_t mode)
1673{
1674 return mode >= PHY_INTERFACE_MODE_RGMII &&
1675 mode <= PHY_INTERFACE_MODE_RGMII_TXID;
1676};
1677
365c1e64 1678/**
4069a572 1679 * phy_interface_mode_is_8023z() - does the PHY interface mode use 802.3z
365c1e64
RK
1680 * negotiation
1681 * @mode: one of &enum phy_interface_t
1682 *
4069a572 1683 * Returns true if the PHY interface mode uses the 16-bit negotiation
365c1e64
RK
1684 * word as defined in 802.3z. (See 802.3-2015 37.2.1 Config_Reg encoding)
1685 */
1686static inline bool phy_interface_mode_is_8023z(phy_interface_t mode)
1687{
1688 return mode == PHY_INTERFACE_MODE_1000BASEX ||
1689 mode == PHY_INTERFACE_MODE_2500BASEX;
1690}
1691
e463d88c
FF
1692/**
1693 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
1694 * is RGMII (all variants)
1695 * @phydev: the phy_device struct
1696 */
1697static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
1698{
32d0f783 1699 return phy_interface_mode_is_rgmii(phydev->interface);
5a11dd7d
FF
1700};
1701
4069a572 1702/**
5a11dd7d
FF
1703 * phy_is_pseudo_fixed_link - Convenience function for testing if this
1704 * PHY is the CPU port facing side of an Ethernet switch, or similar.
1705 * @phydev: the phy_device struct
1706 */
1707static inline bool phy_is_pseudo_fixed_link(struct phy_device *phydev)
1708{
1709 return phydev->is_pseudo_fixed_link;
e463d88c
FF
1710}
1711
78ffc4ac
RK
1712int phy_save_page(struct phy_device *phydev);
1713int phy_select_page(struct phy_device *phydev, int page);
1714int phy_restore_page(struct phy_device *phydev, int oldpage, int ret);
1715int phy_read_paged(struct phy_device *phydev, int page, u32 regnum);
1716int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val);
bf22b343
HK
1717int phy_modify_paged_changed(struct phy_device *phydev, int page, u32 regnum,
1718 u16 mask, u16 set);
78ffc4ac
RK
1719int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum,
1720 u16 mask, u16 set);
1721
7d49a32a 1722struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id,
4017b4d3
SS
1723 bool is_c45,
1724 struct phy_c45_device_ids *c45_ids);
90eff909 1725#if IS_ENABLED(CONFIG_PHYLIB)
114dea60 1726int fwnode_get_phy_id(struct fwnode_handle *fwnode, u32 *phy_id);
0fb16976 1727struct mdio_device *fwnode_mdio_find_device(struct fwnode_handle *fwnode);
425775ed
CJ
1728struct phy_device *fwnode_phy_find_device(struct fwnode_handle *phy_fwnode);
1729struct phy_device *device_phy_find_device(struct device *dev);
4a0faa02 1730struct fwnode_handle *fwnode_get_phy_node(const struct fwnode_handle *fwnode);
ac28b9f8 1731struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45);
4dea547f 1732int phy_device_register(struct phy_device *phy);
90eff909
FF
1733void phy_device_free(struct phy_device *phydev);
1734#else
114dea60
CJ
1735static inline int fwnode_get_phy_id(struct fwnode_handle *fwnode, u32 *phy_id)
1736{
1737 return 0;
1738}
0fb16976
CJ
1739static inline
1740struct mdio_device *fwnode_mdio_find_device(struct fwnode_handle *fwnode)
1741{
1742 return 0;
1743}
1744
425775ed
CJ
1745static inline
1746struct phy_device *fwnode_phy_find_device(struct fwnode_handle *phy_fwnode)
1747{
1748 return NULL;
1749}
1750
1751static inline struct phy_device *device_phy_find_device(struct device *dev)
1752{
1753 return NULL;
1754}
1755
1756static inline
1757struct fwnode_handle *fwnode_get_phy_node(struct fwnode_handle *fwnode)
1758{
1759 return NULL;
1760}
1761
90eff909
FF
1762static inline
1763struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45)
1764{
1765 return NULL;
1766}
1767
1768static inline int phy_device_register(struct phy_device *phy)
1769{
1770 return 0;
1771}
1772
1773static inline void phy_device_free(struct phy_device *phydev) { }
1774#endif /* CONFIG_PHYLIB */
38737e49 1775void phy_device_remove(struct phy_device *phydev);
8b72b301 1776int phy_get_c45_ids(struct phy_device *phydev);
2f5cb434 1777int phy_init_hw(struct phy_device *phydev);
481b5d93
SH
1778int phy_suspend(struct phy_device *phydev);
1779int phy_resume(struct phy_device *phydev);
9c2c2e62 1780int __phy_resume(struct phy_device *phydev);
f0f9b4ed 1781int phy_loopback(struct phy_device *phydev, bool enable);
b2db6f4a
MC
1782int phy_sfp_connect_phy(void *upstream, struct phy_device *phy);
1783void phy_sfp_disconnect_phy(void *upstream, struct phy_device *phy);
298e54fa
RK
1784void phy_sfp_attach(void *upstream, struct sfp_bus *bus);
1785void phy_sfp_detach(void *upstream, struct sfp_bus *bus);
1786int phy_sfp_probe(struct phy_device *phydev,
1787 const struct sfp_upstream_ops *ops);
4017b4d3
SS
1788struct phy_device *phy_attach(struct net_device *dev, const char *bus_id,
1789 phy_interface_t interface);
f8f76db1 1790struct phy_device *phy_find_first(struct mii_bus *bus);
257184d7
AF
1791int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
1792 u32 flags, phy_interface_t interface);
fa94f6d9 1793int phy_connect_direct(struct net_device *dev, struct phy_device *phydev,
4017b4d3
SS
1794 void (*handler)(struct net_device *),
1795 phy_interface_t interface);
1796struct phy_device *phy_connect(struct net_device *dev, const char *bus_id,
1797 void (*handler)(struct net_device *),
1798 phy_interface_t interface);
e1393456
AF
1799void phy_disconnect(struct phy_device *phydev);
1800void phy_detach(struct phy_device *phydev);
1801void phy_start(struct phy_device *phydev);
1802void phy_stop(struct phy_device *phydev);
014068dc 1803int phy_config_aneg(struct phy_device *phydev);
6a23c555 1804int _phy_start_aneg(struct phy_device *phydev);
e1393456 1805int phy_start_aneg(struct phy_device *phydev);
372788f9 1806int phy_aneg_done(struct phy_device *phydev);
2b9672dd
HK
1807int phy_speed_down(struct phy_device *phydev, bool sync);
1808int phy_speed_up(struct phy_device *phydev);
cf9f6079 1809bool phy_check_valid(int speed, int duplex, unsigned long *features);
e1393456 1810
002ba705 1811int phy_restart_aneg(struct phy_device *phydev);
a9668491 1812int phy_reset_after_clk_enable(struct phy_device *phydev);
00db8189 1813
a68a8138
AL
1814#if IS_ENABLED(CONFIG_PHYLIB)
1815int phy_start_cable_test(struct phy_device *phydev,
1816 struct netlink_ext_ack *extack);
1a644de2 1817int phy_start_cable_test_tdr(struct phy_device *phydev,
f2bc8ad3
AL
1818 struct netlink_ext_ack *extack,
1819 const struct phy_tdr_config *config);
a68a8138
AL
1820#else
1821static inline
1822int phy_start_cable_test(struct phy_device *phydev,
1823 struct netlink_ext_ack *extack)
1824{
1825 NL_SET_ERR_MSG(extack, "Kernel not compiled with PHYLIB support");
1826 return -EOPNOTSUPP;
1827}
1a644de2
AL
1828static inline
1829int phy_start_cable_test_tdr(struct phy_device *phydev,
f2bc8ad3
AL
1830 struct netlink_ext_ack *extack,
1831 const struct phy_tdr_config *config)
1a644de2
AL
1832{
1833 NL_SET_ERR_MSG(extack, "Kernel not compiled with PHYLIB support");
1834 return -EOPNOTSUPP;
1835}
a68a8138
AL
1836#endif
1837
bafbdd52
SS
1838static inline void phy_device_reset(struct phy_device *phydev, int value)
1839{
1840 mdio_device_reset(&phydev->mdio, value);
1841}
1842
72ba48be 1843#define phydev_err(_phydev, format, args...) \
e5a03bfd 1844 dev_err(&_phydev->mdio.dev, format, ##args)
72ba48be 1845
a7936798
RV
1846#define phydev_err_probe(_phydev, err, format, args...) \
1847 dev_err_probe(&_phydev->mdio.dev, err, format, ##args)
1848
c4fabb8b
AL
1849#define phydev_info(_phydev, format, args...) \
1850 dev_info(&_phydev->mdio.dev, format, ##args)
1851
ab2a605f
AL
1852#define phydev_warn(_phydev, format, args...) \
1853 dev_warn(&_phydev->mdio.dev, format, ##args)
1854
72ba48be 1855#define phydev_dbg(_phydev, format, args...) \
2eaa38d9 1856 dev_dbg(&_phydev->mdio.dev, format, ##args)
72ba48be 1857
84eff6d1
AL
1858static inline const char *phydev_name(const struct phy_device *phydev)
1859{
e5a03bfd 1860 return dev_name(&phydev->mdio.dev);
84eff6d1
AL
1861}
1862
bec170e5
HK
1863static inline void phy_lock_mdio_bus(struct phy_device *phydev)
1864{
1865 mutex_lock(&phydev->mdio.bus->mdio_lock);
1866}
1867
1868static inline void phy_unlock_mdio_bus(struct phy_device *phydev)
1869{
1870 mutex_unlock(&phydev->mdio.bus->mdio_lock);
1871}
1872
2220943a
AL
1873void phy_attached_print(struct phy_device *phydev, const char *fmt, ...)
1874 __printf(2, 3);
e27f1787
FF
1875char *phy_attached_info_irq(struct phy_device *phydev)
1876 __malloc;
2220943a 1877void phy_attached_info(struct phy_device *phydev);
5acde34a
RK
1878
1879/* Clause 22 PHY */
045925e3 1880int genphy_read_abilities(struct phy_device *phydev);
3fb69bca 1881int genphy_setup_forced(struct phy_device *phydev);
00db8189 1882int genphy_restart_aneg(struct phy_device *phydev);
2a10ab04 1883int genphy_check_and_restart_aneg(struct phy_device *phydev, bool restart);
cd34499c 1884int genphy_config_eee_advert(struct phy_device *phydev);
f4069cd7 1885int __genphy_config_aneg(struct phy_device *phydev, bool changed);
a9fa6e6a 1886int genphy_aneg_done(struct phy_device *phydev);
00db8189 1887int genphy_update_link(struct phy_device *phydev);
8d3dc3ac 1888int genphy_read_lpa(struct phy_device *phydev);
0efc286a 1889int genphy_read_status_fixed(struct phy_device *phydev);
00db8189 1890int genphy_read_status(struct phy_device *phydev);
64807c23 1891int genphy_read_master_slave(struct phy_device *phydev);
0f0ca340
GC
1892int genphy_suspend(struct phy_device *phydev);
1893int genphy_resume(struct phy_device *phydev);
f0f9b4ed 1894int genphy_loopback(struct phy_device *phydev, bool enable);
797ac071 1895int genphy_soft_reset(struct phy_device *phydev);
87de1f05 1896irqreturn_t genphy_handle_interrupt_no_ack(struct phy_device *phydev);
f4069cd7
HK
1897
1898static inline int genphy_config_aneg(struct phy_device *phydev)
1899{
1900 return __genphy_config_aneg(phydev, false);
1901}
1902
4c8e0459
LW
1903static inline int genphy_no_config_intr(struct phy_device *phydev)
1904{
1905 return 0;
1906}
5df7af85
KH
1907int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad,
1908 u16 regnum);
1909int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum,
1910 u16 regnum, u16 val);
5acde34a 1911
fa6e98ce
HK
1912/* Clause 37 */
1913int genphy_c37_config_aneg(struct phy_device *phydev);
9b1d5e05 1914int genphy_c37_read_status(struct phy_device *phydev, bool *changed);
fa6e98ce 1915
5acde34a
RK
1916/* Clause 45 PHY */
1917int genphy_c45_restart_aneg(struct phy_device *phydev);
1af9f168 1918int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart);
5acde34a 1919int genphy_c45_aneg_done(struct phy_device *phydev);
998a8a83 1920int genphy_c45_read_link(struct phy_device *phydev);
5acde34a
RK
1921int genphy_c45_read_lpa(struct phy_device *phydev);
1922int genphy_c45_read_pma(struct phy_device *phydev);
1923int genphy_c45_pma_setup_forced(struct phy_device *phydev);
90532850 1924int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev);
9a5dc8af 1925int genphy_c45_an_config_aneg(struct phy_device *phydev);
5acde34a 1926int genphy_c45_an_disable_aneg(struct phy_device *phydev);
ea4efe25 1927int genphy_c45_read_mdix(struct phy_device *phydev);
ac3f5533 1928int genphy_c45_pma_read_abilities(struct phy_device *phydev);
0c476157 1929int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev);
eba2e4c2 1930int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev);
14e47d1f 1931int genphy_c45_read_eee_abilities(struct phy_device *phydev);
b9a366f3 1932int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev);
70fa3a96 1933int genphy_c45_read_status(struct phy_device *phydev);
2013ad88 1934int genphy_c45_baset1_read_status(struct phy_device *phydev);
94acaeb5 1935int genphy_c45_config_aneg(struct phy_device *phydev);
0ef25ed1 1936int genphy_c45_loopback(struct phy_device *phydev, bool enable);
da702f34
RPNO
1937int genphy_c45_pma_resume(struct phy_device *phydev);
1938int genphy_c45_pma_suspend(struct phy_device *phydev);
63c67f52 1939int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable);
49332341
PB
1940int genphy_c45_plca_get_cfg(struct phy_device *phydev,
1941 struct phy_plca_cfg *plca_cfg);
1942int genphy_c45_plca_set_cfg(struct phy_device *phydev,
1943 const struct phy_plca_cfg *plca_cfg);
1944int genphy_c45_plca_get_status(struct phy_device *phydev,
1945 struct phy_plca_status *plca_st);
022c3f87
OR
1946int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *adv,
1947 unsigned long *lp, bool *is_enabled);
1948int genphy_c45_ethtool_get_eee(struct phy_device *phydev,
d80a5233 1949 struct ethtool_keee *data);
022c3f87 1950int genphy_c45_ethtool_set_eee(struct phy_device *phydev,
d80a5233 1951 struct ethtool_keee *data);
022c3f87 1952int genphy_c45_write_eee_adv(struct phy_device *phydev, unsigned long *adv);
b6478b8c 1953int genphy_c45_an_config_eee_aneg(struct phy_device *phydev);
3eeca4e1 1954int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv);
5acde34a 1955
3970ed49
AL
1956/* Generic C45 PHY driver */
1957extern struct phy_driver genphy_c45_driver;
1958
e8a714e0
FF
1959/* The gen10g_* functions are the old Clause 45 stub */
1960int gen10g_config_aneg(struct phy_device *phydev);
e8a714e0 1961
00fde795
HK
1962static inline int phy_read_status(struct phy_device *phydev)
1963{
1964 if (!phydev->drv)
1965 return -EIO;
1966
1967 if (phydev->drv->read_status)
1968 return phydev->drv->read_status(phydev);
1969 else
1970 return genphy_read_status(phydev);
1971}
1972
00db8189 1973void phy_driver_unregister(struct phy_driver *drv);
d5bf9071 1974void phy_drivers_unregister(struct phy_driver *drv, int n);
be01da72
AL
1975int phy_driver_register(struct phy_driver *new_driver, struct module *owner);
1976int phy_drivers_register(struct phy_driver *new_driver, int n,
1977 struct module *owner);
293e9a3d 1978void phy_error(struct phy_device *phydev);
4f9c85a1 1979void phy_state_machine(struct work_struct *work);
97b33bdf 1980void phy_queue_state_machine(struct phy_device *phydev, unsigned long jiffies);
293e9a3d 1981void phy_trigger_machine(struct phy_device *phydev);
28b2e0d2 1982void phy_mac_interrupt(struct phy_device *phydev);
29935aeb 1983void phy_start_machine(struct phy_device *phydev);
00db8189 1984void phy_stop_machine(struct phy_device *phydev);
5514174f 1985void phy_ethtool_ksettings_get(struct phy_device *phydev,
1986 struct ethtool_link_ksettings *cmd);
2d55173e
PR
1987int phy_ethtool_ksettings_set(struct phy_device *phydev,
1988 const struct ethtool_link_ksettings *cmd);
4017b4d3 1989int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd);
bbbf8430 1990int phy_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
3231e5d2 1991int phy_do_ioctl_running(struct net_device *dev, struct ifreq *ifr, int cmd);
3dd4ef1b 1992int phy_disable_interrupts(struct phy_device *phydev);
434a4315 1993void phy_request_interrupt(struct phy_device *phydev);
07b09289 1994void phy_free_interrupt(struct phy_device *phydev);
e1393456 1995void phy_print_status(struct phy_device *phydev);
0c3e10cb
SA
1996int phy_get_rate_matching(struct phy_device *phydev,
1997 phy_interface_t iface);
73c105ad 1998void phy_set_max_speed(struct phy_device *phydev, u32 max_speed);
41124fa6 1999void phy_remove_link_mode(struct phy_device *phydev, u32 link_mode);
22c0ef6b 2000void phy_advertise_supported(struct phy_device *phydev);
b6469127 2001void phy_advertise_eee_all(struct phy_device *phydev);
c306ad36 2002void phy_support_sym_pause(struct phy_device *phydev);
af8d9bb2 2003void phy_support_asym_pause(struct phy_device *phydev);
49168d19 2004void phy_support_eee(struct phy_device *phydev);
0c122405
AL
2005void phy_set_sym_pause(struct phy_device *phydev, bool rx, bool tx,
2006 bool autoneg);
70814e81 2007void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx);
22b7d299
AL
2008bool phy_validate_pause(struct phy_device *phydev,
2009 struct ethtool_pauseparam *pp);
a87ae8a9 2010void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause);
92252eec
DM
2011
2012s32 phy_get_internal_delay(struct phy_device *phydev, struct device *dev,
2013 const int *delay_values, int size, bool is_rx);
2014
a87ae8a9
RK
2015void phy_resolve_pause(unsigned long *local_adv, unsigned long *partner_adv,
2016 bool *tx_pause, bool *rx_pause);
00db8189 2017
f62220d3 2018int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
4017b4d3 2019 int (*run)(struct phy_device *));
f62220d3 2020int phy_register_fixup_for_id(const char *bus_id,
4017b4d3 2021 int (*run)(struct phy_device *));
f62220d3 2022int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
4017b4d3 2023 int (*run)(struct phy_device *));
f62220d3 2024
f38e7a32
WH
2025int phy_unregister_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask);
2026int phy_unregister_fixup_for_id(const char *bus_id);
2027int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask);
2028
a59a4d19
GC
2029int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable);
2030int phy_get_eee_err(struct phy_device *phydev);
d80a5233
HK
2031int phy_ethtool_set_eee(struct phy_device *phydev, struct ethtool_keee *data);
2032int phy_ethtool_get_eee(struct phy_device *phydev, struct ethtool_keee *data);
42e836eb 2033int phy_ethtool_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol);
4017b4d3
SS
2034void phy_ethtool_get_wol(struct phy_device *phydev,
2035 struct ethtool_wolinfo *wol);
9d9a77ce
PR
2036int phy_ethtool_get_link_ksettings(struct net_device *ndev,
2037 struct ethtool_link_ksettings *cmd);
2038int phy_ethtool_set_link_ksettings(struct net_device *ndev,
2039 const struct ethtool_link_ksettings *cmd);
e86a8987 2040int phy_ethtool_nway_reset(struct net_device *ndev);
9eea577e 2041int phy_package_join(struct phy_device *phydev, int base_addr, size_t priv_size);
471e8fd3 2042int of_phy_package_join(struct phy_device *phydev, size_t priv_size);
63490847
MW
2043void phy_package_leave(struct phy_device *phydev);
2044int devm_phy_package_join(struct device *dev, struct phy_device *phydev,
9eea577e 2045 int base_addr, size_t priv_size);
471e8fd3
CM
2046int devm_of_phy_package_join(struct device *dev, struct phy_device *phydev,
2047 size_t priv_size);
a59a4d19 2048
9b9a8bfc
AF
2049int __init mdio_bus_init(void);
2050void mdio_bus_exit(void);
9e8d438e 2051
17809516
FF
2052int phy_ethtool_get_strings(struct phy_device *phydev, u8 *data);
2053int phy_ethtool_get_sset_count(struct phy_device *phydev);
2054int phy_ethtool_get_stats(struct phy_device *phydev,
2055 struct ethtool_stats *stats, u64 *data);
a23a1e57
PB
2056int phy_ethtool_get_plca_cfg(struct phy_device *phydev,
2057 struct phy_plca_cfg *plca_cfg);
2058int phy_ethtool_set_plca_cfg(struct phy_device *phydev,
2059 const struct phy_plca_cfg *plca_cfg,
2060 struct netlink_ext_ack *extack);
2061int phy_ethtool_get_plca_status(struct phy_device *phydev,
2062 struct phy_plca_status *plca_st);
9b9a8bfc 2063
60495b66
VO
2064int __phy_hwtstamp_get(struct phy_device *phydev,
2065 struct kernel_hwtstamp_config *config);
2066int __phy_hwtstamp_set(struct phy_device *phydev,
2067 struct kernel_hwtstamp_config *config,
2068 struct netlink_ext_ack *extack);
2069
9eea577e
CM
2070static inline int phy_package_address(struct phy_device *phydev,
2071 unsigned int addr_offset)
63490847
MW
2072{
2073 struct phy_package_shared *shared = phydev->shared;
9eea577e 2074 u8 base_addr = shared->base_addr;
63490847 2075
9eea577e 2076 if (addr_offset >= PHY_MAX_ADDR - base_addr)
63490847
MW
2077 return -EIO;
2078
9eea577e
CM
2079 /* we know that addr will be in the range 0..31 and thus the
2080 * implicit cast to a signed int is not a problem.
2081 */
2082 return base_addr + addr_offset;
63490847
MW
2083}
2084
9eea577e
CM
2085static inline int phy_package_read(struct phy_device *phydev,
2086 unsigned int addr_offset, u32 regnum)
63490847 2087{
9eea577e 2088 int addr = phy_package_address(phydev, addr_offset);
63490847 2089
9eea577e
CM
2090 if (addr < 0)
2091 return addr;
2092
2093 return mdiobus_read(phydev->mdio.bus, addr, regnum);
2094}
2095
2096static inline int __phy_package_read(struct phy_device *phydev,
2097 unsigned int addr_offset, u32 regnum)
2098{
2099 int addr = phy_package_address(phydev, addr_offset);
2100
2101 if (addr < 0)
2102 return addr;
63490847 2103
9eea577e 2104 return __mdiobus_read(phydev->mdio.bus, addr, regnum);
63490847
MW
2105}
2106
2107static inline int phy_package_write(struct phy_device *phydev,
9eea577e
CM
2108 unsigned int addr_offset, u32 regnum,
2109 u16 val)
63490847 2110{
9eea577e 2111 int addr = phy_package_address(phydev, addr_offset);
63490847 2112
9eea577e
CM
2113 if (addr < 0)
2114 return addr;
63490847 2115
9eea577e 2116 return mdiobus_write(phydev->mdio.bus, addr, regnum, val);
63490847
MW
2117}
2118
2119static inline int __phy_package_write(struct phy_device *phydev,
9eea577e
CM
2120 unsigned int addr_offset, u32 regnum,
2121 u16 val)
63490847 2122{
9eea577e 2123 int addr = phy_package_address(phydev, addr_offset);
63490847 2124
9eea577e
CM
2125 if (addr < 0)
2126 return addr;
63490847 2127
9eea577e 2128 return __mdiobus_write(phydev->mdio.bus, addr, regnum, val);
63490847
MW
2129}
2130
d63710fc
CM
2131int __phy_package_read_mmd(struct phy_device *phydev,
2132 unsigned int addr_offset, int devad,
2133 u32 regnum);
2134
2135int phy_package_read_mmd(struct phy_device *phydev,
2136 unsigned int addr_offset, int devad,
2137 u32 regnum);
2138
2139int __phy_package_write_mmd(struct phy_device *phydev,
2140 unsigned int addr_offset, int devad,
2141 u32 regnum, u16 val);
2142
2143int phy_package_write_mmd(struct phy_device *phydev,
2144 unsigned int addr_offset, int devad,
2145 u32 regnum, u16 val);
2146
0ef44e5c
AT
2147static inline bool __phy_package_set_once(struct phy_device *phydev,
2148 unsigned int b)
63490847
MW
2149{
2150 struct phy_package_shared *shared = phydev->shared;
2151
2152 if (!shared)
2153 return false;
2154
0ef44e5c
AT
2155 return !test_and_set_bit(b, &shared->flags);
2156}
2157
2158static inline bool phy_package_init_once(struct phy_device *phydev)
2159{
2160 return __phy_package_set_once(phydev, PHY_SHARED_F_INIT_DONE);
2161}
2162
2163static inline bool phy_package_probe_once(struct phy_device *phydev)
2164{
2165 return __phy_package_set_once(phydev, PHY_SHARED_F_PROBE_DONE);
63490847
MW
2166}
2167
81800aef 2168extern const struct bus_type mdio_bus_type;
c31accd1 2169
648ea013
FF
2170struct mdio_board_info {
2171 const char *bus_id;
2172 char modalias[MDIO_NAME_SIZE];
2173 int mdio_addr;
2174 const void *platform_data;
2175};
2176
90eff909 2177#if IS_ENABLED(CONFIG_MDIO_DEVICE)
648ea013
FF
2178int mdiobus_register_board_info(const struct mdio_board_info *info,
2179 unsigned int n);
2180#else
2181static inline int mdiobus_register_board_info(const struct mdio_board_info *i,
2182 unsigned int n)
2183{
2184 return 0;
2185}
2186#endif
2187
2188
c31accd1 2189/**
39097ab6 2190 * phy_module_driver() - Helper macro for registering PHY drivers
c31accd1 2191 * @__phy_drivers: array of PHY drivers to register
39097ab6 2192 * @__count: Numbers of members in array
c31accd1
JH
2193 *
2194 * Helper macro for PHY drivers which do not do anything special in module
2195 * init/exit. Each module may only use this macro once, and calling it
2196 * replaces module_init() and module_exit().
2197 */
2198#define phy_module_driver(__phy_drivers, __count) \
2199static int __init phy_module_init(void) \
2200{ \
be01da72 2201 return phy_drivers_register(__phy_drivers, __count, THIS_MODULE); \
c31accd1
JH
2202} \
2203module_init(phy_module_init); \
2204static void __exit phy_module_exit(void) \
2205{ \
2206 phy_drivers_unregister(__phy_drivers, __count); \
2207} \
2208module_exit(phy_module_exit)
2209
2210#define module_phy_driver(__phy_drivers) \
2211 phy_module_driver(__phy_drivers, ARRAY_SIZE(__phy_drivers))
2212
5db5ea99
FF
2213bool phy_driver_is_genphy(struct phy_device *phydev);
2214bool phy_driver_is_genphy_10g(struct phy_device *phydev);
2215
00db8189 2216#endif /* __PHY_H */
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