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net: phy: fix phylib's dual eee_enabled
[linux.git] / drivers / net / phy / phy-c45.c
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457c8996 1// SPDX-License-Identifier: GPL-2.0-only
5acde34a
RK		 2/*
3 * Clause 45 PHY support
4 */
5#include <linux/ethtool.h>
6#include <linux/export.h>
7#include <linux/mdio.h>
8#include <linux/mii.h>
9#include <linux/phy.h>
10
49332341
PB		 11#include "mdio-open-alliance.h"
12
3da8ffd8
AT		 13/**
14 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
15 * @phydev: target phy_device struct
16 */
17static bool genphy_c45_baset1_able(struct phy_device *phydev)
18{
19 int val;
20
21 if (phydev->pma_extable == -ENODATA) {
22 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
23 if (val < 0)
24 return false;
25
26 phydev->pma_extable = val;
27 }
28
29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1);
30}
31
da702f34
RPNO		 32/**
33 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
34 * @phydev: target phy_device struct
35 */
36static bool genphy_c45_pma_can_sleep(struct phy_device *phydev)
37{
38 int stat1;
39
40 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);
41 if (stat1 < 0)
42 return false;
43
44 return !!(stat1 & MDIO_STAT1_LPOWERABLE);
45}
46
47/**
48 * genphy_c45_pma_resume - wakes up the PMA module
49 * @phydev: target phy_device struct
50 */
51int genphy_c45_pma_resume(struct phy_device *phydev)
52{
53 if (!genphy_c45_pma_can_sleep(phydev))
54 return -EOPNOTSUPP;
55
56 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
57 MDIO_CTRL1_LPOWER);
58}
59EXPORT_SYMBOL_GPL(genphy_c45_pma_resume);
60
61/**
62 * genphy_c45_pma_suspend - suspends the PMA module
63 * @phydev: target phy_device struct
64 */
65int genphy_c45_pma_suspend(struct phy_device *phydev)
66{
67 if (!genphy_c45_pma_can_sleep(phydev))
68 return -EOPNOTSUPP;
69
70 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
71 MDIO_CTRL1_LPOWER);
72}
73EXPORT_SYMBOL_GPL(genphy_c45_pma_suspend);
74
90532850
OR		 75/**
76 * genphy_c45_pma_baset1_setup_master_slave - configures forced master/slave
77 * role of BaseT1 devices.
78 * @phydev: target phy_device struct
79 */
80int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev)
81{
82 int ctl = 0;
83
84 switch (phydev->master_slave_set) {
85 case MASTER_SLAVE_CFG_MASTER_PREFERRED:
86 case MASTER_SLAVE_CFG_MASTER_FORCE:
87 ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST;
88 break;
89 case MASTER_SLAVE_CFG_SLAVE_FORCE:
90 case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
a04dd88f 91 break;
90532850
OR		 92 case MASTER_SLAVE_CFG_UNKNOWN:
93 case MASTER_SLAVE_CFG_UNSUPPORTED:
a04dd88f 94 return 0;
90532850
OR		 95 default:
96 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
97 return -EOPNOTSUPP;
98 }
99
100 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
101 MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl);
102}
103EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_setup_master_slave);
104
5acde34a 105/**
69280228 106 * genphy_c45_pma_setup_forced - configures a forced speed
5acde34a
RK		 107 * @phydev: target phy_device struct
108 */
109int genphy_c45_pma_setup_forced(struct phy_device *phydev)
110{
25108a83 111 int bt1_ctrl, ctrl1, ctrl2, ret;
5acde34a
RK		 112
113 /* Half duplex is not supported */
114 if (phydev->duplex != DUPLEX_FULL)
115 return -EINVAL;
116
117 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
118 if (ctrl1 < 0)
119 return ctrl1;
120
121 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2);
122 if (ctrl2 < 0)
123 return ctrl2;
124
125 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL;
126 /*
127 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1
128 * in 802.3-2012 and 802.3-2015.
129 */
130 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30);
131
132 switch (phydev->speed) {
133 case SPEED_10:
3da8ffd8
AT		 134 if (genphy_c45_baset1_able(phydev))
135 ctrl2 |= MDIO_PMA_CTRL2_BASET1;
136 else
137 ctrl2 |= MDIO_PMA_CTRL2_10BT;
5acde34a
RK		 138 break;
139 case SPEED_100:
140 ctrl1 |= MDIO_PMA_CTRL1_SPEED100;
141 ctrl2 |= MDIO_PMA_CTRL2_100BTX;
142 break;
143 case SPEED_1000:
144 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000;
145 /* Assume 1000base-T */
146 ctrl2 |= MDIO_PMA_CTRL2_1000BT;
147 break;
7fd8afa8
MC		 148 case SPEED_2500:
149 ctrl1 |= MDIO_CTRL1_SPEED2_5G;
150 /* Assume 2.5Gbase-T */
151 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT;
152 break;
153 case SPEED_5000:
154 ctrl1 |= MDIO_CTRL1_SPEED5G;
155 /* Assume 5Gbase-T */
156 ctrl2 |= MDIO_PMA_CTRL2_5GBT;
157 break;
5acde34a
RK		 158 case SPEED_10000:
159 ctrl1 |= MDIO_CTRL1_SPEED10G;
160 /* Assume 10Gbase-T */
161 ctrl2 |= MDIO_PMA_CTRL2_10GBT;
162 break;
163 default:
164 return -EINVAL;
165 }
166
167 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
168 if (ret < 0)
169 return ret;
170
29f000f7
HK		 171 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
172 if (ret < 0)
173 return ret;
174
3da8ffd8 175 if (genphy_c45_baset1_able(phydev)) {
90532850 176 ret = genphy_c45_pma_baset1_setup_master_slave(phydev);
3da8ffd8
AT		 177 if (ret < 0)
178 return ret;
25108a83
SE		 179
180 bt1_ctrl = 0;
181 if (phydev->speed == SPEED_1000)
182 bt1_ctrl = MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000;
183
184 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
185 MDIO_PMA_PMD_BT1_CTRL_STRAP, bt1_ctrl);
186 if (ret < 0)
187 return ret;
3da8ffd8
AT		 188 }
189
29f000f7 190 return genphy_c45_an_disable_aneg(phydev);
5acde34a
RK		 191}
192EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
193
3da8ffd8
AT		 194/* Sets master/slave preference and supported technologies.
195 * The preference is set in the BIT(4) of BASE-T1 AN
196 * advertisement register 7.515 and whether the status
197 * is forced or not, it is set in the BIT(12) of BASE-T1
198 * AN advertisement register 7.514.
199 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation
200 * advertisement register [31:16] if supported.
201 */
202static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev)
203{
3702e404
OR		 204 u16 adv_l_mask, adv_l = 0;
205 u16 adv_m_mask, adv_m = 0;
3da8ffd8 206 int changed = 0;
3da8ffd8
AT		 207 int ret;
208
3702e404
OR		 209 adv_l_mask = MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP |
210 MDIO_AN_T1_ADV_L_PAUSE_ASYM;
8d9a577f
DF		 211 adv_m_mask = MDIO_AN_T1_ADV_M_1000BT1 | MDIO_AN_T1_ADV_M_100BT1 |
212 MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L;
3702e404 213
3da8ffd8
AT		 214 switch (phydev->master_slave_set) {
215 case MASTER_SLAVE_CFG_MASTER_FORCE:
3702e404
OR		 216 adv_m |= MDIO_AN_T1_ADV_M_MST;
217 fallthrough;
3da8ffd8
AT		 218 case MASTER_SLAVE_CFG_SLAVE_FORCE:
219 adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS;
220 break;
221 case MASTER_SLAVE_CFG_MASTER_PREFERRED:
3702e404
OR		 222 adv_m |= MDIO_AN_T1_ADV_M_MST;
223 fallthrough;
3da8ffd8
AT		 224 case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
225 break;
a7f0e4be
OR		 226 case MASTER_SLAVE_CFG_UNKNOWN:
227 case MASTER_SLAVE_CFG_UNSUPPORTED:
3702e404
OR		 228 /* if master/slave role is not specified, do not overwrite it */
229 adv_l_mask &= ~MDIO_AN_T1_ADV_L_FORCE_MS;
230 adv_m_mask &= ~MDIO_AN_T1_ADV_M_MST;
231 break;
3da8ffd8 232 default:
a7f0e4be
OR		 233 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
234 return -EOPNOTSUPP;
3da8ffd8
AT		 235 }
236
3da8ffd8
AT		 237 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising);
238
239 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L,
3702e404 240 adv_l_mask, adv_l);
3da8ffd8
AT		 241 if (ret < 0)
242 return ret;
243 if (ret > 0)
244 changed = 1;
245
246 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising);
247
248 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M,
3702e404 249 adv_m_mask, adv_m);
3da8ffd8
AT		 250 if (ret < 0)
251 return ret;
252 if (ret > 0)
253 changed = 1;
254
255 return changed;
256}
257
9a5dc8af
AL		 258/**
259 * genphy_c45_an_config_aneg - configure advertisement registers
260 * @phydev: target phy_device struct
261 *
262 * Configure advertisement registers based on modes set in phydev->advertising
263 *
264 * Returns negative errno code on failure, 0 if advertisement didn't change,
265 * or 1 if advertised modes changed.
266 */
267int genphy_c45_an_config_aneg(struct phy_device *phydev)
268{
c24a34f5 269 int changed = 0, ret;
9a5dc8af
AL		 270 u32 adv;
271
272 linkmode_and(phydev->advertising, phydev->advertising,
273 phydev->supported);
274
b6478b8c 275 ret = genphy_c45_an_config_eee_aneg(phydev);
5827b168
OR		 276 if (ret < 0)
277 return ret;
278 else if (ret)
279 changed = true;
cc429d52 280
3da8ffd8
AT		 281 if (genphy_c45_baset1_able(phydev))
282 return genphy_c45_baset1_an_config_aneg(phydev);
283
9a5dc8af
AL		 284 adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
285
9731ea06
HK		 286 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
287 ADVERTISE_ALL | ADVERTISE_100BASE4 |
288 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
289 adv);
9a5dc8af
AL		 290 if (ret < 0)
291 return ret;
292 if (ret > 0)
293 changed = 1;
294
295 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
296
9731ea06
HK		 297 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
298 MDIO_AN_10GBT_CTRL_ADV10G |
299 MDIO_AN_10GBT_CTRL_ADV5G |
300 MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
9a5dc8af
AL		 301 if (ret < 0)
302 return ret;
303 if (ret > 0)
304 changed = 1;
305
306 return changed;
307}
308EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg);
309
5acde34a
RK		 310/**
311 * genphy_c45_an_disable_aneg - disable auto-negotiation
312 * @phydev: target phy_device struct
313 *
314 * Disable auto-negotiation in the Clause 45 PHY. The link parameters
e1f82127 315 * are controlled through the PMA/PMD MMD registers.
5acde34a
RK		 316 *
317 * Returns zero on success, negative errno code on failure.
318 */
319int genphy_c45_an_disable_aneg(struct phy_device *phydev)
320{
3da8ffd8 321 u16 reg = MDIO_CTRL1;
5acde34a 322
3da8ffd8
AT		 323 if (genphy_c45_baset1_able(phydev))
324 reg = MDIO_AN_T1_CTRL;
325
326 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
b52c018d 327 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
5acde34a
RK		 328}
329EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
330
331/**
332 * genphy_c45_restart_aneg - Enable and restart auto-negotiation
333 * @phydev: target phy_device struct
334 *
335 * This assumes that the auto-negotiation MMD is present.
336 *
337 * Enable and restart auto-negotiation.
338 */
339int genphy_c45_restart_aneg(struct phy_device *phydev)
340{
3da8ffd8
AT		 341 u16 reg = MDIO_CTRL1;
342
343 if (genphy_c45_baset1_able(phydev))
344 reg = MDIO_AN_T1_CTRL;
345
346 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg,
b52c018d 347 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
5acde34a
RK		 348}
349EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
350
1af9f168
HK		 351/**
352 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation
353 * @phydev: target phy_device struct
354 * @restart: whether aneg restart is requested
355 *
356 * This assumes that the auto-negotiation MMD is present.
357 *
358 * Check, and restart auto-negotiation if needed.
359 */
360int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
361{
3da8ffd8 362 u16 reg = MDIO_CTRL1;
4f31c532 363 int ret;
1af9f168 364
3da8ffd8
AT		 365 if (genphy_c45_baset1_able(phydev))
366 reg = MDIO_AN_T1_CTRL;
367
1af9f168
HK		 368 if (!restart) {
369 /* Configure and restart aneg if it wasn't set before */
3da8ffd8 370 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
1af9f168
HK		 371 if (ret < 0)
372 return ret;
373
374 if (!(ret & MDIO_AN_CTRL1_ENABLE))
375 restart = true;
376 }
377
378 if (restart)
4f31c532 379 return genphy_c45_restart_aneg(phydev);
1af9f168 380
4f31c532 381 return 0;
1af9f168
HK		 382}
383EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
384
5acde34a
RK		 385/**
386 * genphy_c45_aneg_done - return auto-negotiation complete status
387 * @phydev: target phy_device struct
388 *
389 * This assumes that the auto-negotiation MMD is present.
390 *
391 * Reads the status register from the auto-negotiation MMD, returning:
392 * - positive if auto-negotiation is complete
393 * - negative errno code on error
394 * - zero otherwise
395 */
396int genphy_c45_aneg_done(struct phy_device *phydev)
397{
3da8ffd8
AT		 398 int reg = MDIO_STAT1;
399 int val;
400
401 if (genphy_c45_baset1_able(phydev))
402 reg = MDIO_AN_T1_STAT;
403
404 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
5acde34a
RK		 405
406 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0;
407}
408EXPORT_SYMBOL_GPL(genphy_c45_aneg_done);
409
410/**
411 * genphy_c45_read_link - read the overall link status from the MMDs
412 * @phydev: target phy_device struct
5acde34a
RK		 413 *
414 * Read the link status from the specified MMDs, and if they all indicate
a6e11f6b 415 * that the link is up, set phydev->link to 1. If an error is encountered,
5acde34a
RK		 416 * a negative errno will be returned, otherwise zero.
417 */
998a8a83 418int genphy_c45_read_link(struct phy_device *phydev)
5acde34a 419{
c1164bb1 420 u32 mmd_mask = MDIO_DEVS_PMAPMD;
5acde34a
RK		 421 int val, devad;
422 bool link = true;
423
320ed3bf 424 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
c36757eb
HK		 425 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
426 if (val < 0)
427 return val;
428
429 /* Autoneg is being started, therefore disregard current
430 * link status and report link as down.
431 */
432 if (val & MDIO_AN_CTRL1_RESTART) {
433 phydev->link = 0;
434 return 0;
435 }
436 }
437
a6e11f6b 438 while (mmd_mask && link) {
5acde34a
RK		 439 devad = __ffs(mmd_mask);
440 mmd_mask &= ~BIT(devad);
441
442 /* The link state is latched low so that momentary link
93c09704 443 * drops can be detected. Do not double-read the status
e96bd2d3
PO		 444 * in polling mode to detect such short link drops except
445 * the link was already down.
5acde34a 446 */
e96bd2d3 447 if (!phy_polling_mode(phydev) || !phydev->link) {
93c09704
HK		 448 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
449 if (val < 0)
450 return val;
c397ab21
HK		 451 else if (val & MDIO_STAT1_LSTATUS)
452 continue;
93c09704
HK		 453 }
454
5acde34a
RK		 455 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
456 if (val < 0)
457 return val;
458
459 if (!(val & MDIO_STAT1_LSTATUS))
460 link = false;
461 }
462
a6e11f6b
HK		 463 phydev->link = link;
464
465 return 0;
5acde34a
RK		 466}
467EXPORT_SYMBOL_GPL(genphy_c45_read_link);
468
3da8ffd8
AT		 469/* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check
470 * if autoneg is complete. If so read the BASE-T1 Autonegotiation
471 * Advertisement registers filling in the link partner advertisement,
472 * pause and asym_pause members in phydev.
473 */
474static int genphy_c45_baset1_read_lpa(struct phy_device *phydev)
475{
476 int val;
477
478 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
479 if (val < 0)
480 return val;
481
482 if (!(val & MDIO_AN_STAT1_COMPLETE)) {
483 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising);
484 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0);
485 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0);
486
487 phydev->pause = 0;
488 phydev->asym_pause = 0;
489
490 return 0;
491 }
492
493 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1);
494
495 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L);
496 if (val < 0)
497 return val;
498
499 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val);
500 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0;
501 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0;
502
503 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M);
504 if (val < 0)
505 return val;
506
507 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val);
508
509 return 0;
510}
511
5acde34a 512/**
cc1122b0 513 * genphy_c45_read_lpa - read the link partner advertisement and pause
5acde34a
RK		 514 * @phydev: target phy_device struct
515 *
516 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers,
cc1122b0 517 * filling in the link partner advertisement, pause and asym_pause members
5acde34a
RK		 518 * in @phydev. This assumes that the auto-negotiation MMD is present, and
519 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected
520 * to fill in the remainder of the link partner advert from vendor registers.
521 */
522int genphy_c45_read_lpa(struct phy_device *phydev)
523{
524 int val;
525
3da8ffd8
AT		 526 if (genphy_c45_baset1_able(phydev))
527 return genphy_c45_baset1_read_lpa(phydev);
528
5d237a07
HK		 529 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
530 if (val < 0)
531 return val;
532
372fcc1b
HK		 533 if (!(val & MDIO_AN_STAT1_COMPLETE)) {
534 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
535 phydev->lp_advertising);
536 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
537 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0);
538 phydev->pause = 0;
539 phydev->asym_pause = 0;
540
541 return 0;
542 }
543
5d237a07
HK		 544 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising,
545 val & MDIO_AN_STAT1_LPABLE);
546
cc1122b0 547 /* Read the link partner's base page advertisement */
5acde34a
RK		 548 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
549 if (val < 0)
550 return val;
551
5d237a07 552 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val);
5acde34a
RK		 553 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0;
554 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0;
555
cc1122b0 556 /* Read the link partner's 10G advertisement */
5acde34a
RK		 557 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
558 if (val < 0)
559 return val;
560
96c2be34 561 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
5acde34a
RK		 562
563 return 0;
564}
565EXPORT_SYMBOL_GPL(genphy_c45_read_lpa);
566
b9a366f3
OR		 567/**
568 * genphy_c45_pma_baset1_read_master_slave - read forced master/slave
569 * configuration
570 * @phydev: target phy_device struct
571 */
572int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev)
573{
574 int val;
575
576 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
acb8c5ae 577 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
b9a366f3
OR		 578
579 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL);
580 if (val < 0)
581 return val;
582
acb8c5ae
OR		 583 if (val & MDIO_PMA_PMD_BT1_CTRL_CFG_MST) {
584 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
b9a366f3 585 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
acb8c5ae
OR		 586 } else {
587 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
b9a366f3 588 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
acb8c5ae 589 }
b9a366f3
OR		 590
591 return 0;
592}
593EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_master_slave);
594
5acde34a
RK		 595/**
596 * genphy_c45_read_pma - read link speed etc from PMA
597 * @phydev: target phy_device struct
598 */
599int genphy_c45_read_pma(struct phy_device *phydev)
600{
601 int val;
602
3de5ae54
YL		 603 linkmode_zero(phydev->lp_advertising);
604
5acde34a
RK		 605 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
606 if (val < 0)
607 return val;
608
609 switch (val & MDIO_CTRL1_SPEEDSEL) {
610 case 0:
611 phydev->speed = SPEED_10;
612 break;
613 case MDIO_PMA_CTRL1_SPEED100:
614 phydev->speed = SPEED_100;
615 break;
616 case MDIO_PMA_CTRL1_SPEED1000:
617 phydev->speed = SPEED_1000;
618 break;
7fd8afa8
MC		 619 case MDIO_CTRL1_SPEED2_5G:
620 phydev->speed = SPEED_2500;
621 break;
622 case MDIO_CTRL1_SPEED5G:
623 phydev->speed = SPEED_5000;
624 break;
5acde34a
RK		 625 case MDIO_CTRL1_SPEED10G:
626 phydev->speed = SPEED_10000;
627 break;
628 default:
629 phydev->speed = SPEED_UNKNOWN;
630 break;
631 }
632
633 phydev->duplex = DUPLEX_FULL;
634
3da8ffd8 635 if (genphy_c45_baset1_able(phydev)) {
b9a366f3 636 val = genphy_c45_pma_baset1_read_master_slave(phydev);
3da8ffd8
AT		 637 if (val < 0)
638 return val;
3da8ffd8
AT		 639 }
640
5acde34a
RK		 641 return 0;
642}
643EXPORT_SYMBOL_GPL(genphy_c45_read_pma);
921690f2 644
ea4efe25
RK		 645/**
646 * genphy_c45_read_mdix - read mdix status from PMA
647 * @phydev: target phy_device struct
648 */
649int genphy_c45_read_mdix(struct phy_device *phydev)
650{
651 int val;
652
653 if (phydev->speed == SPEED_10000) {
654 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
655 MDIO_PMA_10GBT_SWAPPOL);
656 if (val < 0)
657 return val;
658
659 switch (val) {
660 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
661 phydev->mdix = ETH_TP_MDI;
662 break;
663
664 case 0:
665 phydev->mdix = ETH_TP_MDI_X;
666 break;
667
668 default:
669 phydev->mdix = ETH_TP_MDI_INVALID;
670 break;
671 }
672 }
673
674 return 0;
675}
676EXPORT_SYMBOL_GPL(genphy_c45_read_mdix);
677
022c3f87
OR		 678/**
679 * genphy_c45_write_eee_adv - write advertised EEE link modes
680 * @phydev: target phy_device struct
681 * @adv: the linkmode advertisement settings
682 */
683int genphy_c45_write_eee_adv(struct phy_device *phydev, unsigned long *adv)
684{
972074ea 685 int val, changed = 0;
022c3f87 686
e209519b 687 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
022c3f87
OR		 688 val = linkmode_to_mii_eee_cap1_t(adv);
689
690 /* In eee_broken_modes are stored MDIO_AN_EEE_ADV specific raw
691 * register values.
692 */
693 val &= ~phydev->eee_broken_modes;
694
695 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1
696 * (Register 7.60)
697 */
698 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
699 MDIO_AN_EEE_ADV,
700 MDIO_EEE_100TX | MDIO_EEE_1000T |
701 MDIO_EEE_10GT | MDIO_EEE_1000KX |
702 MDIO_EEE_10GKX4 | MDIO_EEE_10GKR,
703 val);
704 if (val < 0)
705 return val;
706 if (val > 0)
707 changed = 1;
708 }
709
9a1e3129
HK		 710 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) {
711 val = linkmode_to_mii_eee_cap2_t(adv);
712
713 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2
714 * (Register 7.62)
715 */
716 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
717 MDIO_AN_EEE_ADV2,
718 MDIO_EEE_2_5GT | MDIO_EEE_5GT,
719 val);
720 if (val < 0)
721 return val;
722 if (val > 0)
723 changed = 1;
724 }
725
022c3f87
OR		 726 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
727 phydev->supported_eee)) {
728 val = linkmode_adv_to_mii_10base_t1_t(adv);
729 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register
730 * (Register 7.526)
731 */
732 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
733 MDIO_AN_10BT1_AN_CTRL,
734 MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L,
735 val);
736 if (val < 0)
737 return val;
738 if (val > 0)
739 changed = 1;
740 }
741
742 return changed;
743}
744
745/**
746 * genphy_c45_read_eee_adv - read advertised EEE link modes
747 * @phydev: target phy_device struct
748 * @adv: the linkmode advertisement status
749 */
3eeca4e1 750int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv)
022c3f87
OR		 751{
752 int val;
753
e209519b 754 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
022c3f87
OR		 755 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1
756 * (Register 7.60)
757 */
758 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
759 if (val < 0)
760 return val;
761
762 mii_eee_cap1_mod_linkmode_t(adv, val);
763 }
764
9a1e3129
HK		 765 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) {
766 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2
767 * (Register 7.62)
768 */
769 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
770 if (val < 0)
771 return val;
772
773 mii_eee_cap2_mod_linkmode_adv_t(adv, val);
774 }
775
022c3f87
OR		 776 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
777 phydev->supported_eee)) {
778 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register
779 * (Register 7.526)
780 */
781 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL);
782 if (val < 0)
783 return val;
784
785 mii_10base_t1_adv_mod_linkmode_t(adv, val);
786 }
787
788 return 0;
789}
790
791/**
792 * genphy_c45_read_eee_lpa - read advertised LP EEE link modes
793 * @phydev: target phy_device struct
794 * @lpa: the linkmode LP advertisement status
795 */
796static int genphy_c45_read_eee_lpa(struct phy_device *phydev,
797 unsigned long *lpa)
798{
799 int val;
800
e209519b 801 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
022c3f87
OR		 802 /* IEEE 802.3-2018 45.2.7.14 EEE link partner ability 1
803 * (Register 7.61)
804 */
805 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
806 if (val < 0)
807 return val;
808
809 mii_eee_cap1_mod_linkmode_t(lpa, val);
810 }
811
1bbe04e3
HK		 812 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) {
813 /* IEEE 802.3-2022 45.2.7.17 EEE link partner ability 2
814 * (Register 7.63)
815 */
816 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE2);
817 if (val < 0)
818 return val;
819
820 mii_eee_cap2_mod_linkmode_adv_t(lpa, val);
821 }
822
022c3f87
OR		 823 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
824 phydev->supported_eee)) {
825 /* IEEE 802.3cg-2019 45.2.7.26 10BASE-T1 AN status register
826 * (Register 7.527)
827 */
828 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT);
829 if (val < 0)
830 return val;
831
832 mii_10base_t1_adv_mod_linkmode_t(lpa, val);
833 }
834
835 return 0;
836}
837
14e47d1f
OR		 838/**
839 * genphy_c45_read_eee_cap1 - read supported EEE link modes from register 3.20
840 * @phydev: target phy_device struct
841 */
842static int genphy_c45_read_eee_cap1(struct phy_device *phydev)
843{
844 int val;
845
846 /* IEEE 802.3-2018 45.2.3.10 EEE control and capability 1
847 * (Register 3.20)
848 */
849 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
850 if (val < 0)
851 return val;
852
853 /* The 802.3 2018 standard says the top 2 bits are reserved and should
854 * read as 0. Also, it seems unlikely anybody will build a PHY which
855 * supports 100GBASE-R deep sleep all the way down to 100BASE-TX EEE.
856 * If MDIO_PCS_EEE_ABLE is 0xffff assume EEE is not supported.
857 */
858 if (val == 0xffff)
859 return 0;
860
861 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val);
862
863 /* Some buggy devices indicate EEE link modes in MDIO_PCS_EEE_ABLE
864 * which they don't support as indicated by BMSR, ESTATUS etc.
865 */
866 linkmode_and(phydev->supported_eee, phydev->supported_eee,
867 phydev->supported);
868
869 return 0;
870}
871
b63584c8
HK		 872/**
873 * genphy_c45_read_eee_cap2 - read supported EEE link modes from register 3.21
874 * @phydev: target phy_device struct
875 */
876static int genphy_c45_read_eee_cap2(struct phy_device *phydev)
877{
878 int val;
879
880 /* IEEE 802.3-2022 45.2.3.11 EEE control and capability 2
881 * (Register 3.21)
882 */
883 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2);
884 if (val < 0)
885 return val;
886
887 /* IEEE 802.3-2022 45.2.3.11 says 9 bits are reserved. */
888 if (val == 0xffff)
889 return 0;
890
891 mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val);
892
893 return 0;
894}
895
14e47d1f
OR		 896/**
897 * genphy_c45_read_eee_abilities - read supported EEE link modes
898 * @phydev: target phy_device struct
899 */
900int genphy_c45_read_eee_abilities(struct phy_device *phydev)
901{
902 int val;
903
904 /* There is not indicator whether optional register
905 * "EEE control and capability 1" (3.20) is supported. Read it only
906 * on devices with appropriate linkmodes.
907 */
908 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) {
909 val = genphy_c45_read_eee_cap1(phydev);
910 if (val)
911 return val;
912 }
913
b63584c8
HK		 914 /* Same for cap2 (3.21) */
915 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) {
916 val = genphy_c45_read_eee_cap2(phydev);
917 if (val)
918 return val;
919 }
920
14e47d1f
OR		 921 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
922 phydev->supported)) {
923 /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register
924 * (Register 1.2295)
925 */
926 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);
927 if (val < 0)
928 return val;
929
930 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
931 phydev->supported_eee,
932 val & MDIO_PMA_10T1L_STAT_EEE);
933 }
934
935 return 0;
936}
937EXPORT_SYMBOL_GPL(genphy_c45_read_eee_abilities);
938
b6478b8c
OR		 939/**
940 * genphy_c45_an_config_eee_aneg - configure EEE advertisement
941 * @phydev: target phy_device struct
942 */
943int genphy_c45_an_config_eee_aneg(struct phy_device *phydev)
944{
41ffcd95 945 if (!phydev->eee_cfg.eee_enabled) {
3eeca4e1
OR		 946 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {};
947
948 return genphy_c45_write_eee_adv(phydev, adv);
949 }
950
951 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee);
b6478b8c
OR		 952}
953
eba2e4c2
SE		 954/**
955 * genphy_c45_pma_baset1_read_abilities - read supported baset1 link modes from PMA
956 * @phydev: target phy_device struct
957 *
958 * Read the supported link modes from the extended BASE-T1 ability register
959 */
960int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev)
961{
962 int val;
963
964 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1);
965 if (val < 0)
966 return val;
967
968 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
969 phydev->supported,
970 val & MDIO_PMA_PMD_BT1_B10L_ABLE);
971
a60eb720
SE		 972 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT,
973 phydev->supported,
974 val & MDIO_PMA_PMD_BT1_B100_ABLE);
975
976 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT1_Full_BIT,
977 phydev->supported,
978 val & MDIO_PMA_PMD_BT1_B1000_ABLE);
979
eba2e4c2
SE		 980 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
981 if (val < 0)
982 return val;
983
984 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
985 phydev->supported,
986 val & MDIO_AN_STAT1_ABLE);
987
988 return 0;
989}
990EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_abilities);
991
0c476157
OR		 992/**
993 * genphy_c45_pma_read_ext_abilities - read supported link modes from PMA
994 * @phydev: target phy_device struct
995 *
996 * Read the supported link modes from the PMA/PMD extended ability register
997 * (Register 1.11).
998 */
999int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev)
1000{
1001 int val;
1002
1003 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
1004 if (val < 0)
1005 return val;
1006
1007 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
1008 phydev->supported,
1009 val & MDIO_PMA_EXTABLE_10GBLRM);
1010 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1011 phydev->supported,
1012 val & MDIO_PMA_EXTABLE_10GBT);
1013 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
1014 phydev->supported,
1015 val & MDIO_PMA_EXTABLE_10GBKX4);
1016 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1017 phydev->supported,
1018 val & MDIO_PMA_EXTABLE_10GBKR);
1019 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1020 phydev->supported,
1021 val & MDIO_PMA_EXTABLE_1000BT);
1022 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1023 phydev->supported,
1024 val & MDIO_PMA_EXTABLE_1000BKX);
1025
1026 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1027 phydev->supported,
1028 val & MDIO_PMA_EXTABLE_100BTX);
1029 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
1030 phydev->supported,
1031 val & MDIO_PMA_EXTABLE_100BTX);
1032
1033 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
1034 phydev->supported,
1035 val & MDIO_PMA_EXTABLE_10BT);
1036 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
1037 phydev->supported,
1038 val & MDIO_PMA_EXTABLE_10BT);
1039
1040 if (val & MDIO_PMA_EXTABLE_NBT) {
1041 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
1042 MDIO_PMA_NG_EXTABLE);
1043 if (val < 0)
1044 return val;
1045
1046 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
1047 phydev->supported,
1048 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
1049
1050 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
1051 phydev->supported,
1052 val & MDIO_PMA_NG_EXTABLE_5GBT);
1053 }
1054
1055 if (val & MDIO_PMA_EXTABLE_BT1) {
1056 val = genphy_c45_pma_baset1_read_abilities(phydev);
1057 if (val < 0)
1058 return val;
1059 }
1060
1061 return 0;
1062}
1063EXPORT_SYMBOL_GPL(genphy_c45_pma_read_ext_abilities);
1064
ac3f5533
MC		 1065/**
1066 * genphy_c45_pma_read_abilities - read supported link modes from PMA
1067 * @phydev: target phy_device struct
1068 *
1069 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit
1070 * 1.8.9 is set, the list of supported modes is build using the values in the
1071 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related
1072 * modes. If bit 1.11.14 is set, then the list is also extended with the modes
1073 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and
1074 * 5GBASET are supported.
1075 */
1076int genphy_c45_pma_read_abilities(struct phy_device *phydev)
1077{
1078 int val;
1079
b6a4119d 1080 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
320ed3bf 1081 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
b6a4119d
HK		 1082 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
1083 if (val < 0)
1084 return val;
1085
1086 if (val & MDIO_AN_STAT1_ABLE)
1087 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
1088 phydev->supported);
1089 }
1090
ac3f5533
MC		 1091 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
1092 if (val < 0)
1093 return val;
1094
1095 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
1096 phydev->supported,
1097 val & MDIO_PMA_STAT2_10GBSR);
1098
1099 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
1100 phydev->supported,
1101 val & MDIO_PMA_STAT2_10GBLR);
1102
1103 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
1104 phydev->supported,
1105 val & MDIO_PMA_STAT2_10GBER);
1106
1107 if (val & MDIO_PMA_STAT2_EXTABLE) {
0c476157 1108 val = genphy_c45_pma_read_ext_abilities(phydev);
ac3f5533
MC		 1109 if (val < 0)
1110 return val;
ac3f5533
MC		 1111 }
1112
5827b168
OR		 1113 /* This is optional functionality. If not supported, we may get an error
1114 * which should be ignored.
1115 */
1116 genphy_c45_read_eee_abilities(phydev);
1117
ac3f5533
MC		 1118 return 0;
1119}
1120EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);
1121
3da8ffd8
AT		 1122/* Read master/slave preference from registers.
1123 * The preference is read from the BIT(4) of BASE-T1 AN
1124 * advertisement register 7.515 and whether the preference
1125 * is forced or not, it is read from BASE-T1 AN advertisement
1126 * register 7.514.
1127 */
2013ad88 1128int genphy_c45_baset1_read_status(struct phy_device *phydev)
3da8ffd8
AT		 1129{
1130 int ret;
1131 int cfg;
1132
1133 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1134 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1135
1136 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L);
1137 if (ret < 0)
1138 return ret;
1139
1140 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M);
1141 if (cfg < 0)
1142 return cfg;
1143
1144 if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) {
1145 if (cfg & MDIO_AN_T1_ADV_M_MST)
1146 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1147 else
1148 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1149 } else {
1150 if (cfg & MDIO_AN_T1_ADV_M_MST)
1151 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED;
1152 else
1153 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED;
1154 }
1155
1156 return 0;
1157}
2013ad88 1158EXPORT_SYMBOL_GPL(genphy_c45_baset1_read_status);
3da8ffd8 1159
70fa3a96
HK		 1160/**
1161 * genphy_c45_read_status - read PHY status
1162 * @phydev: target phy_device struct
1163 *
1164 * Reads status from PHY and sets phy_device members accordingly.
1165 */
1166int genphy_c45_read_status(struct phy_device *phydev)
1167{
1168 int ret;
1169
1170 ret = genphy_c45_read_link(phydev);
1171 if (ret)
1172 return ret;
1173
1174 phydev->speed = SPEED_UNKNOWN;
1175 phydev->duplex = DUPLEX_UNKNOWN;
1176 phydev->pause = 0;
1177 phydev->asym_pause = 0;
1178
1179 if (phydev->autoneg == AUTONEG_ENABLE) {
1180 ret = genphy_c45_read_lpa(phydev);
1181 if (ret)
1182 return ret;
1183
3da8ffd8
AT		 1184 if (genphy_c45_baset1_able(phydev)) {
1185 ret = genphy_c45_baset1_read_status(phydev);
1186 if (ret < 0)
1187 return ret;
1188 }
1189
70fa3a96
HK		 1190 phy_resolve_aneg_linkmode(phydev);
1191 } else {
1192 ret = genphy_c45_read_pma(phydev);
1193 }
1194
1195 return ret;
1196}
1197EXPORT_SYMBOL_GPL(genphy_c45_read_status);
1198
94acaeb5
MH		 1199/**
1200 * genphy_c45_config_aneg - restart auto-negotiation or forced setup
1201 * @phydev: target phy_device struct
1202 *
1203 * Description: If auto-negotiation is enabled, we configure the
1204 * advertising, and then restart auto-negotiation. If it is not
1205 * enabled, then we force a configuration.
1206 */
1207int genphy_c45_config_aneg(struct phy_device *phydev)
1208{
1209 bool changed = false;
1210 int ret;
1211
1212 if (phydev->autoneg == AUTONEG_DISABLE)
1213 return genphy_c45_pma_setup_forced(phydev);
1214
1215 ret = genphy_c45_an_config_aneg(phydev);
1216 if (ret < 0)
1217 return ret;
1218 if (ret > 0)
1219 changed = true;
1220
1221 return genphy_c45_check_and_restart_aneg(phydev, changed);
1222}
1223EXPORT_SYMBOL_GPL(genphy_c45_config_aneg);
1224
921690f2
RK		 1225/* The gen10g_* functions are the old Clause 45 stub */
1226
e8a714e0 1227int gen10g_config_aneg(struct phy_device *phydev)
921690f2
RK		 1228{
1229 return 0;
1230}
e8a714e0 1231EXPORT_SYMBOL_GPL(gen10g_config_aneg);
921690f2 1232
0ef25ed1
WVK		 1233int genphy_c45_loopback(struct phy_device *phydev, bool enable)
1234{
1235 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
1236 MDIO_PCS_CTRL1_LOOPBACK,
1237 enable ? MDIO_PCS_CTRL1_LOOPBACK : 0);
1238}
1239EXPORT_SYMBOL_GPL(genphy_c45_loopback);
1240
63c67f52
LJ		 1241/**
1242 * genphy_c45_fast_retrain - configure fast retrain registers
1243 * @phydev: target phy_device struct
06338cef 1244 * @enable: enable fast retrain or not
63c67f52
LJ		 1245 *
1246 * Description: If fast-retrain is enabled, we configure PHY as
1247 * advertising fast retrain capable and THP Bypass Request, then
1248 * enable fast retrain. If it is not enabled, we configure fast
1249 * retrain disabled.
1250 */
1251int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable)
1252{
1253 int ret;
1254
1255 if (!enable)
1256 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
1257 MDIO_PMA_10GBR_FSRT_ENABLE);
1258
1259 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) {
1260 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
1261 MDIO_AN_10GBT_CTRL_ADVFSRT2_5G);
1262 if (ret)
1263 return ret;
1264
1265 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2,
1266 MDIO_AN_THP_BP2_5GT);
1267 if (ret)
1268 return ret;
1269 }
1270
1271 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
1272 MDIO_PMA_10GBR_FSRT_ENABLE);
1273}
1274EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain);
1275
49332341
PB		 1276/**
1277 * genphy_c45_plca_get_cfg - get PLCA configuration from standard registers
1278 * @phydev: target phy_device struct
1279 * @plca_cfg: output structure to store the PLCA configuration
1280 *
1281 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1282 * Management Registers specifications, this function can be used to retrieve
1283 * the current PLCA configuration from the standard registers in MMD 31.
1284 */
1285int genphy_c45_plca_get_cfg(struct phy_device *phydev,
1286 struct phy_plca_cfg *plca_cfg)
1287{
1288 int ret;
1289
1290 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER);
1291 if (ret < 0)
1292 return ret;
1293
1294 if ((ret & MDIO_OATC14_PLCA_IDM) != OATC14_IDM)
1295 return -ENODEV;
1296
1297 plca_cfg->version = ret & ~MDIO_OATC14_PLCA_IDM;
1298
1299 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0);
1300 if (ret < 0)
1301 return ret;
1302
1303 plca_cfg->enabled = !!(ret & MDIO_OATC14_PLCA_EN);
1304
1305 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1);
1306 if (ret < 0)
1307 return ret;
1308
1309 plca_cfg->node_cnt = (ret & MDIO_OATC14_PLCA_NCNT) >> 8;
1310 plca_cfg->node_id = (ret & MDIO_OATC14_PLCA_ID);
1311
1312 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR);
1313 if (ret < 0)
1314 return ret;
1315
1316 plca_cfg->to_tmr = ret & MDIO_OATC14_PLCA_TOT;
1317
1318 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST);
1319 if (ret < 0)
1320 return ret;
1321
1322 plca_cfg->burst_cnt = (ret & MDIO_OATC14_PLCA_MAXBC) >> 8;
1323 plca_cfg->burst_tmr = (ret & MDIO_OATC14_PLCA_BTMR);
1324
1325 return 0;
1326}
1327EXPORT_SYMBOL_GPL(genphy_c45_plca_get_cfg);
1328
1329/**
1330 * genphy_c45_plca_set_cfg - set PLCA configuration using standard registers
1331 * @phydev: target phy_device struct
1332 * @plca_cfg: structure containing the PLCA configuration. Fields set to -1 are
1333 * not to be changed.
1334 *
1335 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1336 * Management Registers specifications, this function can be used to modify
1337 * the PLCA configuration using the standard registers in MMD 31.
1338 */
1339int genphy_c45_plca_set_cfg(struct phy_device *phydev,
1340 const struct phy_plca_cfg *plca_cfg)
1341{
1038bfb2 1342 u16 val = 0;
49332341 1343 int ret;
49332341
PB		 1344
1345 // PLCA IDVER is read-only
1346 if (plca_cfg->version >= 0)
1347 return -EINVAL;
1348
1349 // first of all, disable PLCA if required
1350 if (plca_cfg->enabled == 0) {
1351 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
1352 MDIO_OATC14_PLCA_CTRL0,
1353 MDIO_OATC14_PLCA_EN);
1354
1355 if (ret < 0)
1356 return ret;
1357 }
1358
1359 // check if we need to set the PLCA node count, node ID, or both
1360 if (plca_cfg->node_cnt >= 0 || plca_cfg->node_id >= 0) {
1361 /* if one between node count and node ID is -not- to be
1362 * changed, read the register to later perform merge/purge of
1363 * the configuration as appropriate
1364 */
1365 if (plca_cfg->node_cnt < 0 || plca_cfg->node_id < 0) {
1366 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1367 MDIO_OATC14_PLCA_CTRL1);
1368
1369 if (ret < 0)
1370 return ret;
1371
1372 val = ret;
1373 }
1374
1375 if (plca_cfg->node_cnt >= 0)
1376 val = (val & ~MDIO_OATC14_PLCA_NCNT) |
1377 (plca_cfg->node_cnt << 8);
1378
1379 if (plca_cfg->node_id >= 0)
1380 val = (val & ~MDIO_OATC14_PLCA_ID) |
1381 (plca_cfg->node_id);
1382
1383 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1384 MDIO_OATC14_PLCA_CTRL1, val);
1385
1386 if (ret < 0)
1387 return ret;
1388 }
1389
1390 if (plca_cfg->to_tmr >= 0) {
1391 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1392 MDIO_OATC14_PLCA_TOTMR,
1393 plca_cfg->to_tmr);
1394
1395 if (ret < 0)
1396 return ret;
1397 }
1398
1399 // check if we need to set the PLCA burst count, burst timer, or both
1400 if (plca_cfg->burst_cnt >= 0 || plca_cfg->burst_tmr >= 0) {
1401 /* if one between burst count and burst timer is -not- to be
1402 * changed, read the register to later perform merge/purge of
1403 * the configuration as appropriate
1404 */
1405 if (plca_cfg->burst_cnt < 0 || plca_cfg->burst_tmr < 0) {
1406 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1407 MDIO_OATC14_PLCA_BURST);
1408
1409 if (ret < 0)
1410 return ret;
1411
1412 val = ret;
1413 }
1414
1415 if (plca_cfg->burst_cnt >= 0)
1416 val = (val & ~MDIO_OATC14_PLCA_MAXBC) |
1417 (plca_cfg->burst_cnt << 8);
1418
1419 if (plca_cfg->burst_tmr >= 0)
1420 val = (val & ~MDIO_OATC14_PLCA_BTMR) |
1421 (plca_cfg->burst_tmr);
1422
1423 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1424 MDIO_OATC14_PLCA_BURST, val);
1425
1426 if (ret < 0)
1427 return ret;
1428 }
1429
1430 // if we need to enable PLCA, do it at the end
1431 if (plca_cfg->enabled > 0) {
1432 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1433 MDIO_OATC14_PLCA_CTRL0,
1434 MDIO_OATC14_PLCA_EN);
1435
1436 if (ret < 0)
1437 return ret;
1438 }
1439
1440 return 0;
1441}
1442EXPORT_SYMBOL_GPL(genphy_c45_plca_set_cfg);
1443
1444/**
1445 * genphy_c45_plca_get_status - get PLCA status from standard registers
1446 * @phydev: target phy_device struct
1447 * @plca_st: output structure to store the PLCA status
1448 *
1449 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1450 * Management Registers specifications, this function can be used to retrieve
1451 * the current PLCA status information from the standard registers in MMD 31.
1452 */
1453int genphy_c45_plca_get_status(struct phy_device *phydev,
1454 struct phy_plca_status *plca_st)
1455{
1456 int ret;
1457
1458 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS);
1459 if (ret < 0)
1460 return ret;
1461
1462 plca_st->pst = !!(ret & MDIO_OATC14_PLCA_PST);
1463 return 0;
1464}
1465EXPORT_SYMBOL_GPL(genphy_c45_plca_get_status);
1466
022c3f87
OR		 1467/**
1468 * genphy_c45_eee_is_active - get EEE status
1469 * @phydev: target phy_device struct
1470 * @adv: variable to store advertised linkmodes
1471 * @lp: variable to store LP advertised linkmodes
1472 * @is_enabled: variable to store EEE enabled/disabled configuration value
1473 *
1474 * Description: this function will read local and link partner PHY
1475 * advertisements. Compare them return current EEE state.
1476 */
1477int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *adv,
1478 unsigned long *lp, bool *is_enabled)
1479{
1480 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_adv) = {};
1481 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp_lp) = {};
1482 __ETHTOOL_DECLARE_LINK_MODE_MASK(common);
1483 bool eee_enabled, eee_active;
1484 int ret;
1485
1486 ret = genphy_c45_read_eee_adv(phydev, tmp_adv);
1487 if (ret)
1488 return ret;
1489
1490 ret = genphy_c45_read_eee_lpa(phydev, tmp_lp);
1491 if (ret)
1492 return ret;
1493
1494 eee_enabled = !linkmode_empty(tmp_adv);
1495 linkmode_and(common, tmp_adv, tmp_lp);
1496 if (eee_enabled && !linkmode_empty(common))
1497 eee_active = phy_check_valid(phydev->speed, phydev->duplex,
1498 common);
1499 else
1500 eee_active = false;
1501
1502 if (adv)
1503 linkmode_copy(adv, tmp_adv);
1504 if (lp)
1505 linkmode_copy(lp, tmp_lp);
1506 if (is_enabled)
1507 *is_enabled = eee_enabled;
1508
1509 return eee_active;
1510}
1511EXPORT_SYMBOL(genphy_c45_eee_is_active);
1512
1513/**
1514 * genphy_c45_ethtool_get_eee - get EEE supported and status
1515 * @phydev: target phy_device struct
d80a5233 1516 * @data: ethtool_keee data
022c3f87
OR		 1517 *
1518 * Description: it reports the Supported/Advertisement/LP Advertisement
1519 * capabilities.
1520 */
1521int genphy_c45_ethtool_get_eee(struct phy_device *phydev,
d80a5233 1522 struct ethtool_keee *data)
022c3f87
OR		 1523{
1524 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv) = {};
1525 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp) = {};
2bb05261 1526 bool is_enabled;
022c3f87
OR		 1527 int ret;
1528
1529 ret = genphy_c45_eee_is_active(phydev, adv, lp, &is_enabled);
1530 if (ret < 0)
1531 return ret;
1532
1533 data->eee_enabled = is_enabled;
1534 data->eee_active = ret;
2bb05261
HK		 1535 linkmode_copy(data->supported, phydev->supported_eee);
1536 linkmode_copy(data->advertised, adv);
1537 linkmode_copy(data->lp_advertised, lp);
022c3f87
OR		 1538
1539 return 0;
1540}
1541EXPORT_SYMBOL(genphy_c45_ethtool_get_eee);
1542
1543/**
b7c31ccd 1544 * genphy_c45_ethtool_set_eee - set EEE supported and status
022c3f87 1545 * @phydev: target phy_device struct
d80a5233 1546 * @data: ethtool_keee data
022c3f87 1547 *
b7c31ccd
AL		 1548 * Description: sets the Supported/Advertisement/LP Advertisement
1549 * capabilities. If eee_enabled is false, no links modes are
1550 * advertised, but the previously advertised link modes are
1551 * retained. This allows EEE to be enabled/disabled in a
1552 * non-destructive way.
3e43b903
AL		 1553 * Returns either error code, 0 if there was no change, or positive
1554 * value if there was a change which triggered auto-neg.
022c3f87
OR		 1555 */
1556int genphy_c45_ethtool_set_eee(struct phy_device *phydev,
d80a5233 1557 struct ethtool_keee *data)
022c3f87 1558{
022c3f87
OR		 1559 int ret;
1560
1561 if (data->eee_enabled) {
2bb05261 1562 unsigned long *adv = data->advertised;
186b1da7 1563
2bb05261
HK		 1564 if (!linkmode_empty(adv)) {
1565 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp);
2bb05261 1566
b38061fe 1567 if (linkmode_andnot(tmp, adv, phydev->supported_eee)) {
186b1da7
OR		 1568 phydev_warn(phydev, "At least some EEE link modes are not supported.\n");
1569 return -EINVAL;
1570 }
186b1da7 1571 } else {
2bb05261 1572 adv = phydev->supported_eee;
186b1da7 1573 }
3eeca4e1 1574
2bb05261 1575 linkmode_copy(phydev->advertising_eee, adv);
022c3f87
OR		 1576 }
1577
3eeca4e1 1578 ret = genphy_c45_an_config_eee_aneg(phydev);
3e43b903
AL		 1579 if (ret > 0) {
1580 ret = phy_restart_aneg(phydev);
1581 if (ret < 0)
1582 return ret;
1583
1584 /* explicitly return 1, otherwise (ret > 0) value will be
1585 * overwritten by phy_restart_aneg().
1586 */
1587 return 1;
1588 }
022c3f87 1589
b38061fe 1590 return ret;
022c3f87
OR		 1591}
1592EXPORT_SYMBOL(genphy_c45_ethtool_set_eee);
1593
22b56e82 1594struct phy_driver genphy_c45_driver = {
921690f2
RK		 1595 .phy_id = 0xffffffff,
1596 .phy_id_mask = 0xffffffff,
22b56e82 1597 .name = "Generic Clause 45 PHY",
22b56e82 1598 .read_status = genphy_c45_read_status,
921690f2 1599};
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