[linux.git] / arch / sh / boards / board-magicpanelr2.c

/*
 * linux/arch/sh/boards/magicpanel/setup.c
 *
 *  Copyright (C) 2007  Markus Brunner, Mark Jonas
 *
 *  Magic Panel Release 2 board setup
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/smsc911x.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/map.h>
#include <mach/magicpanelr2.h>
#include <asm/heartbeat.h>
#include <cpu/sh7720.h>

#define LAN9115_READY	(__raw_readl(0xA8000084UL) & 0x00000001UL)

/* Prefer cmdline over RedBoot */
static const char *probes[] = { "cmdlinepart", "RedBoot", NULL };

/* Wait until reset finished. Timeout is 100ms. */
static int __init ethernet_reset_finished(void)
{
	int i;

	if (LAN9115_READY)
		return 1;

	for (i = 0; i < 10; ++i) {
		mdelay(10);
		if (LAN9115_READY)
			return 1;
	}

	return 0;
}

static void __init reset_ethernet(void)
{
	/* PMDR: LAN_RESET=on */
	CLRBITS_OUTB(0x10, PORT_PMDR);

	udelay(200);

	/* PMDR: LAN_RESET=off */
	SETBITS_OUTB(0x10, PORT_PMDR);
}

static void __init setup_chip_select(void)
{
	/* CS2: LAN (0x08000000 - 0x0bffffff) */
	/* no idle cycles, normal space, 8 bit data bus */
	__raw_writel(0x36db0400, CS2BCR);
	/* (SW:1.5 WR:3 HW:1.5), ext. wait */
	__raw_writel(0x000003c0, CS2WCR);

	/* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */
	/* no idle cycles, normal space, 8 bit data bus */
	__raw_writel(0x00000200, CS4BCR);
	/* (SW:1.5 WR:3 HW:1.5), ext. wait */
	__raw_writel(0x00100981, CS4WCR);

	/* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */
	/* no idle cycles, normal space, 8 bit data bus */
	__raw_writel(0x00000200, CS5ABCR);
	/* (SW:1.5 WR:3 HW:1.5), ext. wait */
	__raw_writel(0x00100981, CS5AWCR);

	/* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */
	/* no idle cycles, normal space, 8 bit data bus */
	__raw_writel(0x00000200, CS5BBCR);
	/* (SW:1.5 WR:3 HW:1.5), ext. wait */
	__raw_writel(0x00100981, CS5BWCR);

	/* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */
	/* no idle cycles, normal space, 8 bit data bus */
	__raw_writel(0x00000200, CS6ABCR);
	/* (SW:1.5 WR:3 HW:1.5), no ext. wait */
	__raw_writel(0x001009C1, CS6AWCR);
}

static void __init setup_port_multiplexing(void)
{
	/* A7 GPO(LED8);     A6 GPO(LED7);     A5 GPO(LED6);	  A4 GPO(LED5);
	 * A3 GPO(LED4);     A2 GPO(LED3);     A1 GPO(LED2);	  A0 GPO(LED1);
	 */
	__raw_writew(0x5555, PORT_PACR);	/* 01 01 01 01 01 01 01 01 */

	/* B7 GPO(RST4);   B6 GPO(RST3);  B5 GPO(RST2);    B4 GPO(RST1);
	 * B3 GPO(PB3);	   B2 GPO(PB2);	  B1 GPO(PB1);	   B0 GPO(PB0);
	 */
	__raw_writew(0x5555, PORT_PBCR);	/* 01 01 01 01 01 01 01 01 */

	/* C7 GPO(PC7);	  C6 GPO(PC6);	  C5 GPO(PC5);	   C4 GPO(PC4);
	 * C3 LCD_DATA3;  C2 LCD_DATA2;   C1 LCD_DATA1;	   C0 LCD_DATA0;
	 */
	__raw_writew(0x5500, PORT_PCCR);	/* 01 01 01 01 00 00 00 00 */

	/* D7 GPO(PD7);	D6 GPO(PD6);	D5 GPO(PD5);	   D4 GPO(PD4);
	 * D3 GPO(PD3);	D2 GPO(PD2);	D1 GPO(PD1);	   D0 GPO(PD0);
	 */
	__raw_writew(0x5555, PORT_PDCR);	/* 01 01 01 01 01 01 01 01 */

	/* E7 (x);	  E6 GPI(nu);	 E5 GPI(nu);	  E4 LCD_M_DISP;
	 * E3 LCD_CL1;	  E2 LCD_CL2;	 E1 LCD_DON;	  E0 LCD_FLM;
	 */
	__raw_writew(0x3C00, PORT_PECR);	/* 00 11 11 00 00 00 00 00 */

	/* F7 (x);	     F6 DA1(VLCD);     F5 DA0(nc);	  F4 AN3;
	 * F3 AN2(MID_AD);   F2 AN1(EARTH_AD); F1 AN0(TEMP);	  F0 GPI+(nc);
	 */
	__raw_writew(0x0002, PORT_PFCR);	/* 00 00 00 00 00 00 00 10 */

	/* G7 (x);	  G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2);
	 * G3 GPI(KEY1);  G2 GPO(LED11);	G1 GPO(LED10);     G0 GPO(LED9);
	 */
	__raw_writew(0x03D5, PORT_PGCR);	/* 00 00 00 11 11 01 01 01 */

	/* H7 (x);	      H6 /RAS(BRAS);	  H5 /CAS(BCAS); H4 CKE(BCKE);
	 * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR;	 H0 USB1_PWR;
	 */
	__raw_writew(0x0050, PORT_PHCR);	/* 00 00 00 00 01 01 00 00 */

	/* J7 (x);	  J6 AUDCK;	   J5 ASEBRKAK;	    J4 AUDATA3;
	 * J3 AUDATA2;	  J2 AUDATA1;	   J1 AUDATA0;	    J0 AUDSYNC;
	 */
	__raw_writew(0x0000, PORT_PJCR);	/* 00 00 00 00 00 00 00 00 */

	/* K7 (x);	    K6 (x);	     K5 (x);	   K4 (x);
	 * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY)
	 */
	__raw_writew(0x00FF, PORT_PKCR);	/* 00 00 00 00 11 11 11 11 */

	/* L7 TRST;	   L6 TMS;	     L5 TDO;		  L4 TDI;
	 * L3 TCK;	   L2 (x);	     L1 (x);		  L0 (x);
	 */
	__raw_writew(0x0000, PORT_PLCR);	/* 00 00 00 00 00 00 00 00 */

	/* M7 GPO(CURRENT_SINK);    M6 GPO(PWR_SWITCH);     M5 GPO(LAN_SPEED);
	 * M4 GPO(LAN_RESET);       M3 GPO(BUZZER);	    M2 GPO(LCD_BL);
	 * M1 CS5B(CAN3_CS);	    M0 GPI+(nc);
	 */
	__raw_writew(0x5552, PORT_PMCR);	   /* 01 01 01 01 01 01 00 10 */

	/* CURRENT_SINK=off,	PWR_SWITCH=off, LAN_SPEED=100MBit,
	 * LAN_RESET=off,	BUZZER=off,	LCD_BL=off
	 */
#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2
	__raw_writeb(0x30, PORT_PMDR);
#elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3
	__raw_writeb(0xF0, PORT_PMDR);
#else
#error Unknown revision of PLATFORM_MP_R2
#endif

	/* P7 (x);	       P6 (x);		  P5 (x);
	 * P4 GPO(nu);	       P3 IRQ3(LAN_IRQ);  P2 IRQ2(CAN3_IRQ);
	 * P1 IRQ1(CAN2_IRQ);  P0 IRQ0(CAN1_IRQ)
	 */
	__raw_writew(0x0100, PORT_PPCR);	/* 00 00 00 01 00 00 00 00 */
	__raw_writeb(0x10, PORT_PPDR);

	/* R7 A25;	     R6 A24;	     R5 A23;		  R4 A22;
	 * R3 A21;	     R2 A20;	     R1 A19;		  R0 A0;
	 */
	gpio_request(GPIO_FN_A25, NULL);
	gpio_request(GPIO_FN_A24, NULL);
	gpio_request(GPIO_FN_A23, NULL);
	gpio_request(GPIO_FN_A22, NULL);
	gpio_request(GPIO_FN_A21, NULL);
	gpio_request(GPIO_FN_A20, NULL);
	gpio_request(GPIO_FN_A19, NULL);
	gpio_request(GPIO_FN_A0, NULL);

	/* S7 (x);		S6 (x);        S5 (x);	     S4 GPO(EEPROM_CS2);
	 * S3 GPO(EEPROM_CS1);  S2 SIOF0_TXD;  S1 SIOF0_RXD; S0 SIOF0_SCK;
	 */
	__raw_writew(0x0140, PORT_PSCR);	/* 00 00 00 01 01 00 00 00 */

	/* T7 (x);	   T6 (x);	  T5 (x);	  T4 COM1_CTS;
	 * T3 COM1_RTS;	   T2 COM1_TXD;	  T1 COM1_RXD;	  T0 GPO(WDOG)
	 */
	__raw_writew(0x0001, PORT_PTCR);	/* 00 00 00 00 00 00 00 01 */

	/* U7 (x);	     U6 (x);	   U5 (x);	  U4 GPI+(/AC_FAULT);
	 * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD;  U0 TOUCH_SCK;
	 */
	__raw_writew(0x0240, PORT_PUCR);	/* 00 00 00 10 01 00 00 00 */

	/* V7 (x);	  V6 (x);	V5 (x);		  V4 GPO(MID2);
	 * V3 GPO(MID1);  V2 CARD_TxD;	V1 CARD_RxD;	  V0 GPI+(/BAT_FAULT);
	 */
	__raw_writew(0x0142, PORT_PVCR);	/* 00 00 00 01 01 00 00 10 */
}

static void __init mpr2_setup(char **cmdline_p)
{
	/* set Pin Select Register A:
	 * /PCC_CD1, /PCC_CD2,  PCC_BVD1, PCC_BVD2,
	 * /IOIS16,  IRQ4,	IRQ5,	  USB1d_SUSPEND
	 */
	__raw_writew(0xAABC, PORT_PSELA);
	/* set Pin Select Register B:
	 * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC,
	 * LCD_VEPWC,  IIC_SDA,    IIC_SCL, Reserved
	 */
	__raw_writew(0x3C00, PORT_PSELB);
	/* set Pin Select Register C:
	 * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved
	 */
	__raw_writew(0x0000, PORT_PSELC);
	/* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK,
	 * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved
	 */
	__raw_writew(0x0000, PORT_PSELD);
	/* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */
	__raw_writew(0x0101, PORT_UTRCTL);
	/* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */
	__raw_writew(0xA5C0, PORT_UCLKCR_W);

	setup_chip_select();

	setup_port_multiplexing();

	reset_ethernet();

	printk(KERN_INFO "Magic Panel Release 2 A.%i\n",
				CONFIG_SH_MAGIC_PANEL_R2_VERSION);

	if (ethernet_reset_finished() == 0)
		printk(KERN_WARNING "Ethernet not ready\n");
}

static struct resource smsc911x_resources[] = {
	[0] = {
		.start		= 0xa8000000,
		.end		= 0xabffffff,
		.flags		= IORESOURCE_MEM,
	},
	[1] = {
		.start		= 35,
		.end		= 35,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct smsc911x_platform_config smsc911x_config = {
	.phy_interface	= PHY_INTERFACE_MODE_MII,
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	.flags		= SMSC911X_USE_32BIT,
};

static struct platform_device smsc911x_device = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smsc911x_resources),
	.resource	= smsc911x_resources,
	.dev = {
		.platform_data = &smsc911x_config,
	},
};

static struct resource heartbeat_resources[] = {
	[0] = {
		.start	= PA_LED,
		.end	= PA_LED,
		.flags	= IORESOURCE_MEM,
	},
};

static struct heartbeat_data heartbeat_data = {
	.flags		= HEARTBEAT_INVERTED,
};

static struct platform_device heartbeat_device = {
	.name		= "heartbeat",
	.id		= -1,
	.dev	= {
		.platform_data	= &heartbeat_data,
	},
	.num_resources	= ARRAY_SIZE(heartbeat_resources),
	.resource	= heartbeat_resources,
};

static struct mtd_partition *parsed_partitions;

static struct mtd_partition mpr2_partitions[] = {
	/* Reserved for bootloader, read-only */
	{
		.name = "Bootloader",
		.offset = 0x00000000UL,
		.size = MPR2_MTD_BOOTLOADER_SIZE,
		.mask_flags = MTD_WRITEABLE,
	},
	/* Reserved for kernel image */
	{
		.name = "Kernel",
		.offset = MTDPART_OFS_NXTBLK,
		.size = MPR2_MTD_KERNEL_SIZE,
	},
	/* Rest is used for Flash FS */
	{
		.name = "Flash_FS",
		.offset = MTDPART_OFS_NXTBLK,
		.size = MTDPART_SIZ_FULL,
	}
};

static struct physmap_flash_data flash_data = {
	.width		= 2,
};

static struct resource flash_resource = {
	.start		= 0x00000000,
	.end		= 0x2000000UL,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device flash_device = {
	.name		= "physmap-flash",
	.id		= -1,
	.resource	= &flash_resource,
	.num_resources	= 1,
	.dev		= {
		.platform_data = &flash_data,
	},
};

static struct mtd_info *flash_mtd;

static struct map_info mpr2_flash_map = {
	.name = "Magic Panel R2 Flash",
	.size = 0x2000000UL,
	.bankwidth = 2,
};

static void __init set_mtd_partitions(void)
{
	int nr_parts = 0;

	simple_map_init(&mpr2_flash_map);
	flash_mtd = do_map_probe("cfi_probe", &mpr2_flash_map);
	nr_parts = parse_mtd_partitions(flash_mtd, probes,
					&parsed_partitions, 0);
	/* If there is no partition table, used the hard coded table */
	if (nr_parts <= 0) {
		flash_data.parts = mpr2_partitions;
		flash_data.nr_parts = ARRAY_SIZE(mpr2_partitions);
	} else {
		flash_data.nr_parts = nr_parts;
		flash_data.parts = parsed_partitions;
	}
}

/*
 * Add all resources to the platform_device
 */

static struct platform_device *mpr2_devices[] __initdata = {
	&heartbeat_device,
	&smsc911x_device,
	&flash_device,
};


static int __init mpr2_devices_setup(void)
{
	set_mtd_partitions();
	return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices));
}
device_initcall(mpr2_devices_setup);

/*
 * Initialize IRQ setting
 */
static void __init init_mpr2_IRQ(void)
{
	plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */

	irq_set_irq_type(32, IRQ_TYPE_LEVEL_LOW);    /* IRQ0 CAN1 */
	irq_set_irq_type(33, IRQ_TYPE_LEVEL_LOW);    /* IRQ1 CAN2 */
	irq_set_irq_type(34, IRQ_TYPE_LEVEL_LOW);    /* IRQ2 CAN3 */
	irq_set_irq_type(35, IRQ_TYPE_LEVEL_LOW);    /* IRQ3 SMSC9115 */
	irq_set_irq_type(36, IRQ_TYPE_EDGE_RISING);  /* IRQ4 touchscreen */
	irq_set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */

	intc_set_priority(32, 13);		/* IRQ0 CAN1 */
	intc_set_priority(33, 13);		/* IRQ0 CAN2 */
	intc_set_priority(34, 13);		/* IRQ0 CAN3 */
	intc_set_priority(35, 6);		/* IRQ3 SMSC9115 */
}

/*
 * The Machine Vector
 */

static struct sh_machine_vector mv_mpr2 __initmv = {
	.mv_name		= "mpr2",
	.mv_setup		= mpr2_setup,
	.mv_init_irq		= init_mpr2_IRQ,
};
Commit	Line	Data
ded5431f MB	1	/*
	2	* linux/arch/sh/boards/magicpanel/setup.c
	3	*
	4	* Copyright (C) 2007 Markus Brunner, Mark Jonas
	5	*
	6	* Magic Panel Release 2 board setup
	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*/
	12	#include <linux/init.h>
	13	#include <linux/irq.h>
	14	#include <linux/platform_device.h>
ded5431f	15	#include <linux/delay.h>
843284d0	16	#include <linux/gpio.h>
02da916a	17	#include <linux/smsc911x.h>
e87ab0c4 MB	18	#include <linux/mtd/mtd.h>
	19	#include <linux/mtd/partitions.h>
	20	#include <linux/mtd/physmap.h>
	21	#include <linux/mtd/map.h>
7639a454	22	#include <mach/magicpanelr2.h>
ded5431f	23	#include <asm/heartbeat.h>
f7275650	24	#include <cpu/sh7720.h>
ded5431f	25
9d56dd3b	26	#define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL)
ded5431f	27
e87ab0c4 MB	28	/* Prefer cmdline over RedBoot */
	29	static const char *probes[] = { "cmdlinepart", "RedBoot", NULL };
	30
ded5431f MB	31	/* Wait until reset finished. Timeout is 100ms. */
	32	static int __init ethernet_reset_finished(void)
	33	{
	34	int i;
	35
	36	if (LAN9115_READY)
	37	return 1;
	38
	39	for (i = 0; i < 10; ++i) {
	40	mdelay(10);
	41	if (LAN9115_READY)
	42	return 1;
	43	}
	44
	45	return 0;
	46	}
	47
	48	static void __init reset_ethernet(void)
	49	{
	50	/* PMDR: LAN_RESET=on */
	51	CLRBITS_OUTB(0x10, PORT_PMDR);
	52
	53	udelay(200);
	54
	55	/* PMDR: LAN_RESET=off */
	56	SETBITS_OUTB(0x10, PORT_PMDR);
	57	}
	58
	59	static void __init setup_chip_select(void)
	60	{
	61	/* CS2: LAN (0x08000000 - 0x0bffffff) */
	62	/* no idle cycles, normal space, 8 bit data bus */
9d56dd3b	63	__raw_writel(0x36db0400, CS2BCR);
ded5431f	64	/* (SW:1.5 WR:3 HW:1.5), ext. wait */
9d56dd3b	65	__raw_writel(0x000003c0, CS2WCR);
ded5431f MB	66
	67	/* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */
	68	/* no idle cycles, normal space, 8 bit data bus */
9d56dd3b	69	__raw_writel(0x00000200, CS4BCR);
ded5431f	70	/* (SW:1.5 WR:3 HW:1.5), ext. wait */
9d56dd3b	71	__raw_writel(0x00100981, CS4WCR);
ded5431f MB	72
	73	/* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */
	74	/* no idle cycles, normal space, 8 bit data bus */
9d56dd3b	75	__raw_writel(0x00000200, CS5ABCR);
ded5431f	76	/* (SW:1.5 WR:3 HW:1.5), ext. wait */
9d56dd3b	77	__raw_writel(0x00100981, CS5AWCR);
ded5431f MB	78
	79	/* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */
	80	/* no idle cycles, normal space, 8 bit data bus */
9d56dd3b	81	__raw_writel(0x00000200, CS5BBCR);
ded5431f	82	/* (SW:1.5 WR:3 HW:1.5), ext. wait */
9d56dd3b	83	__raw_writel(0x00100981, CS5BWCR);
ded5431f MB	84
	85	/* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */
	86	/* no idle cycles, normal space, 8 bit data bus */
9d56dd3b	87	__raw_writel(0x00000200, CS6ABCR);
ded5431f	88	/* (SW:1.5 WR:3 HW:1.5), no ext. wait */
9d56dd3b	89	__raw_writel(0x001009C1, CS6AWCR);
ded5431f MB	90	}
	91
	92	static void __init setup_port_multiplexing(void)
	93	{
	94	/* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
	95	* A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1);
	96	*/
9d56dd3b	97	__raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */
ded5431f MB	98
	99	/* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
	100	* B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0);
	101	*/
9d56dd3b	102	__raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */
ded5431f MB	103
	104	/* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
	105	* C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0;
	106	*/
9d56dd3b	107	__raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */
ded5431f MB	108
	109	/* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
	110	* D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0);
	111	*/
9d56dd3b	112	__raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */
ded5431f MB	113
	114	/* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
	115	* E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM;
	116	*/
9d56dd3b	117	__raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */
ded5431f MB	118
	119	/* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
	120	* F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc);
	121	*/
9d56dd3b	122	__raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */
ded5431f MB	123
	124	/* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2);
	125	* G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9);
	126	*/
9d56dd3b	127	__raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */
ded5431f MB	128
	129	/* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
	130	* H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR;
	131	*/
9d56dd3b	132	__raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */
ded5431f MB	133
	134	/* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
	135	* J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC;
	136	*/
9d56dd3b	137	__raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */
ded5431f MB	138
	139	/* K7 (x); K6 (x); K5 (x); K4 (x);
	140	* K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY)
	141	*/
9d56dd3b	142	__raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */
ded5431f MB	143
	144	/* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
	145	* L3 TCK; L2 (x); L1 (x); L0 (x);
	146	*/
9d56dd3b	147	__raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */
ded5431f MB	148
	149	/* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED);
	150	* M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL);
	151	* M1 CS5B(CAN3_CS); M0 GPI+(nc);
	152	*/
9d56dd3b	153	__raw_writew(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */
ded5431f MB	154
	155	/* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit,
	156	* LAN_RESET=off, BUZZER=off, LCD_BL=off
	157	*/
	158	#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2
9d56dd3b	159	__raw_writeb(0x30, PORT_PMDR);
ded5431f	160	#elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3
9d56dd3b	161	__raw_writeb(0xF0, PORT_PMDR);
ded5431f MB	162	#else
	163	#error Unknown revision of PLATFORM_MP_R2
	164	#endif
	165
	166	/* P7 (x); P6 (x); P5 (x);
	167	* P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);
	168	* P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ)
	169	*/
9d56dd3b PM	170	__raw_writew(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */
9d56dd3b PM	171	__raw_writeb(0x10, PORT_PPDR);
ded5431f MB	172
	173	/* R7 A25; R6 A24; R5 A23; R4 A22;
	174	* R3 A21; R2 A20; R1 A19; R0 A0;
	175	*/
843284d0 MD	176	gpio_request(GPIO_FN_A25, NULL);
	177	gpio_request(GPIO_FN_A24, NULL);
	178	gpio_request(GPIO_FN_A23, NULL);
	179	gpio_request(GPIO_FN_A22, NULL);
	180	gpio_request(GPIO_FN_A21, NULL);
	181	gpio_request(GPIO_FN_A20, NULL);
	182	gpio_request(GPIO_FN_A19, NULL);
	183	gpio_request(GPIO_FN_A0, NULL);
ded5431f MB	184
	185	/* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
	186	* S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK;
	187	*/
9d56dd3b	188	__raw_writew(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */
ded5431f MB	189
	190	/* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
	191	* T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG)
	192	*/
9d56dd3b	193	__raw_writew(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */
ded5431f MB	194
	195	/* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
	196	* U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK;
	197	*/
9d56dd3b	198	__raw_writew(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */
ded5431f MB	199
	200	/* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
	201	* V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT);
	202	*/
9d56dd3b	203	__raw_writew(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */
ded5431f MB	204	}
	205
	206	static void __init mpr2_setup(char **cmdline_p)
	207	{
ded5431f MB	208	/* set Pin Select Register A:
	209	* /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2,
	210	* /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND
	211	*/
9d56dd3b	212	__raw_writew(0xAABC, PORT_PSELA);
ded5431f MB	213	/* set Pin Select Register B:
	214	* /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC,
	215	* LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved
	216	*/
9d56dd3b	217	__raw_writew(0x3C00, PORT_PSELB);
ded5431f MB	218	/* set Pin Select Register C:
	219	* SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved
	220	*/
9d56dd3b	221	__raw_writew(0x0000, PORT_PSELC);
ded5431f MB	222	/* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK,
	223	* Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved
	224	*/
9d56dd3b	225	__raw_writew(0x0000, PORT_PSELD);
ded5431f	226	/* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */
9d56dd3b	227	__raw_writew(0x0101, PORT_UTRCTL);
ded5431f	228	/* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */
9d56dd3b	229	__raw_writew(0xA5C0, PORT_UCLKCR_W);
ded5431f MB	230
	231	setup_chip_select();
	232
	233	setup_port_multiplexing();
	234
	235	reset_ethernet();
	236
	237	printk(KERN_INFO "Magic Panel Release 2 A.%i\n",
	238	CONFIG_SH_MAGIC_PANEL_R2_VERSION);
	239
	240	if (ethernet_reset_finished() == 0)
	241	printk(KERN_WARNING "Ethernet not ready\n");
	242	}
	243
02da916a	244	static struct resource smsc911x_resources[] = {
ded5431f MB	245	[0] = {
	246	.start = 0xa8000000,
	247	.end = 0xabffffff,
	248	.flags = IORESOURCE_MEM,
	249	},
	250	[1] = {
	251	.start = 35,
	252	.end = 35,
	253	.flags = IORESOURCE_IRQ,
	254	},
	255	};
	256
02da916a SG	257	static struct smsc911x_platform_config smsc911x_config = {
	258	.phy_interface = PHY_INTERFACE_MODE_MII,
	259	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	260	.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	261	.flags = SMSC911X_USE_32BIT,
	262	};
	263
	264	static struct platform_device smsc911x_device = {
	265	.name = "smsc911x",
ded5431f	266	.id = -1,
02da916a SG	267	.num_resources = ARRAY_SIZE(smsc911x_resources),
	268	.resource = smsc911x_resources,
	269	.dev = {
	270	.platform_data = &smsc911x_config,
	271	},
ded5431f MB	272	};
	273
	274	static struct resource heartbeat_resources[] = {
	275	[0] = {
	276	.start = PA_LED,
	277	.end = PA_LED,
	278	.flags = IORESOURCE_MEM,
	279	},
	280	};
	281
	282	static struct heartbeat_data heartbeat_data = {
	283	.flags = HEARTBEAT_INVERTED,
	284	};
	285
	286	static struct platform_device heartbeat_device = {
	287	.name = "heartbeat",
	288	.id = -1,
	289	.dev = {
	290	.platform_data = &heartbeat_data,
	291	},
	292	.num_resources = ARRAY_SIZE(heartbeat_resources),
	293	.resource = heartbeat_resources,
	294	};
	295
e87ab0c4 MB	296	static struct mtd_partition *parsed_partitions;
	297
	298	static struct mtd_partition mpr2_partitions[] = {
	299	/* Reserved for bootloader, read-only */
	300	{
	301	.name = "Bootloader",
	302	.offset = 0x00000000UL,
	303	.size = MPR2_MTD_BOOTLOADER_SIZE,
	304	.mask_flags = MTD_WRITEABLE,
	305	},
	306	/* Reserved for kernel image */
	307	{
	308	.name = "Kernel",
	309	.offset = MTDPART_OFS_NXTBLK,
	310	.size = MPR2_MTD_KERNEL_SIZE,
	311	},
	312	/* Rest is used for Flash FS */
	313	{
	314	.name = "Flash_FS",
	315	.offset = MTDPART_OFS_NXTBLK,
	316	.size = MTDPART_SIZ_FULL,
	317	}
	318	};
	319
	320	static struct physmap_flash_data flash_data = {
	321	.width = 2,
	322	};
	323
	324	static struct resource flash_resource = {
	325	.start = 0x00000000,
	326	.end = 0x2000000UL,
	327	.flags = IORESOURCE_MEM,
	328	};
	329
	330	static struct platform_device flash_device = {
	331	.name = "physmap-flash",
	332	.id = -1,
	333	.resource = &flash_resource,
	334	.num_resources = 1,
	335	.dev = {
	336	.platform_data = &flash_data,
	337	},
	338	};
	339
	340	static struct mtd_info *flash_mtd;
	341
	342	static struct map_info mpr2_flash_map = {
	343	.name = "Magic Panel R2 Flash",
	344	.size = 0x2000000UL,
	345	.bankwidth = 2,
	346	};
	347
	348	static void __init set_mtd_partitions(void)
	349	{
	350	int nr_parts = 0;
	351
	352	simple_map_init(&mpr2_flash_map);
	353	flash_mtd = do_map_probe("cfi_probe", &mpr2_flash_map);
	354	nr_parts = parse_mtd_partitions(flash_mtd, probes,
	355	&parsed_partitions, 0);
	356	/* If there is no partition table, used the hard coded table */
	357	if (nr_parts <= 0) {
	358	flash_data.parts = mpr2_partitions;
	359	flash_data.nr_parts = ARRAY_SIZE(mpr2_partitions);
360	} else {
361	flash_data.nr_parts = nr_parts;
362	flash_data.parts = parsed_partitions;
363	}
364	}
365
366	/*
367	* Add all resources to the platform_device
368	*/
369
ded5431f MB	370	static struct platform_device *mpr2_devices[] __initdata = {
ded5431f MB	371	&heartbeat_device,
02da916a	372	&smsc911x_device,
e87ab0c4	373	&flash_device,
ded5431f MB	374	};
ded5431f MB	375
e87ab0c4	376
ded5431f MB	377	static int __init mpr2_devices_setup(void)
ded5431f MB	378	{
e87ab0c4	379	set_mtd_partitions();
ded5431f MB	380	return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices));
	381	}
	382	device_initcall(mpr2_devices_setup);
	383
	384	/*
	385	* Initialize IRQ setting
	386	*/
	387	static void __init init_mpr2_IRQ(void)
	388	{
	389	plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */
	390
fcb8918f TG	391	irq_set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */
	392	irq_set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */
	393	irq_set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */
	394	irq_set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */
	395	irq_set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */
	396	irq_set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */
ded5431f MB	397
	398	intc_set_priority(32, 13); /* IRQ0 CAN1 */
	399	intc_set_priority(33, 13); /* IRQ0 CAN2 */
	400	intc_set_priority(34, 13); /* IRQ0 CAN3 */
	401	intc_set_priority(35, 6); /* IRQ3 SMSC9115 */
	402	}
	403
	404	/*
	405	* The Machine Vector
	406	*/
	407
	408	static struct sh_machine_vector mv_mpr2 __initmv = {
	409	.mv_name = "mpr2",
	410	.mv_setup = mpr2_setup,
e87ab0c4	411	.mv_init_irq = init_mpr2_IRQ,
ded5431f	412	};