[linux.git] / drivers / gpio / gpio-stmpe.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License, version 2
 * Author: Rabin Vincent <[email protected]> for ST-Ericsson
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/mfd/stmpe.h>
#include <linux/seq_file.h>
#include <linux/bitops.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_RE, REG_FE, REG_IE };

enum { LSB, CSB, MSB };

#define CACHE_NR_REGS	3
/* No variant has more than 24 GPIOs */
#define CACHE_NR_BANKS	(24 / 8)

struct stmpe_gpio {
	struct gpio_chip chip;
	struct stmpe *stmpe;
	struct device *dev;
	struct mutex irq_lock;
	u32 norequest_mask;
	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
	u8 mask = BIT(offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	return !!(ret & mask);
}

static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	u8 reg = stmpe->regs[which + (offset / 8)];
	u8 mask = BIT(offset % 8);

	/*
	 * Some variants have single register for gpio set/clear functionality.
	 * For them we need to write 0 to clear and 1 to set.
	 */
	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
		stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	else
		stmpe_reg_write(stmpe, reg, mask);
}

static int stmpe_gpio_get_direction(struct gpio_chip *chip,
				    unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = BIT(offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	return !(ret & mask);
}

static int stmpe_gpio_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
	u8 mask = BIT(offset % 8);

	stmpe_gpio_set(chip, offset, val);

	return stmpe_set_bits(stmpe, reg, mask, mask);
}

static int stmpe_gpio_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
	u8 mask = BIT(offset % 8);

	return stmpe_set_bits(stmpe, reg, mask, 0);
}

static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;

	if (stmpe_gpio->norequest_mask & BIT(offset))
		return -EINVAL;

	return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
}

static const struct gpio_chip template_chip = {
	.label			= "stmpe",
	.owner			= THIS_MODULE,
	.get_direction		= stmpe_gpio_get_direction,
	.direction_input	= stmpe_gpio_direction_input,
	.get			= stmpe_gpio_get,
	.direction_output	= stmpe_gpio_direction_output,
	.set			= stmpe_gpio_set,
	.request		= stmpe_gpio_request,
	.can_sleep		= true,
};

static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
		return -EINVAL;

	/* STMPE801 and STMPE 1600 don't have RE and FE registers */
	if (stmpe_gpio->stmpe->partnum == STMPE801 ||
	    stmpe_gpio->stmpe->partnum == STMPE1600)
		return 0;

	if (type & IRQ_TYPE_EDGE_RISING)
		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;

	if (type & IRQ_TYPE_EDGE_FALLING)
		stmpe_gpio->regs[REG_FE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;

	return 0;
}

static void stmpe_gpio_irq_lock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);

	mutex_lock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
		[REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
		[REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
		[REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
		[REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
		[REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
		[REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
		[REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
		[REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
		[REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
	};
	int i, j;

	/*
	 * STMPE1600: to be able to get IRQ from pins,
	 * a read must be done on GPMR register, or a write in
	 * GPSR or GPCR registers
	 */
	if (stmpe->partnum == STMPE1600) {
		stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
		stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
	}

	for (i = 0; i < CACHE_NR_REGS; i++) {
		/* STMPE801 and STMPE1600 don't have RE and FE registers */
		if ((stmpe->partnum == STMPE801 ||
		     stmpe->partnum == STMPE1600) &&
		     (i != REG_IE))
			continue;

		for (j = 0; j < num_banks; j++) {
			u8 old = stmpe_gpio->oldregs[i][j];
			u8 new = stmpe_gpio->regs[i][j];

			if (new == old)
				continue;

			stmpe_gpio->oldregs[i][j] = new;
			stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
		}
	}

	mutex_unlock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
}

static void stmpe_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] |= mask;
}

static void stmpe_dbg_show_one(struct seq_file *s,
			       struct gpio_chip *gc,
			       unsigned offset, unsigned gpio)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	const char *label = gpiochip_is_requested(gc, offset);
	bool val = !!stmpe_gpio_get(gc, offset);
	u8 bank = offset / 8;
	u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
	u8 mask = BIT(offset % 8);
	int ret;
	u8 dir;

	ret = stmpe_reg_read(stmpe, dir_reg);
	if (ret < 0)
		return;
	dir = !!(ret & mask);

	if (dir) {
		seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
			   gpio, label ?: "(none)",
			   val ? "hi" : "lo");
	} else {
		u8 edge_det_reg;
		u8 rise_reg;
		u8 fall_reg;
		u8 irqen_reg;

		static const char * const edge_det_values[] = {
			"edge-inactive",
			"edge-asserted",
			"not-supported"
		};
		static const char * const rise_values[] = {
			"no-rising-edge-detection",
			"rising-edge-detection",
			"not-supported"
		};
		static const char * const fall_values[] = {
			"no-falling-edge-detection",
			"falling-edge-detection",
			"not-supported"
		};
		#define NOT_SUPPORTED_IDX 2
		u8 edge_det = NOT_SUPPORTED_IDX;
		u8 rise = NOT_SUPPORTED_IDX;
		u8 fall = NOT_SUPPORTED_IDX;
		bool irqen;

		switch (stmpe->partnum) {
		case STMPE610:
		case STMPE811:
		case STMPE1601:
		case STMPE2401:
		case STMPE2403:
			edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
			ret = stmpe_reg_read(stmpe, edge_det_reg);
			if (ret < 0)
				return;
			edge_det = !!(ret & mask);
			/* fall through */
		case STMPE1801:
			rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
			fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];

			ret = stmpe_reg_read(stmpe, rise_reg);
			if (ret < 0)
				return;
			rise = !!(ret & mask);
			ret = stmpe_reg_read(stmpe, fall_reg);
			if (ret < 0)
				return;
			fall = !!(ret & mask);
			/* fall through */
		case STMPE801:
		case STMPE1600:
			irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
			break;

		default:
			return;
		}

		ret = stmpe_reg_read(stmpe, irqen_reg);
		if (ret < 0)
			return;
		irqen = !!(ret & mask);

		seq_printf(s, " gpio-%-3d (%-20.20s) in  %s %13s %13s %25s %25s",
			   gpio, label ?: "(none)",
			   val ? "hi" : "lo",
			   edge_det_values[edge_det],
			   irqen ? "IRQ-enabled" : "IRQ-disabled",
			   rise_values[rise],
			   fall_values[fall]);
	}
}

static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
{
	unsigned i;
	unsigned gpio = gc->base;

	for (i = 0; i < gc->ngpio; i++, gpio++) {
		stmpe_dbg_show_one(s, gc, i, gpio);
		seq_putc(s, '\n');
	}
}

static struct irq_chip stmpe_gpio_irq_chip = {
	.name			= "stmpe-gpio",
	.irq_bus_lock		= stmpe_gpio_irq_lock,
	.irq_bus_sync_unlock	= stmpe_gpio_irq_sync_unlock,
	.irq_mask		= stmpe_gpio_irq_mask,
	.irq_unmask		= stmpe_gpio_irq_unmask,
	.irq_set_type		= stmpe_gpio_irq_set_type,
};

static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
{
	struct stmpe_gpio *stmpe_gpio = dev;
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 statmsbreg;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	u8 status[num_banks];
	int ret;
	int i;

	/*
	 * the stmpe_block_read() call below, imposes to set statmsbreg
	 * with the register located at the lowest address. As STMPE1600
	 * variant is the only one which respect registers address's order
	 * (LSB regs located at lowest address than MSB ones) whereas all
	 * the others have a registers layout with MSB located before the
	 * LSB regs.
	 */
	if (stmpe->partnum == STMPE1600)
		statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
	else
		statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];

	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < num_banks; i++) {
		int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
			   num_banks - i - 1;
		unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
		unsigned int stat = status[i];

		stat &= enabled;
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = bank * 8 + bit;
			int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
							 line);

			handle_nested_irq(child_irq);
			stat &= ~BIT(bit);
		}

		/*
		 * interrupt status register write has no effect on
		 * 801/1801/1600, bits are cleared when read.
		 * Edge detect register is not present on 801/1600/1801
		 */
		if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
		    stmpe->partnum != STMPE1801) {
			stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
			stmpe_reg_write(stmpe,
					stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
					status[i]);
		}
	}

	return IRQ_HANDLED;
}

static int stmpe_gpio_probe(struct platform_device *pdev)
{
	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
	struct device_node *np = pdev->dev.of_node;
	struct stmpe_gpio *stmpe_gpio;
	int ret, irq;

	stmpe_gpio = kzalloc(sizeof(*stmpe_gpio), GFP_KERNEL);
	if (!stmpe_gpio)
		return -ENOMEM;

	mutex_init(&stmpe_gpio->irq_lock);

	stmpe_gpio->dev = &pdev->dev;
	stmpe_gpio->stmpe = stmpe;
	stmpe_gpio->chip = template_chip;
	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	stmpe_gpio->chip.parent = &pdev->dev;
	stmpe_gpio->chip.of_node = np;
	stmpe_gpio->chip.base = -1;

	if (IS_ENABLED(CONFIG_DEBUG_FS))
                stmpe_gpio->chip.dbg_show = stmpe_dbg_show;

	of_property_read_u32(np, "st,norequest-mask",
			&stmpe_gpio->norequest_mask);
	if (stmpe_gpio->norequest_mask)
		stmpe_gpio->chip.irq.need_valid_mask = true;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		dev_info(&pdev->dev,
			"device configured in no-irq mode: "
			"irqs are not available\n");

	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	if (ret)
		goto out_free;

	ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
	if (ret) {
		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
		goto out_disable;
	}

	if (irq > 0) {
		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
				stmpe_gpio_irq, IRQF_ONESHOT,
				"stmpe-gpio", stmpe_gpio);
		if (ret) {
			dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
			goto out_disable;
		}
		if (stmpe_gpio->norequest_mask) {
			int i;

			/* Forbid unused lines to be mapped as IRQs */
			for (i = 0; i < sizeof(u32); i++)
				if (stmpe_gpio->norequest_mask & BIT(i))
					clear_bit(i, stmpe_gpio->chip.irq.valid_mask);
		}
		ret =  gpiochip_irqchip_add_nested(&stmpe_gpio->chip,
						   &stmpe_gpio_irq_chip,
						   0,
						   handle_simple_irq,
						   IRQ_TYPE_NONE);
		if (ret) {
			dev_err(&pdev->dev,
				"could not connect irqchip to gpiochip\n");
			goto out_disable;
		}

		gpiochip_set_nested_irqchip(&stmpe_gpio->chip,
					    &stmpe_gpio_irq_chip,
					    irq);
	}

	platform_set_drvdata(pdev, stmpe_gpio);

	return 0;

out_disable:
	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
	gpiochip_remove(&stmpe_gpio->chip);
out_free:
	kfree(stmpe_gpio);
	return ret;
}

static struct platform_driver stmpe_gpio_driver = {
	.driver = {
		.suppress_bind_attrs	= true,
		.name			= "stmpe-gpio",
	},
	.probe		= stmpe_gpio_probe,
};

static int __init stmpe_gpio_init(void)
{
	return platform_driver_register(&stmpe_gpio_driver);
}
subsys_initcall(stmpe_gpio_init);
Commit	Line	Data
03f822f5 RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License, version 2
	5	* Author: Rabin Vincent <[email protected]> for ST-Ericsson
	6	*/
	7
03f822f5 RV	8	#include <linux/init.h>
	9	#include <linux/platform_device.h>
	10	#include <linux/slab.h>
	11	#include <linux/gpio.h>
03f822f5	12	#include <linux/interrupt.h>
86605cfe	13	#include <linux/of.h>
03f822f5	14	#include <linux/mfd/stmpe.h>
27ec8a9c	15	#include <linux/seq_file.h>
96b2cca6	16	#include <linux/bitops.h>
03f822f5 RV	17
	18	/*
	19	* These registers are modified under the irq bus lock and cached to avoid
	20	* unnecessary writes in bus_sync_unlock.
	21	*/
	22	enum { REG_RE, REG_FE, REG_IE };
	23
43db289d PC	24	enum { LSB, CSB, MSB };
43db289d PC	25
03f822f5	26	#define CACHE_NR_REGS 3
9e9dc7d9 LW	27	/* No variant has more than 24 GPIOs */
9e9dc7d9 LW	28	#define CACHE_NR_BANKS (24 / 8)
03f822f5 RV	29
	30	struct stmpe_gpio {
	31	struct gpio_chip chip;
	32	struct stmpe *stmpe;
	33	struct device *dev;
	34	struct mutex irq_lock;
1dfb4a0d	35	u32 norequest_mask;
03f822f5 RV	36	/* Caches of interrupt control registers for bus_lock */
	37	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	38	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	39	};
	40
03f822f5 RV	41	static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
03f822f5 RV	42	{
b03c04a0	43	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5	44	struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d	45	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
4e2678b5	46	u8 mask = BIT(offset % 8);
03f822f5 RV	47	int ret;
	48
	49	ret = stmpe_reg_read(stmpe, reg);
	50	if (ret < 0)
	51	return ret;
	52
7535b8be	53	return !!(ret & mask);
03f822f5 RV	54	}
	55
	56	static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	57	{
b03c04a0	58	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5 RV	59	struct stmpe *stmpe = stmpe_gpio->stmpe;
03f822f5 RV	60	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
43db289d	61	u8 reg = stmpe->regs[which + (offset / 8)];
4e2678b5	62	u8 mask = BIT(offset % 8);
03f822f5	63
cccdceb9 VK	64	/*
	65	* Some variants have single register for gpio set/clear functionality.
	66	* For them we need to write 0 to clear and 1 to set.
	67	*/
	68	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
	69	stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	70	else
	71	stmpe_reg_write(stmpe, reg, mask);
03f822f5 RV	72	}
03f822f5 RV	73
8e293fb0 LW	74	static int stmpe_gpio_get_direction(struct gpio_chip *chip,
	75	unsigned offset)
	76	{
	77	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	78	struct stmpe *stmpe = stmpe_gpio->stmpe;
	79	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
4e2678b5	80	u8 mask = BIT(offset % 8);
8e293fb0 LW	81	int ret;
	82
	83	ret = stmpe_reg_read(stmpe, reg);
	84	if (ret < 0)
	85	return ret;
	86
	87	return !(ret & mask);
	88	}
	89
03f822f5 RV	90	static int stmpe_gpio_direction_output(struct gpio_chip *chip,
	91	unsigned offset, int val)
	92	{
b03c04a0	93	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5	94	struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d	95	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
4e2678b5	96	u8 mask = BIT(offset % 8);
03f822f5 RV	97
	98	stmpe_gpio_set(chip, offset, val);
	99
	100	return stmpe_set_bits(stmpe, reg, mask, mask);
	101	}
	102
	103	static int stmpe_gpio_direction_input(struct gpio_chip *chip,
	104	unsigned offset)
	105	{
b03c04a0	106	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5	107	struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d	108	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
4e2678b5	109	u8 mask = BIT(offset % 8);
03f822f5 RV	110
	111	return stmpe_set_bits(stmpe, reg, mask, 0);
	112	}
	113
03f822f5 RV	114	static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
03f822f5 RV	115	{
b03c04a0	116	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5 RV	117	struct stmpe *stmpe = stmpe_gpio->stmpe;
03f822f5 RV	118
4e2678b5	119	if (stmpe_gpio->norequest_mask & BIT(offset))
b8e9cf0b WS	120	return -EINVAL;
b8e9cf0b WS	121
4e2678b5	122	return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
03f822f5 RV	123	}
03f822f5 RV	124
e35b5ab0	125	static const struct gpio_chip template_chip = {
03f822f5 RV	126	.label = "stmpe",
03f822f5 RV	127	.owner = THIS_MODULE,
8e293fb0	128	.get_direction = stmpe_gpio_get_direction,
03f822f5 RV	129	.direction_input = stmpe_gpio_direction_input,
	130	.get = stmpe_gpio_get,
	131	.direction_output = stmpe_gpio_direction_output,
	132	.set = stmpe_gpio_set,
03f822f5	133	.request = stmpe_gpio_request,
9fb1f39e	134	.can_sleep = true,
03f822f5 RV	135	};
03f822f5 RV	136
2a866f39	137	static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
03f822f5	138	{
fe44e70d	139	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	140	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
fc13d5a5	141	int offset = d->hwirq;
03f822f5	142	int regoffset = offset / 8;
4e2678b5	143	int mask = BIT(offset % 8);
03f822f5	144
1fe3bd9e	145	if (type & IRQ_TYPE_LEVEL_LOW \|\| type & IRQ_TYPE_LEVEL_HIGH)
03f822f5 RV	146	return -EINVAL;
03f822f5 RV	147
c6a05a05 PC	148	/* STMPE801 and STMPE 1600 don't have RE and FE registers */
	149	if (stmpe_gpio->stmpe->partnum == STMPE801 \|\|
	150	stmpe_gpio->stmpe->partnum == STMPE1600)
cccdceb9 VK	151	return 0;
cccdceb9 VK	152
1fe3bd9e	153	if (type & IRQ_TYPE_EDGE_RISING)
03f822f5 RV	154	stmpe_gpio->regs[REG_RE][regoffset] \|= mask;
	155	else
	156	stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
	157
1fe3bd9e	158	if (type & IRQ_TYPE_EDGE_FALLING)
03f822f5 RV	159	stmpe_gpio->regs[REG_FE][regoffset] \|= mask;
	160	else
	161	stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
	162
	163	return 0;
	164	}
	165
2a866f39	166	static void stmpe_gpio_irq_lock(struct irq_data *d)
03f822f5	167	{
fe44e70d	168	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	169	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
03f822f5 RV	170
	171	mutex_lock(&stmpe_gpio->irq_lock);
	172	}
	173
2a866f39	174	static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
03f822f5	175	{
fe44e70d	176	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	177	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
03f822f5 RV	178	struct stmpe *stmpe = stmpe_gpio->stmpe;
03f822f5 RV	179	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
43db289d PC	180	static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
	181	[REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
	182	[REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
	183	[REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
	184	[REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
	185	[REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
	186	[REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
	187	[REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
	188	[REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
	189	[REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
03f822f5 RV	190	};
	191	int i, j;
	192
b888fb6f PC	193	/*
	194	* STMPE1600: to be able to get IRQ from pins,
	195	* a read must be done on GPMR register, or a write in
	196	* GPSR or GPCR registers
	197	*/
	198	if (stmpe->partnum == STMPE1600) {
	199	stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
	200	stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
	201	}
	202
03f822f5	203	for (i = 0; i < CACHE_NR_REGS; i++) {
c6a05a05 PC	204	/* STMPE801 and STMPE1600 don't have RE and FE registers */
	205	if ((stmpe->partnum == STMPE801 \|\|
	206	stmpe->partnum == STMPE1600) &&
	207	(i != REG_IE))
cccdceb9 VK	208	continue;
cccdceb9 VK	209
03f822f5 RV	210	for (j = 0; j < num_banks; j++) {
	211	u8 old = stmpe_gpio->oldregs[i][j];
	212	u8 new = stmpe_gpio->regs[i][j];
	213
	214	if (new == old)
	215	continue;
	216
	217	stmpe_gpio->oldregs[i][j] = new;
43db289d	218	stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
03f822f5 RV	219	}
	220	}
	221
	222	mutex_unlock(&stmpe_gpio->irq_lock);
	223	}
	224
2a866f39	225	static void stmpe_gpio_irq_mask(struct irq_data *d)
03f822f5	226	{
fe44e70d	227	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	228	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
fc13d5a5	229	int offset = d->hwirq;
03f822f5	230	int regoffset = offset / 8;
4e2678b5	231	int mask = BIT(offset % 8);
03f822f5 RV	232
	233	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
	234	}
	235
2a866f39	236	static void stmpe_gpio_irq_unmask(struct irq_data *d)
03f822f5	237	{
fe44e70d	238	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	239	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
fc13d5a5	240	int offset = d->hwirq;
03f822f5	241	int regoffset = offset / 8;
4e2678b5	242	int mask = BIT(offset % 8);
03f822f5 RV	243
	244	stmpe_gpio->regs[REG_IE][regoffset] \|= mask;
	245	}
	246
27ec8a9c LW	247	static void stmpe_dbg_show_one(struct seq_file *s,
	248	struct gpio_chip *gc,
	249	unsigned offset, unsigned gpio)
	250	{
b03c04a0	251	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
27ec8a9c LW	252	struct stmpe *stmpe = stmpe_gpio->stmpe;
27ec8a9c LW	253	const char *label = gpiochip_is_requested(gc, offset);
27ec8a9c	254	bool val = !!stmpe_gpio_get(gc, offset);
43db289d PC	255	u8 bank = offset / 8;
43db289d PC	256	u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
4e2678b5	257	u8 mask = BIT(offset % 8);
27ec8a9c LW	258	int ret;
	259	u8 dir;
	260
	261	ret = stmpe_reg_read(stmpe, dir_reg);
	262	if (ret < 0)
	263	return;
	264	dir = !!(ret & mask);
	265
	266	if (dir) {
	267	seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
	268	gpio, label ?: "(none)",
	269	val ? "hi" : "lo");
	270	} else {
287849cb PC	271	u8 edge_det_reg;
	272	u8 rise_reg;
	273	u8 fall_reg;
	274	u8 irqen_reg;
	275
e2843cb6 CIK	276	static const char * const edge_det_values[] = {
	277	"edge-inactive",
	278	"edge-asserted",
	279	"not-supported"
	280	};
	281	static const char * const rise_values[] = {
	282	"no-rising-edge-detection",
	283	"rising-edge-detection",
	284	"not-supported"
	285	};
	286	static const char * const fall_values[] = {
	287	"no-falling-edge-detection",
	288	"falling-edge-detection",
	289	"not-supported"
	290	};
287849cb PC	291	#define NOT_SUPPORTED_IDX 2
	292	u8 edge_det = NOT_SUPPORTED_IDX;
	293	u8 rise = NOT_SUPPORTED_IDX;
	294	u8 fall = NOT_SUPPORTED_IDX;
27ec8a9c LW	295	bool irqen;
27ec8a9c LW	296
287849cb PC	297	switch (stmpe->partnum) {
	298	case STMPE610:
	299	case STMPE811:
	300	case STMPE1601:
	301	case STMPE2401:
	302	case STMPE2403:
43db289d	303	edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
287849cb PC	304	ret = stmpe_reg_read(stmpe, edge_det_reg);
	305	if (ret < 0)
	306	return;
	307	edge_det = !!(ret & mask);
e80df7b8	308	/* fall through */
287849cb	309	case STMPE1801:
43db289d PC	310	rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
	311	fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
	312
287849cb PC	313	ret = stmpe_reg_read(stmpe, rise_reg);
	314	if (ret < 0)
	315	return;
	316	rise = !!(ret & mask);
	317	ret = stmpe_reg_read(stmpe, fall_reg);
	318	if (ret < 0)
	319	return;
	320	fall = !!(ret & mask);
e80df7b8	321	/* fall through */
287849cb	322	case STMPE801:
c6a05a05	323	case STMPE1600:
43db289d	324	irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
287849cb PC	325	break;
	326
	327	default:
27ec8a9c	328	return;
287849cb PC	329	}
287849cb PC	330
27ec8a9c LW	331	ret = stmpe_reg_read(stmpe, irqen_reg);
	332	if (ret < 0)
	333	return;
	334	irqen = !!(ret & mask);
	335
287849cb	336	seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
27ec8a9c LW	337	gpio, label ?: "(none)",
27ec8a9c LW	338	val ? "hi" : "lo",
287849cb PC	339	edge_det_values[edge_det],
	340	irqen ? "IRQ-enabled" : "IRQ-disabled",
	341	rise_values[rise],
	342	fall_values[fall]);
27ec8a9c LW	343	}
	344	}
	345
	346	static void stmpe_dbg_show(struct seq_file s, struct gpio_chip gc)
	347	{
	348	unsigned i;
	349	unsigned gpio = gc->base;
	350
	351	for (i = 0; i < gc->ngpio; i++, gpio++) {
	352	stmpe_dbg_show_one(s, gc, i, gpio);
0d83a5eb	353	seq_putc(s, '\n');
27ec8a9c LW	354	}
	355	}
	356
03f822f5 RV	357	static struct irq_chip stmpe_gpio_irq_chip = {
03f822f5 RV	358	.name = "stmpe-gpio",
2a866f39 LB	359	.irq_bus_lock = stmpe_gpio_irq_lock,
	360	.irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
	361	.irq_mask = stmpe_gpio_irq_mask,
	362	.irq_unmask = stmpe_gpio_irq_unmask,
	363	.irq_set_type = stmpe_gpio_irq_set_type,
03f822f5 RV	364	};
	365
	366	static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
	367	{
	368	struct stmpe_gpio *stmpe_gpio = dev;
	369	struct stmpe *stmpe = stmpe_gpio->stmpe;
c6a05a05	370	u8 statmsbreg;
03f822f5 RV	371	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	372	u8 status[num_banks];
	373	int ret;
	374	int i;
	375
c6a05a05 PC	376	/*
	377	* the stmpe_block_read() call below, imposes to set statmsbreg
	378	* with the register located at the lowest address. As STMPE1600
	379	* variant is the only one which respect registers address's order
	380	* (LSB regs located at lowest address than MSB ones) whereas all
	381	* the others have a registers layout with MSB located before the
	382	* LSB regs.
	383	*/
	384	if (stmpe->partnum == STMPE1600)
	385	statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
	386	else
	387	statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	388
03f822f5 RV	389	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	390	if (ret < 0)
	391	return IRQ_NONE;
	392
	393	for (i = 0; i < num_banks; i++) {
c6a05a05 PC	394	int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
c6a05a05 PC	395	num_banks - i - 1;
03f822f5 RV	396	unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
	397	unsigned int stat = status[i];
	398
	399	stat &= enabled;
	400	if (!stat)
	401	continue;
	402
	403	while (stat) {
	404	int bit = __ffs(stat);
	405	int line = bank * 8 + bit;
f0fbe7bc	406	int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
ed05e204	407	line);
03f822f5	408
ed05e204	409	handle_nested_irq(child_irq);
4e2678b5	410	stat &= ~BIT(bit);
03f822f5 RV	411	}
03f822f5 RV	412
6936e1f8 PC	413	/*
6936e1f8 PC	414	* interrupt status register write has no effect on
c6a05a05 PC	415	* 801/1801/1600, bits are cleared when read.
c6a05a05 PC	416	* Edge detect register is not present on 801/1600/1801
6936e1f8	417	*/
d1ca19cb	418	if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
c6a05a05	419	stmpe->partnum != STMPE1801) {
6936e1f8	420	stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
43db289d	421	stmpe_reg_write(stmpe,
1516c635	422	stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
43db289d	423	status[i]);
6936e1f8	424	}
03f822f5 RV	425	}
	426
	427	return IRQ_HANDLED;
	428	}
	429
3836309d	430	static int stmpe_gpio_probe(struct platform_device *pdev)
03f822f5 RV	431	{
03f822f5 RV	432	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
86605cfe	433	struct device_node *np = pdev->dev.of_node;
03f822f5	434	struct stmpe_gpio *stmpe_gpio;
0f719231	435	int ret, irq;
03f822f5	436
64fec0bc	437	stmpe_gpio = kzalloc(sizeof(*stmpe_gpio), GFP_KERNEL);
03f822f5 RV	438	if (!stmpe_gpio)
	439	return -ENOMEM;
	440
	441	mutex_init(&stmpe_gpio->irq_lock);
	442
	443	stmpe_gpio->dev = &pdev->dev;
	444	stmpe_gpio->stmpe = stmpe;
03f822f5 RV	445	stmpe_gpio->chip = template_chip;
03f822f5 RV	446	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
58383c78	447	stmpe_gpio->chip.parent = &pdev->dev;
9afd9b70	448	stmpe_gpio->chip.of_node = np;
9e9dc7d9	449	stmpe_gpio->chip.base = -1;
03f822f5	450
27ec8a9c LW	451	if (IS_ENABLED(CONFIG_DEBUG_FS))
	452	stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
	453
1dfb4a0d LW	454	of_property_read_u32(np, "st,norequest-mask",
1dfb4a0d LW	455	&stmpe_gpio->norequest_mask);
96b2cca6	456	if (stmpe_gpio->norequest_mask)
dc7b0387	457	stmpe_gpio->chip.irq.need_valid_mask = true;
86605cfe	458
757ad058	459	irq = platform_get_irq(pdev, 0);
9e9dc7d9	460	if (irq < 0)
38040c85	461	dev_info(&pdev->dev,
fe44e70d	462	"device configured in no-irq mode: "
38040c85	463	"irqs are not available\n");
03f822f5 RV	464
	465	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	466	if (ret)
02bf0749	467	goto out_free;
03f822f5	468
b03c04a0	469	ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
3f97d5fc LW	470	if (ret) {
	471	dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
	472	goto out_disable;
	473	}
	474
fe44e70d LW	475	if (irq > 0) {
	476	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
	477	stmpe_gpio_irq, IRQF_ONESHOT,
	478	"stmpe-gpio", stmpe_gpio);
38040c85 CB	479	if (ret) {
38040c85 CB	480	dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
fc13d5a5	481	goto out_disable;
38040c85	482	}
96b2cca6 LW	483	if (stmpe_gpio->norequest_mask) {
	484	int i;
	485
	486	/* Forbid unused lines to be mapped as IRQs */
	487	for (i = 0; i < sizeof(u32); i++)
	488	if (stmpe_gpio->norequest_mask & BIT(i))
dc7b0387	489	clear_bit(i, stmpe_gpio->chip.irq.valid_mask);
96b2cca6	490	}
d245b3f9 LW	491	ret = gpiochip_irqchip_add_nested(&stmpe_gpio->chip,
	492	&stmpe_gpio_irq_chip,
	493	0,
	494	handle_simple_irq,
	495	IRQ_TYPE_NONE);
fe44e70d LW	496	if (ret) {
	497	dev_err(&pdev->dev,
	498	"could not connect irqchip to gpiochip\n");
3f97d5fc	499	goto out_disable;
fe44e70d	500	}
03f822f5	501
d245b3f9 LW	502	gpiochip_set_nested_irqchip(&stmpe_gpio->chip,
	503	&stmpe_gpio_irq_chip,
	504	irq);
03f822f5 RV	505	}
03f822f5 RV	506
03f822f5 RV	507	platform_set_drvdata(pdev, stmpe_gpio);
	508
	509	return 0;
	510
02bf0749 VK	511	out_disable:
02bf0749 VK	512	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
3f97d5fc	513	gpiochip_remove(&stmpe_gpio->chip);
03f822f5 RV	514	out_free:
	515	kfree(stmpe_gpio);
	516	return ret;
	517	}
	518
03f822f5	519	static struct platform_driver stmpe_gpio_driver = {
3b52bb96 PG	520	.driver = {
	521	.suppress_bind_attrs = true,
	522	.name = "stmpe-gpio",
3b52bb96	523	},
03f822f5	524	.probe = stmpe_gpio_probe,
03f822f5 RV	525	};
	526
	527	static int __init stmpe_gpio_init(void)
	528	{
	529	return platform_driver_register(&stmpe_gpio_driver);
	530	}
	531	subsys_initcall(stmpe_gpio_init);