[linux.git] / arch / csky / mm / cachev2.c

// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.

#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/mm.h>
#include <asm/cache.h>
#include <asm/barrier.h>

/* for L1-cache */
#define INS_CACHE		(1 << 0)
#define DATA_CACHE		(1 << 1)
#define CACHE_INV		(1 << 4)
#define CACHE_CLR		(1 << 5)
#define CACHE_OMS		(1 << 6)

void local_icache_inv_all(void *priv)
{
	mtcr("cr17", INS_CACHE|CACHE_INV);
	sync_is();
}

#ifdef CONFIG_CPU_HAS_ICACHE_INS
void icache_inv_range(unsigned long start, unsigned long end)
{
	unsigned long i = start & ~(L1_CACHE_BYTES - 1);

	for (; i < end; i += L1_CACHE_BYTES)
		asm volatile("icache.iva %0\n"::"r"(i):"memory");
	sync_is();
}
#else
struct cache_range {
	unsigned long start;
	unsigned long end;
};

static DEFINE_SPINLOCK(cache_lock);

static inline void cache_op_line(unsigned long i, unsigned int val)
{
	mtcr("cr22", i);
	mtcr("cr17", val);
}

void local_icache_inv_range(void *priv)
{
	struct cache_range *param = priv;
	unsigned long i = param->start & ~(L1_CACHE_BYTES - 1);
	unsigned long flags;

	spin_lock_irqsave(&cache_lock, flags);

	for (; i < param->end; i += L1_CACHE_BYTES)
		cache_op_line(i, INS_CACHE | CACHE_INV | CACHE_OMS);

	spin_unlock_irqrestore(&cache_lock, flags);

	sync_is();
}

void icache_inv_range(unsigned long start, unsigned long end)
{
	struct cache_range param = { start, end };

	if (irqs_disabled())
		local_icache_inv_range(&param);
	else
		on_each_cpu(local_icache_inv_range, &param, 1);
}
#endif

inline void dcache_wb_line(unsigned long start)
{
	asm volatile("dcache.cval1 %0\n"::"r"(start):"memory");
	sync_is();
}

void dcache_wb_range(unsigned long start, unsigned long end)
{
	unsigned long i = start & ~(L1_CACHE_BYTES - 1);

	for (; i < end; i += L1_CACHE_BYTES)
		asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
	sync_is();
}

void cache_wbinv_range(unsigned long start, unsigned long end)
{
	dcache_wb_range(start, end);
	icache_inv_range(start, end);
}
EXPORT_SYMBOL(cache_wbinv_range);

void dma_wbinv_range(unsigned long start, unsigned long end)
{
	unsigned long i = start & ~(L1_CACHE_BYTES - 1);

	for (; i < end; i += L1_CACHE_BYTES)
		asm volatile("dcache.civa %0\n"::"r"(i):"memory");
	sync_is();
}

void dma_inv_range(unsigned long start, unsigned long end)
{
	unsigned long i = start & ~(L1_CACHE_BYTES - 1);

	for (; i < end; i += L1_CACHE_BYTES)
		asm volatile("dcache.iva %0\n"::"r"(i):"memory");
	sync_is();
}

void dma_wb_range(unsigned long start, unsigned long end)
{
	unsigned long i = start & ~(L1_CACHE_BYTES - 1);

	for (; i < end; i += L1_CACHE_BYTES)
		asm volatile("dcache.cva %0\n"::"r"(i):"memory");
	sync_is();
}
Commit	Line	Data
00a9730e GR	1	// SPDX-License-Identifier: GPL-2.0
	2	// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
	3
	4	#include <linux/spinlock.h>
	5	#include <linux/smp.h>
761b4f69	6	#include <linux/mm.h>
00a9730e GR	7	#include <asm/cache.h>
	8	#include <asm/barrier.h>
	9
dd7c983e	10	/* for L1-cache */
761b4f69	11	#define INS_CACHE (1 << 0)
dd7c983e	12	#define DATA_CACHE (1 << 1)
761b4f69	13	#define CACHE_INV (1 << 4)
dd7c983e GR	14	#define CACHE_CLR (1 << 5)
dd7c983e GR	15	#define CACHE_OMS (1 << 6)
761b4f69 GR	16
761b4f69 GR	17	void local_icache_inv_all(void *priv)
00a9730e	18	{
761b4f69	19	mtcr("cr17", INS_CACHE\|CACHE_INV);
00a9730e GR	20	sync_is();
	21	}
	22
761b4f69	23	#ifdef CONFIG_CPU_HAS_ICACHE_INS
00a9730e GR	24	void icache_inv_range(unsigned long start, unsigned long end)
	25	{
	26	unsigned long i = start & ~(L1_CACHE_BYTES - 1);
	27
	28	for (; i < end; i += L1_CACHE_BYTES)
	29	asm volatile("icache.iva %0\n"::"r"(i):"memory");
	30	sync_is();
	31	}
761b4f69	32	#else
dd7c983e GR	33	struct cache_range {
	34	unsigned long start;
	35	unsigned long end;
	36	};
	37
	38	static DEFINE_SPINLOCK(cache_lock);
	39
	40	static inline void cache_op_line(unsigned long i, unsigned int val)
	41	{
	42	mtcr("cr22", i);
	43	mtcr("cr17", val);
	44	}
	45
	46	void local_icache_inv_range(void *priv)
	47	{
	48	struct cache_range *param = priv;
	49	unsigned long i = param->start & ~(L1_CACHE_BYTES - 1);
	50	unsigned long flags;
	51
	52	spin_lock_irqsave(&cache_lock, flags);
	53
	54	for (; i < param->end; i += L1_CACHE_BYTES)
	55	cache_op_line(i, INS_CACHE \| CACHE_INV \| CACHE_OMS);
	56
	57	spin_unlock_irqrestore(&cache_lock, flags);
	58
	59	sync_is();
	60	}
	61
761b4f69 GR	62	void icache_inv_range(unsigned long start, unsigned long end)
761b4f69 GR	63	{
dd7c983e GR	64	struct cache_range param = { start, end };
	65
	66	if (irqs_disabled())
	67	local_icache_inv_range(&param);
	68	else
	69	on_each_cpu(local_icache_inv_range, &param, 1);
761b4f69 GR	70	}
761b4f69 GR	71	#endif
00a9730e	72
761b4f69	73	inline void dcache_wb_line(unsigned long start)
00a9730e	74	{
761b4f69	75	asm volatile("dcache.cval1 %0\n"::"r"(start):"memory");
00a9730e GR	76	sync_is();
	77	}
	78
	79	void dcache_wb_range(unsigned long start, unsigned long end)
	80	{
	81	unsigned long i = start & ~(L1_CACHE_BYTES - 1);
	82
	83	for (; i < end; i += L1_CACHE_BYTES)
	84	asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
	85	sync_is();
	86	}
	87
00a9730e GR	88	void cache_wbinv_range(unsigned long start, unsigned long end)
00a9730e GR	89	{
9025fd48	90	dcache_wb_range(start, end);
761b4f69	91	icache_inv_range(start, end);
00a9730e GR	92	}
	93	EXPORT_SYMBOL(cache_wbinv_range);
	94
	95	void dma_wbinv_range(unsigned long start, unsigned long end)
	96	{
	97	unsigned long i = start & ~(L1_CACHE_BYTES - 1);
	98
	99	for (; i < end; i += L1_CACHE_BYTES)
	100	asm volatile("dcache.civa %0\n"::"r"(i):"memory");
	101	sync_is();
	102	}
	103
ae76f635 GR	104	void dma_inv_range(unsigned long start, unsigned long end)
	105	{
	106	unsigned long i = start & ~(L1_CACHE_BYTES - 1);
	107
	108	for (; i < end; i += L1_CACHE_BYTES)
	109	asm volatile("dcache.iva %0\n"::"r"(i):"memory");
	110	sync_is();
	111	}
	112
00a9730e GR	113	void dma_wb_range(unsigned long start, unsigned long end)
	114	{
	115	unsigned long i = start & ~(L1_CACHE_BYTES - 1);
	116
	117	for (; i < end; i += L1_CACHE_BYTES)
ae76f635	118	asm volatile("dcache.cva %0\n"::"r"(i):"memory");
00a9730e GR	119	sync_is();
00a9730e GR	120	}