[linux.git] / include / kvm / arm_vgic.h

/*
 * Copyright (C) 2015, 2016 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __KVM_ARM_VGIC_H
#define __KVM_ARM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/static_key.h>
#include <linux/types.h>
#include <kvm/iodev.h>
#include <linux/list.h>
#include <linux/jump_label.h>

#include <linux/irqchip/arm-gic-v4.h>

#define VGIC_V3_MAX_CPUS	255
#define VGIC_V2_MAX_CPUS	8
#define VGIC_NR_IRQS_LEGACY     256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)
#define VGIC_MAX_PRIVATE	(VGIC_NR_PRIVATE_IRQS - 1)
#define VGIC_MAX_SPI		1019
#define VGIC_MAX_RESERVED	1023
#define VGIC_MIN_LPI		8192
#define KVM_IRQCHIP_NUM_PINS	(1020 - 32)

#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
			 (irq) <= VGIC_MAX_SPI)

enum vgic_type {
	VGIC_V2,		/* Good ol' GICv2 */
	VGIC_V3,		/* New fancy GICv3 */
};

/* same for all guests, as depending only on the _host's_ GIC model */
struct vgic_global {
	/* type of the host GIC */
	enum vgic_type		type;

	/* Physical address of vgic virtual cpu interface */
	phys_addr_t		vcpu_base;

	/* GICV mapping */
	void __iomem		*vcpu_base_va;

	/* virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Number of implemented list registers */
	int			nr_lr;

	/* Maintenance IRQ number */
	unsigned int		maint_irq;

	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
	int			max_gic_vcpus;

	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
	bool			can_emulate_gicv2;

	/* Hardware has GICv4? */
	bool			has_gicv4;

	/* GIC system register CPU interface */
	struct static_key_false gicv3_cpuif;

	u32			ich_vtr_el2;
};

extern struct vgic_global kvm_vgic_global_state;

#define VGIC_V2_MAX_LRS		(1 << 6)
#define VGIC_V3_MAX_LRS		16
#define VGIC_V3_LR_INDEX(lr)	(VGIC_V3_MAX_LRS - 1 - lr)

enum vgic_irq_config {
	VGIC_CONFIG_EDGE = 0,
	VGIC_CONFIG_LEVEL
};

struct vgic_irq {
	spinlock_t irq_lock;		/* Protects the content of the struct */
	struct list_head lpi_list;	/* Used to link all LPIs together */
	struct list_head ap_list;

	struct kvm_vcpu *vcpu;		/* SGIs and PPIs: The VCPU
					 * SPIs and LPIs: The VCPU whose ap_list
					 * this is queued on.
					 */

	struct kvm_vcpu *target_vcpu;	/* The VCPU that this interrupt should
					 * be sent to, as a result of the
					 * targets reg (v2) or the
					 * affinity reg (v3).
					 */

	u32 intid;			/* Guest visible INTID */
	bool line_level;		/* Level only */
	bool pending_latch;		/* The pending latch state used to calculate
					 * the pending state for both level
					 * and edge triggered IRQs. */
	bool active;			/* not used for LPIs */
	bool enabled;
	bool hw;			/* Tied to HW IRQ */
	struct kref refcount;		/* Used for LPIs */
	u32 hwintid;			/* HW INTID number */
	unsigned int host_irq;		/* linux irq corresponding to hwintid */
	union {
		u8 targets;			/* GICv2 target VCPUs mask */
		u32 mpidr;			/* GICv3 target VCPU */
	};
	u8 source;			/* GICv2 SGIs only */
	u8 priority;
	enum vgic_irq_config config;	/* Level or edge */

	void *owner;			/* Opaque pointer to reserve an interrupt
					   for in-kernel devices. */
};

struct vgic_register_region;
struct vgic_its;

enum iodev_type {
	IODEV_CPUIF,
	IODEV_DIST,
	IODEV_REDIST,
	IODEV_ITS
};

struct vgic_io_device {
	gpa_t base_addr;
	union {
		struct kvm_vcpu *redist_vcpu;
		struct vgic_its *its;
	};
	const struct vgic_register_region *regions;
	enum iodev_type iodev_type;
	int nr_regions;
	struct kvm_io_device dev;
};

struct vgic_its {
	/* The base address of the ITS control register frame */
	gpa_t			vgic_its_base;

	bool			enabled;
	struct vgic_io_device	iodev;
	struct kvm_device	*dev;

	/* These registers correspond to GITS_BASER{0,1} */
	u64			baser_device_table;
	u64			baser_coll_table;

	/* Protects the command queue */
	struct mutex		cmd_lock;
	u64			cbaser;
	u32			creadr;
	u32			cwriter;

	/* migration ABI revision in use */
	u32			abi_rev;

	/* Protects the device and collection lists */
	struct mutex		its_lock;
	struct list_head	device_list;
	struct list_head	collection_list;
};

struct vgic_state_iter;

struct vgic_dist {
	bool			in_kernel;
	bool			ready;
	bool			initialized;

	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	u32			vgic_model;

	/* Do injected MSIs require an additional device ID? */
	bool			msis_require_devid;

	int			nr_spis;

	/* TODO: Consider moving to global state */
	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* base addresses in guest physical address space: */
	gpa_t			vgic_dist_base;		/* distributor */
	union {
		/* either a GICv2 CPU interface */
		gpa_t			vgic_cpu_base;
		/* or a number of GICv3 redistributor regions */
		struct {
			gpa_t		vgic_redist_base;
			gpa_t		vgic_redist_free_offset;
		};
	};

	/* distributor enabled */
	bool			enabled;

	struct vgic_irq		*spis;

	struct vgic_io_device	dist_iodev;

	bool			has_its;

	/*
	 * Contains the attributes and gpa of the LPI configuration table.
	 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
	 * one address across all redistributors.
	 * GICv3 spec: 6.1.2 "LPI Configuration tables"
	 */
	u64			propbaser;

	/* Protects the lpi_list and the count value below. */
	spinlock_t		lpi_list_lock;
	struct list_head	lpi_list_head;
	int			lpi_list_count;

	/* used by vgic-debug */
	struct vgic_state_iter *iter;

	/*
	 * GICv4 ITS per-VM data, containing the IRQ domain, the VPE
	 * array, the property table pointer as well as allocation
	 * data. This essentially ties the Linux IRQ core and ITS
	 * together, and avoids leaking KVM's data structures anywhere
	 * else.
	 */
	struct its_vm		its_vm;
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u64		vgic_elrsr;	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_V2_MAX_LRS];
};

struct vgic_v3_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_sre;	/* Restored only, change ignored */
	u32		vgic_elrsr;	/* Saved only */
	u32		vgic_ap0r[4];
	u32		vgic_ap1r[4];
	u64		vgic_lr[VGIC_V3_MAX_LRS];

	/*
	 * GICv4 ITS per-VPE data, containing the doorbell IRQ, the
	 * pending table pointer, the its_vm pointer and a few other
	 * HW specific things. As for the its_vm structure, this is
	 * linking the Linux IRQ subsystem and the ITS together.
	 */
	struct its_vpe	its_vpe;
};

struct vgic_cpu {
	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
		struct vgic_v3_cpu_if	vgic_v3;
	};

	unsigned int used_lrs;
	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];

	spinlock_t ap_list_lock;	/* Protects the ap_list */

	/*
	 * List of IRQs that this VCPU should consider because they are either
	 * Active or Pending (hence the name; AP list), or because they recently
	 * were one of the two and need to be migrated off this list to another
	 * VCPU.
	 */
	struct list_head ap_list_head;

	/*
	 * Members below are used with GICv3 emulation only and represent
	 * parts of the redistributor.
	 */
	struct vgic_io_device	rd_iodev;
	struct vgic_io_device	sgi_iodev;

	/* Contains the attributes and gpa of the LPI pending tables. */
	u64 pendbaser;

	bool lpis_enabled;

	/* Cache guest priority bits */
	u32 num_pri_bits;

	/* Cache guest interrupt ID bits */
	u32 num_id_bits;
};

extern struct static_key_false vgic_v2_cpuif_trap;
extern struct static_key_false vgic_v3_cpuif_trap;

int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
void kvm_vgic_early_init(struct kvm *kvm);
int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
int kvm_vgic_create(struct kvm *kvm, u32 type);
void kvm_vgic_destroy(struct kvm *kvm);
void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
int kvm_vgic_map_resources(struct kvm *kvm);
int kvm_vgic_hyp_init(void);
void kvm_vgic_init_cpu_hardware(void);

int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
			bool level, void *owner);
int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
			  u32 vintid);
int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);

int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);

void kvm_vgic_load(struct kvm_vcpu *vcpu);
void kvm_vgic_put(struct kvm_vcpu *vcpu);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k)	((k)->arch.vgic.initialized)
#define vgic_ready(k)		((k)->arch.vgic.ready)
#define vgic_valid_spi(k, i)	(((i) >= VGIC_NR_PRIVATE_IRQS) && \
			((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))

bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);

void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);

/**
 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 *
 * The host's GIC naturally limits the maximum amount of VCPUs a guest
 * can use.
 */
static inline int kvm_vgic_get_max_vcpus(void)
{
	return kvm_vgic_global_state.max_gic_vcpus;
}

int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);

/**
 * kvm_vgic_setup_default_irq_routing:
 * Setup a default flat gsi routing table mapping all SPIs
 */
int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);

int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner);

struct kvm_kernel_irq_routing_entry;

int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq,
			       struct kvm_kernel_irq_routing_entry *irq_entry);

int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq,
				 struct kvm_kernel_irq_routing_entry *irq_entry);

void kvm_vgic_v4_enable_doorbell(struct kvm_vcpu *vcpu);
void kvm_vgic_v4_disable_doorbell(struct kvm_vcpu *vcpu);

#endif /* __KVM_ARM_VGIC_H */
Commit	Line	Data
1a89dd91	1	/*
50926d82	2	* Copyright (C) 2015, 2016 ARM Ltd.
1a89dd91 MZ	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
50926d82	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
1a89dd91	15	*/
50926d82 MZ	16	#ifndef __KVM_ARM_VGIC_H
50926d82 MZ	17	#define __KVM_ARM_VGIC_H
b18b5778	18
b47ef92a MZ	19	#include <linux/kernel.h>
b47ef92a MZ	20	#include <linux/kvm.h>
b47ef92a MZ	21	#include <linux/irqreturn.h>
b47ef92a MZ	22	#include <linux/spinlock.h>
fb5ee369	23	#include <linux/static_key.h>
b47ef92a	24	#include <linux/types.h>
6777f77f	25	#include <kvm/iodev.h>
424c3383	26	#include <linux/list.h>
5a7a8426	27	#include <linux/jump_label.h>
1a89dd91	28
74fe55dc MZ	29	#include <linux/irqchip/arm-gic-v4.h>
74fe55dc MZ	30
50926d82 MZ	31	#define VGIC_V3_MAX_CPUS 255
	32	#define VGIC_V2_MAX_CPUS 8
	33	#define VGIC_NR_IRQS_LEGACY 256
b47ef92a MZ	34	#define VGIC_NR_SGIS 16
	35	#define VGIC_NR_PPIS 16
	36	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
50926d82 MZ	37	#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
	38	#define VGIC_MAX_SPI 1019
	39	#define VGIC_MAX_RESERVED 1023
	40	#define VGIC_MIN_LPI 8192
180ae7b1	41	#define KVM_IRQCHIP_NUM_PINS (1020 - 32)
8f186d52	42
3cba4af3	43	#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
ebb127f2 CD	44	#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
ebb127f2 CD	45	(irq) <= VGIC_MAX_SPI)
3cba4af3	46
50926d82 MZ	47	enum vgic_type {
	48	VGIC_V2, /* Good ol' GICv2 */
	49	VGIC_V3, /* New fancy GICv3 */
	50	};
b47ef92a	51
50926d82 MZ	52	/* same for all guests, as depending only on the _host's_ GIC model */
	53	struct vgic_global {
	54	/* type of the host GIC */
	55	enum vgic_type type;
b47ef92a	56
50926d82 MZ	57	/* Physical address of vgic virtual cpu interface */
50926d82 MZ	58	phys_addr_t vcpu_base;
b47ef92a	59
bf8feb39 MZ	60	/* GICV mapping */
	61	void __iomem *vcpu_base_va;
	62
50926d82 MZ	63	/* virtual control interface mapping */
50926d82 MZ	64	void __iomem *vctrl_base;
b47ef92a	65
50926d82 MZ	66	/* Number of implemented list registers */
50926d82 MZ	67	int nr_lr;
8d5c6b06	68
50926d82 MZ	69	/* Maintenance IRQ number */
50926d82 MZ	70	unsigned int maint_irq;
1a9b1305	71
50926d82 MZ	72	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
50926d82 MZ	73	int max_gic_vcpus;
8d5c6b06	74
50926d82 MZ	75	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
50926d82 MZ	76	bool can_emulate_gicv2;
5a7a8426	77
e7c48059 MZ	78	/* Hardware has GICv4? */
	79	bool has_gicv4;
	80
5a7a8426 VM	81	/* GIC system register CPU interface */
5a7a8426 VM	82	struct static_key_false gicv3_cpuif;
d017d7b0 VK	83
d017d7b0 VK	84	u32 ich_vtr_el2;
8d5c6b06 MZ	85	};
8d5c6b06 MZ	86
50926d82	87	extern struct vgic_global kvm_vgic_global_state;
beee38b9	88
50926d82 MZ	89	#define VGIC_V2_MAX_LRS (1 << 6)
	90	#define VGIC_V3_MAX_LRS 16
	91	#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
8d5c6b06	92
50926d82 MZ	93	enum vgic_irq_config {
	94	VGIC_CONFIG_EDGE = 0,
	95	VGIC_CONFIG_LEVEL
ca85f623 MZ	96	};
ca85f623 MZ	97
50926d82 MZ	98	struct vgic_irq {
50926d82 MZ	99	spinlock_t irq_lock; /* Protects the content of the struct */
3802411d	100	struct list_head lpi_list; /* Used to link all LPIs together */
50926d82 MZ	101	struct list_head ap_list;
	102
	103	struct kvm_vcpu vcpu; / SGIs and PPIs: The VCPU
	104	* SPIs and LPIs: The VCPU whose ap_list
	105	* this is queued on.
	106	*/
	107
	108	struct kvm_vcpu target_vcpu; / The VCPU that this interrupt should
	109	* be sent to, as a result of the
	110	* targets reg (v2) or the
	111	* affinity reg (v3).
	112	*/
	113
	114	u32 intid; /* Guest visible INTID */
50926d82	115	bool line_level; /* Level only */
8694e4da CD	116	bool pending_latch; /* The pending latch state used to calculate
	117	* the pending state for both level
	118	* and edge triggered IRQs. */
50926d82 MZ	119	bool active; /* not used for LPIs */
	120	bool enabled;
	121	bool hw; /* Tied to HW IRQ */
5dd4b924	122	struct kref refcount; /* Used for LPIs */
50926d82	123	u32 hwintid; /* HW INTID number */
47bbd31f	124	unsigned int host_irq; /* linux irq corresponding to hwintid */
50926d82 MZ	125	union {
	126	u8 targets; /* GICv2 target VCPUs mask */
	127	u32 mpidr; /* GICv3 target VCPU */
	128	};
	129	u8 source; /* GICv2 SGIs only */
	130	u8 priority;
	131	enum vgic_irq_config config; /* Level or edge */
c6ccd30e CD	132
	133	void owner; / Opaque pointer to reserve an interrupt
	134	for in-kernel devices. */
b26e5fda AP	135	};
b26e5fda AP	136
50926d82	137	struct vgic_register_region;
59c5ab40 AP	138	struct vgic_its;
	139
	140	enum iodev_type {
	141	IODEV_CPUIF,
	142	IODEV_DIST,
	143	IODEV_REDIST,
	144	IODEV_ITS
	145	};
50926d82	146
6777f77f	147	struct vgic_io_device {
50926d82	148	gpa_t base_addr;
59c5ab40 AP	149	union {
	150	struct kvm_vcpu *redist_vcpu;
	151	struct vgic_its *its;
	152	};
50926d82	153	const struct vgic_register_region *regions;
59c5ab40	154	enum iodev_type iodev_type;
50926d82	155	int nr_regions;
6777f77f AP	156	struct kvm_io_device dev;
	157	};
	158
59c5ab40 AP	159	struct vgic_its {
	160	/* The base address of the ITS control register frame */
	161	gpa_t vgic_its_base;
	162
	163	bool enabled;
	164	struct vgic_io_device iodev;
bb717644	165	struct kvm_device *dev;
424c3383 AP	166
	167	/* These registers correspond to GITS_BASER{0,1} */
	168	u64 baser_device_table;
	169	u64 baser_coll_table;
	170
	171	/* Protects the command queue */
	172	struct mutex cmd_lock;
	173	u64 cbaser;
	174	u32 creadr;
	175	u32 cwriter;
	176
71afe470 EA	177	/* migration ABI revision in use */
	178	u32 abi_rev;
	179
424c3383 AP	180	/* Protects the device and collection lists */
	181	struct mutex its_lock;
	182	struct list_head device_list;
	183	struct list_head collection_list;
59c5ab40 AP	184	};
59c5ab40 AP	185
10f92c4c CD	186	struct vgic_state_iter;
10f92c4c CD	187
1a89dd91	188	struct vgic_dist {
f982cf4e	189	bool in_kernel;
01ac5e34	190	bool ready;
50926d82	191	bool initialized;
b47ef92a	192
59892136 AP	193	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	194	u32 vgic_model;
	195
0e4e82f1 AP	196	/* Do injected MSIs require an additional device ID? */
	197	bool msis_require_devid;
	198
50926d82	199	int nr_spis;
c1bfb577	200
50926d82	201	/* TODO: Consider moving to global state */
b47ef92a MZ	202	/* Virtual control interface mapping */
	203	void __iomem *vctrl_base;
	204
50926d82 MZ	205	/* base addresses in guest physical address space: */
50926d82 MZ	206	gpa_t vgic_dist_base; /* distributor */
a0675c25	207	union {
50926d82 MZ	208	/* either a GICv2 CPU interface */
	209	gpa_t vgic_cpu_base;
	210	/* or a number of GICv3 redistributor regions */
552c9f47 CD	211	struct {
	212	gpa_t vgic_redist_base;
	213	gpa_t vgic_redist_free_offset;
	214	};
a0675c25	215	};
b47ef92a	216
50926d82 MZ	217	/* distributor enabled */
50926d82 MZ	218	bool enabled;
47a98b15	219
50926d82	220	struct vgic_irq *spis;
b47ef92a	221
a9cf86f6	222	struct vgic_io_device dist_iodev;
0aa1de57	223
1085fdc6 AP	224	bool has_its;
1085fdc6 AP	225
0aa1de57 AP	226	/*
	227	* Contains the attributes and gpa of the LPI configuration table.
	228	* Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
	229	* one address across all redistributors.
	230	* GICv3 spec: 6.1.2 "LPI Configuration tables"
	231	*/
	232	u64 propbaser;
3802411d AP	233
	234	/* Protects the lpi_list and the count value below. */
	235	spinlock_t lpi_list_lock;
	236	struct list_head lpi_list_head;
	237	int lpi_list_count;
10f92c4c CD	238
	239	/* used by vgic-debug */
	240	struct vgic_state_iter *iter;
74fe55dc MZ	241
	242	/*
	243	* GICv4 ITS per-VM data, containing the IRQ domain, the VPE
	244	* array, the property table pointer as well as allocation
	245	* data. This essentially ties the Linux IRQ core and ITS
	246	* together, and avoids leaking KVM's data structures anywhere
	247	* else.
	248	*/
	249	struct its_vm its_vm;
1a89dd91 MZ	250	};
1a89dd91 MZ	251
eede821d MZ	252	struct vgic_v2_cpu_if {
	253	u32 vgic_hcr;
	254	u32 vgic_vmcr;
2df36a5d	255	u64 vgic_elrsr; /* Saved only */
eede821d	256	u32 vgic_apr;
8f186d52	257	u32 vgic_lr[VGIC_V2_MAX_LRS];
eede821d MZ	258	};
eede821d MZ	259
b2fb1c0d	260	struct vgic_v3_cpu_if {
b2fb1c0d MZ	261	u32 vgic_hcr;
b2fb1c0d MZ	262	u32 vgic_vmcr;
2f5fa41a	263	u32 vgic_sre; /* Restored only, change ignored */
b2fb1c0d MZ	264	u32 vgic_elrsr; /* Saved only */
	265	u32 vgic_ap0r[4];
	266	u32 vgic_ap1r[4];
	267	u64 vgic_lr[VGIC_V3_MAX_LRS];
74fe55dc MZ	268
	269	/*
	270	* GICv4 ITS per-VPE data, containing the doorbell IRQ, the
	271	* pending table pointer, the its_vm pointer and a few other
	272	* HW specific things. As for the its_vm structure, this is
	273	* linking the Linux IRQ subsystem and the ITS together.
	274	*/
	275	struct its_vpe its_vpe;
b2fb1c0d MZ	276	};
b2fb1c0d MZ	277
1a89dd91	278	struct vgic_cpu {
9d949dce	279	/* CPU vif control registers for world switch */
eede821d MZ	280	union {
eede821d MZ	281	struct vgic_v2_cpu_if vgic_v2;
b2fb1c0d	282	struct vgic_v3_cpu_if vgic_v3;
eede821d	283	};
6c3d63c9	284
50926d82 MZ	285	unsigned int used_lrs;
50926d82 MZ	286	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
1a89dd91	287
50926d82	288	spinlock_t ap_list_lock; /* Protects the ap_list */
9d949dce	289
50926d82 MZ	290	/*
	291	* List of IRQs that this VCPU should consider because they are either
	292	* Active or Pending (hence the name; AP list), or because they recently
	293	* were one of the two and need to be migrated off this list to another
	294	* VCPU.
	295	*/
	296	struct list_head ap_list_head;
495dd859	297
8f6cdc1c AP	298	/*
	299	* Members below are used with GICv3 emulation only and represent
	300	* parts of the redistributor.
	301	*/
	302	struct vgic_io_device rd_iodev;
	303	struct vgic_io_device sgi_iodev;
0aa1de57 AP	304
	305	/* Contains the attributes and gpa of the LPI pending tables. */
	306	u64 pendbaser;
	307
	308	bool lpis_enabled;
d017d7b0 VK	309
	310	/* Cache guest priority bits */
	311	u32 num_pri_bits;
	312
	313	/* Cache guest interrupt ID bits */
	314	u32 num_id_bits;
50926d82	315	};
1a89dd91	316
fb5ee369	317	extern struct static_key_false vgic_v2_cpuif_trap;
59da1cbf	318	extern struct static_key_false vgic_v3_cpuif_trap;
fb5ee369	319
ce01e4e8	320	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
6c3d63c9	321	void kvm_vgic_early_init(struct kvm *kvm);
1aab6f46	322	int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
59892136	323	int kvm_vgic_create(struct kvm *kvm, u32 type);
c1bfb577	324	void kvm_vgic_destroy(struct kvm *kvm);
6c3d63c9	325	void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
c1bfb577	326	void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
50926d82 MZ	327	int kvm_vgic_map_resources(struct kvm *kvm);
50926d82 MZ	328	int kvm_vgic_hyp_init(void);
5b0d2cc2	329	void kvm_vgic_init_cpu_hardware(void);
50926d82 MZ	330
50926d82 MZ	331	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
cb3f0ad8	332	bool level, void *owner);
47bbd31f EA	333	int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
	334	u32 vintid);
	335	int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
	336	bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);
1a89dd91	337
50926d82 MZ	338	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
50926d82 MZ	339
328e5664 CD	340	void kvm_vgic_load(struct kvm_vcpu *vcpu);
	341	void kvm_vgic_put(struct kvm_vcpu *vcpu);
	342
f982cf4e	343	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
50926d82	344	#define vgic_initialized(k) ((k)->arch.vgic.initialized)
c52edf5f	345	#define vgic_ready(k) ((k)->arch.vgic.ready)
2defaff4	346	#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
50926d82 MZ	347	((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
	348
	349	bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
	350	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
	351	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
9d949dce	352
50926d82	353	void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
8f186d52	354
50926d82 MZ	355	/**
	356	* kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
	357	*
	358	* The host's GIC naturally limits the maximum amount of VCPUs a guest
	359	* can use.
	360	*/
	361	static inline int kvm_vgic_get_max_vcpus(void)
	362	{
	363	return kvm_vgic_global_state.max_gic_vcpus;
	364	}
	365
0e4e82f1 AP	366	int kvm_send_userspace_msi(struct kvm kvm, struct kvm_msi msi);
0e4e82f1 AP	367
180ae7b1 EA	368	/**
	369	* kvm_vgic_setup_default_irq_routing:
	370	* Setup a default flat gsi routing table mapping all SPIs
	371	*/
	372	int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
	373
c6ccd30e CD	374	int kvm_vgic_set_owner(struct kvm_vcpu vcpu, unsigned int intid, void owner);
c6ccd30e CD	375
196b1364 MZ	376	struct kvm_kernel_irq_routing_entry;
	377
	378	int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq,
	379	struct kvm_kernel_irq_routing_entry *irq_entry);
	380
	381	int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq,
	382	struct kvm_kernel_irq_routing_entry *irq_entry);
	383
df9ba959 MZ	384	void kvm_vgic_v4_enable_doorbell(struct kvm_vcpu *vcpu);
	385	void kvm_vgic_v4_disable_doorbell(struct kvm_vcpu *vcpu);
	386
50926d82	387	#endif /* __KVM_ARM_VGIC_H */