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qlge: bugfix: Add missing pci_unmap_page call in receive path.
[linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <[email protected]>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
743d32ad 53#define DRV_VERSION "1.22"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 66
67#define TX_RING_SIZE 512
68#define TX_DEF_PENDING (TX_RING_SIZE - 1)
69#define TX_MIN_PENDING 64
b19666d9 70#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 71
793b883e 72#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 73#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 74#define TX_WATCHDOG (5 * HZ)
75#define NAPI_WEIGHT 64
76#define PHY_RETRIES 1000
77
f4331a6d
SH		 78#define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
cb5d9547
SH		 81#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
cd28ab6a 83static const u32 default_msg =
793b883e
SH		 84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 87
793b883e 88static int debug = -1; /* defaults above */
cd28ab6a
SH		 89module_param(debug, int, 0);
90MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
14d0263f 92static int copybreak __read_mostly = 128;
bdb5c58e
SH		 93module_param(copybreak, int, 0);
94MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
fb2690a9
SH		 96static int disable_msi = 0;
97module_param(disable_msi, int, 0);
98MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
e6cac9ba 100static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 140 { 0 }
141};
793b883e 142
cd28ab6a
SH		 143MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145/* Avoid conditionals by using array */
146static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 149
d1b139c0
SH		 150static void sky2_set_multicast(struct net_device *dev);
151
af043aa5 152/* Access to PHY via serial interconnect */
ef743d33 153static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 154{
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
af043aa5
SH		 168
169 udelay(10);
cd28ab6a 170 }
ef743d33 171
af043aa5 172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 173 return -ETIMEDOUT;
af043aa5
SH		 174
175io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
cd28ab6a
SH		 178}
179
ef743d33 180static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 181{
182 int i;
183
793b883e 184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
af043aa5 197 udelay(10);
cd28ab6a
SH		 198 }
199
af043aa5 200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 201 return -ETIMEDOUT;
af043aa5
SH		 202io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
ef743d33
SH		 205}
206
af043aa5 207static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 208{
209 u16 v;
af043aa5 210 __gm_phy_read(hw, port, reg, &v);
ef743d33 211 return v;
cd28ab6a
SH		 212}
213
5afa0a9c 214
ae306cca
SH		 215static void sky2_power_on(struct sky2_hw *hw)
216{
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 220
ae306cca
SH		 221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 223
ae306cca
SH		 224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 232
ea76e635 233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 234 u32 reg;
5afa0a9c 235
b32f40c4 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 237
b32f40c4 238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 247
b32f40c4 248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 254
255 sky2_read32(hw, B2_GP_IO);
5afa0a9c 256 }
ae306cca 257}
5afa0a9c 258
ae306cca
SH		 259static void sky2_power_aux(struct sky2_hw *hw)
260{
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 275}
276
d3bcfbeb 277static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 278{
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 283
cd28ab6a
SH		 284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292}
293
16ad91e1
SH		 294/* flow control to advertise bits */
295static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300};
301
302/* flow control to advertise bits when using 1000BaseX */
303static const u16 fiber_fc_adv[] = {
df3fe1f3 304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 308};
309
310/* flow control to GMA disable bits */
311static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316};
317
318
cd28ab6a
SH		 319static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320{
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 323
ea76e635
SH		 324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 329 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
53419c68 332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 333 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 334 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
53419c68
SH		 337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 344 if (sky2_is_copper(hw)) {
05745c4a 345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
cd28ab6a
SH		 358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
53419c68 365 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 366 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 368 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
cd28ab6a
SH		 373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 378 }
cd28ab6a 379
b89165f2
SH		 380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
ea76e635 383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 385
b89165f2
SH		 386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 401 }
b89165f2
SH		 402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 404 }
405
7800fddc 406 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
2eaba1a2 409 reg = 0;
cd28ab6a
SH		 410
411 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 412 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
709c6e7b 425
16ad91e1 426 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 432
16ad91e1 433 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 434 }
cd28ab6a
SH		 435
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
438 } else {
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
441
2eaba1a2
SH		 442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 444
445 switch (sky2->speed) {
446 case SPEED_1000:
447 ctrl |= PHY_CT_SP1000;
2eaba1a2 448 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 449 break;
450 case SPEED_100:
451 ctrl |= PHY_CT_SP100;
2eaba1a2 452 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 453 break;
454 }
455
2eaba1a2
SH		 456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
2eaba1a2 461
2eaba1a2 462
16ad91e1 463 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 464
465 /* Forward pause packets to GMAC? */
16ad91e1 466 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
468 else
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 470 }
471
2eaba1a2
SH		 472 gma_write16(hw, port, GM_GP_CTRL, reg);
473
05745c4a 474 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
476
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
479
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
482 ledover = 0;
483
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
488
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
490
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
496 break;
497
05745c4a
SH		 498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
502
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
506
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
511
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
cd28ab6a 515 case CHIP_ID_YUKON_XL:
793b883e 516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 517
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
520
521 /* set LED Function Control register */
ed6d32c7
SH		 522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 527
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 536
537 /* restore page register */
793b883e 538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 539 break;
93745494 540
ed6d32c7 541 case CHIP_ID_YUKON_EC_U:
93745494 542 case CHIP_ID_YUKON_EX:
ed4d4161 543 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
545
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
548
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
555
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
561 break;
cd28ab6a
SH		 562
563 default:
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 566
cd28ab6a 567 /* turn off the Rx LED (LED_RX) */
a84d0a3d 568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 569 }
570
0ce8b98d 571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 572 /* apply fixes in PHY AFE */
ed6d32c7
SH		 573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
574
977bdf06 575 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 578
0ce8b98d
SH		 579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
583 }
977bdf06
SH		 584
585 /* set page register to 0 */
9467a8fc 586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 594 /* no effect on Yukon-XL */
977bdf06 595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 596
977bdf06
SH		 597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 600 }
cd28ab6a 601
977bdf06
SH		 602 if (ledover)
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
604
605 }
2eaba1a2 606
d571b694 607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
610 else
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
612}
613
b96936da
SH		 614static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
616
617static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 618{
619 u32 reg1;
d3bcfbeb 620
82637e80 621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 623 reg1 &= ~phy_power[port];
d3bcfbeb 624
b96936da 625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 626 reg1 |= coma_mode[port];
627
b32f40c4 628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 631
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 636}
167f53d0 637
b96936da
SH		 638static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
639{
640 u32 reg1;
db99b988
SH		 641 u16 ctrl;
642
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
645
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
648
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
652
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
657
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
660 }
661
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
665
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 670
e484d5f5 671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 672 /* enable Power Down */
673 ctrl |= PHY_M_PC_POW_D_ENA;
674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 675
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 678 }
679
680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
681 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
682 }
b96936da
SH		 683
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
685 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 686 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 687 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 689}
690
1b537565
SH		 691/* Force a renegotiation */
692static void sky2_phy_reinit(struct sky2_port *sky2)
693{
e07b1aa8 694 spin_lock_bh(&sky2->phy_lock);
1b537565 695 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 696 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 697}
698
e3173832
SH		 699/* Put device in state to listen for Wake On Lan */
700static void sky2_wol_init(struct sky2_port *sky2)
701{
702 struct sky2_hw *hw = sky2->hw;
703 unsigned port = sky2->port;
704 enum flow_control save_mode;
705 u16 ctrl;
706 u32 reg1;
707
708 /* Bring hardware out of reset */
709 sky2_write16(hw, B0_CTST, CS_RST_CLR);
710 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
711
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
714
715 /* Force to 10/100
716 * sky2_reset will re-enable on resume
717 */
718 save_mode = sky2->flow_mode;
719 ctrl = sky2->advertising;
720
721 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
722 sky2->flow_mode = FC_NONE;
b96936da
SH		 723
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_power_up(hw, port);
726 sky2_phy_init(hw, port);
727 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 728
729 sky2->flow_mode = save_mode;
730 sky2->advertising = ctrl;
731
732 /* Set GMAC to no flow control and auto update for speed/duplex */
733 gma_write16(hw, port, GM_GP_CTRL,
734 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
735 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
736
737 /* Set WOL address */
738 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
739 sky2->netdev->dev_addr, ETH_ALEN);
740
741 /* Turn on appropriate WOL control bits */
742 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
743 ctrl = 0;
744 if (sky2->wol & WAKE_PHY)
745 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
746 else
747 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
748
749 if (sky2->wol & WAKE_MAGIC)
750 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
751 else
752 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
753
754 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
755 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
756
757 /* Turn on legacy PCI-Express PME mode */
b32f40c4 758 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 759 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 760 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 761
762 /* block receiver */
763 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
764
765}
766
69161611
SH		 767static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
768{
05745c4a
SH		 769 struct net_device *dev = hw->dev[port];
770
ed4d4161
SH		 771 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
772 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
773 hw->chip_id == CHIP_ID_YUKON_FE_P ||
774 hw->chip_id == CHIP_ID_YUKON_SUPR) {
775 /* Yukon-Extreme B0 and further Extreme devices */
776 /* enable Store & Forward mode for TX */
05745c4a 777
ed4d4161
SH		 778 if (dev->mtu <= ETH_DATA_LEN)
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 781
ed4d4161
SH		 782 else
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
784 TX_JUMBO_ENA| TX_STFW_ENA);
785 } else {
786 if (dev->mtu <= ETH_DATA_LEN)
787 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
788 else {
789 /* set Tx GMAC FIFO Almost Empty Threshold */
790 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
791 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 792
ed4d4161
SH		 793 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
794
795 /* Can't do offload because of lack of store/forward */
796 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
797 }
69161611
SH		 798 }
799}
800
cd28ab6a
SH		 801static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
802{
803 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
804 u16 reg;
25cccecc 805 u32 rx_reg;
cd28ab6a
SH		 806 int i;
807 const u8 *addr = hw->dev[port]->dev_addr;
808
f350339c
SH		 809 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
810 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 811
812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
813
793b883e 814 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 815 /* WA DEV_472 -- looks like crossed wires on port 2 */
816 /* clear GMAC 1 Control reset */
817 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
818 do {
819 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
820 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
821 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
822 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
823 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
824 }
825
793b883e 826 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 827
2eaba1a2
SH		 828 /* Enable Transmit FIFO Underrun */
829 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
830
e07b1aa8 831 spin_lock_bh(&sky2->phy_lock);
b96936da 832 sky2_phy_power_up(hw, port);
cd28ab6a 833 sky2_phy_init(hw, port);
e07b1aa8 834 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 835
836 /* MIB clear */
837 reg = gma_read16(hw, port, GM_PHY_ADDR);
838 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
839
43f2f104
SH		 840 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
841 gma_read16(hw, port, i);
cd28ab6a
SH		 842 gma_write16(hw, port, GM_PHY_ADDR, reg);
843
844 /* transmit control */
845 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
846
847 /* receive control reg: unicast + multicast + no FCS */
848 gma_write16(hw, port, GM_RX_CTRL,
793b883e 849 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 850
851 /* transmit flow control */
852 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
853
854 /* transmit parameter */
855 gma_write16(hw, port, GM_TX_PARAM,
856 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
857 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
858 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
859 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
860
861 /* serial mode register */
862 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 863 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 864
6b1a3aef 865 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 866 reg |= GM_SMOD_JUMBO_ENA;
867
868 gma_write16(hw, port, GM_SERIAL_MODE, reg);
869
cd28ab6a
SH		 870 /* virtual address for data */
871 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
872
793b883e
SH		 873 /* physical address: used for pause frames */
874 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
875
876 /* ignore counter overflows */
cd28ab6a
SH		 877 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
878 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
879 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
880
881 /* Configure Rx MAC FIFO */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 883 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 884 if (hw->chip_id == CHIP_ID_YUKON_EX ||
885 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 886 rx_reg |= GMF_RX_OVER_ON;
69161611 887
25cccecc 888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 889
798fdd07
SH		 890 if (hw->chip_id == CHIP_ID_YUKON_XL) {
891 /* Hardware errata - clear flush mask */
892 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
893 } else {
894 /* Flush Rx MAC FIFO on any flow control or error */
895 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
896 }
cd28ab6a 897
8df9a876 898 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 899 reg = RX_GMF_FL_THR_DEF + 1;
900 /* Another magic mystery workaround from sk98lin */
901 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
902 hw->chip_rev == CHIP_REV_YU_FE2_A0)
903 reg = 0x178;
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 905
906 /* Configure Tx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
908 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 909
e0c28116 910 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 911 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 912 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 913 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 914
69161611 915 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 916 }
917
e970d1f8
SH		 918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
920 /* disable dynamic watermark */
921 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
922 reg &= ~TX_DYN_WM_ENA;
923 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
924 }
cd28ab6a
SH		 925}
926
67712901
SH		 927/* Assign Ram Buffer allocation to queue */
928static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 929{
67712901
SH		 930 u32 end;
931
932 /* convert from K bytes to qwords used for hw register */
933 start *= 1024/8;
934 space *= 1024/8;
935 end = start + space - 1;
793b883e 936
cd28ab6a
SH		 937 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
938 sky2_write32(hw, RB_ADDR(q, RB_START), start);
939 sky2_write32(hw, RB_ADDR(q, RB_END), end);
940 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
941 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
942
943 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 944 u32 tp = space - space/4;
793b883e 945
1c28f6ba
SH		 946 /* On receive queue's set the thresholds
947 * give receiver priority when > 3/4 full
948 * send pause when down to 2K
949 */
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 952
1c28f6ba
SH		 953 tp = space - 2048/8;
954 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
955 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 956 } else {
957 /* Enable store & forward on Tx queue's because
958 * Tx FIFO is only 1K on Yukon
959 */
960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
961 }
962
963 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 964 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 965}
966
cd28ab6a 967/* Setup Bus Memory Interface */
af4ed7e6 968static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 969{
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
971 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
972 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 973 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 974}
975
cd28ab6a
SH		 976/* Setup prefetch unit registers. This is the interface between
977 * hardware and driver list elements
978 */
8cc048e3 979static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 980 u64 addr, u32 last)
981{
cd28ab6a
SH		 982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
984 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
986 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
987 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 988
989 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 990}
991
793b883e
SH		 992static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
993{
994 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
995
cb5d9547 996 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 997 le->ctrl = 0;
793b883e
SH		 998 return le;
999}
cd28ab6a 1000
88f5f0ca
SH		 1001static void tx_init(struct sky2_port *sky2)
1002{
1003 struct sky2_tx_le *le;
1004
1005 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->tx_tcpsum = 0;
1007 sky2->tx_last_mss = 0;
1008
1009 le = get_tx_le(sky2);
1010 le->addr = 0;
1011 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 1012}
1013
291ea614
SH		 1014static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1015 struct sky2_tx_le *le)
1016{
1017 return sky2->tx_ring + (le - sky2->tx_le);
1018}
1019
290d4de5
SH		 1020/* Update chip's next pointer */
1021static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1022{
50432cb5 1023 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1024 wmb();
50432cb5
SH		 1025 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1026
1027 /* Synchronize I/O on since next processor may write to tail */
1028 mmiowb();
cd28ab6a
SH		 1029}
1030
793b883e 1031
cd28ab6a
SH		 1032static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1033{
1034 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1035 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1036 le->ctrl = 0;
cd28ab6a
SH		 1037 return le;
1038}
1039
14d0263f
SH		 1040/* Build description to hardware for one receive segment */
1041static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1042 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1043{
1044 struct sky2_rx_le *le;
1045
86c6887e 1046 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1047 le = sky2_next_rx(sky2);
86c6887e 1048 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1049 le->opcode = OP_ADDR64 | HW_OWNER;
1050 }
793b883e 1051
cd28ab6a 1052 le = sky2_next_rx(sky2);
734d1868
SH		 1053 le->addr = cpu_to_le32((u32) map);
1054 le->length = cpu_to_le16(len);
14d0263f 1055 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1056}
1057
14d0263f
SH		 1058/* Build description to hardware for one possibly fragmented skb */
1059static void sky2_rx_submit(struct sky2_port *sky2,
1060 const struct rx_ring_info *re)
1061{
1062 int i;
1063
1064 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1065
1066 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1067 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1068}
1069
1070
1071static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1072 unsigned size)
1073{
1074 struct sk_buff *skb = re->skb;
1075 int i;
1076
1077 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1078 pci_unmap_len_set(re, data_size, size);
1079
1080 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1081 re->frag_addr[i] = pci_map_page(pdev,
1082 skb_shinfo(skb)->frags[i].page,
1083 skb_shinfo(skb)->frags[i].page_offset,
1084 skb_shinfo(skb)->frags[i].size,
1085 PCI_DMA_FROMDEVICE);
1086}
1087
1088static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1089{
1090 struct sk_buff *skb = re->skb;
1091 int i;
1092
1093 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1094 PCI_DMA_FROMDEVICE);
1095
1096 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1097 pci_unmap_page(pdev, re->frag_addr[i],
1098 skb_shinfo(skb)->frags[i].size,
1099 PCI_DMA_FROMDEVICE);
1100}
793b883e 1101
cd28ab6a
SH		 1102/* Tell chip where to start receive checksum.
1103 * Actually has two checksums, but set both same to avoid possible byte
1104 * order problems.
1105 */
793b883e 1106static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1107{
ea76e635 1108 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1109
ea76e635
SH		 1110 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1111 le->ctrl = 0;
1112 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1113
ea76e635
SH		 1114 sky2_write32(sky2->hw,
1115 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1116 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1117}
1118
6b1a3aef
SH		 1119/*
1120 * The RX Stop command will not work for Yukon-2 if the BMU does not
1121 * reach the end of packet and since we can't make sure that we have
1122 * incoming data, we must reset the BMU while it is not doing a DMA
1123 * transfer. Since it is possible that the RX path is still active,
1124 * the RX RAM buffer will be stopped first, so any possible incoming
1125 * data will not trigger a DMA. After the RAM buffer is stopped, the
1126 * BMU is polled until any DMA in progress is ended and only then it
1127 * will be reset.
1128 */
1129static void sky2_rx_stop(struct sky2_port *sky2)
1130{
1131 struct sky2_hw *hw = sky2->hw;
1132 unsigned rxq = rxqaddr[sky2->port];
1133 int i;
1134
1135 /* disable the RAM Buffer receive queue */
1136 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1137
1138 for (i = 0; i < 0xffff; i++)
1139 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1140 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1141 goto stopped;
1142
1143 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1144 sky2->netdev->name);
1145stopped:
1146 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1147
1148 /* reset the Rx prefetch unit */
1149 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1150 mmiowb();
6b1a3aef 1151}
793b883e 1152
d571b694 1153/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1154static void sky2_rx_clean(struct sky2_port *sky2)
1155{
1156 unsigned i;
1157
1158 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1159 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1160 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1161
1162 if (re->skb) {
14d0263f 1163 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1164 kfree_skb(re->skb);
1165 re->skb = NULL;
1166 }
1167 }
1168}
1169
ef743d33
SH		 1170/* Basic MII support */
1171static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1172{
1173 struct mii_ioctl_data *data = if_mii(ifr);
1174 struct sky2_port *sky2 = netdev_priv(dev);
1175 struct sky2_hw *hw = sky2->hw;
1176 int err = -EOPNOTSUPP;
1177
1178 if (!netif_running(dev))
1179 return -ENODEV; /* Phy still in reset */
1180
d89e1343 1181 switch (cmd) {
ef743d33
SH		 1182 case SIOCGMIIPHY:
1183 data->phy_id = PHY_ADDR_MARV;
1184
1185 /* fallthru */
1186 case SIOCGMIIREG: {
1187 u16 val = 0;
91c86df5 1188
e07b1aa8 1189 spin_lock_bh(&sky2->phy_lock);
ef743d33 1190 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1191 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1192
ef743d33
SH		 1193 data->val_out = val;
1194 break;
1195 }
1196
1197 case SIOCSMIIREG:
1198 if (!capable(CAP_NET_ADMIN))
1199 return -EPERM;
1200
e07b1aa8 1201 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1202 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1203 data->val_in);
e07b1aa8 1204 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1205 break;
1206 }
1207 return err;
1208}
1209
d1f13708 1210#ifdef SKY2_VLAN_TAG_USED
d494eacd 1211static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1212{
d494eacd 1213 if (onoff) {
3d4e66f5
SH		 1214 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1215 RX_VLAN_STRIP_ON);
1216 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1217 TX_VLAN_TAG_ON);
1218 } else {
1219 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1220 RX_VLAN_STRIP_OFF);
1221 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1222 TX_VLAN_TAG_OFF);
1223 }
d494eacd
SH		 1224}
1225
1226static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1227{
1228 struct sky2_port *sky2 = netdev_priv(dev);
1229 struct sky2_hw *hw = sky2->hw;
1230 u16 port = sky2->port;
1231
1232 netif_tx_lock_bh(dev);
1233 napi_disable(&hw->napi);
1234
1235 sky2->vlgrp = grp;
1236 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1237
d1d08d12 1238 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1239 napi_enable(&hw->napi);
2bb8c262 1240 netif_tx_unlock_bh(dev);
d1f13708
SH		 1241}
1242#endif
1243
82788c7a 1244/*
14d0263f
SH		 1245 * Allocate an skb for receiving. If the MTU is large enough
1246 * make the skb non-linear with a fragment list of pages.
82788c7a 1247 */
14d0263f 1248static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1249{
1250 struct sk_buff *skb;
14d0263f 1251 int i;
82788c7a 1252
39dbd958 1253 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1254 unsigned char *start;
1255 /*
1256 * Workaround for a bug in FIFO that cause hang
1257 * if the FIFO if the receive buffer is not 64 byte aligned.
1258 * The buffer returned from netdev_alloc_skb is
1259 * aligned except if slab debugging is enabled.
1260 */
1261 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1262 if (!skb)
1263 goto nomem;
1264 start = PTR_ALIGN(skb->data, 8);
1265 skb_reserve(skb, start - skb->data);
1266 } else {
1267 skb = netdev_alloc_skb(sky2->netdev,
1268 sky2->rx_data_size + NET_IP_ALIGN);
1269 if (!skb)
1270 goto nomem;
1271 skb_reserve(skb, NET_IP_ALIGN);
1272 }
14d0263f
SH		 1273
1274 for (i = 0; i < sky2->rx_nfrags; i++) {
1275 struct page *page = alloc_page(GFP_ATOMIC);
1276
1277 if (!page)
1278 goto free_partial;
1279 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1280 }
1281
1282 return skb;
14d0263f
SH		 1283free_partial:
1284 kfree_skb(skb);
1285nomem:
1286 return NULL;
82788c7a
SH		 1287}
1288
55c9dd35
SH		 1289static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1290{
1291 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1292}
1293
cd28ab6a
SH		 1294/*
1295 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1296 * Normal case this ends up creating one list element for skb
1297 * in the receive ring. Worst case if using large MTU and each
1298 * allocation falls on a different 64 bit region, that results
1299 * in 6 list elements per ring entry.
1300 * One element is used for checksum enable/disable, and one
1301 * extra to avoid wrap.
cd28ab6a 1302 */
6b1a3aef 1303static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1304{
6b1a3aef 1305 struct sky2_hw *hw = sky2->hw;
14d0263f 1306 struct rx_ring_info *re;
6b1a3aef 1307 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1308 unsigned i, size, thresh;
cd28ab6a 1309
6b1a3aef 1310 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1311 sky2_qset(hw, rxq);
977bdf06 1312
c3905bc4
SH		 1313 /* On PCI express lowering the watermark gives better performance */
1314 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1315 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1316
1317 /* These chips have no ram buffer?
1318 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1319 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1320 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1321 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1322 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1323
6b1a3aef
SH		 1324 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1325
ea76e635
SH		 1326 if (!(hw->flags & SKY2_HW_NEW_LE))
1327 rx_set_checksum(sky2);
14d0263f
SH		 1328
1329 /* Space needed for frame data + headers rounded up */
f957da2a 1330 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1331
1332 /* Stopping point for hardware truncation */
1333 thresh = (size - 8) / sizeof(u32);
1334
5f06eba4 1335 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1336 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1337
5f06eba4
SH		 1338 /* Compute residue after pages */
1339 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1340
5f06eba4
SH		 1341 /* Optimize to handle small packets and headers */
1342 if (size < copybreak)
1343 size = copybreak;
1344 if (size < ETH_HLEN)
1345 size = ETH_HLEN;
14d0263f 1346
14d0263f
SH		 1347 sky2->rx_data_size = size;
1348
1349 /* Fill Rx ring */
793b883e 1350 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1351 re = sky2->rx_ring + i;
cd28ab6a 1352
14d0263f 1353 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1354 if (!re->skb)
1355 goto nomem;
1356
14d0263f
SH		 1357 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1358 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1359 }
1360
a1433ac4
SH		 1361 /*
1362 * The receiver hangs if it receives frames larger than the
1363 * packet buffer. As a workaround, truncate oversize frames, but
1364 * the register is limited to 9 bits, so if you do frames > 2052
1365 * you better get the MTU right!
1366 */
a1433ac4
SH		 1367 if (thresh > 0x1ff)
1368 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1369 else {
1370 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1371 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1372 }
1373
6b1a3aef 1374 /* Tell chip about available buffers */
55c9dd35 1375 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1376 return 0;
1377nomem:
1378 sky2_rx_clean(sky2);
1379 return -ENOMEM;
1380}
1381
1382/* Bring up network interface. */
1383static int sky2_up(struct net_device *dev)
1384{
1385 struct sky2_port *sky2 = netdev_priv(dev);
1386 struct sky2_hw *hw = sky2->hw;
1387 unsigned port = sky2->port;
e0c28116 1388 u32 imask, ramsize;
ee7abb04 1389 int cap, err = -ENOMEM;
843a46f4 1390 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1391
ee7abb04
SH		 1392 /*
1393 * On dual port PCI-X card, there is an problem where status
1394 * can be received out of order due to split transactions
843a46f4 1395 */
ee7abb04
SH		 1396 if (otherdev && netif_running(otherdev) &&
1397 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1398 u16 cmd;
1399
b32f40c4 1400 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1401 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1402 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1403
ee7abb04 1404 }
843a46f4 1405
cd28ab6a
SH		 1406 if (netif_msg_ifup(sky2))
1407 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1408
55d7b4e6
SH		 1409 netif_carrier_off(dev);
1410
cd28ab6a
SH		 1411 /* must be power of 2 */
1412 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1413 TX_RING_SIZE *
1414 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1415 &sky2->tx_le_map);
1416 if (!sky2->tx_le)
1417 goto err_out;
1418
6cdbbdf3 1419 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1420 GFP_KERNEL);
1421 if (!sky2->tx_ring)
1422 goto err_out;
88f5f0ca
SH		 1423
1424 tx_init(sky2);
cd28ab6a
SH		 1425
1426 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1427 &sky2->rx_le_map);
1428 if (!sky2->rx_le)
1429 goto err_out;
1430 memset(sky2->rx_le, 0, RX_LE_BYTES);
1431
291ea614 1432 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1433 GFP_KERNEL);
1434 if (!sky2->rx_ring)
1435 goto err_out;
1436
1437 sky2_mac_init(hw, port);
1438
e0c28116
SH		 1439 /* Register is number of 4K blocks on internal RAM buffer. */
1440 ramsize = sky2_read8(hw, B2_E_0) * 4;
1441 if (ramsize > 0) {
67712901 1442 u32 rxspace;
cd28ab6a 1443
39dbd958 1444 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1445 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1446 if (ramsize < 16)
1447 rxspace = ramsize / 2;
1448 else
1449 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1450
67712901
SH		 1451 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1452 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1453
1454 /* Make sure SyncQ is disabled */
1455 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1456 RB_RST_SET);
1457 }
793b883e 1458
af4ed7e6 1459 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1460
69161611
SH		 1461 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1462 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1463 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1464
977bdf06 1465 /* Set almost empty threshold */
c2716fb4
SH		 1466 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1467 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1468 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1469
6b1a3aef
SH		 1470 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1471 TX_RING_SIZE - 1);
cd28ab6a 1472
d494eacd
SH		 1473#ifdef SKY2_VLAN_TAG_USED
1474 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1475#endif
1476
6b1a3aef 1477 err = sky2_rx_start(sky2);
6de16237 1478 if (err)
cd28ab6a
SH		 1479 goto err_out;
1480
cd28ab6a 1481 /* Enable interrupts from phy/mac for port */
e07b1aa8 1482 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1483 imask |= portirq_msk[port];
e07b1aa8
SH		 1484 sky2_write32(hw, B0_IMSK, imask);
1485
a7bffe72 1486 sky2_set_multicast(dev);
cd28ab6a
SH		 1487 return 0;
1488
1489err_out:
1b537565 1490 if (sky2->rx_le) {
cd28ab6a
SH		 1491 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1492 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1493 sky2->rx_le = NULL;
1494 }
1495 if (sky2->tx_le) {
cd28ab6a
SH		 1496 pci_free_consistent(hw->pdev,
1497 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1498 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1499 sky2->tx_le = NULL;
1500 }
1501 kfree(sky2->tx_ring);
1502 kfree(sky2->rx_ring);
cd28ab6a 1503
1b537565
SH		 1504 sky2->tx_ring = NULL;
1505 sky2->rx_ring = NULL;
cd28ab6a
SH		 1506 return err;
1507}
1508
793b883e
SH		 1509/* Modular subtraction in ring */
1510static inline int tx_dist(unsigned tail, unsigned head)
1511{
cb5d9547 1512 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1513}
cd28ab6a 1514
793b883e
SH		 1515/* Number of list elements available for next tx */
1516static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1517{
793b883e 1518 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1519}
1520
793b883e 1521/* Estimate of number of transmit list elements required */
28bd181a 1522static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1523{
793b883e
SH		 1524 unsigned count;
1525
1526 count = sizeof(dma_addr_t) / sizeof(u32);
1527 count += skb_shinfo(skb)->nr_frags * count;
1528
89114afd 1529 if (skb_is_gso(skb))
793b883e
SH		 1530 ++count;
1531
84fa7933 1532 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1533 ++count;
1534
1535 return count;
cd28ab6a
SH		 1536}
1537
793b883e
SH		 1538/*
1539 * Put one packet in ring for transmit.
1540 * A single packet can generate multiple list elements, and
1541 * the number of ring elements will probably be less than the number
1542 * of list elements used.
1543 */
cd28ab6a
SH		 1544static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1545{
1546 struct sky2_port *sky2 = netdev_priv(dev);
1547 struct sky2_hw *hw = sky2->hw;
d1f13708 1548 struct sky2_tx_le *le = NULL;
6cdbbdf3 1549 struct tx_ring_info *re;
cd28ab6a
SH		 1550 unsigned i, len;
1551 dma_addr_t mapping;
cd28ab6a
SH		 1552 u16 mss;
1553 u8 ctrl;
1554
2bb8c262
SH		 1555 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1556 return NETDEV_TX_BUSY;
cd28ab6a 1557
793b883e 1558 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1559 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1560 dev->name, sky2->tx_prod, skb->len);
1561
cd28ab6a
SH		 1562 len = skb_headlen(skb);
1563 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1564
86c6887e
SH		 1565 /* Send high bits if needed */
1566 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1567 le = get_tx_le(sky2);
86c6887e 1568 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1569 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1570 }
cd28ab6a
SH		 1571
1572 /* Check for TCP Segmentation Offload */
7967168c 1573 mss = skb_shinfo(skb)->gso_size;
793b883e 1574 if (mss != 0) {
ea76e635
SH		 1575
1576 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1577 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1578
1579 if (mss != sky2->tx_last_mss) {
1580 le = get_tx_le(sky2);
1581 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1582
1583 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1584 le->opcode = OP_MSS | HW_OWNER;
1585 else
1586 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1587 sky2->tx_last_mss = mss;
1588 }
cd28ab6a
SH		 1589 }
1590
cd28ab6a 1591 ctrl = 0;
d1f13708
SH		 1592#ifdef SKY2_VLAN_TAG_USED
1593 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1594 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1595 if (!le) {
1596 le = get_tx_le(sky2);
f65b138c 1597 le->addr = 0;
d1f13708 1598 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1599 } else
1600 le->opcode |= OP_VLAN;
1601 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1602 ctrl |= INS_VLAN;
1603 }
1604#endif
1605
1606 /* Handle TCP checksum offload */
84fa7933 1607 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1608 /* On Yukon EX (some versions) encoding change. */
ea76e635 1609 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1610 ctrl |= CALSUM; /* auto checksum */
1611 else {
1612 const unsigned offset = skb_transport_offset(skb);
1613 u32 tcpsum;
1614
1615 tcpsum = offset << 16; /* sum start */
1616 tcpsum |= offset + skb->csum_offset; /* sum write */
1617
1618 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1619 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1620 ctrl |= UDPTCP;
1621
1622 if (tcpsum != sky2->tx_tcpsum) {
1623 sky2->tx_tcpsum = tcpsum;
1624
1625 le = get_tx_le(sky2);
1626 le->addr = cpu_to_le32(tcpsum);
1627 le->length = 0; /* initial checksum value */
1628 le->ctrl = 1; /* one packet */
1629 le->opcode = OP_TCPLISW | HW_OWNER;
1630 }
1d179332 1631 }
cd28ab6a
SH		 1632 }
1633
1634 le = get_tx_le(sky2);
f65b138c 1635 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1636 le->length = cpu_to_le16(len);
1637 le->ctrl = ctrl;
793b883e 1638 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1639
291ea614 1640 re = tx_le_re(sky2, le);
cd28ab6a 1641 re->skb = skb;
6cdbbdf3 1642 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1643 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1644
1645 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1646 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1647
1648 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1649 frag->size, PCI_DMA_TODEVICE);
86c6887e
SH		 1650
1651 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1652 le = get_tx_le(sky2);
86c6887e 1653 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1654 le->ctrl = 0;
1655 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1656 }
1657
1658 le = get_tx_le(sky2);
f65b138c 1659 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1660 le->length = cpu_to_le16(frag->size);
1661 le->ctrl = ctrl;
793b883e 1662 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1663
291ea614
SH		 1664 re = tx_le_re(sky2, le);
1665 re->skb = skb;
1666 pci_unmap_addr_set(re, mapaddr, mapping);
1667 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1668 }
6cdbbdf3 1669
cd28ab6a
SH		 1670 le->ctrl |= EOP;
1671
97bda706
SH		 1672 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1673 netif_stop_queue(dev);
b19666d9 1674
290d4de5 1675 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1676
cd28ab6a
SH		 1677 dev->trans_start = jiffies;
1678 return NETDEV_TX_OK;
1679}
1680
cd28ab6a 1681/*
793b883e
SH		 1682 * Free ring elements from starting at tx_cons until "done"
1683 *
1684 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1685 * buffers so make sure not to free skb to early.
cd28ab6a 1686 */
d11c13e7 1687static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1688{
d11c13e7 1689 struct net_device *dev = sky2->netdev;
af2a58ac 1690 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1691 unsigned idx;
cd28ab6a 1692
0e3ff6aa 1693 BUG_ON(done >= TX_RING_SIZE);
2224795d 1694
291ea614
SH		 1695 for (idx = sky2->tx_cons; idx != done;
1696 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1697 struct sky2_tx_le *le = sky2->tx_le + idx;
1698 struct tx_ring_info *re = sky2->tx_ring + idx;
1699
1700 switch(le->opcode & ~HW_OWNER) {
1701 case OP_LARGESEND:
1702 case OP_PACKET:
1703 pci_unmap_single(pdev,
1704 pci_unmap_addr(re, mapaddr),
1705 pci_unmap_len(re, maplen),
1706 PCI_DMA_TODEVICE);
af2a58ac 1707 break;
291ea614
SH		 1708 case OP_BUFFER:
1709 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1710 pci_unmap_len(re, maplen),
734d1868 1711 PCI_DMA_TODEVICE);
291ea614
SH		 1712 break;
1713 }
1714
1715 if (le->ctrl & EOP) {
1716 if (unlikely(netif_msg_tx_done(sky2)))
1717 printk(KERN_DEBUG "%s: tx done %u\n",
1718 dev->name, idx);
3cf26753 1719
7138a0f5
SH		 1720 dev->stats.tx_packets++;
1721 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1722
794b2bd2 1723 dev_kfree_skb_any(re->skb);
3cf26753 1724 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1725 }
793b883e 1726 }
793b883e 1727
291ea614 1728 sky2->tx_cons = idx;
50432cb5
SH		 1729 smp_mb();
1730
22e11703 1731 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1732 netif_wake_queue(dev);
cd28ab6a
SH		 1733}
1734
1735/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1736static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1737{
2bb8c262
SH		 1738 struct sky2_port *sky2 = netdev_priv(dev);
1739
1740 netif_tx_lock_bh(dev);
d11c13e7 1741 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1742 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1743}
1744
1745/* Network shutdown */
1746static int sky2_down(struct net_device *dev)
1747{
1748 struct sky2_port *sky2 = netdev_priv(dev);
1749 struct sky2_hw *hw = sky2->hw;
1750 unsigned port = sky2->port;
1751 u16 ctrl;
e07b1aa8 1752 u32 imask;
cd28ab6a 1753
1b537565
SH		 1754 /* Never really got started! */
1755 if (!sky2->tx_le)
1756 return 0;
1757
cd28ab6a
SH		 1758 if (netif_msg_ifdown(sky2))
1759 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1760
ebc646f6
SH		 1761 /* Disable port IRQ */
1762 imask = sky2_read32(hw, B0_IMSK);
1763 imask &= ~portirq_msk[port];
1764 sky2_write32(hw, B0_IMSK, imask);
1765
6de16237
SH		 1766 synchronize_irq(hw->pdev->irq);
1767
d3bcfbeb 1768 sky2_gmac_reset(hw, port);
793b883e 1769
cd28ab6a
SH		 1770 /* Stop transmitter */
1771 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1772 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1773
1774 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1775 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1776
1777 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1778 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1779 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1780
6de16237
SH		 1781 /* Make sure no packets are pending */
1782 napi_synchronize(&hw->napi);
1783
cd28ab6a
SH		 1784 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1785
1786 /* Workaround shared GMAC reset */
793b883e
SH		 1787 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1788 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1789 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1790
1791 /* Disable Force Sync bit and Enable Alloc bit */
1792 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1793 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1794
1795 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1796 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1797 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1798
1799 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1800 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1801 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1802
1803 /* Reset the Tx prefetch units */
1804 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1805 PREF_UNIT_RST_SET);
1806
1807 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1808
6b1a3aef 1809 sky2_rx_stop(sky2);
cd28ab6a
SH		 1810
1811 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1812 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1813
b96936da 1814 sky2_phy_power_down(hw, port);
d3bcfbeb 1815
d571b694 1816 /* turn off LED's */
cd28ab6a
SH		 1817 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1818
2bb8c262 1819 sky2_tx_clean(dev);
cd28ab6a
SH		 1820 sky2_rx_clean(sky2);
1821
1822 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1823 sky2->rx_le, sky2->rx_le_map);
1824 kfree(sky2->rx_ring);
1825
1826 pci_free_consistent(hw->pdev,
1827 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1828 sky2->tx_le, sky2->tx_le_map);
1829 kfree(sky2->tx_ring);
1830
1b537565
SH		 1831 sky2->tx_le = NULL;
1832 sky2->rx_le = NULL;
1833
1834 sky2->rx_ring = NULL;
1835 sky2->tx_ring = NULL;
1836
cd28ab6a
SH		 1837 return 0;
1838}
1839
1840static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1841{
ea76e635 1842 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1843 return SPEED_1000;
1844
05745c4a
SH		 1845 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1846 if (aux & PHY_M_PS_SPEED_100)
1847 return SPEED_100;
1848 else
1849 return SPEED_10;
1850 }
cd28ab6a
SH		 1851
1852 switch (aux & PHY_M_PS_SPEED_MSK) {
1853 case PHY_M_PS_SPEED_1000:
1854 return SPEED_1000;
1855 case PHY_M_PS_SPEED_100:
1856 return SPEED_100;
1857 default:
1858 return SPEED_10;
1859 }
1860}
1861
1862static void sky2_link_up(struct sky2_port *sky2)
1863{
1864 struct sky2_hw *hw = sky2->hw;
1865 unsigned port = sky2->port;
1866 u16 reg;
16ad91e1
SH		 1867 static const char *fc_name[] = {
1868 [FC_NONE] = "none",
1869 [FC_TX] = "tx",
1870 [FC_RX] = "rx",
1871 [FC_BOTH] = "both",
1872 };
cd28ab6a 1873
cd28ab6a 1874 /* enable Rx/Tx */
2eaba1a2 1875 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1876 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1877 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1878
1879 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1880
1881 netif_carrier_on(sky2->netdev);
cd28ab6a 1882
75e80683 1883 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1884
cd28ab6a 1885 /* Turn on link LED */
793b883e 1886 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1887 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1888
1889 if (netif_msg_link(sky2))
1890 printk(KERN_INFO PFX
d571b694 1891 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1892 sky2->netdev->name, sky2->speed,
1893 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1894 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1895}
1896
1897static void sky2_link_down(struct sky2_port *sky2)
1898{
1899 struct sky2_hw *hw = sky2->hw;
1900 unsigned port = sky2->port;
1901 u16 reg;
1902
1903 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1904
1905 reg = gma_read16(hw, port, GM_GP_CTRL);
1906 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1907 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1908
cd28ab6a 1909 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1910
1911 /* Turn on link LED */
1912 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1913
1914 if (netif_msg_link(sky2))
1915 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1916
cd28ab6a
SH		 1917 sky2_phy_init(hw, port);
1918}
1919
16ad91e1
SH		 1920static enum flow_control sky2_flow(int rx, int tx)
1921{
1922 if (rx)
1923 return tx ? FC_BOTH : FC_RX;
1924 else
1925 return tx ? FC_TX : FC_NONE;
1926}
1927
793b883e
SH		 1928static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1929{
1930 struct sky2_hw *hw = sky2->hw;
1931 unsigned port = sky2->port;
da4c1ff4 1932 u16 advert, lpa;
793b883e 1933
da4c1ff4 1934 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1935 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1936 if (lpa & PHY_M_AN_RF) {
1937 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1938 return -1;
1939 }
1940
793b883e
SH		 1941 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1942 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1943 sky2->netdev->name);
1944 return -1;
1945 }
1946
793b883e 1947 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1948 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1949
da4c1ff4
SH		 1950 /* Since the pause result bits seem to in different positions on
1951 * different chips. look at registers.
1952 */
ea76e635 1953 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1954 /* Shift for bits in fiber PHY */
1955 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1956 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1957
1958 if (advert & ADVERTISE_1000XPAUSE)
1959 advert |= ADVERTISE_PAUSE_CAP;
1960 if (advert & ADVERTISE_1000XPSE_ASYM)
1961 advert |= ADVERTISE_PAUSE_ASYM;
1962 if (lpa & LPA_1000XPAUSE)
1963 lpa |= LPA_PAUSE_CAP;
1964 if (lpa & LPA_1000XPAUSE_ASYM)
1965 lpa |= LPA_PAUSE_ASYM;
1966 }
793b883e 1967
da4c1ff4
SH		 1968 sky2->flow_status = FC_NONE;
1969 if (advert & ADVERTISE_PAUSE_CAP) {
1970 if (lpa & LPA_PAUSE_CAP)
1971 sky2->flow_status = FC_BOTH;
1972 else if (advert & ADVERTISE_PAUSE_ASYM)
1973 sky2->flow_status = FC_RX;
1974 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1975 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1976 sky2->flow_status = FC_TX;
1977 }
793b883e 1978
16ad91e1 1979 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1980 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1981 sky2->flow_status = FC_NONE;
2eaba1a2 1982
da4c1ff4 1983 if (sky2->flow_status & FC_TX)
793b883e
SH		 1984 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1985 else
1986 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1987
1988 return 0;
1989}
cd28ab6a 1990
e07b1aa8
SH		 1991/* Interrupt from PHY */
1992static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1993{
e07b1aa8
SH		 1994 struct net_device *dev = hw->dev[port];
1995 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1996 u16 istatus, phystat;
1997
ebc646f6
SH		 1998 if (!netif_running(dev))
1999 return;
2000
e07b1aa8
SH		 2001 spin_lock(&sky2->phy_lock);
2002 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2003 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2004
cd28ab6a
SH		 2005 if (netif_msg_intr(sky2))
2006 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2007 sky2->netdev->name, istatus, phystat);
2008
2eaba1a2 2009 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 2010 if (sky2_autoneg_done(sky2, phystat) == 0)
2011 sky2_link_up(sky2);
2012 goto out;
2013 }
cd28ab6a 2014
793b883e
SH		 2015 if (istatus & PHY_M_IS_LSP_CHANGE)
2016 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2017
793b883e
SH		 2018 if (istatus & PHY_M_IS_DUP_CHANGE)
2019 sky2->duplex =
2020 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2021
793b883e
SH		 2022 if (istatus & PHY_M_IS_LST_CHANGE) {
2023 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2024 sky2_link_up(sky2);
793b883e
SH		 2025 else
2026 sky2_link_down(sky2);
cd28ab6a 2027 }
793b883e 2028out:
e07b1aa8 2029 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2030}
2031
62335ab0 2032/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2033 * and tx queue is full (stopped).
2034 */
cd28ab6a
SH		 2035static void sky2_tx_timeout(struct net_device *dev)
2036{
2037 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2038 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2039
2040 if (netif_msg_timer(sky2))
2041 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2042
8f24664d 2043 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2044 dev->name, sky2->tx_cons, sky2->tx_prod,
2045 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2046 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2047
81906791
SH		 2048 /* can't restart safely under softirq */
2049 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2050}
2051
2052static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2053{
6b1a3aef
SH		 2054 struct sky2_port *sky2 = netdev_priv(dev);
2055 struct sky2_hw *hw = sky2->hw;
b628ed98 2056 unsigned port = sky2->port;
6b1a3aef
SH		 2057 int err;
2058 u16 ctl, mode;
e07b1aa8 2059 u32 imask;
cd28ab6a
SH		 2060
2061 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2062 return -EINVAL;
2063
05745c4a
SH		 2064 if (new_mtu > ETH_DATA_LEN &&
2065 (hw->chip_id == CHIP_ID_YUKON_FE ||
2066 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2067 return -EINVAL;
2068
6b1a3aef
SH		 2069 if (!netif_running(dev)) {
2070 dev->mtu = new_mtu;
2071 return 0;
2072 }
2073
e07b1aa8 2074 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2075 sky2_write32(hw, B0_IMSK, 0);
2076
018d1c66
SH		 2077 dev->trans_start = jiffies; /* prevent tx timeout */
2078 netif_stop_queue(dev);
bea3348e 2079 napi_disable(&hw->napi);
018d1c66 2080
e07b1aa8
SH		 2081 synchronize_irq(hw->pdev->irq);
2082
39dbd958 2083 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2084 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2085
2086 ctl = gma_read16(hw, port, GM_GP_CTRL);
2087 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2088 sky2_rx_stop(sky2);
2089 sky2_rx_clean(sky2);
cd28ab6a
SH		 2090
2091 dev->mtu = new_mtu;
14d0263f 2092
6b1a3aef
SH		 2093 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2094 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2095
2096 if (dev->mtu > ETH_DATA_LEN)
2097 mode |= GM_SMOD_JUMBO_ENA;
2098
b628ed98 2099 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2100
b628ed98 2101 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2102
6b1a3aef 2103 err = sky2_rx_start(sky2);
e07b1aa8 2104 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2105
d1d08d12 2106 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2107 napi_enable(&hw->napi);
2108
1b537565
SH		 2109 if (err)
2110 dev_close(dev);
2111 else {
b628ed98 2112 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2113
1b537565
SH		 2114 netif_wake_queue(dev);
2115 }
2116
cd28ab6a
SH		 2117 return err;
2118}
2119
14d0263f
SH		 2120/* For small just reuse existing skb for next receive */
2121static struct sk_buff *receive_copy(struct sky2_port *sky2,
2122 const struct rx_ring_info *re,
2123 unsigned length)
2124{
2125 struct sk_buff *skb;
2126
2127 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2128 if (likely(skb)) {
2129 skb_reserve(skb, 2);
2130 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2131 length, PCI_DMA_FROMDEVICE);
d626f62b 2132 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2133 skb->ip_summed = re->skb->ip_summed;
2134 skb->csum = re->skb->csum;
2135 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2136 length, PCI_DMA_FROMDEVICE);
2137 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2138 skb_put(skb, length);
14d0263f
SH		 2139 }
2140 return skb;
2141}
2142
2143/* Adjust length of skb with fragments to match received data */
2144static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2145 unsigned int length)
2146{
2147 int i, num_frags;
2148 unsigned int size;
2149
2150 /* put header into skb */
2151 size = min(length, hdr_space);
2152 skb->tail += size;
2153 skb->len += size;
2154 length -= size;
2155
2156 num_frags = skb_shinfo(skb)->nr_frags;
2157 for (i = 0; i < num_frags; i++) {
2158 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2159
2160 if (length == 0) {
2161 /* don't need this page */
2162 __free_page(frag->page);
2163 --skb_shinfo(skb)->nr_frags;
2164 } else {
2165 size = min(length, (unsigned) PAGE_SIZE);
2166
2167 frag->size = size;
2168 skb->data_len += size;
2169 skb->truesize += size;
2170 skb->len += size;
2171 length -= size;
2172 }
2173 }
2174}
2175
2176/* Normal packet - take skb from ring element and put in a new one */
2177static struct sk_buff *receive_new(struct sky2_port *sky2,
2178 struct rx_ring_info *re,
2179 unsigned int length)
2180{
2181 struct sk_buff *skb, *nskb;
2182 unsigned hdr_space = sky2->rx_data_size;
2183
14d0263f
SH		 2184 /* Don't be tricky about reusing pages (yet) */
2185 nskb = sky2_rx_alloc(sky2);
2186 if (unlikely(!nskb))
2187 return NULL;
2188
2189 skb = re->skb;
2190 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2191
2192 prefetch(skb->data);
2193 re->skb = nskb;
2194 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2195
2196 if (skb_shinfo(skb)->nr_frags)
2197 skb_put_frags(skb, hdr_space, length);
2198 else
489b10c1 2199 skb_put(skb, length);
14d0263f
SH		 2200 return skb;
2201}
2202
cd28ab6a
SH		 2203/*
2204 * Receive one packet.
d571b694 2205 * For larger packets, get new buffer.
cd28ab6a 2206 */
497d7c86 2207static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2208 u16 length, u32 status)
2209{
497d7c86 2210 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2211 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2212 struct sk_buff *skb = NULL;
d6532232
SH		 2213 u16 count = (status & GMR_FS_LEN) >> 16;
2214
2215#ifdef SKY2_VLAN_TAG_USED
2216 /* Account for vlan tag */
2217 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2218 count -= VLAN_HLEN;
2219#endif
cd28ab6a
SH		 2220
2221 if (unlikely(netif_msg_rx_status(sky2)))
2222 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2223 dev->name, sky2->rx_next, status, length);
cd28ab6a 2224
793b883e 2225 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2226 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2227
3b12e014
SH		 2228 /* This chip has hardware problems that generates bogus status.
2229 * So do only marginal checking and expect higher level protocols
2230 * to handle crap frames.
2231 */
2232 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2233 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2234 length != count)
2235 goto okay;
2236
42eeea01 2237 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2238 goto error;
2239
42eeea01
SH		 2240 if (!(status & GMR_FS_RX_OK))
2241 goto resubmit;
2242
d6532232
SH		 2243 /* if length reported by DMA does not match PHY, packet was truncated */
2244 if (length != count)
3b12e014 2245 goto len_error;
71749531 2246
3b12e014 2247okay:
14d0263f
SH		 2248 if (length < copybreak)
2249 skb = receive_copy(sky2, re, length);
2250 else
2251 skb = receive_new(sky2, re, length);
793b883e 2252resubmit:
14d0263f 2253 sky2_rx_submit(sky2, re);
79e57d32 2254
cd28ab6a
SH		 2255 return skb;
2256
3b12e014 2257len_error:
71749531
SH		 2258 /* Truncation of overlength packets
2259 causes PHY length to not match MAC length */
7138a0f5 2260 ++dev->stats.rx_length_errors;
d6532232 2261 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2262 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2263 dev->name, status, length);
d6532232 2264 goto resubmit;
71749531 2265
cd28ab6a 2266error:
7138a0f5 2267 ++dev->stats.rx_errors;
b6d77734 2268 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2269 dev->stats.rx_over_errors++;
b6d77734
SH		 2270 goto resubmit;
2271 }
6e15b712 2272
3be92a70 2273 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2274 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2275 dev->name, status, length);
793b883e
SH		 2276
2277 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2278 dev->stats.rx_length_errors++;
cd28ab6a 2279 if (status & GMR_FS_FRAGMENT)
7138a0f5 2280 dev->stats.rx_frame_errors++;
cd28ab6a 2281 if (status & GMR_FS_CRC_ERR)
7138a0f5 2282 dev->stats.rx_crc_errors++;
79e57d32 2283
793b883e 2284 goto resubmit;
cd28ab6a
SH		 2285}
2286
e07b1aa8
SH		 2287/* Transmit complete */
2288static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2289{
e07b1aa8 2290 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2291
e07b1aa8 2292 if (netif_running(dev)) {
2bb8c262 2293 netif_tx_lock(dev);
e07b1aa8 2294 sky2_tx_complete(sky2, last);
2bb8c262 2295 netif_tx_unlock(dev);
2224795d 2296 }
cd28ab6a
SH		 2297}
2298
e07b1aa8 2299/* Process status response ring */
26691830 2300static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2301{
e07b1aa8 2302 int work_done = 0;
55c9dd35 2303 unsigned rx[2] = { 0, 0 };
a8fd6266 2304
af2a58ac 2305 rmb();
26691830 2306 do {
55c9dd35 2307 struct sky2_port *sky2;
13210ce5 2308 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2309 unsigned port;
13210ce5 2310 struct net_device *dev;
cd28ab6a 2311 struct sk_buff *skb;
cd28ab6a
SH		 2312 u32 status;
2313 u16 length;
ab5adecb
SH		 2314 u8 opcode = le->opcode;
2315
2316 if (!(opcode & HW_OWNER))
2317 break;
cd28ab6a 2318
cb5d9547 2319 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2320
ab5adecb 2321 port = le->css & CSS_LINK_BIT;
69161611 2322 dev = hw->dev[port];
13210ce5 2323 sky2 = netdev_priv(dev);
f65b138c
SH		 2324 length = le16_to_cpu(le->length);
2325 status = le32_to_cpu(le->status);
cd28ab6a 2326
ab5adecb
SH		 2327 le->opcode = 0;
2328 switch (opcode & ~HW_OWNER) {
cd28ab6a 2329 case OP_RXSTAT:
55c9dd35 2330 ++rx[port];
497d7c86 2331 skb = sky2_receive(dev, length, status);
3225b919 2332 if (unlikely(!skb)) {
7138a0f5 2333 dev->stats.rx_dropped++;
55c9dd35 2334 break;
3225b919 2335 }
13210ce5 2336
69161611 2337 /* This chip reports checksum status differently */
05745c4a 2338 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2339 if (sky2->rx_csum &&
2340 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2341 (le->css & CSS_TCPUDPCSOK))
2342 skb->ip_summed = CHECKSUM_UNNECESSARY;
2343 else
2344 skb->ip_summed = CHECKSUM_NONE;
2345 }
2346
13210ce5 2347 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2348 dev->stats.rx_packets++;
2349 dev->stats.rx_bytes += skb->len;
13210ce5
SH		 2350 dev->last_rx = jiffies;
2351
d1f13708
SH		 2352#ifdef SKY2_VLAN_TAG_USED
2353 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2354 vlan_hwaccel_receive_skb(skb,
2355 sky2->vlgrp,
2356 be16_to_cpu(sky2->rx_tag));
2357 } else
2358#endif
cd28ab6a 2359 netif_receive_skb(skb);
13210ce5 2360
22e11703 2361 /* Stop after net poll weight */
13210ce5
SH		 2362 if (++work_done >= to_do)
2363 goto exit_loop;
cd28ab6a
SH		 2364 break;
2365
d1f13708
SH		 2366#ifdef SKY2_VLAN_TAG_USED
2367 case OP_RXVLAN:
2368 sky2->rx_tag = length;
2369 break;
2370
2371 case OP_RXCHKSVLAN:
2372 sky2->rx_tag = length;
2373 /* fall through */
2374#endif
cd28ab6a 2375 case OP_RXCHKS:
87418307
SH		 2376 if (!sky2->rx_csum)
2377 break;
2378
05745c4a
SH		 2379 /* If this happens then driver assuming wrong format */
2380 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2381 if (net_ratelimit())
2382 printk(KERN_NOTICE "%s: unexpected"
2383 " checksum status\n",
2384 dev->name);
69161611 2385 break;
05745c4a 2386 }
69161611 2387
87418307
SH		 2388 /* Both checksum counters are programmed to start at
2389 * the same offset, so unless there is a problem they
2390 * should match. This failure is an early indication that
2391 * hardware receive checksumming won't work.
2392 */
2393 if (likely(status >> 16 == (status & 0xffff))) {
2394 skb = sky2->rx_ring[sky2->rx_next].skb;
2395 skb->ip_summed = CHECKSUM_COMPLETE;
2396 skb->csum = status & 0xffff;
2397 } else {
2398 printk(KERN_NOTICE PFX "%s: hardware receive "
2399 "checksum problem (status = %#x)\n",
2400 dev->name, status);
2401 sky2->rx_csum = 0;
2402 sky2_write32(sky2->hw,
69161611 2403 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2404 BMU_DIS_RX_CHKSUM);
2405 }
cd28ab6a
SH		 2406 break;
2407
2408 case OP_TXINDEXLE:
13b97b74 2409 /* TX index reports status for both ports */
f55925d7
SH		 2410 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2411 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2412 if (hw->dev[1])
2413 sky2_tx_done(hw->dev[1],
2414 ((status >> 24) & 0xff)
2415 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2416 break;
2417
cd28ab6a
SH		 2418 default:
2419 if (net_ratelimit())
793b883e 2420 printk(KERN_WARNING PFX
ab5adecb 2421 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2422 }
26691830 2423 } while (hw->st_idx != idx);
cd28ab6a 2424
fe2a24df
SH		 2425 /* Fully processed status ring so clear irq */
2426 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2427
13210ce5 2428exit_loop:
55c9dd35
SH		 2429 if (rx[0])
2430 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2431
55c9dd35
SH		 2432 if (rx[1])
2433 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2434
e07b1aa8 2435 return work_done;
cd28ab6a
SH		 2436}
2437
2438static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2439{
2440 struct net_device *dev = hw->dev[port];
2441
3be92a70
SH		 2442 if (net_ratelimit())
2443 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2444 dev->name, status);
cd28ab6a
SH		 2445
2446 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2447 if (net_ratelimit())
2448 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2449 dev->name);
cd28ab6a
SH		 2450 /* Clear IRQ */
2451 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2452 }
2453
2454 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2455 if (net_ratelimit())
2456 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2457 dev->name);
cd28ab6a
SH		 2458
2459 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2460 }
2461
2462 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2463 if (net_ratelimit())
2464 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2465 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2466 }
2467
2468 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2469 if (net_ratelimit())
2470 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2471 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2472 }
2473
2474 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2475 if (net_ratelimit())
2476 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2477 dev->name);
cd28ab6a
SH		 2478 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2479 }
2480}
2481
2482static void sky2_hw_intr(struct sky2_hw *hw)
2483{
555382cb 2484 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2485 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2486 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2487
2488 status &= hwmsk;
cd28ab6a 2489
793b883e 2490 if (status & Y2_IS_TIST_OV)
cd28ab6a 2491 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2492
2493 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2494 u16 pci_err;
2495
82637e80 2496 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2497 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2498 if (net_ratelimit())
555382cb 2499 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2500 pci_err);
cd28ab6a 2501
b32f40c4 2502 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2503 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2504 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2505 }
2506
2507 if (status & Y2_IS_PCI_EXP) {
d571b694 2508 /* PCI-Express uncorrectable Error occurred */
555382cb 2509 u32 err;
cd28ab6a 2510
82637e80 2511 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2512 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2513 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2514 0xfffffffful);
3be92a70 2515 if (net_ratelimit())
555382cb 2516 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2517
7782c8c4 2518 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2519 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2520 }
2521
2522 if (status & Y2_HWE_L1_MASK)
2523 sky2_hw_error(hw, 0, status);
2524 status >>= 8;
2525 if (status & Y2_HWE_L1_MASK)
2526 sky2_hw_error(hw, 1, status);
2527}
2528
2529static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2530{
2531 struct net_device *dev = hw->dev[port];
2532 struct sky2_port *sky2 = netdev_priv(dev);
2533 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2534
2535 if (netif_msg_intr(sky2))
2536 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2537 dev->name, status);
2538
a3caeada
SH		 2539 if (status & GM_IS_RX_CO_OV)
2540 gma_read16(hw, port, GM_RX_IRQ_SRC);
2541
2542 if (status & GM_IS_TX_CO_OV)
2543 gma_read16(hw, port, GM_TX_IRQ_SRC);
2544
cd28ab6a 2545 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2546 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2547 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2548 }
2549
2550 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2551 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2552 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2553 }
cd28ab6a
SH		 2554}
2555
40b01727
SH		 2556/* This should never happen it is a bug. */
2557static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2558 u16 q, unsigned ring_size)
d257924e
SH		 2559{
2560 struct net_device *dev = hw->dev[port];
2561 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2562 unsigned idx;
2563 const u64 *le = (q == Q_R1 || q == Q_R2)
2564 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2565
40b01727
SH		 2566 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2567 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2568 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2569 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2570
40b01727 2571 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2572}
cd28ab6a 2573
75e80683
SH		 2574static int sky2_rx_hung(struct net_device *dev)
2575{
2576 struct sky2_port *sky2 = netdev_priv(dev);
2577 struct sky2_hw *hw = sky2->hw;
2578 unsigned port = sky2->port;
2579 unsigned rxq = rxqaddr[port];
2580 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2581 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2582 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2583 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2584
2585 /* If idle and MAC or PCI is stuck */
2586 if (sky2->check.last == dev->last_rx &&
2587 ((mac_rp == sky2->check.mac_rp &&
2588 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2589 /* Check if the PCI RX hang */
2590 (fifo_rp == sky2->check.fifo_rp &&
2591 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2592 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2593 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2594 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2595 return 1;
2596 } else {
2597 sky2->check.last = dev->last_rx;
2598 sky2->check.mac_rp = mac_rp;
2599 sky2->check.mac_lev = mac_lev;
2600 sky2->check.fifo_rp = fifo_rp;
2601 sky2->check.fifo_lev = fifo_lev;
2602 return 0;
2603 }
2604}
2605
32c2c300 2606static void sky2_watchdog(unsigned long arg)
d27ed387 2607{
01bd7564 2608 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2609
75e80683 2610 /* Check for lost IRQ once a second */
32c2c300 2611 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2612 napi_schedule(&hw->napi);
75e80683
SH		 2613 } else {
2614 int i, active = 0;
2615
2616 for (i = 0; i < hw->ports; i++) {
bea3348e 2617 struct net_device *dev = hw->dev[i];
75e80683
SH		 2618 if (!netif_running(dev))
2619 continue;
2620 ++active;
2621
2622 /* For chips with Rx FIFO, check if stuck */
39dbd958 2623 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2624 sky2_rx_hung(dev)) {
2625 pr_info(PFX "%s: receiver hang detected\n",
2626 dev->name);
2627 schedule_work(&hw->restart_work);
2628 return;
2629 }
2630 }
2631
2632 if (active == 0)
2633 return;
32c2c300 2634 }
01bd7564 2635
75e80683 2636 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2637}
2638
40b01727
SH		 2639/* Hardware/software error handling */
2640static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2641{
40b01727
SH		 2642 if (net_ratelimit())
2643 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2644
1e5f1283
SH		 2645 if (status & Y2_IS_HW_ERR)
2646 sky2_hw_intr(hw);
d257924e 2647
1e5f1283
SH		 2648 if (status & Y2_IS_IRQ_MAC1)
2649 sky2_mac_intr(hw, 0);
cd28ab6a 2650
1e5f1283
SH		 2651 if (status & Y2_IS_IRQ_MAC2)
2652 sky2_mac_intr(hw, 1);
cd28ab6a 2653
1e5f1283 2654 if (status & Y2_IS_CHK_RX1)
40b01727 2655 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2656
1e5f1283 2657 if (status & Y2_IS_CHK_RX2)
40b01727 2658 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2659
1e5f1283 2660 if (status & Y2_IS_CHK_TXA1)
40b01727 2661 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2662
1e5f1283 2663 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2664 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2665}
2666
bea3348e 2667static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2668{
bea3348e 2669 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2670 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2671 int work_done = 0;
26691830 2672 u16 idx;
40b01727
SH		 2673
2674 if (unlikely(status & Y2_IS_ERROR))
2675 sky2_err_intr(hw, status);
2676
2677 if (status & Y2_IS_IRQ_PHY1)
2678 sky2_phy_intr(hw, 0);
2679
2680 if (status & Y2_IS_IRQ_PHY2)
2681 sky2_phy_intr(hw, 1);
cd28ab6a 2682
26691830
SH		 2683 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2684 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2685
2686 if (work_done >= work_limit)
26691830
SH		 2687 goto done;
2688 }
6f535763 2689
26691830
SH		 2690 /* Bug/Errata workaround?
2691 * Need to kick the TX irq moderation timer.
2692 */
2693 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2694 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2695 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2696 }
26691830
SH		 2697 napi_complete(napi);
2698 sky2_read32(hw, B0_Y2_SP_LISR);
2699done:
6f535763 2700
bea3348e 2701 return work_done;
e07b1aa8
SH		 2702}
2703
7d12e780 2704static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2705{
2706 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2707 u32 status;
2708
2709 /* Reading this mask interrupts as side effect */
2710 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2711 if (status == 0 || status == ~0)
2712 return IRQ_NONE;
793b883e 2713
e07b1aa8 2714 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2715
2716 napi_schedule(&hw->napi);
793b883e 2717
cd28ab6a
SH		 2718 return IRQ_HANDLED;
2719}
2720
2721#ifdef CONFIG_NET_POLL_CONTROLLER
2722static void sky2_netpoll(struct net_device *dev)
2723{
2724 struct sky2_port *sky2 = netdev_priv(dev);
2725
bea3348e 2726 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2727}
2728#endif
2729
2730/* Chip internal frequency for clock calculations */
05745c4a 2731static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2732{
793b883e 2733 switch (hw->chip_id) {
cd28ab6a 2734 case CHIP_ID_YUKON_EC:
5a5b1ea0 2735 case CHIP_ID_YUKON_EC_U:
93745494 2736 case CHIP_ID_YUKON_EX:
ed4d4161 2737 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2738 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2739 return 125;
2740
cd28ab6a 2741 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2742 return 100;
2743
2744 case CHIP_ID_YUKON_FE_P:
2745 return 50;
2746
2747 case CHIP_ID_YUKON_XL:
2748 return 156;
2749
2750 default:
2751 BUG();
cd28ab6a
SH		 2752 }
2753}
2754
fb17358f 2755static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2756{
fb17358f 2757 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2758}
2759
fb17358f 2760static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2761{
fb17358f 2762 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2763}
2764
fb17358f 2765
e3173832 2766static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2767{
b89165f2 2768 u8 t8;
cd28ab6a 2769
167f53d0 2770 /* Enable all clocks and check for bad PCI access */
b32f40c4 2771 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2772
cd28ab6a 2773 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2774
cd28ab6a 2775 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2776 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2777
2778 switch(hw->chip_id) {
2779 case CHIP_ID_YUKON_XL:
39dbd958 2780 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2781 break;
2782
2783 case CHIP_ID_YUKON_EC_U:
2784 hw->flags = SKY2_HW_GIGABIT
2785 | SKY2_HW_NEWER_PHY
2786 | SKY2_HW_ADV_POWER_CTL;
2787 break;
2788
2789 case CHIP_ID_YUKON_EX:
2790 hw->flags = SKY2_HW_GIGABIT
2791 | SKY2_HW_NEWER_PHY
2792 | SKY2_HW_NEW_LE
2793 | SKY2_HW_ADV_POWER_CTL;
2794
2795 /* New transmit checksum */
2796 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2797 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2798 break;
2799
2800 case CHIP_ID_YUKON_EC:
2801 /* This rev is really old, and requires untested workarounds */
2802 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2803 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2804 return -EOPNOTSUPP;
2805 }
39dbd958 2806 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2807 break;
2808
2809 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2810 break;
2811
05745c4a
SH		 2812 case CHIP_ID_YUKON_FE_P:
2813 hw->flags = SKY2_HW_NEWER_PHY
2814 | SKY2_HW_NEW_LE
2815 | SKY2_HW_AUTO_TX_SUM
2816 | SKY2_HW_ADV_POWER_CTL;
2817 break;
ed4d4161
SH		 2818
2819 case CHIP_ID_YUKON_SUPR:
2820 hw->flags = SKY2_HW_GIGABIT
2821 | SKY2_HW_NEWER_PHY
2822 | SKY2_HW_NEW_LE
2823 | SKY2_HW_AUTO_TX_SUM
2824 | SKY2_HW_ADV_POWER_CTL;
2825 break;
2826
0ce8b98d
SH		 2827 case CHIP_ID_YUKON_UL_2:
2828 hw->flags = SKY2_HW_GIGABIT
2829 | SKY2_HW_ADV_POWER_CTL;
2830 break;
2831
ea76e635 2832 default:
b02a9258
SH		 2833 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2834 hw->chip_id);
cd28ab6a
SH		 2835 return -EOPNOTSUPP;
2836 }
2837
ea76e635
SH		 2838 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2839 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2840 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2841
e3173832
SH		 2842 hw->ports = 1;
2843 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2844 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2845 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2846 ++hw->ports;
2847 }
2848
2849 return 0;
2850}
2851
2852static void sky2_reset(struct sky2_hw *hw)
2853{
555382cb 2854 struct pci_dev *pdev = hw->pdev;
e3173832 2855 u16 status;
555382cb
SH		 2856 int i, cap;
2857 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2858
cd28ab6a 2859 /* disable ASF */
4f44d8ba
SH		 2860 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2861 status = sky2_read16(hw, HCU_CCSR);
2862 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2863 HCU_CCSR_UC_STATE_MSK);
2864 sky2_write16(hw, HCU_CCSR, status);
2865 } else
2866 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2867 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2868
2869 /* do a SW reset */
2870 sky2_write8(hw, B0_CTST, CS_RST_SET);
2871 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2872
ac93a394
SH		 2873 /* allow writes to PCI config */
2874 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2875
cd28ab6a 2876 /* clear PCI errors, if any */
b32f40c4 2877 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2878 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2879 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2880
2881 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2882
555382cb
SH		 2883 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2884 if (cap) {
7782c8c4
SH		 2885 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2886 0xfffffffful);
555382cb
SH		 2887
2888 /* If error bit is stuck on ignore it */
2889 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2890 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2891 else
555382cb
SH		 2892 hwe_mask |= Y2_IS_PCI_EXP;
2893 }
cd28ab6a 2894
ae306cca 2895 sky2_power_on(hw);
82637e80 2896 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2897
2898 for (i = 0; i < hw->ports; i++) {
2899 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2900 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2901
ed4d4161
SH		 2902 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2903 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2904 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2905 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2906 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2907 }
2908
793b883e
SH		 2909 /* Clear I2C IRQ noise */
2910 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2911
2912 /* turn off hardware timer (unused) */
2913 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2914 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2915
cd28ab6a
SH		 2916 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2917
69634ee7
SH		 2918 /* Turn off descriptor polling */
2919 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2920
2921 /* Turn off receive timestamp */
2922 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2923 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2924
2925 /* enable the Tx Arbiters */
2926 for (i = 0; i < hw->ports; i++)
2927 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2928
2929 /* Initialize ram interface */
2930 for (i = 0; i < hw->ports; i++) {
793b883e 2931 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2932
2933 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2934 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2935 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2936 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2937 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2938 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2939 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2940 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2941 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2942 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2943 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2944 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2945 }
2946
555382cb 2947 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2948
cd28ab6a 2949 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2950 sky2_gmac_reset(hw, i);
cd28ab6a 2951
cd28ab6a
SH		 2952 memset(hw->st_le, 0, STATUS_LE_BYTES);
2953 hw->st_idx = 0;
2954
2955 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2956 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2957
2958 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2959 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2960
2961 /* Set the list last index */
793b883e 2962 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2963
290d4de5
SH		 2964 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2965 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2966
290d4de5
SH		 2967 /* set Status-FIFO ISR watermark */
2968 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2969 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2970 else
2971 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2972
290d4de5 2973 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2974 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2975 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2976
793b883e 2977 /* enable status unit */
cd28ab6a
SH		 2978 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2979
2980 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2981 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2982 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2983}
2984
81906791
SH		 2985static void sky2_restart(struct work_struct *work)
2986{
2987 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2988 struct net_device *dev;
2989 int i, err;
2990
81906791 2991 rtnl_lock();
81906791
SH		 2992 for (i = 0; i < hw->ports; i++) {
2993 dev = hw->dev[i];
2994 if (netif_running(dev))
2995 sky2_down(dev);
2996 }
2997
8cfcbe99
SH		 2998 napi_disable(&hw->napi);
2999 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3000 sky2_reset(hw);
3001 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3002 napi_enable(&hw->napi);
81906791
SH		 3003
3004 for (i = 0; i < hw->ports; i++) {
3005 dev = hw->dev[i];
3006 if (netif_running(dev)) {
3007 err = sky2_up(dev);
3008 if (err) {
3009 printk(KERN_INFO PFX "%s: could not restart %d\n",
3010 dev->name, err);
3011 dev_close(dev);
3012 }
3013 }
3014 }
3015
81906791
SH		 3016 rtnl_unlock();
3017}
3018
e3173832
SH		 3019static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3020{
3021 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3022}
3023
3024static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3025{
3026 const struct sky2_port *sky2 = netdev_priv(dev);
3027
3028 wol->supported = sky2_wol_supported(sky2->hw);
3029 wol->wolopts = sky2->wol;
3030}
3031
3032static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3033{
3034 struct sky2_port *sky2 = netdev_priv(dev);
3035 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3036
9d731d77
RW		 3037 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3038 || !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3039 return -EOPNOTSUPP;
3040
3041 sky2->wol = wol->wolopts;
3042
05745c4a
SH		 3043 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3044 hw->chip_id == CHIP_ID_YUKON_EX ||
3045 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3046 sky2_write32(hw, B0_CTST, sky2->wol
3047 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3048
9d731d77
RW		 3049 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3050
e3173832
SH		 3051 if (!netif_running(dev))
3052 sky2_wol_init(sky2);
cd28ab6a
SH		 3053 return 0;
3054}
3055
28bd181a 3056static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3057{
b89165f2
SH		 3058 if (sky2_is_copper(hw)) {
3059 u32 modes = SUPPORTED_10baseT_Half
3060 | SUPPORTED_10baseT_Full
3061 | SUPPORTED_100baseT_Half
3062 | SUPPORTED_100baseT_Full
3063 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3064
ea76e635 3065 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3066 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3067 | SUPPORTED_1000baseT_Full;
3068 return modes;
cd28ab6a 3069 } else
b89165f2
SH		 3070 return SUPPORTED_1000baseT_Half
3071 | SUPPORTED_1000baseT_Full
3072 | SUPPORTED_Autoneg
3073 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3074}
3075
793b883e 3076static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3077{
3078 struct sky2_port *sky2 = netdev_priv(dev);
3079 struct sky2_hw *hw = sky2->hw;
3080
3081 ecmd->transceiver = XCVR_INTERNAL;
3082 ecmd->supported = sky2_supported_modes(hw);
3083 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3084 if (sky2_is_copper(hw)) {
cd28ab6a 3085 ecmd->port = PORT_TP;
b89165f2
SH		 3086 ecmd->speed = sky2->speed;
3087 } else {
3088 ecmd->speed = SPEED_1000;
cd28ab6a 3089 ecmd->port = PORT_FIBRE;
b89165f2 3090 }
cd28ab6a
SH		 3091
3092 ecmd->advertising = sky2->advertising;
3093 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3094 ecmd->duplex = sky2->duplex;
3095 return 0;
3096}
3097
3098static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3099{
3100 struct sky2_port *sky2 = netdev_priv(dev);
3101 const struct sky2_hw *hw = sky2->hw;
3102 u32 supported = sky2_supported_modes(hw);
3103
3104 if (ecmd->autoneg == AUTONEG_ENABLE) {
3105 ecmd->advertising = supported;
3106 sky2->duplex = -1;
3107 sky2->speed = -1;
3108 } else {
3109 u32 setting;
3110
793b883e 3111 switch (ecmd->speed) {
cd28ab6a
SH		 3112 case SPEED_1000:
3113 if (ecmd->duplex == DUPLEX_FULL)
3114 setting = SUPPORTED_1000baseT_Full;
3115 else if (ecmd->duplex == DUPLEX_HALF)
3116 setting = SUPPORTED_1000baseT_Half;
3117 else
3118 return -EINVAL;
3119 break;
3120 case SPEED_100:
3121 if (ecmd->duplex == DUPLEX_FULL)
3122 setting = SUPPORTED_100baseT_Full;
3123 else if (ecmd->duplex == DUPLEX_HALF)
3124 setting = SUPPORTED_100baseT_Half;
3125 else
3126 return -EINVAL;
3127 break;
3128
3129 case SPEED_10:
3130 if (ecmd->duplex == DUPLEX_FULL)
3131 setting = SUPPORTED_10baseT_Full;
3132 else if (ecmd->duplex == DUPLEX_HALF)
3133 setting = SUPPORTED_10baseT_Half;
3134 else
3135 return -EINVAL;
3136 break;
3137 default:
3138 return -EINVAL;
3139 }
3140
3141 if ((setting & supported) == 0)
3142 return -EINVAL;
3143
3144 sky2->speed = ecmd->speed;
3145 sky2->duplex = ecmd->duplex;
3146 }
3147
3148 sky2->autoneg = ecmd->autoneg;
3149 sky2->advertising = ecmd->advertising;
3150
d1b139c0 3151 if (netif_running(dev)) {
1b537565 3152 sky2_phy_reinit(sky2);
d1b139c0
SH		 3153 sky2_set_multicast(dev);
3154 }
cd28ab6a
SH		 3155
3156 return 0;
3157}
3158
3159static void sky2_get_drvinfo(struct net_device *dev,
3160 struct ethtool_drvinfo *info)
3161{
3162 struct sky2_port *sky2 = netdev_priv(dev);
3163
3164 strcpy(info->driver, DRV_NAME);
3165 strcpy(info->version, DRV_VERSION);
3166 strcpy(info->fw_version, "N/A");
3167 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3168}
3169
3170static const struct sky2_stat {
793b883e
SH		 3171 char name[ETH_GSTRING_LEN];
3172 u16 offset;
cd28ab6a
SH		 3173} sky2_stats[] = {
3174 { "tx_bytes", GM_TXO_OK_HI },
3175 { "rx_bytes", GM_RXO_OK_HI },
3176 { "tx_broadcast", GM_TXF_BC_OK },
3177 { "rx_broadcast", GM_RXF_BC_OK },
3178 { "tx_multicast", GM_TXF_MC_OK },
3179 { "rx_multicast", GM_RXF_MC_OK },
3180 { "tx_unicast", GM_TXF_UC_OK },
3181 { "rx_unicast", GM_RXF_UC_OK },
3182 { "tx_mac_pause", GM_TXF_MPAUSE },
3183 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3184 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3185 { "late_collision",GM_TXF_LAT_COL },
3186 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3187 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3188 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3189
d2604540 3190 { "rx_short", GM_RXF_SHT },
cd28ab6a 3191 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3192 { "rx_64_byte_packets", GM_RXF_64B },
3193 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3194 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3195 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3196 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3197 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3198 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3199 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3200 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3201 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3202 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3203
3204 { "tx_64_byte_packets", GM_TXF_64B },
3205 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3206 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3207 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3208 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3209 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3210 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3211 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3212};
3213
cd28ab6a
SH		 3214static u32 sky2_get_rx_csum(struct net_device *dev)
3215{
3216 struct sky2_port *sky2 = netdev_priv(dev);
3217
3218 return sky2->rx_csum;
3219}
3220
3221static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3222{
3223 struct sky2_port *sky2 = netdev_priv(dev);
3224
3225 sky2->rx_csum = data;
793b883e 3226
cd28ab6a
SH		 3227 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3228 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3229
3230 return 0;
3231}
3232
3233static u32 sky2_get_msglevel(struct net_device *netdev)
3234{
3235 struct sky2_port *sky2 = netdev_priv(netdev);
3236 return sky2->msg_enable;
3237}
3238
9a7ae0a9
SH		 3239static int sky2_nway_reset(struct net_device *dev)
3240{
3241 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3242
16ad91e1 3243 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3244 return -EINVAL;
3245
1b537565 3246 sky2_phy_reinit(sky2);
d1b139c0 3247 sky2_set_multicast(dev);
9a7ae0a9
SH		 3248
3249 return 0;
3250}
3251
793b883e 3252static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3253{
3254 struct sky2_hw *hw = sky2->hw;
3255 unsigned port = sky2->port;
3256 int i;
3257
3258 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3259 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3260 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3261 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3262
793b883e 3263 for (i = 2; i < count; i++)
cd28ab6a
SH		 3264 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3265}
3266
cd28ab6a
SH		 3267static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3268{
3269 struct sky2_port *sky2 = netdev_priv(netdev);
3270 sky2->msg_enable = value;
3271}
3272
b9f2c044 3273static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3274{
b9f2c044
JG		 3275 switch (sset) {
3276 case ETH_SS_STATS:
3277 return ARRAY_SIZE(sky2_stats);
3278 default:
3279 return -EOPNOTSUPP;
3280 }
cd28ab6a
SH		 3281}
3282
3283static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3284 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3285{
3286 struct sky2_port *sky2 = netdev_priv(dev);
3287
793b883e 3288 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3289}
3290
793b883e 3291static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3292{
3293 int i;
3294
3295 switch (stringset) {
3296 case ETH_SS_STATS:
3297 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3298 memcpy(data + i * ETH_GSTRING_LEN,
3299 sky2_stats[i].name, ETH_GSTRING_LEN);
3300 break;
3301 }
3302}
3303
cd28ab6a
SH		 3304static int sky2_set_mac_address(struct net_device *dev, void *p)
3305{
3306 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3307 struct sky2_hw *hw = sky2->hw;
3308 unsigned port = sky2->port;
3309 const struct sockaddr *addr = p;
cd28ab6a
SH		 3310
3311 if (!is_valid_ether_addr(addr->sa_data))
3312 return -EADDRNOTAVAIL;
3313
cd28ab6a 3314 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3315 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3316 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3317 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3318 dev->dev_addr, ETH_ALEN);
1b537565 3319
a8ab1ec0
SH		 3320 /* virtual address for data */
3321 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3322
3323 /* physical address: used for pause frames */
3324 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3325
3326 return 0;
cd28ab6a
SH		 3327}
3328
a052b52f
SH		 3329static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3330{
3331 u32 bit;
3332
3333 bit = ether_crc(ETH_ALEN, addr) & 63;
3334 filter[bit >> 3] |= 1 << (bit & 7);
3335}
3336
cd28ab6a
SH		 3337static void sky2_set_multicast(struct net_device *dev)
3338{
3339 struct sky2_port *sky2 = netdev_priv(dev);
3340 struct sky2_hw *hw = sky2->hw;
3341 unsigned port = sky2->port;
3342 struct dev_mc_list *list = dev->mc_list;
3343 u16 reg;
3344 u8 filter[8];
a052b52f
SH		 3345 int rx_pause;
3346 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3347
a052b52f 3348 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3349 memset(filter, 0, sizeof(filter));
3350
3351 reg = gma_read16(hw, port, GM_RX_CTRL);
3352 reg |= GM_RXCR_UCF_ENA;
3353
d571b694 3354 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3355 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3356 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3357 memset(filter, 0xff, sizeof(filter));
a052b52f 3358 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3359 reg &= ~GM_RXCR_MCF_ENA;
3360 else {
3361 int i;
3362 reg |= GM_RXCR_MCF_ENA;
3363
a052b52f
SH		 3364 if (rx_pause)
3365 sky2_add_filter(filter, pause_mc_addr);
3366
3367 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3368 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3369 }
3370
cd28ab6a 3371 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3372 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3373 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3374 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3375 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3376 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3377 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3378 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3379
3380 gma_write16(hw, port, GM_RX_CTRL, reg);
3381}
3382
3383/* Can have one global because blinking is controlled by
3384 * ethtool and that is always under RTNL mutex
3385 */
a84d0a3d 3386static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3387{
a84d0a3d
SH		 3388 struct sky2_hw *hw = sky2->hw;
3389 unsigned port = sky2->port;
793b883e 3390
a84d0a3d
SH		 3391 spin_lock_bh(&sky2->phy_lock);
3392 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3393 hw->chip_id == CHIP_ID_YUKON_EX ||
3394 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3395 u16 pg;
793b883e
SH		 3396 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3398
a84d0a3d
SH		 3399 switch (mode) {
3400 case MO_LED_OFF:
3401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3402 PHY_M_LEDC_LOS_CTRL(8) |
3403 PHY_M_LEDC_INIT_CTRL(8) |
3404 PHY_M_LEDC_STA1_CTRL(8) |
3405 PHY_M_LEDC_STA0_CTRL(8));
3406 break;
3407 case MO_LED_ON:
3408 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3409 PHY_M_LEDC_LOS_CTRL(9) |
3410 PHY_M_LEDC_INIT_CTRL(9) |
3411 PHY_M_LEDC_STA1_CTRL(9) |
3412 PHY_M_LEDC_STA0_CTRL(9));
3413 break;
3414 case MO_LED_BLINK:
3415 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3416 PHY_M_LEDC_LOS_CTRL(0xa) |
3417 PHY_M_LEDC_INIT_CTRL(0xa) |
3418 PHY_M_LEDC_STA1_CTRL(0xa) |
3419 PHY_M_LEDC_STA0_CTRL(0xa));
3420 break;
3421 case MO_LED_NORM:
3422 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3423 PHY_M_LEDC_LOS_CTRL(1) |
3424 PHY_M_LEDC_INIT_CTRL(8) |
3425 PHY_M_LEDC_STA1_CTRL(7) |
3426 PHY_M_LEDC_STA0_CTRL(7));
3427 }
793b883e 3428
a84d0a3d
SH		 3429 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3430 } else
7d2e3cb7 3431 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3432 PHY_M_LED_MO_DUP(mode) |
3433 PHY_M_LED_MO_10(mode) |
3434 PHY_M_LED_MO_100(mode) |
3435 PHY_M_LED_MO_1000(mode) |
3436 PHY_M_LED_MO_RX(mode) |
3437 PHY_M_LED_MO_TX(mode));
3438
3439 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3440}
3441
3442/* blink LED's for finding board */
3443static int sky2_phys_id(struct net_device *dev, u32 data)
3444{
3445 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3446 unsigned int i;
cd28ab6a 3447
a84d0a3d
SH		 3448 if (data == 0)
3449 data = UINT_MAX;
cd28ab6a 3450
a84d0a3d
SH		 3451 for (i = 0; i < data; i++) {
3452 sky2_led(sky2, MO_LED_ON);
3453 if (msleep_interruptible(500))
3454 break;
3455 sky2_led(sky2, MO_LED_OFF);
3456 if (msleep_interruptible(500))
3457 break;
793b883e 3458 }
a84d0a3d 3459 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3460
3461 return 0;
3462}
3463
3464static void sky2_get_pauseparam(struct net_device *dev,
3465 struct ethtool_pauseparam *ecmd)
3466{
3467 struct sky2_port *sky2 = netdev_priv(dev);
3468
16ad91e1
SH		 3469 switch (sky2->flow_mode) {
3470 case FC_NONE:
3471 ecmd->tx_pause = ecmd->rx_pause = 0;
3472 break;
3473 case FC_TX:
3474 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3475 break;
3476 case FC_RX:
3477 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3478 break;
3479 case FC_BOTH:
3480 ecmd->tx_pause = ecmd->rx_pause = 1;
3481 }
3482
cd28ab6a
SH		 3483 ecmd->autoneg = sky2->autoneg;
3484}
3485
3486static int sky2_set_pauseparam(struct net_device *dev,
3487 struct ethtool_pauseparam *ecmd)
3488{
3489 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3490
3491 sky2->autoneg = ecmd->autoneg;
16ad91e1 3492 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3493
16ad91e1
SH		 3494 if (netif_running(dev))
3495 sky2_phy_reinit(sky2);
cd28ab6a 3496
2eaba1a2 3497 return 0;
cd28ab6a
SH		 3498}
3499
fb17358f
SH		 3500static int sky2_get_coalesce(struct net_device *dev,
3501 struct ethtool_coalesce *ecmd)
3502{
3503 struct sky2_port *sky2 = netdev_priv(dev);
3504 struct sky2_hw *hw = sky2->hw;
3505
3506 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3507 ecmd->tx_coalesce_usecs = 0;
3508 else {
3509 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3510 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3511 }
3512 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3513
3514 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3515 ecmd->rx_coalesce_usecs = 0;
3516 else {
3517 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3518 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3519 }
3520 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3521
3522 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3523 ecmd->rx_coalesce_usecs_irq = 0;
3524 else {
3525 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3526 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3527 }
3528
3529 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3530
3531 return 0;
3532}
3533
3534/* Note: this affect both ports */
3535static int sky2_set_coalesce(struct net_device *dev,
3536 struct ethtool_coalesce *ecmd)
3537{
3538 struct sky2_port *sky2 = netdev_priv(dev);
3539 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3540 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3541
77b3d6a2
SH		 3542 if (ecmd->tx_coalesce_usecs > tmax ||
3543 ecmd->rx_coalesce_usecs > tmax ||
3544 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3545 return -EINVAL;
3546
ff81fbbe 3547 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3548 return -EINVAL;
ff81fbbe 3549 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3550 return -EINVAL;
ff81fbbe 3551 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3552 return -EINVAL;
3553
3554 if (ecmd->tx_coalesce_usecs == 0)
3555 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3556 else {
3557 sky2_write32(hw, STAT_TX_TIMER_INI,
3558 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3559 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3560 }
3561 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3562
3563 if (ecmd->rx_coalesce_usecs == 0)
3564 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3565 else {
3566 sky2_write32(hw, STAT_LEV_TIMER_INI,
3567 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3568 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3569 }
3570 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3571
3572 if (ecmd->rx_coalesce_usecs_irq == 0)
3573 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3574 else {
d28d4870 3575 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3576 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3577 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3578 }
3579 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3580 return 0;
3581}
3582
793b883e
SH		 3583static void sky2_get_ringparam(struct net_device *dev,
3584 struct ethtool_ringparam *ering)
3585{
3586 struct sky2_port *sky2 = netdev_priv(dev);
3587
3588 ering->rx_max_pending = RX_MAX_PENDING;
3589 ering->rx_mini_max_pending = 0;
3590 ering->rx_jumbo_max_pending = 0;
3591 ering->tx_max_pending = TX_RING_SIZE - 1;
3592
3593 ering->rx_pending = sky2->rx_pending;
3594 ering->rx_mini_pending = 0;
3595 ering->rx_jumbo_pending = 0;
3596 ering->tx_pending = sky2->tx_pending;
3597}
3598
3599static int sky2_set_ringparam(struct net_device *dev,
3600 struct ethtool_ringparam *ering)
3601{
3602 struct sky2_port *sky2 = netdev_priv(dev);
3603 int err = 0;
3604
3605 if (ering->rx_pending > RX_MAX_PENDING ||
3606 ering->rx_pending < 8 ||
3607 ering->tx_pending < MAX_SKB_TX_LE ||
3608 ering->tx_pending > TX_RING_SIZE - 1)
3609 return -EINVAL;
3610
3611 if (netif_running(dev))
3612 sky2_down(dev);
3613
3614 sky2->rx_pending = ering->rx_pending;
3615 sky2->tx_pending = ering->tx_pending;
3616
1b537565 3617 if (netif_running(dev)) {
793b883e 3618 err = sky2_up(dev);
1b537565
SH		 3619 if (err)
3620 dev_close(dev);
3621 }
793b883e
SH		 3622
3623 return err;
3624}
3625
793b883e
SH		 3626static int sky2_get_regs_len(struct net_device *dev)
3627{
6e4cbb34 3628 return 0x4000;
793b883e
SH		 3629}
3630
3631/*
3632 * Returns copy of control register region
3ead5db7 3633 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3634 */
3635static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3636 void *p)
3637{
3638 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3639 const void __iomem *io = sky2->hw->regs;
295b54c4 3640 unsigned int b;
793b883e
SH		 3641
3642 regs->version = 1;
793b883e 3643
295b54c4
SH		 3644 for (b = 0; b < 128; b++) {
3645 /* This complicated switch statement is to make sure and
3646 * only access regions that are unreserved.
3647 * Some blocks are only valid on dual port cards.
3648 * and block 3 has some special diagnostic registers that
3649 * are poison.
3650 */
3651 switch (b) {
3652 case 3:
3653 /* skip diagnostic ram region */
3654 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3655 break;
3ead5db7 3656
295b54c4
SH		 3657 /* dual port cards only */
3658 case 5: /* Tx Arbiter 2 */
3659 case 9: /* RX2 */
3660 case 14 ... 15: /* TX2 */
3661 case 17: case 19: /* Ram Buffer 2 */
3662 case 22 ... 23: /* Tx Ram Buffer 2 */
3663 case 25: /* Rx MAC Fifo 1 */
3664 case 27: /* Tx MAC Fifo 2 */
3665 case 31: /* GPHY 2 */
3666 case 40 ... 47: /* Pattern Ram 2 */
3667 case 52: case 54: /* TCP Segmentation 2 */
3668 case 112 ... 116: /* GMAC 2 */
3669 if (sky2->hw->ports == 1)
3670 goto reserved;
3671 /* fall through */
3672 case 0: /* Control */
3673 case 2: /* Mac address */
3674 case 4: /* Tx Arbiter 1 */
3675 case 7: /* PCI express reg */
3676 case 8: /* RX1 */
3677 case 12 ... 13: /* TX1 */
3678 case 16: case 18:/* Rx Ram Buffer 1 */
3679 case 20 ... 21: /* Tx Ram Buffer 1 */
3680 case 24: /* Rx MAC Fifo 1 */
3681 case 26: /* Tx MAC Fifo 1 */
3682 case 28 ... 29: /* Descriptor and status unit */
3683 case 30: /* GPHY 1*/
3684 case 32 ... 39: /* Pattern Ram 1 */
3685 case 48: case 50: /* TCP Segmentation 1 */
3686 case 56 ... 60: /* PCI space */
3687 case 80 ... 84: /* GMAC 1 */
3688 memcpy_fromio(p, io, 128);
3689 break;
3690 default:
3691reserved:
3692 memset(p, 0, 128);
3693 }
3ead5db7 3694
295b54c4
SH		 3695 p += 128;
3696 io += 128;
3697 }
793b883e 3698}
cd28ab6a 3699
b628ed98
SH		 3700/* In order to do Jumbo packets on these chips, need to turn off the
3701 * transmit store/forward. Therefore checksum offload won't work.
3702 */
3703static int no_tx_offload(struct net_device *dev)
3704{
3705 const struct sky2_port *sky2 = netdev_priv(dev);
3706 const struct sky2_hw *hw = sky2->hw;
3707
69161611 3708 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3709}
3710
3711static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3712{
3713 if (data && no_tx_offload(dev))
3714 return -EINVAL;
3715
3716 return ethtool_op_set_tx_csum(dev, data);
3717}
3718
3719
3720static int sky2_set_tso(struct net_device *dev, u32 data)
3721{
3722 if (data && no_tx_offload(dev))
3723 return -EINVAL;
3724
3725 return ethtool_op_set_tso(dev, data);
3726}
3727
f4331a6d
SH		 3728static int sky2_get_eeprom_len(struct net_device *dev)
3729{
3730 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3731 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3732 u16 reg2;
3733
b32f40c4 3734 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3735 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3736}
3737
1413235c 3738static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3739{
1413235c 3740 unsigned long start = jiffies;
f4331a6d 3741
1413235c
SH		 3742 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3743 /* Can take up to 10.6 ms for write */
3744 if (time_after(jiffies, start + HZ/4)) {
3745 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3746 return -ETIMEDOUT;
3747 }
3748 mdelay(1);
3749 }
167f53d0 3750
1413235c
SH		 3751 return 0;
3752}
167f53d0 3753
1413235c
SH		 3754static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3755 u16 offset, size_t length)
3756{
3757 int rc = 0;
3758
3759 while (length > 0) {
3760 u32 val;
3761
3762 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3763 rc = sky2_vpd_wait(hw, cap, 0);
3764 if (rc)
3765 break;
3766
3767 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3768
3769 memcpy(data, &val, min(sizeof(val), length));
3770 offset += sizeof(u32);
3771 data += sizeof(u32);
3772 length -= sizeof(u32);
3773 }
3774
3775 return rc;
f4331a6d
SH		 3776}
3777
1413235c
SH		 3778static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3779 u16 offset, unsigned int length)
f4331a6d 3780{
1413235c
SH		 3781 unsigned int i;
3782 int rc = 0;
3783
3784 for (i = 0; i < length; i += sizeof(u32)) {
3785 u32 val = *(u32 *)(data + i);
3786
3787 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3788 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3789
3790 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3791 if (rc)
3792 break;
3793 }
3794 return rc;
f4331a6d
SH		 3795}
3796
3797static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3798 u8 *data)
3799{
3800 struct sky2_port *sky2 = netdev_priv(dev);
3801 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3802
3803 if (!cap)
3804 return -EINVAL;
3805
3806 eeprom->magic = SKY2_EEPROM_MAGIC;
3807
1413235c 3808 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3809}
3810
3811static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3812 u8 *data)
3813{
3814 struct sky2_port *sky2 = netdev_priv(dev);
3815 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3816
3817 if (!cap)
3818 return -EINVAL;
3819
3820 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3821 return -EINVAL;
3822
1413235c
SH		 3823 /* Partial writes not supported */
3824 if ((eeprom->offset & 3) || (eeprom->len & 3))
3825 return -EINVAL;
f4331a6d 3826
1413235c 3827 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3828}
3829
3830
7282d491 3831static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3832 .get_settings = sky2_get_settings,
3833 .set_settings = sky2_set_settings,
3834 .get_drvinfo = sky2_get_drvinfo,
3835 .get_wol = sky2_get_wol,
3836 .set_wol = sky2_set_wol,
3837 .get_msglevel = sky2_get_msglevel,
3838 .set_msglevel = sky2_set_msglevel,
3839 .nway_reset = sky2_nway_reset,
3840 .get_regs_len = sky2_get_regs_len,
3841 .get_regs = sky2_get_regs,
3842 .get_link = ethtool_op_get_link,
3843 .get_eeprom_len = sky2_get_eeprom_len,
3844 .get_eeprom = sky2_get_eeprom,
3845 .set_eeprom = sky2_set_eeprom,
f4331a6d 3846 .set_sg = ethtool_op_set_sg,
f4331a6d 3847 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3848 .set_tso = sky2_set_tso,
3849 .get_rx_csum = sky2_get_rx_csum,
3850 .set_rx_csum = sky2_set_rx_csum,
3851 .get_strings = sky2_get_strings,
3852 .get_coalesce = sky2_get_coalesce,
3853 .set_coalesce = sky2_set_coalesce,
3854 .get_ringparam = sky2_get_ringparam,
3855 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3856 .get_pauseparam = sky2_get_pauseparam,
3857 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3858 .phys_id = sky2_phys_id,
b9f2c044 3859 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3860 .get_ethtool_stats = sky2_get_ethtool_stats,
3861};
3862
3cf26753
SH		 3863#ifdef CONFIG_SKY2_DEBUG
3864
3865static struct dentry *sky2_debug;
3866
3867static int sky2_debug_show(struct seq_file *seq, void *v)
3868{
3869 struct net_device *dev = seq->private;
3870 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3871 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3872 unsigned port = sky2->port;
3873 unsigned idx, last;
3874 int sop;
3875
3876 if (!netif_running(dev))
3877 return -ENETDOWN;
3878
3879 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3880 sky2_read32(hw, B0_ISRC),
3881 sky2_read32(hw, B0_IMSK),
3882 sky2_read32(hw, B0_Y2_SP_ICR));
3883
bea3348e 3884 napi_disable(&hw->napi);
3cf26753
SH		 3885 last = sky2_read16(hw, STAT_PUT_IDX);
3886
3887 if (hw->st_idx == last)
3888 seq_puts(seq, "Status ring (empty)\n");
3889 else {
3890 seq_puts(seq, "Status ring\n");
3891 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3892 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3893 const struct sky2_status_le *le = hw->st_le + idx;
3894 seq_printf(seq, "[%d] %#x %d %#x\n",
3895 idx, le->opcode, le->length, le->status);
3896 }
3897 seq_puts(seq, "\n");
3898 }
3899
3900 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3901 sky2->tx_cons, sky2->tx_prod,
3902 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3903 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3904
3905 /* Dump contents of tx ring */
3906 sop = 1;
3907 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3908 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3909 const struct sky2_tx_le *le = sky2->tx_le + idx;
3910 u32 a = le32_to_cpu(le->addr);
3911
3912 if (sop)
3913 seq_printf(seq, "%u:", idx);
3914 sop = 0;
3915
3916 switch(le->opcode & ~HW_OWNER) {
3917 case OP_ADDR64:
3918 seq_printf(seq, " %#x:", a);
3919 break;
3920 case OP_LRGLEN:
3921 seq_printf(seq, " mtu=%d", a);
3922 break;
3923 case OP_VLAN:
3924 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3925 break;
3926 case OP_TCPLISW:
3927 seq_printf(seq, " csum=%#x", a);
3928 break;
3929 case OP_LARGESEND:
3930 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3931 break;
3932 case OP_PACKET:
3933 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3934 break;
3935 case OP_BUFFER:
3936 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3937 break;
3938 default:
3939 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3940 a, le16_to_cpu(le->length));
3941 }
3942
3943 if (le->ctrl & EOP) {
3944 seq_putc(seq, '\n');
3945 sop = 1;
3946 }
3947 }
3948
3949 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3950 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3951 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3952 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3953
d1d08d12 3954 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 3955 napi_enable(&hw->napi);
3cf26753
SH		 3956 return 0;
3957}
3958
3959static int sky2_debug_open(struct inode *inode, struct file *file)
3960{
3961 return single_open(file, sky2_debug_show, inode->i_private);
3962}
3963
3964static const struct file_operations sky2_debug_fops = {
3965 .owner = THIS_MODULE,
3966 .open = sky2_debug_open,
3967 .read = seq_read,
3968 .llseek = seq_lseek,
3969 .release = single_release,
3970};
3971
3972/*
3973 * Use network device events to create/remove/rename
3974 * debugfs file entries
3975 */
3976static int sky2_device_event(struct notifier_block *unused,
3977 unsigned long event, void *ptr)
3978{
3979 struct net_device *dev = ptr;
5b296bc9 3980 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 3981
1436b301 3982 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 3983 return NOTIFY_DONE;
3cf26753 3984
5b296bc9
SH		 3985 switch(event) {
3986 case NETDEV_CHANGENAME:
3987 if (sky2->debugfs) {
3988 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3989 sky2_debug, dev->name);
3990 }
3991 break;
3cf26753 3992
5b296bc9
SH		 3993 case NETDEV_GOING_DOWN:
3994 if (sky2->debugfs) {
3995 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3996 dev->name);
3997 debugfs_remove(sky2->debugfs);
3998 sky2->debugfs = NULL;
3cf26753 3999 }
5b296bc9
SH		 4000 break;
4001
4002 case NETDEV_UP:
4003 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4004 sky2_debug, dev,
4005 &sky2_debug_fops);
4006 if (IS_ERR(sky2->debugfs))
4007 sky2->debugfs = NULL;
3cf26753
SH		 4008 }
4009
4010 return NOTIFY_DONE;
4011}
4012
4013static struct notifier_block sky2_notifier = {
4014 .notifier_call = sky2_device_event,
4015};
4016
4017
4018static __init void sky2_debug_init(void)
4019{
4020 struct dentry *ent;
4021
4022 ent = debugfs_create_dir("sky2", NULL);
4023 if (!ent || IS_ERR(ent))
4024 return;
4025
4026 sky2_debug = ent;
4027 register_netdevice_notifier(&sky2_notifier);
4028}
4029
4030static __exit void sky2_debug_cleanup(void)
4031{
4032 if (sky2_debug) {
4033 unregister_netdevice_notifier(&sky2_notifier);
4034 debugfs_remove(sky2_debug);
4035 sky2_debug = NULL;
4036 }
4037}
4038
4039#else
4040#define sky2_debug_init()
4041#define sky2_debug_cleanup()
4042#endif
4043
1436b301
SH		 4044/* Two copies of network device operations to handle special case of
4045 not allowing netpoll on second port */
4046static const struct net_device_ops sky2_netdev_ops[2] = {
4047 {
4048 .ndo_open = sky2_up,
4049 .ndo_stop = sky2_down,
00829823 4050 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4051 .ndo_do_ioctl = sky2_ioctl,
4052 .ndo_validate_addr = eth_validate_addr,
4053 .ndo_set_mac_address = sky2_set_mac_address,
4054 .ndo_set_multicast_list = sky2_set_multicast,
4055 .ndo_change_mtu = sky2_change_mtu,
4056 .ndo_tx_timeout = sky2_tx_timeout,
4057#ifdef SKY2_VLAN_TAG_USED
4058 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4059#endif
4060#ifdef CONFIG_NET_POLL_CONTROLLER
4061 .ndo_poll_controller = sky2_netpoll,
4062#endif
4063 },
4064 {
4065 .ndo_open = sky2_up,
4066 .ndo_stop = sky2_down,
00829823 4067 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4068 .ndo_do_ioctl = sky2_ioctl,
4069 .ndo_validate_addr = eth_validate_addr,
4070 .ndo_set_mac_address = sky2_set_mac_address,
4071 .ndo_set_multicast_list = sky2_set_multicast,
4072 .ndo_change_mtu = sky2_change_mtu,
4073 .ndo_tx_timeout = sky2_tx_timeout,
4074#ifdef SKY2_VLAN_TAG_USED
4075 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4076#endif
4077 },
4078};
3cf26753 4079
cd28ab6a
SH		 4080/* Initialize network device */
4081static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4082 unsigned port,
be63a21c 4083 int highmem, int wol)
cd28ab6a
SH		 4084{
4085 struct sky2_port *sky2;
4086 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4087
4088 if (!dev) {
898eb71c 4089 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4090 return NULL;
4091 }
4092
cd28ab6a 4093 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4094 dev->irq = hw->pdev->irq;
cd28ab6a 4095 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4096 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4097 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4098
4099 sky2 = netdev_priv(dev);
4100 sky2->netdev = dev;
4101 sky2->hw = hw;
4102 sky2->msg_enable = netif_msg_init(debug, default_msg);
4103
cd28ab6a
SH		 4104 /* Auto speed and flow control */
4105 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4106 sky2->flow_mode = FC_BOTH;
4107
cd28ab6a
SH		 4108 sky2->duplex = -1;
4109 sky2->speed = -1;
4110 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4111 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4112 sky2->wol = wol;
75d070c5 4113
e07b1aa8 4114 spin_lock_init(&sky2->phy_lock);
793b883e 4115 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4116 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4117
4118 hw->dev[port] = dev;
4119
4120 sky2->port = port;
4121
4a50a876 4122 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4123 if (highmem)
4124 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4125
d1f13708 4126#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4127 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4128 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4129 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4130 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4131 }
d1f13708
SH		 4132#endif
4133
cd28ab6a 4134 /* read the mac address */
793b883e 4135 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4136 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4137
cd28ab6a
SH		 4138 return dev;
4139}
4140
28bd181a 4141static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4142{
4143 const struct sky2_port *sky2 = netdev_priv(dev);
4144
4145 if (netif_msg_probe(sky2))
e174961c
JB		 4146 printk(KERN_INFO PFX "%s: addr %pM\n",
4147 dev->name, dev->dev_addr);
cd28ab6a
SH		 4148}
4149
fb2690a9 4150/* Handle software interrupt used during MSI test */
7d12e780 4151static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4152{
4153 struct sky2_hw *hw = dev_id;
4154 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4155
4156 if (status == 0)
4157 return IRQ_NONE;
4158
4159 if (status & Y2_IS_IRQ_SW) {
ea76e635 4160 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4161 wake_up(&hw->msi_wait);
4162 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4163 }
4164 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4165
4166 return IRQ_HANDLED;
4167}
4168
4169/* Test interrupt path by forcing a a software IRQ */
4170static int __devinit sky2_test_msi(struct sky2_hw *hw)
4171{
4172 struct pci_dev *pdev = hw->pdev;
4173 int err;
4174
bb507fe1
SH		 4175 init_waitqueue_head (&hw->msi_wait);
4176
fb2690a9
SH		 4177 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4178
b0a20ded 4179 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4180 if (err) {
b02a9258 4181 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4182 return err;
4183 }
4184
fb2690a9 4185 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4186 sky2_read8(hw, B0_CTST);
fb2690a9 4187
ea76e635 4188 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4189
ea76e635 4190 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4191 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4192 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4193 "switching to INTx mode.\n");
fb2690a9
SH		 4194
4195 err = -EOPNOTSUPP;
4196 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4197 }
4198
4199 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4200 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4201
4202 free_irq(pdev->irq, hw);
4203
4204 return err;
4205}
4206
c844d483
SH		 4207/*
4208 * Read and parse the first part of Vital Product Data
4209 */
4210#define VPD_SIZE 128
4211#define VPD_MAGIC 0x82
4212
4213static void __devinit sky2_vpd_info(struct sky2_hw *hw)
4214{
4215 int cap = pci_find_capability(hw->pdev, PCI_CAP_ID_VPD);
4216 const u8 *p;
4217 u8 *vpd_buf = NULL;
4218 u16 len;
4219 static struct vpd_tag {
4220 char tag[2];
4221 char *label;
4222 } vpd_tags[] = {
4223 { "PN", "Part Number" },
4224 { "EC", "Engineering Level" },
4225 { "MN", "Manufacturer" },
4226 };
4227
4228 if (!cap)
4229 goto out;
4230
4231 vpd_buf = kmalloc(VPD_SIZE, GFP_KERNEL);
4232 if (!vpd_buf)
4233 goto out;
4234
4235 if (sky2_vpd_read(hw, cap, vpd_buf, 0, VPD_SIZE))
4236 goto out;
4237
4238 if (vpd_buf[0] != VPD_MAGIC)
4239 goto out;
4240 len = vpd_buf[1];
4241 if (len == 0 || len > VPD_SIZE - 4)
4242 goto out;
4243 p = vpd_buf + 3;
4244 dev_info(&hw->pdev->dev, "%.*s\n", len, p);
4245 p += len;
4246
4247 while (p < vpd_buf + VPD_SIZE - 4) {
4248 int i;
4249
4250 if (!memcmp("RW", p, 2)) /* end marker */
4251 break;
4252
4253 len = p[2];
4254 if (len > (p - vpd_buf) - 4)
4255 break;
4256
4257 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4258 if (!memcmp(vpd_tags[i].tag, p, 2)) {
4259 printk(KERN_DEBUG " %s: %.*s\n",
4260 vpd_tags[i].label, len, p + 3);
4261 break;
4262 }
4263 }
4264 p += len + 3;
4265 }
4266out:
4267 kfree(vpd_buf);
4268}
4269
c7127a34
SH		 4270/* This driver supports yukon2 chipset only */
4271static const char *sky2_name(u8 chipid, char *buf, int sz)
4272{
4273 const char *name[] = {
4274 "XL", /* 0xb3 */
4275 "EC Ultra", /* 0xb4 */
4276 "Extreme", /* 0xb5 */
4277 "EC", /* 0xb6 */
4278 "FE", /* 0xb7 */
4279 "FE+", /* 0xb8 */
4280 "Supreme", /* 0xb9 */
0ce8b98d 4281 "UL 2", /* 0xba */
c7127a34
SH		 4282 };
4283
0ce8b98d 4284 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4285 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4286 else
4287 snprintf(buf, sz, "(chip %#x)", chipid);
4288 return buf;
4289}
4290
cd28ab6a
SH		 4291static int __devinit sky2_probe(struct pci_dev *pdev,
4292 const struct pci_device_id *ent)
4293{
7f60c64b 4294 struct net_device *dev;
cd28ab6a 4295 struct sky2_hw *hw;
be63a21c 4296 int err, using_dac = 0, wol_default;
c7127a34 4297 char buf1[16];
cd28ab6a 4298
793b883e
SH		 4299 err = pci_enable_device(pdev);
4300 if (err) {
b02a9258 4301 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4302 goto err_out;
4303 }
4304
793b883e
SH		 4305 err = pci_request_regions(pdev, DRV_NAME);
4306 if (err) {
b02a9258 4307 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4308 goto err_out_disable;
cd28ab6a
SH		 4309 }
4310
4311 pci_set_master(pdev);
4312
d1f3d4dd
SH		 4313 if (sizeof(dma_addr_t) > sizeof(u32) &&
4314 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4315 using_dac = 1;
4316 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4317 if (err < 0) {
b02a9258
SH		 4318 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4319 "for consistent allocations\n");
d1f3d4dd
SH		 4320 goto err_out_free_regions;
4321 }
d1f3d4dd 4322 } else {
cd28ab6a
SH		 4323 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4324 if (err) {
b02a9258 4325 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4326 goto err_out_free_regions;
4327 }
4328 }
d1f3d4dd 4329
9d731d77 4330 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4331
cd28ab6a 4332 err = -ENOMEM;
6aad85d6 4333 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4334 if (!hw) {
b02a9258 4335 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4336 goto err_out_free_regions;
4337 }
4338
cd28ab6a 4339 hw->pdev = pdev;
cd28ab6a
SH		 4340
4341 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4342 if (!hw->regs) {
b02a9258 4343 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4344 goto err_out_free_hw;
4345 }
4346
56a645cc 4347#ifdef __BIG_ENDIAN
f65b138c
SH		 4348 /* The sk98lin vendor driver uses hardware byte swapping but
4349 * this driver uses software swapping.
4350 */
56a645cc
SH		 4351 {
4352 u32 reg;
b32f40c4 4353 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4354 reg &= ~PCI_REV_DESC;
b32f40c4 4355 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4356 }
4357#endif
4358
08c06d8a 4359 /* ring for status responses */
167f53d0 4360 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4361 if (!hw->st_le)
4362 goto err_out_iounmap;
4363
e3173832 4364 err = sky2_init(hw);
cd28ab6a 4365 if (err)
793b883e 4366 goto err_out_iounmap;
cd28ab6a 4367
c844d483
SH		 4368 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4369 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4370
e3173832
SH		 4371 sky2_reset(hw);
4372
c844d483
SH		 4373 sky2_vpd_info(hw);
4374
be63a21c 4375 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b
SH		 4376 if (!dev) {
4377 err = -ENOMEM;
cd28ab6a 4378 goto err_out_free_pci;
7f60c64b 4379 }
cd28ab6a 4380
9fa1b1f3
SH		 4381 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4382 err = sky2_test_msi(hw);
4383 if (err == -EOPNOTSUPP)
4384 pci_disable_msi(pdev);
4385 else if (err)
4386 goto err_out_free_netdev;
4387 }
4388
793b883e
SH		 4389 err = register_netdev(dev);
4390 if (err) {
b02a9258 4391 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4392 goto err_out_free_netdev;
4393 }
4394
6de16237
SH		 4395 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4396
ea76e635
SH		 4397 err = request_irq(pdev->irq, sky2_intr,
4398 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4399 dev->name, hw);
9fa1b1f3 4400 if (err) {
b02a9258 4401 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4402 goto err_out_unregister;
4403 }
4404 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4405 napi_enable(&hw->napi);
9fa1b1f3 4406
cd28ab6a
SH		 4407 sky2_show_addr(dev);
4408
7f60c64b
SH		 4409 if (hw->ports > 1) {
4410 struct net_device *dev1;
4411
be63a21c 4412 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4413 if (!dev1)
4414 dev_warn(&pdev->dev, "allocation for second device failed\n");
4415 else if ((err = register_netdev(dev1))) {
4416 dev_warn(&pdev->dev,
4417 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4418 hw->dev[1] = NULL;
4419 free_netdev(dev1);
b02a9258
SH		 4420 } else
4421 sky2_show_addr(dev1);
cd28ab6a
SH		 4422 }
4423
32c2c300 4424 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4425 INIT_WORK(&hw->restart_work, sky2_restart);
4426
793b883e
SH		 4427 pci_set_drvdata(pdev, hw);
4428
cd28ab6a
SH		 4429 return 0;
4430
793b883e 4431err_out_unregister:
ea76e635 4432 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4433 pci_disable_msi(pdev);
793b883e 4434 unregister_netdev(dev);
cd28ab6a
SH		 4435err_out_free_netdev:
4436 free_netdev(dev);
cd28ab6a 4437err_out_free_pci:
793b883e 4438 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4439 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4440err_out_iounmap:
4441 iounmap(hw->regs);
4442err_out_free_hw:
4443 kfree(hw);
4444err_out_free_regions:
4445 pci_release_regions(pdev);
44a1d2e5 4446err_out_disable:
cd28ab6a 4447 pci_disable_device(pdev);
cd28ab6a 4448err_out:
549a68c3 4449 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4450 return err;
4451}
4452
4453static void __devexit sky2_remove(struct pci_dev *pdev)
4454{
793b883e 4455 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4456 int i;
cd28ab6a 4457
793b883e 4458 if (!hw)
cd28ab6a
SH		 4459 return;
4460
32c2c300 4461 del_timer_sync(&hw->watchdog_timer);
6de16237 4462 cancel_work_sync(&hw->restart_work);
d27ed387 4463
b877fe28 4464 for (i = hw->ports-1; i >= 0; --i)
6de16237 4465 unregister_netdev(hw->dev[i]);
81906791 4466
d27ed387 4467 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4468
ae306cca
SH		 4469 sky2_power_aux(hw);
4470
cd28ab6a 4471 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4472 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4473 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4474
4475 free_irq(pdev->irq, hw);
ea76e635 4476 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4477 pci_disable_msi(pdev);
793b883e 4478 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4479 pci_release_regions(pdev);
4480 pci_disable_device(pdev);
793b883e 4481
b877fe28 4482 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4483 free_netdev(hw->dev[i]);
4484
cd28ab6a
SH		 4485 iounmap(hw->regs);
4486 kfree(hw);
5afa0a9c 4487
cd28ab6a
SH		 4488 pci_set_drvdata(pdev, NULL);
4489}
4490
4491#ifdef CONFIG_PM
4492static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4493{
793b883e 4494 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4495 int i, wol = 0;
cd28ab6a 4496
549a68c3
SH		 4497 if (!hw)
4498 return 0;
4499
063a0b38
SH		 4500 del_timer_sync(&hw->watchdog_timer);
4501 cancel_work_sync(&hw->restart_work);
4502
f05267e7 4503 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4504 struct net_device *dev = hw->dev[i];
e3173832 4505 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4506
063a0b38 4507 netif_device_detach(dev);
e3173832 4508 if (netif_running(dev))
5afa0a9c 4509 sky2_down(dev);
e3173832
SH		 4510
4511 if (sky2->wol)
4512 sky2_wol_init(sky2);
4513
4514 wol |= sky2->wol;
cd28ab6a
SH		 4515 }
4516
8ab8fca2 4517 sky2_write32(hw, B0_IMSK, 0);
6de16237 4518 napi_disable(&hw->napi);
ae306cca 4519 sky2_power_aux(hw);
e3173832 4520
d374c1c1 4521 pci_save_state(pdev);
e3173832 4522 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4523 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4524
2ccc99b7 4525 return 0;
cd28ab6a
SH		 4526}
4527
4528static int sky2_resume(struct pci_dev *pdev)
4529{
793b883e 4530 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4531 int i, err;
cd28ab6a 4532
549a68c3
SH		 4533 if (!hw)
4534 return 0;
4535
f71eb1a2
SH		 4536 err = pci_set_power_state(pdev, PCI_D0);
4537 if (err)
4538 goto out;
ae306cca
SH		 4539
4540 err = pci_restore_state(pdev);
4541 if (err)
4542 goto out;
4543
cd28ab6a 4544 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4545
4546 /* Re-enable all clocks */
05745c4a
SH		 4547 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4548 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4549 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4550 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4551
e3173832 4552 sky2_reset(hw);
8ab8fca2 4553 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4554 napi_enable(&hw->napi);
8ab8fca2 4555
f05267e7 4556 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4557 struct net_device *dev = hw->dev[i];
063a0b38
SH		 4558
4559 netif_device_attach(dev);
6a5706b9 4560 if (netif_running(dev)) {
08c06d8a
SH		 4561 err = sky2_up(dev);
4562 if (err) {
4563 printk(KERN_ERR PFX "%s: could not up: %d\n",
4564 dev->name, err);
68c28898 4565 rtnl_lock();
08c06d8a 4566 dev_close(dev);
68c28898 4567 rtnl_unlock();
eb35cf60 4568 goto out;
5afa0a9c 4569 }
cd28ab6a
SH		 4570 }
4571 }
eb35cf60 4572
ae306cca 4573 return 0;
08c06d8a 4574out:
b02a9258 4575 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4576 pci_disable_device(pdev);
08c06d8a 4577 return err;
cd28ab6a
SH		 4578}
4579#endif
4580
e3173832
SH		 4581static void sky2_shutdown(struct pci_dev *pdev)
4582{
4583 struct sky2_hw *hw = pci_get_drvdata(pdev);
4584 int i, wol = 0;
4585
549a68c3
SH		 4586 if (!hw)
4587 return;
4588
5c0d6b34 4589 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4590
4591 for (i = 0; i < hw->ports; i++) {
4592 struct net_device *dev = hw->dev[i];
4593 struct sky2_port *sky2 = netdev_priv(dev);
4594
4595 if (sky2->wol) {
4596 wol = 1;
4597 sky2_wol_init(sky2);
4598 }
4599 }
4600
4601 if (wol)
4602 sky2_power_aux(hw);
4603
4604 pci_enable_wake(pdev, PCI_D3hot, wol);
4605 pci_enable_wake(pdev, PCI_D3cold, wol);
4606
4607 pci_disable_device(pdev);
f71eb1a2 4608 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4609}
4610
cd28ab6a 4611static struct pci_driver sky2_driver = {
793b883e
SH		 4612 .name = DRV_NAME,
4613 .id_table = sky2_id_table,
4614 .probe = sky2_probe,
4615 .remove = __devexit_p(sky2_remove),
cd28ab6a 4616#ifdef CONFIG_PM
793b883e
SH		 4617 .suspend = sky2_suspend,
4618 .resume = sky2_resume,
cd28ab6a 4619#endif
e3173832 4620 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4621};
4622
4623static int __init sky2_init_module(void)
4624{
c844d483
SH		 4625 pr_info(PFX "driver version " DRV_VERSION "\n");
4626
3cf26753 4627 sky2_debug_init();
50241c4c 4628 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4629}
4630
4631static void __exit sky2_cleanup_module(void)
4632{
4633 pci_unregister_driver(&sky2_driver);
3cf26753 4634 sky2_debug_cleanup();
cd28ab6a
SH		 4635}
4636
4637module_init(sky2_init_module);
4638module_exit(sky2_cleanup_module);
4639
4640MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4641MODULE_AUTHOR("Stephen Hemminger <[email protected]>");
cd28ab6a 4642MODULE_LICENSE("GPL");
5f4f9dc1 4643MODULE_VERSION(DRV_VERSION);
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