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ASoC: arizona: call wm_adsp2_remove when codec driver is removed
[linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
cf17c83c 18#include <linux/list.h>
2159ad93
MB		 19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
973838a0 22#include <linux/regulator/consumer.h>
2159ad93 23#include <linux/slab.h>
cdcd7f72 24#include <linux/vmalloc.h>
6ab2b7b4 25#include <linux/workqueue.h>
f9f55e31 26#include <linux/debugfs.h>
2159ad93
MB		 27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/jack.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34
2159ad93
MB		 35#include "wm_adsp.h"
36
37#define adsp_crit(_dsp, fmt, ...) \
38 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
39#define adsp_err(_dsp, fmt, ...) \
40 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41#define adsp_warn(_dsp, fmt, ...) \
42 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43#define adsp_info(_dsp, fmt, ...) \
44 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45#define adsp_dbg(_dsp, fmt, ...) \
46 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
47
48#define ADSP1_CONTROL_1 0x00
49#define ADSP1_CONTROL_2 0x02
50#define ADSP1_CONTROL_3 0x03
51#define ADSP1_CONTROL_4 0x04
52#define ADSP1_CONTROL_5 0x06
53#define ADSP1_CONTROL_6 0x07
54#define ADSP1_CONTROL_7 0x08
55#define ADSP1_CONTROL_8 0x09
56#define ADSP1_CONTROL_9 0x0A
57#define ADSP1_CONTROL_10 0x0B
58#define ADSP1_CONTROL_11 0x0C
59#define ADSP1_CONTROL_12 0x0D
60#define ADSP1_CONTROL_13 0x0F
61#define ADSP1_CONTROL_14 0x10
62#define ADSP1_CONTROL_15 0x11
63#define ADSP1_CONTROL_16 0x12
64#define ADSP1_CONTROL_17 0x13
65#define ADSP1_CONTROL_18 0x14
66#define ADSP1_CONTROL_19 0x16
67#define ADSP1_CONTROL_20 0x17
68#define ADSP1_CONTROL_21 0x18
69#define ADSP1_CONTROL_22 0x1A
70#define ADSP1_CONTROL_23 0x1B
71#define ADSP1_CONTROL_24 0x1C
72#define ADSP1_CONTROL_25 0x1E
73#define ADSP1_CONTROL_26 0x20
74#define ADSP1_CONTROL_27 0x21
75#define ADSP1_CONTROL_28 0x22
76#define ADSP1_CONTROL_29 0x23
77#define ADSP1_CONTROL_30 0x24
78#define ADSP1_CONTROL_31 0x26
79
80/*
81 * ADSP1 Control 19
82 */
83#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
84#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86
87
88/*
89 * ADSP1 Control 30
90 */
91#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
92#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
93#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
94#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
95#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
96#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
97#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
98#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
99#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
100#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
101#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
102#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
103#define ADSP1_START 0x0001 /* DSP1_START */
104#define ADSP1_START_MASK 0x0001 /* DSP1_START */
105#define ADSP1_START_SHIFT 0 /* DSP1_START */
106#define ADSP1_START_WIDTH 1 /* DSP1_START */
107
94e205bf
CR		 108/*
109 * ADSP1 Control 31
110 */
111#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
112#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
113#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
114
2d30b575
MB		 115#define ADSP2_CONTROL 0x0
116#define ADSP2_CLOCKING 0x1
117#define ADSP2_STATUS1 0x4
118#define ADSP2_WDMA_CONFIG_1 0x30
119#define ADSP2_WDMA_CONFIG_2 0x31
120#define ADSP2_RDMA_CONFIG_1 0x34
2159ad93 121
10337b07
RF		 122#define ADSP2_SCRATCH0 0x40
123#define ADSP2_SCRATCH1 0x41
124#define ADSP2_SCRATCH2 0x42
125#define ADSP2_SCRATCH3 0x43
126
2159ad93
MB		 127/*
128 * ADSP2 Control
129 */
130
131#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
132#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
133#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
134#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
135#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
136#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
137#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
138#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
139#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
140#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
141#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
142#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
143#define ADSP2_START 0x0001 /* DSP1_START */
144#define ADSP2_START_MASK 0x0001 /* DSP1_START */
145#define ADSP2_START_SHIFT 0 /* DSP1_START */
146#define ADSP2_START_WIDTH 1 /* DSP1_START */
147
973838a0
MB		 148/*
149 * ADSP2 clocking
150 */
151#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
152#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
153#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
154
2159ad93
MB		 155/*
156 * ADSP2 Status 1
157 */
158#define ADSP2_RAM_RDY 0x0001
159#define ADSP2_RAM_RDY_MASK 0x0001
160#define ADSP2_RAM_RDY_SHIFT 0
161#define ADSP2_RAM_RDY_WIDTH 1
162
cf17c83c
MB		 163struct wm_adsp_buf {
164 struct list_head list;
165 void *buf;
166};
167
168static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
169 struct list_head *list)
170{
171 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
172
173 if (buf == NULL)
174 return NULL;
175
cdcd7f72 176 buf->buf = vmalloc(len);
cf17c83c 177 if (!buf->buf) {
cdcd7f72 178 vfree(buf);
cf17c83c
MB		 179 return NULL;
180 }
cdcd7f72 181 memcpy(buf->buf, src, len);
cf17c83c
MB		 182
183 if (list)
184 list_add_tail(&buf->list, list);
185
186 return buf;
187}
188
189static void wm_adsp_buf_free(struct list_head *list)
190{
191 while (!list_empty(list)) {
192 struct wm_adsp_buf *buf = list_first_entry(list,
193 struct wm_adsp_buf,
194 list);
195 list_del(&buf->list);
cdcd7f72 196 vfree(buf->buf);
cf17c83c
MB		 197 kfree(buf);
198 }
199}
200
04d1300f
CK		 201#define WM_ADSP_FW_MBC_VSS 0
202#define WM_ADSP_FW_HIFI 1
203#define WM_ADSP_FW_TX 2
204#define WM_ADSP_FW_TX_SPK 3
205#define WM_ADSP_FW_RX 4
206#define WM_ADSP_FW_RX_ANC 5
207#define WM_ADSP_FW_CTRL 6
208#define WM_ADSP_FW_ASR 7
209#define WM_ADSP_FW_TRACE 8
210#define WM_ADSP_FW_SPK_PROT 9
211#define WM_ADSP_FW_MISC 10
212
213#define WM_ADSP_NUM_FW 11
dd84f925 214
1023dbd9 215static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
04d1300f
CK		 216 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
217 [WM_ADSP_FW_HIFI] = "MasterHiFi",
218 [WM_ADSP_FW_TX] = "Tx",
219 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
220 [WM_ADSP_FW_RX] = "Rx",
221 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
222 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
223 [WM_ADSP_FW_ASR] = "ASR Assist",
224 [WM_ADSP_FW_TRACE] = "Dbg Trace",
225 [WM_ADSP_FW_SPK_PROT] = "Protection",
226 [WM_ADSP_FW_MISC] = "Misc",
1023dbd9
MB		 227};
228
2cd19bdb
CK		 229struct wm_adsp_system_config_xm_hdr {
230 __be32 sys_enable;
231 __be32 fw_id;
232 __be32 fw_rev;
233 __be32 boot_status;
234 __be32 watchdog;
235 __be32 dma_buffer_size;
236 __be32 rdma[6];
237 __be32 wdma[8];
238 __be32 build_job_name[3];
239 __be32 build_job_number;
240};
241
242struct wm_adsp_alg_xm_struct {
243 __be32 magic;
244 __be32 smoothing;
245 __be32 threshold;
246 __be32 host_buf_ptr;
247 __be32 start_seq;
248 __be32 high_water_mark;
249 __be32 low_water_mark;
250 __be64 smoothed_power;
251};
252
253struct wm_adsp_buffer {
254 __be32 X_buf_base; /* XM base addr of first X area */
255 __be32 X_buf_size; /* Size of 1st X area in words */
256 __be32 X_buf_base2; /* XM base addr of 2nd X area */
257 __be32 X_buf_brk; /* Total X size in words */
258 __be32 Y_buf_base; /* YM base addr of Y area */
259 __be32 wrap; /* Total size X and Y in words */
260 __be32 high_water_mark; /* Point at which IRQ is asserted */
261 __be32 irq_count; /* bits 1-31 count IRQ assertions */
262 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
263 __be32 next_write_index; /* word index of next write */
264 __be32 next_read_index; /* word index of next read */
265 __be32 error; /* error if any */
266 __be32 oldest_block_index; /* word index of oldest surviving */
267 __be32 requested_rewind; /* how many blocks rewind was done */
268 __be32 reserved_space; /* internal */
269 __be32 min_free; /* min free space since stream start */
270 __be32 blocks_written[2]; /* total blocks written (64 bit) */
271 __be32 words_written[2]; /* total words written (64 bit) */
272};
273
274struct wm_adsp_compr_buf {
275 struct wm_adsp *dsp;
276
277 struct wm_adsp_buffer_region *regions;
278 u32 host_buf_ptr;
565ace46
CK		 279
280 u32 error;
281 u32 irq_count;
282 int read_index;
283 int avail;
2cd19bdb
CK		 284};
285
406abc95
CK		 286struct wm_adsp_compr {
287 struct wm_adsp *dsp;
95fe9597 288 struct wm_adsp_compr_buf *buf;
406abc95
CK		 289
290 struct snd_compr_stream *stream;
291 struct snd_compressed_buffer size;
565ace46 292
83a40ce9 293 u32 *raw_buf;
565ace46 294 unsigned int copied_total;
da2b3358
CK		 295
296 unsigned int sample_rate;
406abc95
CK		 297};
298
299#define WM_ADSP_DATA_WORD_SIZE 3
300
301#define WM_ADSP_MIN_FRAGMENTS 1
302#define WM_ADSP_MAX_FRAGMENTS 256
303#define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
304#define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
305
2cd19bdb
CK		 306#define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
307
308#define HOST_BUFFER_FIELD(field) \
309 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
310
311#define ALG_XM_FIELD(field) \
312 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
313
314static int wm_adsp_buffer_init(struct wm_adsp *dsp);
315static int wm_adsp_buffer_free(struct wm_adsp *dsp);
316
317struct wm_adsp_buffer_region {
318 unsigned int offset;
319 unsigned int cumulative_size;
320 unsigned int mem_type;
321 unsigned int base_addr;
322};
323
324struct wm_adsp_buffer_region_def {
325 unsigned int mem_type;
326 unsigned int base_offset;
327 unsigned int size_offset;
328};
329
3a9686c4 330static const struct wm_adsp_buffer_region_def default_regions[] = {
2cd19bdb
CK		 331 {
332 .mem_type = WMFW_ADSP2_XM,
333 .base_offset = HOST_BUFFER_FIELD(X_buf_base),
334 .size_offset = HOST_BUFFER_FIELD(X_buf_size),
335 },
336 {
337 .mem_type = WMFW_ADSP2_XM,
338 .base_offset = HOST_BUFFER_FIELD(X_buf_base2),
339 .size_offset = HOST_BUFFER_FIELD(X_buf_brk),
340 },
341 {
342 .mem_type = WMFW_ADSP2_YM,
343 .base_offset = HOST_BUFFER_FIELD(Y_buf_base),
344 .size_offset = HOST_BUFFER_FIELD(wrap),
345 },
346};
347
406abc95
CK		 348struct wm_adsp_fw_caps {
349 u32 id;
350 struct snd_codec_desc desc;
2cd19bdb 351 int num_regions;
3a9686c4 352 const struct wm_adsp_buffer_region_def *region_defs;
406abc95
CK		 353};
354
e6d00f34 355static const struct wm_adsp_fw_caps ctrl_caps[] = {
406abc95
CK		 356 {
357 .id = SND_AUDIOCODEC_BESPOKE,
358 .desc = {
359 .max_ch = 1,
360 .sample_rates = { 16000 },
361 .num_sample_rates = 1,
362 .formats = SNDRV_PCM_FMTBIT_S16_LE,
363 },
e6d00f34
CK		 364 .num_regions = ARRAY_SIZE(default_regions),
365 .region_defs = default_regions,
406abc95
CK		 366 },
367};
368
7ce4283c
CK		 369static const struct wm_adsp_fw_caps trace_caps[] = {
370 {
371 .id = SND_AUDIOCODEC_BESPOKE,
372 .desc = {
373 .max_ch = 8,
374 .sample_rates = {
375 4000, 8000, 11025, 12000, 16000, 22050,
376 24000, 32000, 44100, 48000, 64000, 88200,
377 96000, 176400, 192000
378 },
379 .num_sample_rates = 15,
380 .formats = SNDRV_PCM_FMTBIT_S16_LE,
381 },
382 .num_regions = ARRAY_SIZE(default_regions),
383 .region_defs = default_regions,
406abc95
CK		 384 },
385};
386
387static const struct {
1023dbd9 388 const char *file;
406abc95
CK		 389 int compr_direction;
390 int num_caps;
391 const struct wm_adsp_fw_caps *caps;
1023dbd9 392} wm_adsp_fw[WM_ADSP_NUM_FW] = {
04d1300f
CK		 393 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
394 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
395 [WM_ADSP_FW_TX] = { .file = "tx" },
396 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
397 [WM_ADSP_FW_RX] = { .file = "rx" },
398 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
406abc95
CK		 399 [WM_ADSP_FW_CTRL] = {
400 .file = "ctrl",
401 .compr_direction = SND_COMPRESS_CAPTURE,
e6d00f34
CK		 402 .num_caps = ARRAY_SIZE(ctrl_caps),
403 .caps = ctrl_caps,
406abc95 404 },
04d1300f 405 [WM_ADSP_FW_ASR] = { .file = "asr" },
7ce4283c
CK		 406 [WM_ADSP_FW_TRACE] = {
407 .file = "trace",
408 .compr_direction = SND_COMPRESS_CAPTURE,
409 .num_caps = ARRAY_SIZE(trace_caps),
410 .caps = trace_caps,
411 },
04d1300f
CK		 412 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
413 [WM_ADSP_FW_MISC] = { .file = "misc" },
1023dbd9
MB		 414};
415
6ab2b7b4
DP		 416struct wm_coeff_ctl_ops {
417 int (*xget)(struct snd_kcontrol *kcontrol,
418 struct snd_ctl_elem_value *ucontrol);
419 int (*xput)(struct snd_kcontrol *kcontrol,
420 struct snd_ctl_elem_value *ucontrol);
421 int (*xinfo)(struct snd_kcontrol *kcontrol,
422 struct snd_ctl_elem_info *uinfo);
423};
424
6ab2b7b4
DP		 425struct wm_coeff_ctl {
426 const char *name;
2323736d 427 const char *fw_name;
3809f001 428 struct wm_adsp_alg_region alg_region;
6ab2b7b4 429 struct wm_coeff_ctl_ops ops;
3809f001 430 struct wm_adsp *dsp;
6ab2b7b4
DP		 431 unsigned int enabled:1;
432 struct list_head list;
433 void *cache;
2323736d 434 unsigned int offset;
6ab2b7b4 435 size_t len;
0c2e3f34 436 unsigned int set:1;
6ab2b7b4 437 struct snd_kcontrol *kcontrol;
26c22a19 438 unsigned int flags;
6ab2b7b4
DP		 439};
440
f9f55e31
RF		 441#ifdef CONFIG_DEBUG_FS
442static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
443{
444 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
445
f9f55e31
RF		 446 kfree(dsp->wmfw_file_name);
447 dsp->wmfw_file_name = tmp;
f9f55e31
RF		 448}
449
450static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
451{
452 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
453
f9f55e31
RF		 454 kfree(dsp->bin_file_name);
455 dsp->bin_file_name = tmp;
f9f55e31
RF		 456}
457
458static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
459{
f9f55e31
RF		 460 kfree(dsp->wmfw_file_name);
461 kfree(dsp->bin_file_name);
462 dsp->wmfw_file_name = NULL;
463 dsp->bin_file_name = NULL;
f9f55e31
RF		 464}
465
466static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
467 char __user *user_buf,
468 size_t count, loff_t *ppos)
469{
470 struct wm_adsp *dsp = file->private_data;
471 ssize_t ret;
472
078e7183 473 mutex_lock(&dsp->pwr_lock);
f9f55e31
RF		 474
475 if (!dsp->wmfw_file_name || !dsp->running)
476 ret = 0;
477 else
478 ret = simple_read_from_buffer(user_buf, count, ppos,
479 dsp->wmfw_file_name,
480 strlen(dsp->wmfw_file_name));
481
078e7183 482 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 483 return ret;
484}
485
486static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
487 char __user *user_buf,
488 size_t count, loff_t *ppos)
489{
490 struct wm_adsp *dsp = file->private_data;
491 ssize_t ret;
492
078e7183 493 mutex_lock(&dsp->pwr_lock);
f9f55e31
RF		 494
495 if (!dsp->bin_file_name || !dsp->running)
496 ret = 0;
497 else
498 ret = simple_read_from_buffer(user_buf, count, ppos,
499 dsp->bin_file_name,
500 strlen(dsp->bin_file_name));
501
078e7183 502 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 503 return ret;
504}
505
506static const struct {
507 const char *name;
508 const struct file_operations fops;
509} wm_adsp_debugfs_fops[] = {
510 {
511 .name = "wmfw_file_name",
512 .fops = {
513 .open = simple_open,
514 .read = wm_adsp_debugfs_wmfw_read,
515 },
516 },
517 {
518 .name = "bin_file_name",
519 .fops = {
520 .open = simple_open,
521 .read = wm_adsp_debugfs_bin_read,
522 },
523 },
524};
525
526static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
527 struct snd_soc_codec *codec)
528{
529 struct dentry *root = NULL;
530 char *root_name;
531 int i;
532
533 if (!codec->component.debugfs_root) {
534 adsp_err(dsp, "No codec debugfs root\n");
535 goto err;
536 }
537
538 root_name = kmalloc(PAGE_SIZE, GFP_KERNEL);
539 if (!root_name)
540 goto err;
541
542 snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num);
543 root = debugfs_create_dir(root_name, codec->component.debugfs_root);
544 kfree(root_name);
545
546 if (!root)
547 goto err;
548
549 if (!debugfs_create_bool("running", S_IRUGO, root, &dsp->running))
550 goto err;
551
552 if (!debugfs_create_x32("fw_id", S_IRUGO, root, &dsp->fw_id))
553 goto err;
554
555 if (!debugfs_create_x32("fw_version", S_IRUGO, root,
556 &dsp->fw_id_version))
557 goto err;
558
559 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
560 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
561 S_IRUGO, root, dsp,
562 &wm_adsp_debugfs_fops[i].fops))
563 goto err;
564 }
565
566 dsp->debugfs_root = root;
567 return;
568
569err:
570 debugfs_remove_recursive(root);
571 adsp_err(dsp, "Failed to create debugfs\n");
572}
573
574static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
575{
576 wm_adsp_debugfs_clear(dsp);
577 debugfs_remove_recursive(dsp->debugfs_root);
578}
579#else
580static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
581 struct snd_soc_codec *codec)
582{
583}
584
585static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
586{
587}
588
589static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
590 const char *s)
591{
592}
593
594static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
595 const char *s)
596{
597}
598
599static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
600{
601}
602#endif
603
1023dbd9
MB		 604static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
605 struct snd_ctl_elem_value *ucontrol)
606{
ea53bf77 607 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 608 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 609 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
1023dbd9 610
15c66570 611 ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
1023dbd9
MB		 612
613 return 0;
614}
615
616static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
617 struct snd_ctl_elem_value *ucontrol)
618{
ea53bf77 619 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 620 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 621 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
d27c5e15 622 int ret = 0;
1023dbd9 623
15c66570 624 if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
1023dbd9
MB		 625 return 0;
626
15c66570 627 if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
1023dbd9
MB		 628 return -EINVAL;
629
d27c5e15
CK		 630 mutex_lock(&dsp[e->shift_l].pwr_lock);
631
406abc95 632 if (dsp[e->shift_l].running || dsp[e->shift_l].compr)
d27c5e15
CK		 633 ret = -EBUSY;
634 else
15c66570 635 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
1023dbd9 636
d27c5e15 637 mutex_unlock(&dsp[e->shift_l].pwr_lock);
1023dbd9 638
d27c5e15 639 return ret;
1023dbd9
MB		 640}
641
642static const struct soc_enum wm_adsp_fw_enum[] = {
643 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
644 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
645 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
646 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
647};
648
336d0442 649const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
1023dbd9
MB		 650 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
651 wm_adsp_fw_get, wm_adsp_fw_put),
652 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
653 wm_adsp_fw_get, wm_adsp_fw_put),
654 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
655 wm_adsp_fw_get, wm_adsp_fw_put),
336d0442
RF		 656 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
657 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 658};
336d0442 659EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
2159ad93
MB		 660
661static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
662 int type)
663{
664 int i;
665
666 for (i = 0; i < dsp->num_mems; i++)
667 if (dsp->mem[i].type == type)
668 return &dsp->mem[i];
669
670 return NULL;
671}
672
3809f001 673static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
45b9ee72
MB		 674 unsigned int offset)
675{
3809f001 676 if (WARN_ON(!mem))
6c452bda 677 return offset;
3809f001 678 switch (mem->type) {
45b9ee72 679 case WMFW_ADSP1_PM:
3809f001 680 return mem->base + (offset * 3);
45b9ee72 681 case WMFW_ADSP1_DM:
3809f001 682 return mem->base + (offset * 2);
45b9ee72 683 case WMFW_ADSP2_XM:
3809f001 684 return mem->base + (offset * 2);
45b9ee72 685 case WMFW_ADSP2_YM:
3809f001 686 return mem->base + (offset * 2);
45b9ee72 687 case WMFW_ADSP1_ZM:
3809f001 688 return mem->base + (offset * 2);
45b9ee72 689 default:
6c452bda 690 WARN(1, "Unknown memory region type");
45b9ee72
MB		 691 return offset;
692 }
693}
694
10337b07
RF		 695static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
696{
697 u16 scratch[4];
698 int ret;
699
700 ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0,
701 scratch, sizeof(scratch));
702 if (ret) {
703 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
704 return;
705 }
706
707 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
708 be16_to_cpu(scratch[0]),
709 be16_to_cpu(scratch[1]),
710 be16_to_cpu(scratch[2]),
711 be16_to_cpu(scratch[3]));
712}
713
7585a5b0 714static int wm_coeff_info(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 715 struct snd_ctl_elem_info *uinfo)
716{
7585a5b0 717 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4
DP		 718
719 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
720 uinfo->count = ctl->len;
721 return 0;
722}
723
c9f8dd71 724static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 725 const void *buf, size_t len)
726{
3809f001 727 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
6ab2b7b4 728 const struct wm_adsp_region *mem;
3809f001 729 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 730 void *scratch;
731 int ret;
732 unsigned int reg;
733
3809f001 734 mem = wm_adsp_find_region(dsp, alg_region->type);
6ab2b7b4 735 if (!mem) {
3809f001
CK		 736 adsp_err(dsp, "No base for region %x\n",
737 alg_region->type);
6ab2b7b4
DP		 738 return -EINVAL;
739 }
740
2323736d 741 reg = ctl->alg_region.base + ctl->offset;
6ab2b7b4
DP		 742 reg = wm_adsp_region_to_reg(mem, reg);
743
4f8ea6d7 744 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
6ab2b7b4
DP		 745 if (!scratch)
746 return -ENOMEM;
747
3809f001 748 ret = regmap_raw_write(dsp->regmap, reg, scratch,
4f8ea6d7 749 len);
6ab2b7b4 750 if (ret) {
3809f001 751 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
4f8ea6d7 752 len, reg, ret);
6ab2b7b4
DP		 753 kfree(scratch);
754 return ret;
755 }
4f8ea6d7 756 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
6ab2b7b4
DP		 757
758 kfree(scratch);
759
760 return 0;
761}
762
7585a5b0 763static int wm_coeff_put(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 764 struct snd_ctl_elem_value *ucontrol)
765{
7585a5b0 766 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4 767 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 768 int ret = 0;
769
770 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4
DP		 771
772 memcpy(ctl->cache, p, ctl->len);
773
65d17a9c 774 ctl->set = 1;
168d10e7
CK		 775 if (ctl->enabled)
776 ret = wm_coeff_write_control(ctl, p, ctl->len);
6ab2b7b4 777
168d10e7
CK		 778 mutex_unlock(&ctl->dsp->pwr_lock);
779
780 return ret;
6ab2b7b4
DP		 781}
782
c9f8dd71 783static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 784 void *buf, size_t len)
785{
3809f001 786 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
6ab2b7b4 787 const struct wm_adsp_region *mem;
3809f001 788 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 789 void *scratch;
790 int ret;
791 unsigned int reg;
792
3809f001 793 mem = wm_adsp_find_region(dsp, alg_region->type);
6ab2b7b4 794 if (!mem) {
3809f001
CK		 795 adsp_err(dsp, "No base for region %x\n",
796 alg_region->type);
6ab2b7b4
DP		 797 return -EINVAL;
798 }
799
2323736d 800 reg = ctl->alg_region.base + ctl->offset;
6ab2b7b4
DP		 801 reg = wm_adsp_region_to_reg(mem, reg);
802
4f8ea6d7 803 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
6ab2b7b4
DP		 804 if (!scratch)
805 return -ENOMEM;
806
4f8ea6d7 807 ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
6ab2b7b4 808 if (ret) {
3809f001 809 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
5602a643 810 len, reg, ret);
6ab2b7b4
DP		 811 kfree(scratch);
812 return ret;
813 }
4f8ea6d7 814 adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
6ab2b7b4 815
4f8ea6d7 816 memcpy(buf, scratch, len);
6ab2b7b4
DP		 817 kfree(scratch);
818
819 return 0;
820}
821
7585a5b0 822static int wm_coeff_get(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 823 struct snd_ctl_elem_value *ucontrol)
824{
7585a5b0 825 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4 826 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 827 int ret = 0;
828
829 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4 830
26c22a19
CK		 831 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
832 if (ctl->enabled)
168d10e7 833 ret = wm_coeff_read_control(ctl, p, ctl->len);
26c22a19 834 else
168d10e7
CK		 835 ret = -EPERM;
836 } else {
bc1765d6
CK		 837 if (!ctl->flags && ctl->enabled)
838 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
839
168d10e7 840 memcpy(p, ctl->cache, ctl->len);
26c22a19
CK		 841 }
842
168d10e7 843 mutex_unlock(&ctl->dsp->pwr_lock);
26c22a19 844
168d10e7 845 return ret;
6ab2b7b4
DP		 846}
847
6ab2b7b4 848struct wmfw_ctl_work {
3809f001 849 struct wm_adsp *dsp;
6ab2b7b4
DP		 850 struct wm_coeff_ctl *ctl;
851 struct work_struct work;
852};
853
3809f001 854static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
6ab2b7b4
DP		 855{
856 struct snd_kcontrol_new *kcontrol;
857 int ret;
858
92bb4c32 859 if (!ctl || !ctl->name)
6ab2b7b4
DP		 860 return -EINVAL;
861
862 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
863 if (!kcontrol)
864 return -ENOMEM;
865 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
866
867 kcontrol->name = ctl->name;
868 kcontrol->info = wm_coeff_info;
869 kcontrol->get = wm_coeff_get;
870 kcontrol->put = wm_coeff_put;
871 kcontrol->private_value = (unsigned long)ctl;
872
26c22a19
CK		 873 if (ctl->flags) {
874 if (ctl->flags & WMFW_CTL_FLAG_WRITEABLE)
875 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
876 if (ctl->flags & WMFW_CTL_FLAG_READABLE)
877 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_READ;
878 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
879 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_VOLATILE;
cc815c4b
CK		 880 } else {
881 kcontrol->access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
882 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_VOLATILE;
26c22a19
CK		 883 }
884
7d00cd97 885 ret = snd_soc_add_card_controls(dsp->card, kcontrol, 1);
6ab2b7b4
DP		 886 if (ret < 0)
887 goto err_kcontrol;
888
889 kfree(kcontrol);
890
7d00cd97 891 ctl->kcontrol = snd_soc_card_get_kcontrol(dsp->card, ctl->name);
81ad93ec 892
6ab2b7b4
DP		 893 return 0;
894
895err_kcontrol:
896 kfree(kcontrol);
897 return ret;
898}
899
b21acc1c
CK		 900static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
901{
902 struct wm_coeff_ctl *ctl;
903 int ret;
904
905 list_for_each_entry(ctl, &dsp->ctl_list, list) {
906 if (!ctl->enabled || ctl->set)
907 continue;
26c22a19
CK		 908 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
909 continue;
910
7d00cd97 911 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
b21acc1c
CK		 912 if (ret < 0)
913 return ret;
914 }
915
916 return 0;
917}
918
919static int wm_coeff_sync_controls(struct wm_adsp *dsp)
920{
921 struct wm_coeff_ctl *ctl;
922 int ret;
923
924 list_for_each_entry(ctl, &dsp->ctl_list, list) {
925 if (!ctl->enabled)
926 continue;
26c22a19 927 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
7d00cd97 928 ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len);
b21acc1c
CK		 929 if (ret < 0)
930 return ret;
931 }
932 }
933
934 return 0;
935}
936
937static void wm_adsp_ctl_work(struct work_struct *work)
938{
939 struct wmfw_ctl_work *ctl_work = container_of(work,
940 struct wmfw_ctl_work,
941 work);
942
943 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
944 kfree(ctl_work);
945}
946
66225e98
RF		 947static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
948{
949 kfree(ctl->cache);
950 kfree(ctl->name);
951 kfree(ctl);
952}
953
b21acc1c
CK		 954static int wm_adsp_create_control(struct wm_adsp *dsp,
955 const struct wm_adsp_alg_region *alg_region,
2323736d 956 unsigned int offset, unsigned int len,
26c22a19
CK		 957 const char *subname, unsigned int subname_len,
958 unsigned int flags)
b21acc1c
CK		 959{
960 struct wm_coeff_ctl *ctl;
961 struct wmfw_ctl_work *ctl_work;
962 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
963 char *region_name;
964 int ret;
965
26c22a19
CK		 966 if (flags & WMFW_CTL_FLAG_SYS)
967 return 0;
968
b21acc1c
CK		 969 switch (alg_region->type) {
970 case WMFW_ADSP1_PM:
971 region_name = "PM";
972 break;
973 case WMFW_ADSP1_DM:
974 region_name = "DM";
975 break;
976 case WMFW_ADSP2_XM:
977 region_name = "XM";
978 break;
979 case WMFW_ADSP2_YM:
980 region_name = "YM";
981 break;
982 case WMFW_ADSP1_ZM:
983 region_name = "ZM";
984 break;
985 default:
2323736d 986 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
b21acc1c
CK		 987 return -EINVAL;
988 }
989
cb5b57a9
CK		 990 switch (dsp->fw_ver) {
991 case 0:
992 case 1:
993 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
994 dsp->num, region_name, alg_region->alg);
995 break;
996 default:
997 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
998 "DSP%d%c %.12s %x", dsp->num, *region_name,
999 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1000
1001 /* Truncate the subname from the start if it is too long */
1002 if (subname) {
1003 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1004 int skip = 0;
1005
1006 if (subname_len > avail)
1007 skip = subname_len - avail;
1008
1009 snprintf(name + ret,
1010 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
1011 subname_len - skip, subname + skip);
1012 }
1013 break;
1014 }
b21acc1c 1015
7585a5b0 1016 list_for_each_entry(ctl, &dsp->ctl_list, list) {
b21acc1c
CK		 1017 if (!strcmp(ctl->name, name)) {
1018 if (!ctl->enabled)
1019 ctl->enabled = 1;
1020 return 0;
1021 }
1022 }
1023
1024 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1025 if (!ctl)
1026 return -ENOMEM;
2323736d 1027 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
b21acc1c
CK		 1028 ctl->alg_region = *alg_region;
1029 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1030 if (!ctl->name) {
1031 ret = -ENOMEM;
1032 goto err_ctl;
1033 }
1034 ctl->enabled = 1;
1035 ctl->set = 0;
1036 ctl->ops.xget = wm_coeff_get;
1037 ctl->ops.xput = wm_coeff_put;
1038 ctl->dsp = dsp;
1039
26c22a19 1040 ctl->flags = flags;
2323736d 1041 ctl->offset = offset;
b21acc1c
CK		 1042 if (len > 512) {
1043 adsp_warn(dsp, "Truncating control %s from %d\n",
1044 ctl->name, len);
1045 len = 512;
1046 }
1047 ctl->len = len;
1048 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1049 if (!ctl->cache) {
1050 ret = -ENOMEM;
1051 goto err_ctl_name;
1052 }
1053
2323736d
CK		 1054 list_add(&ctl->list, &dsp->ctl_list);
1055
b21acc1c
CK		 1056 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1057 if (!ctl_work) {
1058 ret = -ENOMEM;
1059 goto err_ctl_cache;
1060 }
1061
1062 ctl_work->dsp = dsp;
1063 ctl_work->ctl = ctl;
1064 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1065 schedule_work(&ctl_work->work);
1066
1067 return 0;
1068
1069err_ctl_cache:
1070 kfree(ctl->cache);
1071err_ctl_name:
1072 kfree(ctl->name);
1073err_ctl:
1074 kfree(ctl);
1075
1076 return ret;
1077}
1078
2323736d
CK		 1079struct wm_coeff_parsed_alg {
1080 int id;
1081 const u8 *name;
1082 int name_len;
1083 int ncoeff;
1084};
1085
1086struct wm_coeff_parsed_coeff {
1087 int offset;
1088 int mem_type;
1089 const u8 *name;
1090 int name_len;
1091 int ctl_type;
1092 int flags;
1093 int len;
1094};
1095
cb5b57a9
CK		 1096static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1097{
1098 int length;
1099
1100 switch (bytes) {
1101 case 1:
1102 length = **pos;
1103 break;
1104 case 2:
8299ee81 1105 length = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 1106 break;
1107 default:
1108 return 0;
1109 }
1110
1111 if (str)
1112 *str = *pos + bytes;
1113
1114 *pos += ((length + bytes) + 3) & ~0x03;
1115
1116 return length;
1117}
1118
1119static int wm_coeff_parse_int(int bytes, const u8 **pos)
1120{
1121 int val = 0;
1122
1123 switch (bytes) {
1124 case 2:
8299ee81 1125 val = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 1126 break;
1127 case 4:
8299ee81 1128 val = le32_to_cpu(*((__le32 *)*pos));
cb5b57a9
CK		 1129 break;
1130 default:
1131 break;
1132 }
1133
1134 *pos += bytes;
1135
1136 return val;
1137}
1138
2323736d
CK		 1139static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1140 struct wm_coeff_parsed_alg *blk)
1141{
1142 const struct wmfw_adsp_alg_data *raw;
1143
cb5b57a9
CK		 1144 switch (dsp->fw_ver) {
1145 case 0:
1146 case 1:
1147 raw = (const struct wmfw_adsp_alg_data *)*data;
1148 *data = raw->data;
2323736d 1149
cb5b57a9
CK		 1150 blk->id = le32_to_cpu(raw->id);
1151 blk->name = raw->name;
1152 blk->name_len = strlen(raw->name);
1153 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1154 break;
1155 default:
1156 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1157 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1158 &blk->name);
1159 wm_coeff_parse_string(sizeof(u16), data, NULL);
1160 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1161 break;
1162 }
2323736d
CK		 1163
1164 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1165 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1166 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1167}
1168
1169static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1170 struct wm_coeff_parsed_coeff *blk)
1171{
1172 const struct wmfw_adsp_coeff_data *raw;
cb5b57a9
CK		 1173 const u8 *tmp;
1174 int length;
2323736d 1175
cb5b57a9
CK		 1176 switch (dsp->fw_ver) {
1177 case 0:
1178 case 1:
1179 raw = (const struct wmfw_adsp_coeff_data *)*data;
1180 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1181
1182 blk->offset = le16_to_cpu(raw->hdr.offset);
1183 blk->mem_type = le16_to_cpu(raw->hdr.type);
1184 blk->name = raw->name;
1185 blk->name_len = strlen(raw->name);
1186 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1187 blk->flags = le16_to_cpu(raw->flags);
1188 blk->len = le32_to_cpu(raw->len);
1189 break;
1190 default:
1191 tmp = *data;
1192 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1193 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1194 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1195 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1196 &blk->name);
1197 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1198 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1199 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1200 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1201 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1202
1203 *data = *data + sizeof(raw->hdr) + length;
1204 break;
1205 }
2323736d
CK		 1206
1207 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1208 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1209 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1210 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1211 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1212 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1213}
1214
1215static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1216 const struct wmfw_region *region)
1217{
1218 struct wm_adsp_alg_region alg_region = {};
1219 struct wm_coeff_parsed_alg alg_blk;
1220 struct wm_coeff_parsed_coeff coeff_blk;
1221 const u8 *data = region->data;
1222 int i, ret;
1223
1224 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1225 for (i = 0; i < alg_blk.ncoeff; i++) {
1226 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1227
1228 switch (coeff_blk.ctl_type) {
1229 case SNDRV_CTL_ELEM_TYPE_BYTES:
1230 break;
1231 default:
1232 adsp_err(dsp, "Unknown control type: %d\n",
1233 coeff_blk.ctl_type);
1234 return -EINVAL;
1235 }
1236
1237 alg_region.type = coeff_blk.mem_type;
1238 alg_region.alg = alg_blk.id;
1239
1240 ret = wm_adsp_create_control(dsp, &alg_region,
1241 coeff_blk.offset,
1242 coeff_blk.len,
1243 coeff_blk.name,
26c22a19
CK		 1244 coeff_blk.name_len,
1245 coeff_blk.flags);
2323736d
CK		 1246 if (ret < 0)
1247 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1248 coeff_blk.name_len, coeff_blk.name, ret);
1249 }
1250
1251 return 0;
1252}
1253
2159ad93
MB		 1254static int wm_adsp_load(struct wm_adsp *dsp)
1255{
cf17c83c 1256 LIST_HEAD(buf_list);
2159ad93
MB		 1257 const struct firmware *firmware;
1258 struct regmap *regmap = dsp->regmap;
1259 unsigned int pos = 0;
1260 const struct wmfw_header *header;
1261 const struct wmfw_adsp1_sizes *adsp1_sizes;
1262 const struct wmfw_adsp2_sizes *adsp2_sizes;
1263 const struct wmfw_footer *footer;
1264 const struct wmfw_region *region;
1265 const struct wm_adsp_region *mem;
1266 const char *region_name;
1267 char *file, *text;
cf17c83c 1268 struct wm_adsp_buf *buf;
2159ad93
MB		 1269 unsigned int reg;
1270 int regions = 0;
1271 int ret, offset, type, sizes;
1272
1273 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1274 if (file == NULL)
1275 return -ENOMEM;
1276
1023dbd9
MB		 1277 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
1278 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1279 file[PAGE_SIZE - 1] = '\0';
1280
1281 ret = request_firmware(&firmware, file, dsp->dev);
1282 if (ret != 0) {
1283 adsp_err(dsp, "Failed to request '%s'\n", file);
1284 goto out;
1285 }
1286 ret = -EINVAL;
1287
1288 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1289 if (pos >= firmware->size) {
1290 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1291 file, firmware->size);
1292 goto out_fw;
1293 }
1294
7585a5b0 1295 header = (void *)&firmware->data[0];
2159ad93
MB		 1296
1297 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1298 adsp_err(dsp, "%s: invalid magic\n", file);
1299 goto out_fw;
1300 }
1301
2323736d
CK		 1302 switch (header->ver) {
1303 case 0:
c61e59fe
CK		 1304 adsp_warn(dsp, "%s: Depreciated file format %d\n",
1305 file, header->ver);
1306 break;
2323736d 1307 case 1:
cb5b57a9 1308 case 2:
2323736d
CK		 1309 break;
1310 default:
2159ad93
MB		 1311 adsp_err(dsp, "%s: unknown file format %d\n",
1312 file, header->ver);
1313 goto out_fw;
1314 }
2323736d 1315
3626992a 1316 adsp_info(dsp, "Firmware version: %d\n", header->ver);
2323736d 1317 dsp->fw_ver = header->ver;
2159ad93
MB		 1318
1319 if (header->core != dsp->type) {
1320 adsp_err(dsp, "%s: invalid core %d != %d\n",
1321 file, header->core, dsp->type);
1322 goto out_fw;
1323 }
1324
1325 switch (dsp->type) {
1326 case WMFW_ADSP1:
1327 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1328 adsp1_sizes = (void *)&(header[1]);
1329 footer = (void *)&(adsp1_sizes[1]);
1330 sizes = sizeof(*adsp1_sizes);
1331
1332 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
1333 file, le32_to_cpu(adsp1_sizes->dm),
1334 le32_to_cpu(adsp1_sizes->pm),
1335 le32_to_cpu(adsp1_sizes->zm));
1336 break;
1337
1338 case WMFW_ADSP2:
1339 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1340 adsp2_sizes = (void *)&(header[1]);
1341 footer = (void *)&(adsp2_sizes[1]);
1342 sizes = sizeof(*adsp2_sizes);
1343
1344 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1345 file, le32_to_cpu(adsp2_sizes->xm),
1346 le32_to_cpu(adsp2_sizes->ym),
1347 le32_to_cpu(adsp2_sizes->pm),
1348 le32_to_cpu(adsp2_sizes->zm));
1349 break;
1350
1351 default:
6c452bda 1352 WARN(1, "Unknown DSP type");
2159ad93
MB		 1353 goto out_fw;
1354 }
1355
1356 if (le32_to_cpu(header->len) != sizeof(*header) +
1357 sizes + sizeof(*footer)) {
1358 adsp_err(dsp, "%s: unexpected header length %d\n",
1359 file, le32_to_cpu(header->len));
1360 goto out_fw;
1361 }
1362
1363 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1364 le64_to_cpu(footer->timestamp));
1365
1366 while (pos < firmware->size &&
1367 pos - firmware->size > sizeof(*region)) {
1368 region = (void *)&(firmware->data[pos]);
1369 region_name = "Unknown";
1370 reg = 0;
1371 text = NULL;
1372 offset = le32_to_cpu(region->offset) & 0xffffff;
1373 type = be32_to_cpu(region->type) & 0xff;
1374 mem = wm_adsp_find_region(dsp, type);
7585a5b0 1375
2159ad93
MB		 1376 switch (type) {
1377 case WMFW_NAME_TEXT:
1378 region_name = "Firmware name";
1379 text = kzalloc(le32_to_cpu(region->len) + 1,
1380 GFP_KERNEL);
1381 break;
2323736d
CK		 1382 case WMFW_ALGORITHM_DATA:
1383 region_name = "Algorithm";
1384 ret = wm_adsp_parse_coeff(dsp, region);
1385 if (ret != 0)
1386 goto out_fw;
1387 break;
2159ad93
MB		 1388 case WMFW_INFO_TEXT:
1389 region_name = "Information";
1390 text = kzalloc(le32_to_cpu(region->len) + 1,
1391 GFP_KERNEL);
1392 break;
1393 case WMFW_ABSOLUTE:
1394 region_name = "Absolute";
1395 reg = offset;
1396 break;
1397 case WMFW_ADSP1_PM:
2159ad93 1398 region_name = "PM";
45b9ee72 1399 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1400 break;
1401 case WMFW_ADSP1_DM:
2159ad93 1402 region_name = "DM";
45b9ee72 1403 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1404 break;
1405 case WMFW_ADSP2_XM:
2159ad93 1406 region_name = "XM";
45b9ee72 1407 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1408 break;
1409 case WMFW_ADSP2_YM:
2159ad93 1410 region_name = "YM";
45b9ee72 1411 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1412 break;
1413 case WMFW_ADSP1_ZM:
2159ad93 1414 region_name = "ZM";
45b9ee72 1415 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1416 break;
1417 default:
1418 adsp_warn(dsp,
1419 "%s.%d: Unknown region type %x at %d(%x)\n",
1420 file, regions, type, pos, pos);
1421 break;
1422 }
1423
1424 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1425 regions, le32_to_cpu(region->len), offset,
1426 region_name);
1427
1428 if (text) {
1429 memcpy(text, region->data, le32_to_cpu(region->len));
1430 adsp_info(dsp, "%s: %s\n", file, text);
1431 kfree(text);
1432 }
1433
1434 if (reg) {
cdcd7f72
CK		 1435 buf = wm_adsp_buf_alloc(region->data,
1436 le32_to_cpu(region->len),
1437 &buf_list);
1438 if (!buf) {
1439 adsp_err(dsp, "Out of memory\n");
1440 ret = -ENOMEM;
1441 goto out_fw;
1442 }
c1a7898d 1443
cdcd7f72
CK		 1444 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1445 le32_to_cpu(region->len));
1446 if (ret != 0) {
1447 adsp_err(dsp,
1448 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1449 file, regions,
1450 le32_to_cpu(region->len), offset,
1451 region_name, ret);
1452 goto out_fw;
2159ad93
MB		 1453 }
1454 }
1455
1456 pos += le32_to_cpu(region->len) + sizeof(*region);
1457 regions++;
1458 }
cf17c83c
MB		 1459
1460 ret = regmap_async_complete(regmap);
1461 if (ret != 0) {
1462 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1463 goto out_fw;
1464 }
1465
2159ad93
MB		 1466 if (pos > firmware->size)
1467 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1468 file, regions, pos - firmware->size);
1469
f9f55e31
RF		 1470 wm_adsp_debugfs_save_wmfwname(dsp, file);
1471
2159ad93 1472out_fw:
cf17c83c
MB		 1473 regmap_async_complete(regmap);
1474 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1475 release_firmware(firmware);
1476out:
1477 kfree(file);
1478
1479 return ret;
1480}
1481
2323736d
CK		 1482static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1483 const struct wm_adsp_alg_region *alg_region)
1484{
1485 struct wm_coeff_ctl *ctl;
1486
1487 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1488 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1489 alg_region->alg == ctl->alg_region.alg &&
1490 alg_region->type == ctl->alg_region.type) {
1491 ctl->alg_region.base = alg_region->base;
1492 }
1493 }
1494}
1495
3809f001 1496static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
b618a185 1497 unsigned int pos, unsigned int len)
db40517c 1498{
b618a185
CK		 1499 void *alg;
1500 int ret;
db40517c 1501 __be32 val;
db40517c 1502
3809f001 1503 if (n_algs == 0) {
b618a185
CK		 1504 adsp_err(dsp, "No algorithms\n");
1505 return ERR_PTR(-EINVAL);
db40517c
MB		 1506 }
1507
3809f001
CK		 1508 if (n_algs > 1024) {
1509 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
b618a185
CK		 1510 return ERR_PTR(-EINVAL);
1511 }
db40517c 1512
b618a185
CK		 1513 /* Read the terminator first to validate the length */
1514 ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val));
1515 if (ret != 0) {
1516 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1517 ret);
1518 return ERR_PTR(ret);
1519 }
db40517c 1520
b618a185
CK		 1521 if (be32_to_cpu(val) != 0xbedead)
1522 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1523 pos + len, be32_to_cpu(val));
d62f4bc6 1524
b618a185
CK		 1525 alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA);
1526 if (!alg)
1527 return ERR_PTR(-ENOMEM);
db40517c 1528
b618a185
CK		 1529 ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2);
1530 if (ret != 0) {
7d00cd97 1531 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
b618a185
CK		 1532 kfree(alg);
1533 return ERR_PTR(ret);
1534 }
ac50009f 1535
b618a185
CK		 1536 return alg;
1537}
ac50009f 1538
14197095
CK		 1539static struct wm_adsp_alg_region *
1540 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
1541{
1542 struct wm_adsp_alg_region *alg_region;
1543
1544 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
1545 if (id == alg_region->alg && type == alg_region->type)
1546 return alg_region;
1547 }
1548
1549 return NULL;
1550}
1551
d9d20e17
CK		 1552static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1553 int type, __be32 id,
1554 __be32 base)
1555{
1556 struct wm_adsp_alg_region *alg_region;
1557
1558 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1559 if (!alg_region)
1560 return ERR_PTR(-ENOMEM);
1561
1562 alg_region->type = type;
1563 alg_region->alg = be32_to_cpu(id);
1564 alg_region->base = be32_to_cpu(base);
1565
1566 list_add_tail(&alg_region->list, &dsp->alg_regions);
1567
2323736d
CK		 1568 if (dsp->fw_ver > 0)
1569 wm_adsp_ctl_fixup_base(dsp, alg_region);
1570
d9d20e17
CK		 1571 return alg_region;
1572}
1573
b618a185
CK		 1574static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1575{
1576 struct wmfw_adsp1_id_hdr adsp1_id;
1577 struct wmfw_adsp1_alg_hdr *adsp1_alg;
3809f001 1578 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1579 const struct wm_adsp_region *mem;
1580 unsigned int pos, len;
3809f001 1581 size_t n_algs;
b618a185 1582 int i, ret;
db40517c 1583
b618a185
CK		 1584 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1585 if (WARN_ON(!mem))
1586 return -EINVAL;
1587
1588 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1589 sizeof(adsp1_id));
1590 if (ret != 0) {
1591 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1592 ret);
1593 return ret;
1594 }
db40517c 1595
3809f001 1596 n_algs = be32_to_cpu(adsp1_id.n_algs);
b618a185
CK		 1597 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
1598 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1599 dsp->fw_id,
1600 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
1601 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
1602 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
3809f001 1603 n_algs);
b618a185 1604
d9d20e17
CK		 1605 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1606 adsp1_id.fw.id, adsp1_id.zm);
1607 if (IS_ERR(alg_region))
1608 return PTR_ERR(alg_region);
d62f4bc6 1609
d9d20e17
CK		 1610 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1611 adsp1_id.fw.id, adsp1_id.dm);
1612 if (IS_ERR(alg_region))
1613 return PTR_ERR(alg_region);
db40517c 1614
b618a185 1615 pos = sizeof(adsp1_id) / 2;
3809f001 1616 len = (sizeof(*adsp1_alg) * n_algs) / 2;
b618a185 1617
3809f001 1618 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1619 if (IS_ERR(adsp1_alg))
1620 return PTR_ERR(adsp1_alg);
1621
3809f001 1622 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1623 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1624 i, be32_to_cpu(adsp1_alg[i].alg.id),
1625 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1626 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
1627 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1628 be32_to_cpu(adsp1_alg[i].dm),
1629 be32_to_cpu(adsp1_alg[i].zm));
ac50009f 1630
d9d20e17
CK		 1631 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1632 adsp1_alg[i].alg.id,
1633 adsp1_alg[i].dm);
1634 if (IS_ERR(alg_region)) {
1635 ret = PTR_ERR(alg_region);
b618a185
CK		 1636 goto out;
1637 }
2323736d
CK		 1638 if (dsp->fw_ver == 0) {
1639 if (i + 1 < n_algs) {
1640 len = be32_to_cpu(adsp1_alg[i + 1].dm);
1641 len -= be32_to_cpu(adsp1_alg[i].dm);
1642 len *= 4;
1643 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1644 len, NULL, 0, 0);
2323736d
CK		 1645 } else {
1646 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1647 be32_to_cpu(adsp1_alg[i].alg.id));
1648 }
b618a185 1649 }
ac50009f 1650
d9d20e17
CK		 1651 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1652 adsp1_alg[i].alg.id,
1653 adsp1_alg[i].zm);
1654 if (IS_ERR(alg_region)) {
1655 ret = PTR_ERR(alg_region);
b618a185
CK		 1656 goto out;
1657 }
2323736d
CK		 1658 if (dsp->fw_ver == 0) {
1659 if (i + 1 < n_algs) {
1660 len = be32_to_cpu(adsp1_alg[i + 1].zm);
1661 len -= be32_to_cpu(adsp1_alg[i].zm);
1662 len *= 4;
1663 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1664 len, NULL, 0, 0);
2323736d
CK		 1665 } else {
1666 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1667 be32_to_cpu(adsp1_alg[i].alg.id));
1668 }
b618a185 1669 }
db40517c
MB		 1670 }
1671
b618a185
CK		 1672out:
1673 kfree(adsp1_alg);
1674 return ret;
1675}
db40517c 1676
b618a185
CK		 1677static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
1678{
1679 struct wmfw_adsp2_id_hdr adsp2_id;
1680 struct wmfw_adsp2_alg_hdr *adsp2_alg;
3809f001 1681 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1682 const struct wm_adsp_region *mem;
1683 unsigned int pos, len;
3809f001 1684 size_t n_algs;
b618a185
CK		 1685 int i, ret;
1686
1687 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
1688 if (WARN_ON(!mem))
d62f4bc6 1689 return -EINVAL;
d62f4bc6 1690
b618a185
CK		 1691 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
1692 sizeof(adsp2_id));
db40517c 1693 if (ret != 0) {
b618a185
CK		 1694 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1695 ret);
db40517c
MB		 1696 return ret;
1697 }
1698
3809f001 1699 n_algs = be32_to_cpu(adsp2_id.n_algs);
b618a185 1700 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
f9f55e31 1701 dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
b618a185
CK		 1702 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1703 dsp->fw_id,
f9f55e31
RF		 1704 (dsp->fw_id_version & 0xff0000) >> 16,
1705 (dsp->fw_id_version & 0xff00) >> 8,
1706 dsp->fw_id_version & 0xff,
3809f001 1707 n_algs);
b618a185 1708
d9d20e17
CK		 1709 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1710 adsp2_id.fw.id, adsp2_id.xm);
1711 if (IS_ERR(alg_region))
1712 return PTR_ERR(alg_region);
db40517c 1713
d9d20e17
CK		 1714 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1715 adsp2_id.fw.id, adsp2_id.ym);
1716 if (IS_ERR(alg_region))
1717 return PTR_ERR(alg_region);
db40517c 1718
d9d20e17
CK		 1719 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1720 adsp2_id.fw.id, adsp2_id.zm);
1721 if (IS_ERR(alg_region))
1722 return PTR_ERR(alg_region);
db40517c 1723
b618a185 1724 pos = sizeof(adsp2_id) / 2;
3809f001 1725 len = (sizeof(*adsp2_alg) * n_algs) / 2;
db40517c 1726
3809f001 1727 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1728 if (IS_ERR(adsp2_alg))
1729 return PTR_ERR(adsp2_alg);
471f4885 1730
3809f001 1731 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1732 adsp_info(dsp,
1733 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1734 i, be32_to_cpu(adsp2_alg[i].alg.id),
1735 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1736 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
1737 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1738 be32_to_cpu(adsp2_alg[i].xm),
1739 be32_to_cpu(adsp2_alg[i].ym),
1740 be32_to_cpu(adsp2_alg[i].zm));
db40517c 1741
d9d20e17
CK		 1742 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1743 adsp2_alg[i].alg.id,
1744 adsp2_alg[i].xm);
1745 if (IS_ERR(alg_region)) {
1746 ret = PTR_ERR(alg_region);
b618a185
CK		 1747 goto out;
1748 }
2323736d
CK		 1749 if (dsp->fw_ver == 0) {
1750 if (i + 1 < n_algs) {
1751 len = be32_to_cpu(adsp2_alg[i + 1].xm);
1752 len -= be32_to_cpu(adsp2_alg[i].xm);
1753 len *= 4;
1754 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1755 len, NULL, 0, 0);
2323736d
CK		 1756 } else {
1757 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1758 be32_to_cpu(adsp2_alg[i].alg.id));
1759 }
b618a185 1760 }
471f4885 1761
d9d20e17
CK		 1762 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1763 adsp2_alg[i].alg.id,
1764 adsp2_alg[i].ym);
1765 if (IS_ERR(alg_region)) {
1766 ret = PTR_ERR(alg_region);
b618a185
CK		 1767 goto out;
1768 }
2323736d
CK		 1769 if (dsp->fw_ver == 0) {
1770 if (i + 1 < n_algs) {
1771 len = be32_to_cpu(adsp2_alg[i + 1].ym);
1772 len -= be32_to_cpu(adsp2_alg[i].ym);
1773 len *= 4;
1774 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1775 len, NULL, 0, 0);
2323736d
CK		 1776 } else {
1777 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1778 be32_to_cpu(adsp2_alg[i].alg.id));
1779 }
b618a185 1780 }
471f4885 1781
d9d20e17
CK		 1782 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1783 adsp2_alg[i].alg.id,
1784 adsp2_alg[i].zm);
1785 if (IS_ERR(alg_region)) {
1786 ret = PTR_ERR(alg_region);
b618a185
CK		 1787 goto out;
1788 }
2323736d
CK		 1789 if (dsp->fw_ver == 0) {
1790 if (i + 1 < n_algs) {
1791 len = be32_to_cpu(adsp2_alg[i + 1].zm);
1792 len -= be32_to_cpu(adsp2_alg[i].zm);
1793 len *= 4;
1794 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1795 len, NULL, 0, 0);
2323736d
CK		 1796 } else {
1797 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1798 be32_to_cpu(adsp2_alg[i].alg.id));
1799 }
db40517c
MB		 1800 }
1801 }
1802
1803out:
b618a185 1804 kfree(adsp2_alg);
db40517c
MB		 1805 return ret;
1806}
1807
2159ad93
MB		 1808static int wm_adsp_load_coeff(struct wm_adsp *dsp)
1809{
cf17c83c 1810 LIST_HEAD(buf_list);
2159ad93
MB		 1811 struct regmap *regmap = dsp->regmap;
1812 struct wmfw_coeff_hdr *hdr;
1813 struct wmfw_coeff_item *blk;
1814 const struct firmware *firmware;
471f4885
MB		 1815 const struct wm_adsp_region *mem;
1816 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 1817 const char *region_name;
1818 int ret, pos, blocks, type, offset, reg;
1819 char *file;
cf17c83c 1820 struct wm_adsp_buf *buf;
2159ad93
MB		 1821
1822 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1823 if (file == NULL)
1824 return -ENOMEM;
1825
1023dbd9
MB		 1826 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
1827 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1828 file[PAGE_SIZE - 1] = '\0';
1829
1830 ret = request_firmware(&firmware, file, dsp->dev);
1831 if (ret != 0) {
1832 adsp_warn(dsp, "Failed to request '%s'\n", file);
1833 ret = 0;
1834 goto out;
1835 }
1836 ret = -EINVAL;
1837
1838 if (sizeof(*hdr) >= firmware->size) {
1839 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1840 file, firmware->size);
1841 goto out_fw;
1842 }
1843
7585a5b0 1844 hdr = (void *)&firmware->data[0];
2159ad93
MB		 1845 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
1846 adsp_err(dsp, "%s: invalid magic\n", file);
a4cdbec7 1847 goto out_fw;
2159ad93
MB		 1848 }
1849
c712326d
MB		 1850 switch (be32_to_cpu(hdr->rev) & 0xff) {
1851 case 1:
1852 break;
1853 default:
1854 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
1855 file, be32_to_cpu(hdr->rev) & 0xff);
1856 ret = -EINVAL;
1857 goto out_fw;
1858 }
1859
2159ad93
MB		 1860 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
1861 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
1862 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
1863 le32_to_cpu(hdr->ver) & 0xff);
1864
1865 pos = le32_to_cpu(hdr->len);
1866
1867 blocks = 0;
1868 while (pos < firmware->size &&
1869 pos - firmware->size > sizeof(*blk)) {
7585a5b0 1870 blk = (void *)(&firmware->data[pos]);
2159ad93 1871
c712326d
MB		 1872 type = le16_to_cpu(blk->type);
1873 offset = le16_to_cpu(blk->offset);
2159ad93
MB		 1874
1875 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
1876 file, blocks, le32_to_cpu(blk->id),
1877 (le32_to_cpu(blk->ver) >> 16) & 0xff,
1878 (le32_to_cpu(blk->ver) >> 8) & 0xff,
1879 le32_to_cpu(blk->ver) & 0xff);
1880 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
1881 file, blocks, le32_to_cpu(blk->len), offset, type);
1882
1883 reg = 0;
1884 region_name = "Unknown";
1885 switch (type) {
c712326d
MB		 1886 case (WMFW_NAME_TEXT << 8):
1887 case (WMFW_INFO_TEXT << 8):
2159ad93 1888 break;
c712326d 1889 case (WMFW_ABSOLUTE << 8):
f395a218
MB		 1890 /*
1891 * Old files may use this for global
1892 * coefficients.
1893 */
1894 if (le32_to_cpu(blk->id) == dsp->fw_id &&
1895 offset == 0) {
1896 region_name = "global coefficients";
1897 mem = wm_adsp_find_region(dsp, type);
1898 if (!mem) {
1899 adsp_err(dsp, "No ZM\n");
1900 break;
1901 }
1902 reg = wm_adsp_region_to_reg(mem, 0);
1903
1904 } else {
1905 region_name = "register";
1906 reg = offset;
1907 }
2159ad93 1908 break;
471f4885
MB		 1909
1910 case WMFW_ADSP1_DM:
1911 case WMFW_ADSP1_ZM:
1912 case WMFW_ADSP2_XM:
1913 case WMFW_ADSP2_YM:
1914 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
1915 file, blocks, le32_to_cpu(blk->len),
1916 type, le32_to_cpu(blk->id));
1917
1918 mem = wm_adsp_find_region(dsp, type);
1919 if (!mem) {
1920 adsp_err(dsp, "No base for region %x\n", type);
1921 break;
1922 }
1923
14197095
CK		 1924 alg_region = wm_adsp_find_alg_region(dsp, type,
1925 le32_to_cpu(blk->id));
1926 if (alg_region) {
1927 reg = alg_region->base;
1928 reg = wm_adsp_region_to_reg(mem, reg);
1929 reg += offset;
1930 } else {
471f4885
MB		 1931 adsp_err(dsp, "No %x for algorithm %x\n",
1932 type, le32_to_cpu(blk->id));
14197095 1933 }
471f4885
MB		 1934 break;
1935
2159ad93 1936 default:
25c62f7e
MB		 1937 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
1938 file, blocks, type, pos);
2159ad93
MB		 1939 break;
1940 }
1941
1942 if (reg) {
cf17c83c
MB		 1943 buf = wm_adsp_buf_alloc(blk->data,
1944 le32_to_cpu(blk->len),
1945 &buf_list);
a76fefab
MB		 1946 if (!buf) {
1947 adsp_err(dsp, "Out of memory\n");
f4b82812
WY		 1948 ret = -ENOMEM;
1949 goto out_fw;
a76fefab
MB		 1950 }
1951
20da6d5a
MB		 1952 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
1953 file, blocks, le32_to_cpu(blk->len),
1954 reg);
cf17c83c
MB		 1955 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1956 le32_to_cpu(blk->len));
2159ad93
MB		 1957 if (ret != 0) {
1958 adsp_err(dsp,
43bc3bf6
DP		 1959 "%s.%d: Failed to write to %x in %s: %d\n",
1960 file, blocks, reg, region_name, ret);
2159ad93
MB		 1961 }
1962 }
1963
be951017 1964 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2159ad93
MB		 1965 blocks++;
1966 }
1967
cf17c83c
MB		 1968 ret = regmap_async_complete(regmap);
1969 if (ret != 0)
1970 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1971
2159ad93
MB		 1972 if (pos > firmware->size)
1973 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1974 file, blocks, pos - firmware->size);
1975
f9f55e31
RF		 1976 wm_adsp_debugfs_save_binname(dsp, file);
1977
2159ad93 1978out_fw:
9da7a5a9 1979 regmap_async_complete(regmap);
2159ad93 1980 release_firmware(firmware);
cf17c83c 1981 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1982out:
1983 kfree(file);
f4b82812 1984 return ret;
2159ad93
MB		 1985}
1986
3809f001 1987int wm_adsp1_init(struct wm_adsp *dsp)
5e7a7a22 1988{
3809f001 1989 INIT_LIST_HEAD(&dsp->alg_regions);
5e7a7a22 1990
078e7183
CK		 1991 mutex_init(&dsp->pwr_lock);
1992
5e7a7a22
MB		 1993 return 0;
1994}
1995EXPORT_SYMBOL_GPL(wm_adsp1_init);
1996
2159ad93
MB		 1997int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1998 struct snd_kcontrol *kcontrol,
1999 int event)
2000{
72718517 2001 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2159ad93
MB		 2002 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2003 struct wm_adsp *dsp = &dsps[w->shift];
b0101b4f 2004 struct wm_adsp_alg_region *alg_region;
6ab2b7b4 2005 struct wm_coeff_ctl *ctl;
2159ad93 2006 int ret;
7585a5b0 2007 unsigned int val;
2159ad93 2008
00200107 2009 dsp->card = codec->component.card;
92bb4c32 2010
078e7183
CK		 2011 mutex_lock(&dsp->pwr_lock);
2012
2159ad93
MB		 2013 switch (event) {
2014 case SND_SOC_DAPM_POST_PMU:
2015 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2016 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2017
94e205bf
CR		 2018 /*
2019 * For simplicity set the DSP clock rate to be the
2020 * SYSCLK rate rather than making it configurable.
2021 */
7585a5b0 2022 if (dsp->sysclk_reg) {
94e205bf
CR		 2023 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2024 if (ret != 0) {
2025 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2026 ret);
078e7183 2027 goto err_mutex;
94e205bf
CR		 2028 }
2029
7d00cd97 2030 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
94e205bf
CR		 2031
2032 ret = regmap_update_bits(dsp->regmap,
2033 dsp->base + ADSP1_CONTROL_31,
2034 ADSP1_CLK_SEL_MASK, val);
2035 if (ret != 0) {
2036 adsp_err(dsp, "Failed to set clock rate: %d\n",
2037 ret);
078e7183 2038 goto err_mutex;
94e205bf
CR		 2039 }
2040 }
2041
2159ad93
MB		 2042 ret = wm_adsp_load(dsp);
2043 if (ret != 0)
078e7183 2044 goto err_ena;
2159ad93 2045
b618a185 2046 ret = wm_adsp1_setup_algs(dsp);
db40517c 2047 if (ret != 0)
078e7183 2048 goto err_ena;
db40517c 2049
2159ad93
MB		 2050 ret = wm_adsp_load_coeff(dsp);
2051 if (ret != 0)
078e7183 2052 goto err_ena;
2159ad93 2053
0c2e3f34 2054 /* Initialize caches for enabled and unset controls */
81ad93ec 2055 ret = wm_coeff_init_control_caches(dsp);
6ab2b7b4 2056 if (ret != 0)
078e7183 2057 goto err_ena;
6ab2b7b4 2058
0c2e3f34 2059 /* Sync set controls */
81ad93ec 2060 ret = wm_coeff_sync_controls(dsp);
6ab2b7b4 2061 if (ret != 0)
078e7183 2062 goto err_ena;
6ab2b7b4 2063
2159ad93
MB		 2064 /* Start the core running */
2065 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2066 ADSP1_CORE_ENA | ADSP1_START,
2067 ADSP1_CORE_ENA | ADSP1_START);
2068 break;
2069
2070 case SND_SOC_DAPM_PRE_PMD:
2071 /* Halt the core */
2072 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2073 ADSP1_CORE_ENA | ADSP1_START, 0);
2074
2075 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2076 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2077
2078 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2079 ADSP1_SYS_ENA, 0);
6ab2b7b4 2080
81ad93ec 2081 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 2082 ctl->enabled = 0;
b0101b4f
DP		 2083
2084 while (!list_empty(&dsp->alg_regions)) {
2085 alg_region = list_first_entry(&dsp->alg_regions,
2086 struct wm_adsp_alg_region,
2087 list);
2088 list_del(&alg_region->list);
2089 kfree(alg_region);
2090 }
2159ad93
MB		 2091 break;
2092
2093 default:
2094 break;
2095 }
2096
078e7183
CK		 2097 mutex_unlock(&dsp->pwr_lock);
2098
2159ad93
MB		 2099 return 0;
2100
078e7183 2101err_ena:
2159ad93
MB		 2102 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2103 ADSP1_SYS_ENA, 0);
078e7183
CK		 2104err_mutex:
2105 mutex_unlock(&dsp->pwr_lock);
2106
2159ad93
MB		 2107 return ret;
2108}
2109EXPORT_SYMBOL_GPL(wm_adsp1_event);
2110
2111static int wm_adsp2_ena(struct wm_adsp *dsp)
2112{
2113 unsigned int val;
2114 int ret, count;
2115
1552c325
MB		 2116 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
2117 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2159ad93
MB		 2118 if (ret != 0)
2119 return ret;
2120
2121 /* Wait for the RAM to start, should be near instantaneous */
939fd1e8 2122 for (count = 0; count < 10; ++count) {
7d00cd97 2123 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2159ad93
MB		 2124 if (ret != 0)
2125 return ret;
939fd1e8
CK		 2126
2127 if (val & ADSP2_RAM_RDY)
2128 break;
2129
2130 msleep(1);
2131 }
2159ad93
MB		 2132
2133 if (!(val & ADSP2_RAM_RDY)) {
2134 adsp_err(dsp, "Failed to start DSP RAM\n");
2135 return -EBUSY;
2136 }
2137
2138 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2159ad93
MB		 2139
2140 return 0;
2141}
2142
18b1a902 2143static void wm_adsp2_boot_work(struct work_struct *work)
2159ad93 2144{
d8a64d6a
CK		 2145 struct wm_adsp *dsp = container_of(work,
2146 struct wm_adsp,
2147 boot_work);
2159ad93
MB		 2148 int ret;
2149
078e7183
CK		 2150 mutex_lock(&dsp->pwr_lock);
2151
d8a64d6a
CK		 2152 ret = wm_adsp2_ena(dsp);
2153 if (ret != 0)
078e7183 2154 goto err_mutex;
2159ad93 2155
d8a64d6a
CK		 2156 ret = wm_adsp_load(dsp);
2157 if (ret != 0)
078e7183 2158 goto err_ena;
2159ad93 2159
b618a185 2160 ret = wm_adsp2_setup_algs(dsp);
d8a64d6a 2161 if (ret != 0)
078e7183 2162 goto err_ena;
db40517c 2163
d8a64d6a
CK		 2164 ret = wm_adsp_load_coeff(dsp);
2165 if (ret != 0)
078e7183 2166 goto err_ena;
2159ad93 2167
d8a64d6a
CK		 2168 /* Initialize caches for enabled and unset controls */
2169 ret = wm_coeff_init_control_caches(dsp);
2170 if (ret != 0)
078e7183 2171 goto err_ena;
6ab2b7b4 2172
d8a64d6a
CK		 2173 /* Sync set controls */
2174 ret = wm_coeff_sync_controls(dsp);
2175 if (ret != 0)
078e7183 2176 goto err_ena;
d8a64d6a 2177
d8a64d6a
CK		 2178 dsp->running = true;
2179
078e7183
CK		 2180 mutex_unlock(&dsp->pwr_lock);
2181
d8a64d6a 2182 return;
6ab2b7b4 2183
078e7183 2184err_ena:
d8a64d6a
CK		 2185 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2186 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
078e7183
CK		 2187err_mutex:
2188 mutex_unlock(&dsp->pwr_lock);
d8a64d6a
CK		 2189}
2190
d82d767f
CK		 2191static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq)
2192{
2193 int ret;
2194
2195 ret = regmap_update_bits_async(dsp->regmap,
2196 dsp->base + ADSP2_CLOCKING,
2197 ADSP2_CLK_SEL_MASK,
2198 freq << ADSP2_CLK_SEL_SHIFT);
2199 if (ret != 0)
2200 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
2201}
2202
12db5edd 2203int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
d82d767f
CK		 2204 struct snd_kcontrol *kcontrol, int event,
2205 unsigned int freq)
12db5edd 2206{
72718517 2207 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
12db5edd
CK		 2208 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2209 struct wm_adsp *dsp = &dsps[w->shift];
2210
00200107 2211 dsp->card = codec->component.card;
12db5edd
CK		 2212
2213 switch (event) {
2214 case SND_SOC_DAPM_PRE_PMU:
d82d767f 2215 wm_adsp2_set_dspclk(dsp, freq);
12db5edd
CK		 2216 queue_work(system_unbound_wq, &dsp->boot_work);
2217 break;
2218 default:
2219 break;
cab27258 2220 }
12db5edd
CK		 2221
2222 return 0;
2223}
2224EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
2225
d8a64d6a
CK		 2226int wm_adsp2_event(struct snd_soc_dapm_widget *w,
2227 struct snd_kcontrol *kcontrol, int event)
2228{
72718517 2229 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
d8a64d6a
CK		 2230 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2231 struct wm_adsp *dsp = &dsps[w->shift];
2232 struct wm_adsp_alg_region *alg_region;
2233 struct wm_coeff_ctl *ctl;
2234 int ret;
2235
d8a64d6a
CK		 2236 switch (event) {
2237 case SND_SOC_DAPM_POST_PMU:
d8a64d6a
CK		 2238 flush_work(&dsp->boot_work);
2239
2240 if (!dsp->running)
2241 return -EIO;
6ab2b7b4 2242
d8a64d6a
CK		 2243 ret = regmap_update_bits(dsp->regmap,
2244 dsp->base + ADSP2_CONTROL,
00e4c3b6
CK		 2245 ADSP2_CORE_ENA | ADSP2_START,
2246 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 2247 if (ret != 0)
2248 goto err;
2cd19bdb
CK		 2249
2250 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2251 ret = wm_adsp_buffer_init(dsp);
2252
2159ad93
MB		 2253 break;
2254
2255 case SND_SOC_DAPM_PRE_PMD:
10337b07
RF		 2256 /* Log firmware state, it can be useful for analysis */
2257 wm_adsp2_show_fw_status(dsp);
2258
078e7183
CK		 2259 mutex_lock(&dsp->pwr_lock);
2260
f9f55e31
RF		 2261 wm_adsp_debugfs_clear(dsp);
2262
2263 dsp->fw_id = 0;
2264 dsp->fw_id_version = 0;
1023dbd9
MB		 2265 dsp->running = false;
2266
2159ad93 2267 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 2268 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
2269 ADSP2_START, 0);
973838a0 2270
2d30b575
MB		 2271 /* Make sure DMAs are quiesced */
2272 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2273 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2274 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2275
81ad93ec 2276 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 2277 ctl->enabled = 0;
6ab2b7b4 2278
471f4885
MB		 2279 while (!list_empty(&dsp->alg_regions)) {
2280 alg_region = list_first_entry(&dsp->alg_regions,
2281 struct wm_adsp_alg_region,
2282 list);
2283 list_del(&alg_region->list);
2284 kfree(alg_region);
2285 }
ddbc5efe 2286
2cd19bdb
CK		 2287 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2288 wm_adsp_buffer_free(dsp);
2289
078e7183
CK		 2290 mutex_unlock(&dsp->pwr_lock);
2291
ddbc5efe 2292 adsp_dbg(dsp, "Shutdown complete\n");
2159ad93
MB		 2293 break;
2294
2295 default:
2296 break;
2297 }
2298
2299 return 0;
2300err:
2301 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 2302 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 2303 return ret;
2304}
2305EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0 2306
f5e2ce92
RF		 2307int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2308{
f9f55e31
RF		 2309 wm_adsp2_init_debugfs(dsp, codec);
2310
218e5087 2311 return snd_soc_add_codec_controls(codec,
336d0442
RF		 2312 &wm_adsp_fw_controls[dsp->num - 1],
2313 1);
f5e2ce92
RF		 2314}
2315EXPORT_SYMBOL_GPL(wm_adsp2_codec_probe);
2316
2317int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2318{
f9f55e31
RF		 2319 wm_adsp2_cleanup_debugfs(dsp);
2320
f5e2ce92
RF		 2321 return 0;
2322}
2323EXPORT_SYMBOL_GPL(wm_adsp2_codec_remove);
2324
81ac58b1 2325int wm_adsp2_init(struct wm_adsp *dsp)
973838a0
MB		 2326{
2327 int ret;
2328
10a2b662
MB		 2329 /*
2330 * Disable the DSP memory by default when in reset for a small
2331 * power saving.
2332 */
3809f001 2333 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
10a2b662
MB		 2334 ADSP2_MEM_ENA, 0);
2335 if (ret != 0) {
3809f001 2336 adsp_err(dsp, "Failed to clear memory retention: %d\n", ret);
10a2b662
MB		 2337 return ret;
2338 }
2339
3809f001
CK		 2340 INIT_LIST_HEAD(&dsp->alg_regions);
2341 INIT_LIST_HEAD(&dsp->ctl_list);
2342 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
6ab2b7b4 2343
078e7183
CK		 2344 mutex_init(&dsp->pwr_lock);
2345
973838a0
MB		 2346 return 0;
2347}
2348EXPORT_SYMBOL_GPL(wm_adsp2_init);
0a37c6ef 2349
66225e98
RF		 2350void wm_adsp2_remove(struct wm_adsp *dsp)
2351{
2352 struct wm_coeff_ctl *ctl;
2353
2354 while (!list_empty(&dsp->ctl_list)) {
2355 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
2356 list);
2357 list_del(&ctl->list);
2358 wm_adsp_free_ctl_blk(ctl);
2359 }
2360}
2361EXPORT_SYMBOL_GPL(wm_adsp2_remove);
2362
406abc95
CK		 2363int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
2364{
2365 struct wm_adsp_compr *compr;
2366 int ret = 0;
2367
2368 mutex_lock(&dsp->pwr_lock);
2369
2370 if (wm_adsp_fw[dsp->fw].num_caps == 0) {
2371 adsp_err(dsp, "Firmware does not support compressed API\n");
2372 ret = -ENXIO;
2373 goto out;
2374 }
2375
2376 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
2377 adsp_err(dsp, "Firmware does not support stream direction\n");
2378 ret = -EINVAL;
2379 goto out;
2380 }
2381
95fe9597
CK		 2382 if (dsp->compr) {
2383 /* It is expect this limitation will be removed in future */
2384 adsp_err(dsp, "Only a single stream supported per DSP\n");
2385 ret = -EBUSY;
2386 goto out;
2387 }
2388
406abc95
CK		 2389 compr = kzalloc(sizeof(*compr), GFP_KERNEL);
2390 if (!compr) {
2391 ret = -ENOMEM;
2392 goto out;
2393 }
2394
2395 compr->dsp = dsp;
2396 compr->stream = stream;
2397
2398 dsp->compr = compr;
2399
2400 stream->runtime->private_data = compr;
2401
2402out:
2403 mutex_unlock(&dsp->pwr_lock);
2404
2405 return ret;
2406}
2407EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
2408
2409int wm_adsp_compr_free(struct snd_compr_stream *stream)
2410{
2411 struct wm_adsp_compr *compr = stream->runtime->private_data;
2412 struct wm_adsp *dsp = compr->dsp;
2413
2414 mutex_lock(&dsp->pwr_lock);
2415
2416 dsp->compr = NULL;
2417
83a40ce9 2418 kfree(compr->raw_buf);
406abc95
CK		 2419 kfree(compr);
2420
2421 mutex_unlock(&dsp->pwr_lock);
2422
2423 return 0;
2424}
2425EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
2426
2427static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
2428 struct snd_compr_params *params)
2429{
2430 struct wm_adsp_compr *compr = stream->runtime->private_data;
2431 struct wm_adsp *dsp = compr->dsp;
2432 const struct wm_adsp_fw_caps *caps;
2433 const struct snd_codec_desc *desc;
2434 int i, j;
2435
2436 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
2437 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
2438 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
2439 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
2440 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
2441 adsp_err(dsp, "Invalid buffer fragsize=%d fragments=%d\n",
2442 params->buffer.fragment_size,
2443 params->buffer.fragments);
2444
2445 return -EINVAL;
2446 }
2447
2448 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
2449 caps = &wm_adsp_fw[dsp->fw].caps[i];
2450 desc = &caps->desc;
2451
2452 if (caps->id != params->codec.id)
2453 continue;
2454
2455 if (stream->direction == SND_COMPRESS_PLAYBACK) {
2456 if (desc->max_ch < params->codec.ch_out)
2457 continue;
2458 } else {
2459 if (desc->max_ch < params->codec.ch_in)
2460 continue;
2461 }
2462
2463 if (!(desc->formats & (1 << params->codec.format)))
2464 continue;
2465
2466 for (j = 0; j < desc->num_sample_rates; ++j)
2467 if (desc->sample_rates[j] == params->codec.sample_rate)
2468 return 0;
2469 }
2470
2471 adsp_err(dsp, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
2472 params->codec.id, params->codec.ch_in, params->codec.ch_out,
2473 params->codec.sample_rate, params->codec.format);
2474 return -EINVAL;
2475}
2476
565ace46
CK		 2477static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
2478{
2479 return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
2480}
2481
406abc95
CK		 2482int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
2483 struct snd_compr_params *params)
2484{
2485 struct wm_adsp_compr *compr = stream->runtime->private_data;
83a40ce9 2486 unsigned int size;
406abc95
CK		 2487 int ret;
2488
2489 ret = wm_adsp_compr_check_params(stream, params);
2490 if (ret)
2491 return ret;
2492
2493 compr->size = params->buffer;
2494
2495 adsp_dbg(compr->dsp, "fragment_size=%d fragments=%d\n",
2496 compr->size.fragment_size, compr->size.fragments);
2497
83a40ce9
CK		 2498 size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
2499 compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
2500 if (!compr->raw_buf)
2501 return -ENOMEM;
2502
da2b3358
CK		 2503 compr->sample_rate = params->codec.sample_rate;
2504
406abc95
CK		 2505 return 0;
2506}
2507EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
2508
2509int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
2510 struct snd_compr_caps *caps)
2511{
2512 struct wm_adsp_compr *compr = stream->runtime->private_data;
2513 int fw = compr->dsp->fw;
2514 int i;
2515
2516 if (wm_adsp_fw[fw].caps) {
2517 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
2518 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
2519
2520 caps->num_codecs = i;
2521 caps->direction = wm_adsp_fw[fw].compr_direction;
2522
2523 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
2524 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
2525 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
2526 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
2527 }
2528
2529 return 0;
2530}
2531EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
2532
2cd19bdb
CK		 2533static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
2534 unsigned int mem_addr,
2535 unsigned int num_words, u32 *data)
2536{
2537 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
2538 unsigned int i, reg;
2539 int ret;
2540
2541 if (!mem)
2542 return -EINVAL;
2543
2544 reg = wm_adsp_region_to_reg(mem, mem_addr);
2545
2546 ret = regmap_raw_read(dsp->regmap, reg, data,
2547 sizeof(*data) * num_words);
2548 if (ret < 0)
2549 return ret;
2550
2551 for (i = 0; i < num_words; ++i)
2552 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
2553
2554 return 0;
2555}
2556
2557static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
2558 unsigned int mem_addr, u32 *data)
2559{
2560 return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
2561}
2562
2563static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
2564 unsigned int mem_addr, u32 data)
2565{
2566 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
2567 unsigned int reg;
2568
2569 if (!mem)
2570 return -EINVAL;
2571
2572 reg = wm_adsp_region_to_reg(mem, mem_addr);
2573
2574 data = cpu_to_be32(data & 0x00ffffffu);
2575
2576 return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
2577}
2578
2579static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
2580 unsigned int field_offset, u32 *data)
2581{
2582 return wm_adsp_read_data_word(buf->dsp, WMFW_ADSP2_XM,
2583 buf->host_buf_ptr + field_offset, data);
2584}
2585
2586static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
2587 unsigned int field_offset, u32 data)
2588{
2589 return wm_adsp_write_data_word(buf->dsp, WMFW_ADSP2_XM,
2590 buf->host_buf_ptr + field_offset, data);
2591}
2592
2593static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf)
2594{
2595 struct wm_adsp_alg_region *alg_region;
2596 struct wm_adsp *dsp = buf->dsp;
2597 u32 xmalg, addr, magic;
2598 int i, ret;
2599
2600 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
2601 xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32);
2602
2603 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
2604 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
2605 if (ret < 0)
2606 return ret;
2607
2608 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
2609 return -EINVAL;
2610
2611 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
2612 for (i = 0; i < 5; ++i) {
2613 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
2614 &buf->host_buf_ptr);
2615 if (ret < 0)
2616 return ret;
2617
2618 if (buf->host_buf_ptr)
2619 break;
2620
2621 usleep_range(1000, 2000);
2622 }
2623
2624 if (!buf->host_buf_ptr)
2625 return -EIO;
2626
2627 adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
2628
2629 return 0;
2630}
2631
2632static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
2633{
2634 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
2635 struct wm_adsp_buffer_region *region;
2636 u32 offset = 0;
2637 int i, ret;
2638
2639 for (i = 0; i < caps->num_regions; ++i) {
2640 region = &buf->regions[i];
2641
2642 region->offset = offset;
2643 region->mem_type = caps->region_defs[i].mem_type;
2644
2645 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
2646 &region->base_addr);
2647 if (ret < 0)
2648 return ret;
2649
2650 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
2651 &offset);
2652 if (ret < 0)
2653 return ret;
2654
2655 region->cumulative_size = offset;
2656
2657 adsp_dbg(buf->dsp,
2658 "region=%d type=%d base=%04x off=%04x size=%04x\n",
2659 i, region->mem_type, region->base_addr,
2660 region->offset, region->cumulative_size);
2661 }
2662
2663 return 0;
2664}
2665
2666static int wm_adsp_buffer_init(struct wm_adsp *dsp)
2667{
2668 struct wm_adsp_compr_buf *buf;
2669 int ret;
2670
2671 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
2672 if (!buf)
2673 return -ENOMEM;
2674
2675 buf->dsp = dsp;
565ace46
CK		 2676 buf->read_index = -1;
2677 buf->irq_count = 0xFFFFFFFF;
2cd19bdb
CK		 2678
2679 ret = wm_adsp_buffer_locate(buf);
2680 if (ret < 0) {
2681 adsp_err(dsp, "Failed to acquire host buffer: %d\n", ret);
2682 goto err_buffer;
2683 }
2684
2685 buf->regions = kcalloc(wm_adsp_fw[dsp->fw].caps->num_regions,
2686 sizeof(*buf->regions), GFP_KERNEL);
2687 if (!buf->regions) {
2688 ret = -ENOMEM;
2689 goto err_buffer;
2690 }
2691
2692 ret = wm_adsp_buffer_populate(buf);
2693 if (ret < 0) {
2694 adsp_err(dsp, "Failed to populate host buffer: %d\n", ret);
2695 goto err_regions;
2696 }
2697
2698 dsp->buffer = buf;
2699
2700 return 0;
2701
2702err_regions:
2703 kfree(buf->regions);
2704err_buffer:
2705 kfree(buf);
2706 return ret;
2707}
2708
2709static int wm_adsp_buffer_free(struct wm_adsp *dsp)
2710{
2711 if (dsp->buffer) {
2712 kfree(dsp->buffer->regions);
2713 kfree(dsp->buffer);
2714
2715 dsp->buffer = NULL;
2716 }
2717
2718 return 0;
2719}
2720
95fe9597
CK		 2721static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
2722{
2723 return compr->buf != NULL;
2724}
2725
2726static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
2727{
2728 /*
2729 * Note this will be more complex once each DSP can support multiple
2730 * streams
2731 */
2732 if (!compr->dsp->buffer)
2733 return -EINVAL;
2734
2735 compr->buf = compr->dsp->buffer;
2736
2737 return 0;
2738}
2739
2740int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
2741{
2742 struct wm_adsp_compr *compr = stream->runtime->private_data;
2743 struct wm_adsp *dsp = compr->dsp;
2744 int ret = 0;
2745
2746 adsp_dbg(dsp, "Trigger: %d\n", cmd);
2747
2748 mutex_lock(&dsp->pwr_lock);
2749
2750 switch (cmd) {
2751 case SNDRV_PCM_TRIGGER_START:
2752 if (wm_adsp_compr_attached(compr))
2753 break;
2754
2755 ret = wm_adsp_compr_attach(compr);
2756 if (ret < 0) {
2757 adsp_err(dsp, "Failed to link buffer and stream: %d\n",
2758 ret);
2759 break;
2760 }
565ace46
CK		 2761
2762 /* Trigger the IRQ at one fragment of data */
2763 ret = wm_adsp_buffer_write(compr->buf,
2764 HOST_BUFFER_FIELD(high_water_mark),
2765 wm_adsp_compr_frag_words(compr));
2766 if (ret < 0) {
2767 adsp_err(dsp, "Failed to set high water mark: %d\n",
2768 ret);
2769 break;
2770 }
95fe9597
CK		 2771 break;
2772 case SNDRV_PCM_TRIGGER_STOP:
2773 break;
2774 default:
2775 ret = -EINVAL;
2776 break;
2777 }
2778
2779 mutex_unlock(&dsp->pwr_lock);
2780
2781 return ret;
2782}
2783EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
2784
565ace46
CK		 2785static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
2786{
2787 int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
2788
2789 return buf->regions[last_region].cumulative_size;
2790}
2791
2792static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
2793{
2794 u32 next_read_index, next_write_index;
2795 int write_index, read_index, avail;
2796 int ret;
2797
2798 /* Only sync read index if we haven't already read a valid index */
2799 if (buf->read_index < 0) {
2800 ret = wm_adsp_buffer_read(buf,
2801 HOST_BUFFER_FIELD(next_read_index),
2802 &next_read_index);
2803 if (ret < 0)
2804 return ret;
2805
2806 read_index = sign_extend32(next_read_index, 23);
2807
2808 if (read_index < 0) {
2809 adsp_dbg(buf->dsp, "Avail check on unstarted stream\n");
2810 return 0;
2811 }
2812
2813 buf->read_index = read_index;
2814 }
2815
2816 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
2817 &next_write_index);
2818 if (ret < 0)
2819 return ret;
2820
2821 write_index = sign_extend32(next_write_index, 23);
2822
2823 avail = write_index - buf->read_index;
2824 if (avail < 0)
2825 avail += wm_adsp_buffer_size(buf);
2826
2827 adsp_dbg(buf->dsp, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
2828 buf->read_index, write_index, avail);
2829
2830 buf->avail = avail;
2831
2832 return 0;
2833}
2834
2835int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
2836{
2837 struct wm_adsp_compr_buf *buf = dsp->buffer;
83a40ce9 2838 struct wm_adsp_compr *compr = dsp->compr;
565ace46
CK		 2839 int ret = 0;
2840
2841 mutex_lock(&dsp->pwr_lock);
2842
2843 if (!buf) {
565ace46
CK		 2844 ret = -ENODEV;
2845 goto out;
2846 }
2847
2848 adsp_dbg(dsp, "Handling buffer IRQ\n");
2849
2850 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
2851 if (ret < 0) {
2852 adsp_err(dsp, "Failed to check buffer error: %d\n", ret);
2853 goto out;
2854 }
2855 if (buf->error != 0) {
2856 adsp_err(dsp, "Buffer error occurred: %d\n", buf->error);
2857 ret = -EIO;
2858 goto out;
2859 }
2860
2861 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
2862 &buf->irq_count);
2863 if (ret < 0) {
2864 adsp_err(dsp, "Failed to get irq_count: %d\n", ret);
2865 goto out;
2866 }
2867
2868 ret = wm_adsp_buffer_update_avail(buf);
2869 if (ret < 0) {
2870 adsp_err(dsp, "Error reading avail: %d\n", ret);
2871 goto out;
2872 }
2873
c7dae7c4 2874 if (compr && compr->stream)
83a40ce9
CK		 2875 snd_compr_fragment_elapsed(compr->stream);
2876
565ace46
CK		 2877out:
2878 mutex_unlock(&dsp->pwr_lock);
2879
2880 return ret;
2881}
2882EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
2883
2884static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
2885{
2886 if (buf->irq_count & 0x01)
2887 return 0;
2888
2889 adsp_dbg(buf->dsp, "Enable IRQ(0x%x) for next fragment\n",
2890 buf->irq_count);
2891
2892 buf->irq_count |= 0x01;
2893
2894 return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
2895 buf->irq_count);
2896}
2897
2898int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
2899 struct snd_compr_tstamp *tstamp)
2900{
2901 struct wm_adsp_compr *compr = stream->runtime->private_data;
2902 struct wm_adsp_compr_buf *buf = compr->buf;
2903 struct wm_adsp *dsp = compr->dsp;
2904 int ret = 0;
2905
2906 adsp_dbg(dsp, "Pointer request\n");
2907
2908 mutex_lock(&dsp->pwr_lock);
2909
2910 if (!compr->buf) {
2911 ret = -ENXIO;
2912 goto out;
2913 }
2914
2915 if (compr->buf->error) {
2916 ret = -EIO;
2917 goto out;
2918 }
2919
2920 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
2921 ret = wm_adsp_buffer_update_avail(buf);
2922 if (ret < 0) {
2923 adsp_err(dsp, "Error reading avail: %d\n", ret);
2924 goto out;
2925 }
2926
2927 /*
2928 * If we really have less than 1 fragment available tell the
2929 * DSP to inform us once a whole fragment is available.
2930 */
2931 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
2932 ret = wm_adsp_buffer_reenable_irq(buf);
2933 if (ret < 0) {
2934 adsp_err(dsp,
2935 "Failed to re-enable buffer IRQ: %d\n",
2936 ret);
2937 goto out;
2938 }
2939 }
2940 }
2941
2942 tstamp->copied_total = compr->copied_total;
2943 tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
da2b3358 2944 tstamp->sampling_rate = compr->sample_rate;
565ace46
CK		 2945
2946out:
2947 mutex_unlock(&dsp->pwr_lock);
2948
2949 return ret;
2950}
2951EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
2952
83a40ce9
CK		 2953static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
2954{
2955 struct wm_adsp_compr_buf *buf = compr->buf;
2956 u8 *pack_in = (u8 *)compr->raw_buf;
2957 u8 *pack_out = (u8 *)compr->raw_buf;
2958 unsigned int adsp_addr;
2959 int mem_type, nwords, max_read;
2960 int i, j, ret;
2961
2962 /* Calculate read parameters */
2963 for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
2964 if (buf->read_index < buf->regions[i].cumulative_size)
2965 break;
2966
2967 if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
2968 return -EINVAL;
2969
2970 mem_type = buf->regions[i].mem_type;
2971 adsp_addr = buf->regions[i].base_addr +
2972 (buf->read_index - buf->regions[i].offset);
2973
2974 max_read = wm_adsp_compr_frag_words(compr);
2975 nwords = buf->regions[i].cumulative_size - buf->read_index;
2976
2977 if (nwords > target)
2978 nwords = target;
2979 if (nwords > buf->avail)
2980 nwords = buf->avail;
2981 if (nwords > max_read)
2982 nwords = max_read;
2983 if (!nwords)
2984 return 0;
2985
2986 /* Read data from DSP */
2987 ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr,
2988 nwords, compr->raw_buf);
2989 if (ret < 0)
2990 return ret;
2991
2992 /* Remove the padding bytes from the data read from the DSP */
2993 for (i = 0; i < nwords; i++) {
2994 for (j = 0; j < WM_ADSP_DATA_WORD_SIZE; j++)
2995 *pack_out++ = *pack_in++;
2996
2997 pack_in += sizeof(*(compr->raw_buf)) - WM_ADSP_DATA_WORD_SIZE;
2998 }
2999
3000 /* update read index to account for words read */
3001 buf->read_index += nwords;
3002 if (buf->read_index == wm_adsp_buffer_size(buf))
3003 buf->read_index = 0;
3004
3005 ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
3006 buf->read_index);
3007 if (ret < 0)
3008 return ret;
3009
3010 /* update avail to account for words read */
3011 buf->avail -= nwords;
3012
3013 return nwords;
3014}
3015
3016static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
3017 char __user *buf, size_t count)
3018{
3019 struct wm_adsp *dsp = compr->dsp;
3020 int ntotal = 0;
3021 int nwords, nbytes;
3022
3023 adsp_dbg(dsp, "Requested read of %zu bytes\n", count);
3024
3025 if (!compr->buf)
3026 return -ENXIO;
3027
3028 if (compr->buf->error)
3029 return -EIO;
3030
3031 count /= WM_ADSP_DATA_WORD_SIZE;
3032
3033 do {
3034 nwords = wm_adsp_buffer_capture_block(compr, count);
3035 if (nwords < 0) {
3036 adsp_err(dsp, "Failed to capture block: %d\n", nwords);
3037 return nwords;
3038 }
3039
3040 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
3041
3042 adsp_dbg(dsp, "Read %d bytes\n", nbytes);
3043
3044 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
3045 adsp_err(dsp, "Failed to copy data to user: %d, %d\n",
3046 ntotal, nbytes);
3047 return -EFAULT;
3048 }
3049
3050 count -= nwords;
3051 ntotal += nbytes;
3052 } while (nwords > 0 && count > 0);
3053
3054 compr->copied_total += ntotal;
3055
3056 return ntotal;
3057}
3058
3059int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
3060 size_t count)
3061{
3062 struct wm_adsp_compr *compr = stream->runtime->private_data;
3063 struct wm_adsp *dsp = compr->dsp;
3064 int ret;
3065
3066 mutex_lock(&dsp->pwr_lock);
3067
3068 if (stream->direction == SND_COMPRESS_CAPTURE)
3069 ret = wm_adsp_compr_read(compr, buf, count);
3070 else
3071 ret = -ENOTSUPP;
3072
3073 mutex_unlock(&dsp->pwr_lock);
3074
3075 return ret;
3076}
3077EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
3078
0a37c6ef 3079MODULE_LICENSE("GPL v2");
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