[linux.git] / drivers / ptp / ptp_idt82p33.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * PTP hardware clock driver for the IDT 82P33XXX family of clocks.
 *
 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
 */
#ifndef PTP_IDT82P33_H
#define PTP_IDT82P33_H

#include <linux/ktime.h>
#include <linux/mfd/idt82p33_reg.h>
#include <linux/regmap.h>

#define FW_FILENAME	"idt82p33xxx.bin"
#define MAX_PHC_PLL	(2)
#define MAX_TRIG_CLK	(3)
#define MAX_PER_OUT	(11)
#define TOD_BYTE_COUNT	(10)
#define DCO_MAX_PPB     (92000)
#define MAX_MEASURMENT_COUNT	(5)
#define SNAP_THRESHOLD_NS	(10000)
#define IMMEDIATE_SNAP_THRESHOLD_NS (50000)
#define DDCO_THRESHOLD_NS	(5)
#define IDT82P33_MAX_WRITE_COUNT	(512)

#define PLLMASK_ADDR_HI	0xFF
#define PLLMASK_ADDR_LO	0xA5

#define PLL0_OUTMASK_ADDR_HI	0xFF
#define PLL0_OUTMASK_ADDR_LO	0xB0

#define PLL1_OUTMASK_ADDR_HI	0xFF
#define PLL1_OUTMASK_ADDR_LO	0xB2

#define PLL2_OUTMASK_ADDR_HI	0xFF
#define PLL2_OUTMASK_ADDR_LO	0xB4

#define PLL3_OUTMASK_ADDR_HI	0xFF
#define PLL3_OUTMASK_ADDR_LO	0xB6

#define DEFAULT_PLL_MASK	(0x01)
#define DEFAULT_OUTPUT_MASK_PLL0	(0xc0)
#define DEFAULT_OUTPUT_MASK_PLL1	DEFAULT_OUTPUT_MASK_PLL0

/**
 * @brief Maximum absolute value for write phase offset in nanoseconds
 */
#define WRITE_PHASE_OFFSET_LIMIT (20000l)

/** @brief Phase offset resolution
 *
 *  DPLL phase offset = 10^15 fs / ( System Clock  * 2^13)
 *                    = 10^15 fs / ( 1638400000 * 2^23)
 *                    = 74.5058059692382 fs
 */
#define IDT_T0DPLL_PHASE_RESOL 74506

/* PTP Hardware Clock interface */
struct idt82p33_channel {
	struct ptp_clock_info	caps;
	struct ptp_clock	*ptp_clock;
	struct idt82p33		*idt82p33;
	enum pll_mode		pll_mode;
	/* Workaround for TOD-to-output alignment issue */
	struct delayed_work	adjtime_work;
	s32			current_freq;
	/* double dco mode */
	bool			ddco;
	u8			output_mask;
	/* last input trigger for extts */
	u8			tod_trigger;
	bool			discard_next_extts;
	u8			plln;
	/* remember last tod_sts for extts */
	u8			extts_tod_sts[TOD_BYTE_COUNT];
	u16			dpll_tod_cnfg;
	u16			dpll_tod_trigger;
	u16			dpll_tod_sts;
	u16			dpll_mode_cnfg;
	u16			dpll_freq_cnfg;
	u16			dpll_phase_cnfg;
	u16			dpll_sync_cnfg;
	u16			dpll_input_mode_cnfg;
};

struct idt82p33 {
	struct idt82p33_channel	channel[MAX_PHC_PLL];
	struct device		*dev;
	u8			pll_mask;
	/* Polls for external time stamps */
	u8			extts_mask;
	bool			extts_single_shot;
	struct delayed_work	extts_work;
	/* Remember the ptp channel to report extts */
	struct idt82p33_channel	*event_channel[MAX_PHC_PLL];
	/* Mutex to protect operations from being interrupted */
	struct mutex		*lock;
	struct regmap		*regmap;
	struct device		*mfd;
	/* Overhead calculation for adjtime */
	ktime_t			start_time;
	int			calculate_overhead_flag;
	s64			tod_write_overhead_ns;
};

/* firmware interface */
struct idt82p33_fwrc {
	u8 hiaddr;
	u8 loaddr;
	u8 value;
	u8 reserved;
} __packed;

#endif /* PTP_IDT82P33_H */
Commit	Line	Data
57a10d8c ML	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* PTP hardware clock driver for the IDT 82P33XXX family of clocks.
	4	*
	5	* Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
	6	*/
	7	#ifndef PTP_IDT82P33_H
	8	#define PTP_IDT82P33_H
	9
	10	#include <linux/ktime.h>
013a3e7c ML	11	#include <linux/mfd/idt82p33_reg.h>
013a3e7c ML	12	#include <linux/regmap.h>
57a10d8c	13
57a10d8c	14	#define FW_FILENAME "idt82p33xxx.bin"
013a3e7c	15	#define MAX_PHC_PLL (2)
ad3cc776 ML	16	#define MAX_TRIG_CLK (3)
ad3cc776 ML	17	#define MAX_PER_OUT (11)
013a3e7c ML	18	#define TOD_BYTE_COUNT (10)
	19	#define DCO_MAX_PPB (92000)
	20	#define MAX_MEASURMENT_COUNT (5)
	21	#define SNAP_THRESHOLD_NS (10000)
	22	#define IMMEDIATE_SNAP_THRESHOLD_NS (50000)
	23	#define DDCO_THRESHOLD_NS (5)
	24	#define IDT82P33_MAX_WRITE_COUNT (512)
57a10d8c ML	25
	26	#define PLLMASK_ADDR_HI 0xFF
	27	#define PLLMASK_ADDR_LO 0xA5
	28
	29	#define PLL0_OUTMASK_ADDR_HI 0xFF
	30	#define PLL0_OUTMASK_ADDR_LO 0xB0
	31
	32	#define PLL1_OUTMASK_ADDR_HI 0xFF
	33	#define PLL1_OUTMASK_ADDR_LO 0xB2
	34
	35	#define PLL2_OUTMASK_ADDR_HI 0xFF
	36	#define PLL2_OUTMASK_ADDR_LO 0xB4
	37
	38	#define PLL3_OUTMASK_ADDR_HI 0xFF
	39	#define PLL3_OUTMASK_ADDR_LO 0xB6
	40
	41	#define DEFAULT_PLL_MASK (0x01)
	42	#define DEFAULT_OUTPUT_MASK_PLL0 (0xc0)
	43	#define DEFAULT_OUTPUT_MASK_PLL1 DEFAULT_OUTPUT_MASK_PLL0
	44
013a3e7c	45	/**
e156e4d2	46	* @brief Maximum absolute value for write phase offset in nanoseconds
013a3e7c	47	*/
e156e4d2	48	#define WRITE_PHASE_OFFSET_LIMIT (20000l)
013a3e7c ML	49
	50	/** @brief Phase offset resolution
	51	*
	52	* DPLL phase offset = 10^15 fs / ( System Clock * 2^13)
	53	* = 10^15 fs / ( 1638400000 * 2^23)
	54	* = 74.5058059692382 fs
	55	*/
	56	#define IDT_T0DPLL_PHASE_RESOL 74506
	57
57a10d8c ML	58	/* PTP Hardware Clock interface */
	59	struct idt82p33_channel {
	60	struct ptp_clock_info caps;
	61	struct ptp_clock *ptp_clock;
013a3e7c ML	62	struct idt82p33 *idt82p33;
013a3e7c ML	63	enum pll_mode pll_mode;
ad3cc776 ML	64	/* Workaround for TOD-to-output alignment issue */
	65	struct delayed_work adjtime_work;
	66	s32 current_freq;
	67	/* double dco mode */
	68	bool ddco;
57a10d8c	69	u8 output_mask;
ad3cc776 ML	70	/* last input trigger for extts */
	71	u8 tod_trigger;
	72	bool discard_next_extts;
	73	u8 plln;
	74	/* remember last tod_sts for extts */
	75	u8 extts_tod_sts[TOD_BYTE_COUNT];
57a10d8c ML	76	u16 dpll_tod_cnfg;
	77	u16 dpll_tod_trigger;
	78	u16 dpll_tod_sts;
	79	u16 dpll_mode_cnfg;
	80	u16 dpll_freq_cnfg;
	81	u16 dpll_phase_cnfg;
	82	u16 dpll_sync_cnfg;
	83	u16 dpll_input_mode_cnfg;
	84	};
	85
	86	struct idt82p33 {
013a3e7c ML	87	struct idt82p33_channel channel[MAX_PHC_PLL];
	88	struct device *dev;
	89	u8 pll_mask;
ad3cc776 ML	90	/* Polls for external time stamps */
	91	u8 extts_mask;
	92	bool extts_single_shot;
	93	struct delayed_work extts_work;
	94	/* Remember the ptp channel to report extts */
	95	struct idt82p33_channel *event_channel[MAX_PHC_PLL];
013a3e7c ML	96	/* Mutex to protect operations from being interrupted */
	97	struct mutex *lock;
	98	struct regmap *regmap;
	99	struct device *mfd;
	100	/* Overhead calculation for adjtime */
	101	ktime_t start_time;
	102	int calculate_overhead_flag;
	103	s64 tod_write_overhead_ns;
57a10d8c ML	104	};
	105
	106	/* firmware interface */
	107	struct idt82p33_fwrc {
	108	u8 hiaddr;
	109	u8 loaddr;
	110	u8 value;
	111	u8 reserved;
	112	} __packed;
	113
57a10d8c	114	#endif /* PTP_IDT82P33_H */