[linux.git] / drivers / rtc / rtc-rs5c313.c

/*
 * Ricoh RS5C313 RTC device/driver
 *  Copyright (C) 2007 Nobuhiro Iwamatsu
 *
 *  2005-09-19 modifed by kogiidena
 *
 * Based on the old drivers/char/rs5c313_rtc.c  by:
 *  Copyright (C) 2000 Philipp Rumpf <[email protected]>
 *  Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
 *
 * Based on code written by Paul Gortmaker.
 *  Copyright (C) 1996 Paul Gortmaker
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Based on other minimal char device drivers, like Alan's
 * watchdog, Ted's random, etc. etc.
 *
 *	1.07	Paul Gortmaker.
 *	1.08	Miquel van Smoorenburg: disallow certain things on the
 *		DEC Alpha as the CMOS clock is also used for other things.
 *	1.09	Nikita Schmidt: epoch support and some Alpha cleanup.
 *	1.09a	Pete Zaitcev: Sun SPARC
 *	1.09b	Jeff Garzik: Modularize, init cleanup
 *	1.09c	Jeff Garzik: SMP cleanup
 *	1.10    Paul Barton-Davis: add support for async I/O
 *	1.10a	Andrea Arcangeli: Alpha updates
 *	1.10b	Andrew Morton: SMP lock fix
 *	1.10c	Cesar Barros: SMP locking fixes and cleanup
 *	1.10d	Paul Gortmaker: delete paranoia check in rtc_exit
 *	1.10e	Maciej W. Rozycki: Handle DECstation's year weirdness.
 *      1.11    Takashi Iwai: Kernel access functions
 *			      rtc_register/rtc_unregister/rtc_control
 *      1.11a   Daniele Bellucci: Audit create_proc_read_entry in rtc_init
 *	1.12	Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer
 *		CONFIG_HPET_EMULATE_RTC
 *	1.13	Nobuhiro Iwamatsu: Updata driver.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/err.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <linux/bcd.h>
#include <linux/delay.h>
#include <linux/io.h>

#define DRV_NAME	"rs5c313"

#ifdef CONFIG_SH_LANDISK
/*****************************************************/
/* LANDISK dependence part of RS5C313                */
/*****************************************************/

#define SCSMR1		0xFFE00000
#define SCSCR1		0xFFE00008
#define SCSMR1_CA	0x80
#define SCSCR1_CKE	0x03
#define SCSPTR1		0xFFE0001C
#define SCSPTR1_EIO	0x80
#define SCSPTR1_SPB1IO	0x08
#define SCSPTR1_SPB1DT	0x04
#define SCSPTR1_SPB0IO	0x02
#define SCSPTR1_SPB0DT	0x01

#define SDA_OEN		SCSPTR1_SPB1IO
#define SDA		SCSPTR1_SPB1DT
#define SCL_OEN		SCSPTR1_SPB0IO
#define SCL		SCSPTR1_SPB0DT

/* RICOH RS5C313 CE port */
#define RS5C313_CE	0xB0000003

/* RICOH RS5C313 CE port bit */
#define RS5C313_CE_RTCCE	0x02

/* SCSPTR1 data */
unsigned char scsptr1_data;

#define RS5C313_CEENABLE    __raw_writeb(RS5C313_CE_RTCCE, RS5C313_CE);
#define RS5C313_CEDISABLE   __raw_writeb(0x00, RS5C313_CE)
#define RS5C313_MISCOP      __raw_writeb(0x02, 0xB0000008)

static void rs5c313_init_port(void)
{
	/* Set SCK as I/O port and Initialize SCSPTR1 data & I/O port. */
	__raw_writeb(__raw_readb(SCSMR1) & ~SCSMR1_CA, SCSMR1);
	__raw_writeb(__raw_readb(SCSCR1) & ~SCSCR1_CKE, SCSCR1);

	/* And Initialize SCL for RS5C313 clock */
	scsptr1_data = __raw_readb(SCSPTR1) | SCL;	/* SCL:H */
	__raw_writeb(scsptr1_data, SCSPTR1);
	scsptr1_data = __raw_readb(SCSPTR1) | SCL_OEN;	/* SCL output enable */
	__raw_writeb(scsptr1_data, SCSPTR1);
	RS5C313_CEDISABLE;	/* CE:L */
}

static void rs5c313_write_data(unsigned char data)
{
	int i;

	for (i = 0; i < 8; i++) {
		/* SDA:Write Data */
		scsptr1_data = (scsptr1_data & ~SDA) |
				((((0x80 >> i) & data) >> (7 - i)) << 2);
		__raw_writeb(scsptr1_data, SCSPTR1);
		if (i == 0) {
			scsptr1_data |= SDA_OEN;	/* SDA:output enable */
			__raw_writeb(scsptr1_data, SCSPTR1);
		}
		ndelay(700);
		scsptr1_data &= ~SCL;	/* SCL:L */
		__raw_writeb(scsptr1_data, SCSPTR1);
		ndelay(700);
		scsptr1_data |= SCL;	/* SCL:H */
		__raw_writeb(scsptr1_data, SCSPTR1);
	}

	scsptr1_data &= ~SDA_OEN;	/* SDA:output disable */
	__raw_writeb(scsptr1_data, SCSPTR1);
}

static unsigned char rs5c313_read_data(void)
{
	int i;
	unsigned char data = 0;

	for (i = 0; i < 8; i++) {
		ndelay(700);
		/* SDA:Read Data */
		data |= ((__raw_readb(SCSPTR1) & SDA) >> 2) << (7 - i);
		scsptr1_data &= ~SCL;	/* SCL:L */
		__raw_writeb(scsptr1_data, SCSPTR1);
		ndelay(700);
		scsptr1_data |= SCL;	/* SCL:H */
		__raw_writeb(scsptr1_data, SCSPTR1);
	}
	return data & 0x0F;
}

#endif /* CONFIG_SH_LANDISK */

/*****************************************************/
/* machine independence part of RS5C313              */
/*****************************************************/

/* RICOH RS5C313 address */
#define RS5C313_ADDR_SEC	0x00
#define RS5C313_ADDR_SEC10	0x01
#define RS5C313_ADDR_MIN	0x02
#define RS5C313_ADDR_MIN10	0x03
#define RS5C313_ADDR_HOUR	0x04
#define RS5C313_ADDR_HOUR10	0x05
#define RS5C313_ADDR_WEEK	0x06
#define RS5C313_ADDR_INTINTVREG	0x07
#define RS5C313_ADDR_DAY	0x08
#define RS5C313_ADDR_DAY10	0x09
#define RS5C313_ADDR_MON	0x0A
#define RS5C313_ADDR_MON10	0x0B
#define RS5C313_ADDR_YEAR	0x0C
#define RS5C313_ADDR_YEAR10	0x0D
#define RS5C313_ADDR_CNTREG	0x0E
#define RS5C313_ADDR_TESTREG	0x0F

/* RICOH RS5C313 control register */
#define RS5C313_CNTREG_ADJ_BSY	0x01
#define RS5C313_CNTREG_WTEN_XSTP	0x02
#define RS5C313_CNTREG_12_24	0x04
#define RS5C313_CNTREG_CTFG	0x08

/* RICOH RS5C313 test register */
#define RS5C313_TESTREG_TEST	0x01

/* RICOH RS5C313 control bit */
#define RS5C313_CNTBIT_READ	0x40
#define RS5C313_CNTBIT_AD	0x20
#define RS5C313_CNTBIT_DT	0x10

static unsigned char rs5c313_read_reg(unsigned char addr)
{

	rs5c313_write_data(addr | RS5C313_CNTBIT_READ | RS5C313_CNTBIT_AD);
	return rs5c313_read_data();
}

static void rs5c313_write_reg(unsigned char addr, unsigned char data)
{
	data &= 0x0f;
	rs5c313_write_data(addr | RS5C313_CNTBIT_AD);
	rs5c313_write_data(data | RS5C313_CNTBIT_DT);
	return;
}

static inline unsigned char rs5c313_read_cntreg(void)
{
	return rs5c313_read_reg(RS5C313_ADDR_CNTREG);
}

static inline void rs5c313_write_cntreg(unsigned char data)
{
	rs5c313_write_reg(RS5C313_ADDR_CNTREG, data);
}

static inline void rs5c313_write_intintvreg(unsigned char data)
{
	rs5c313_write_reg(RS5C313_ADDR_INTINTVREG, data);
}

static int rs5c313_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	int data;
	int cnt;

	cnt = 0;
	while (1) {
		RS5C313_CEENABLE;	/* CE:H */

		/* Initialize control reg. 24 hour */
		rs5c313_write_cntreg(0x04);

		if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
			break;

		RS5C313_CEDISABLE;
		ndelay(700);	/* CE:L */

		if (cnt++ > 100) {
			dev_err(dev, "%s: timeout error\n", __func__);
			return -EIO;
		}
	}

	data = rs5c313_read_reg(RS5C313_ADDR_SEC);
	data |= (rs5c313_read_reg(RS5C313_ADDR_SEC10) << 4);
	tm->tm_sec = bcd2bin(data);

	data = rs5c313_read_reg(RS5C313_ADDR_MIN);
	data |= (rs5c313_read_reg(RS5C313_ADDR_MIN10) << 4);
	tm->tm_min = bcd2bin(data);

	data = rs5c313_read_reg(RS5C313_ADDR_HOUR);
	data |= (rs5c313_read_reg(RS5C313_ADDR_HOUR10) << 4);
	tm->tm_hour = bcd2bin(data);

	data = rs5c313_read_reg(RS5C313_ADDR_DAY);
	data |= (rs5c313_read_reg(RS5C313_ADDR_DAY10) << 4);
	tm->tm_mday = bcd2bin(data);

	data = rs5c313_read_reg(RS5C313_ADDR_MON);
	data |= (rs5c313_read_reg(RS5C313_ADDR_MON10) << 4);
	tm->tm_mon = bcd2bin(data) - 1;

	data = rs5c313_read_reg(RS5C313_ADDR_YEAR);
	data |= (rs5c313_read_reg(RS5C313_ADDR_YEAR10) << 4);
	tm->tm_year = bcd2bin(data);

	if (tm->tm_year < 70)
		tm->tm_year += 100;

	data = rs5c313_read_reg(RS5C313_ADDR_WEEK);
	tm->tm_wday = bcd2bin(data);

	RS5C313_CEDISABLE;
	ndelay(700);		/* CE:L */

	return 0;
}

static int rs5c313_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	int data;
	int cnt;

	cnt = 0;
	/* busy check. */
	while (1) {
		RS5C313_CEENABLE;	/* CE:H */

		/* Initiatlize control reg. 24 hour */
		rs5c313_write_cntreg(0x04);

		if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
			break;
		RS5C313_MISCOP;
		RS5C313_CEDISABLE;
		ndelay(700);	/* CE:L */

		if (cnt++ > 100) {
			dev_err(dev, "%s: timeout error\n", __func__);
			return -EIO;
		}
	}

	data = bin2bcd(tm->tm_sec);
	rs5c313_write_reg(RS5C313_ADDR_SEC, data);
	rs5c313_write_reg(RS5C313_ADDR_SEC10, (data >> 4));

	data = bin2bcd(tm->tm_min);
	rs5c313_write_reg(RS5C313_ADDR_MIN, data);
	rs5c313_write_reg(RS5C313_ADDR_MIN10, (data >> 4));

	data = bin2bcd(tm->tm_hour);
	rs5c313_write_reg(RS5C313_ADDR_HOUR, data);
	rs5c313_write_reg(RS5C313_ADDR_HOUR10, (data >> 4));

	data = bin2bcd(tm->tm_mday);
	rs5c313_write_reg(RS5C313_ADDR_DAY, data);
	rs5c313_write_reg(RS5C313_ADDR_DAY10, (data >> 4));

	data = bin2bcd(tm->tm_mon + 1);
	rs5c313_write_reg(RS5C313_ADDR_MON, data);
	rs5c313_write_reg(RS5C313_ADDR_MON10, (data >> 4));

	data = bin2bcd(tm->tm_year % 100);
	rs5c313_write_reg(RS5C313_ADDR_YEAR, data);
	rs5c313_write_reg(RS5C313_ADDR_YEAR10, (data >> 4));

	data = bin2bcd(tm->tm_wday);
	rs5c313_write_reg(RS5C313_ADDR_WEEK, data);

	RS5C313_CEDISABLE;	/* CE:H */
	ndelay(700);

	return 0;
}

static void rs5c313_check_xstp_bit(void)
{
	struct rtc_time tm;
	int cnt;

	RS5C313_CEENABLE;	/* CE:H */
	if (rs5c313_read_cntreg() & RS5C313_CNTREG_WTEN_XSTP) {
		/* INT interval reg. OFF */
		rs5c313_write_intintvreg(0x00);
		/* Initialize control reg. 24 hour & adjust */
		rs5c313_write_cntreg(0x07);

		/* busy check. */
		for (cnt = 0; cnt < 100; cnt++) {
			if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
				break;
			RS5C313_MISCOP;
		}

		memset(&tm, 0, sizeof(struct rtc_time));
		tm.tm_mday	= 1;
		tm.tm_mon	= 1 - 1;
		tm.tm_year	= 2000 - 1900;

		rs5c313_rtc_set_time(NULL, &tm);
		pr_err("invalid value, resetting to 1 Jan 2000\n");
	}
	RS5C313_CEDISABLE;
	ndelay(700);		/* CE:L */
}

static const struct rtc_class_ops rs5c313_rtc_ops = {
	.read_time = rs5c313_rtc_read_time,
	.set_time = rs5c313_rtc_set_time,
};

static int rs5c313_rtc_probe(struct platform_device *pdev)
{
	struct rtc_device *rtc = devm_rtc_device_register(&pdev->dev, "rs5c313",
				&rs5c313_rtc_ops, THIS_MODULE);

	if (IS_ERR(rtc))
		return PTR_ERR(rtc);

	platform_set_drvdata(pdev, rtc);

	return 0;
}

static struct platform_driver rs5c313_rtc_platform_driver = {
	.driver         = {
		.name   = DRV_NAME,
	},
	.probe	= rs5c313_rtc_probe,
};

static int __init rs5c313_rtc_init(void)
{
	int err;

	err = platform_driver_register(&rs5c313_rtc_platform_driver);
	if (err)
		return err;

	rs5c313_init_port();
	rs5c313_check_xstp_bit();

	return 0;
}

static void __exit rs5c313_rtc_exit(void)
{
	platform_driver_unregister(&rs5c313_rtc_platform_driver);
}

module_init(rs5c313_rtc_init);
module_exit(rs5c313_rtc_exit);

MODULE_AUTHOR("kogiidena , Nobuhiro Iwamatsu <[email protected]>");
MODULE_DESCRIPTION("Ricoh RS5C313 RTC device driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
e9f2bd81 NI	1	/*
	2	* Ricoh RS5C313 RTC device/driver
	3	* Copyright (C) 2007 Nobuhiro Iwamatsu
	4	*
	5	* 2005-09-19 modifed by kogiidena
	6	*
	7	* Based on the old drivers/char/rs5c313_rtc.c by:
	8	* Copyright (C) 2000 Philipp Rumpf <[email protected]>
	9	* Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
	10	*
	11	* Based on code written by Paul Gortmaker.
	12	* Copyright (C) 1996 Paul Gortmaker
	13	*
	14	* This file is subject to the terms and conditions of the GNU General Public
	15	* License. See the file "COPYING" in the main directory of this archive
	16	* for more details.
	17	*
	18	* Based on other minimal char device drivers, like Alan's
	19	* watchdog, Ted's random, etc. etc.
	20	*
	21	* 1.07 Paul Gortmaker.
	22	* 1.08 Miquel van Smoorenburg: disallow certain things on the
	23	* DEC Alpha as the CMOS clock is also used for other things.
	24	* 1.09 Nikita Schmidt: epoch support and some Alpha cleanup.
	25	* 1.09a Pete Zaitcev: Sun SPARC
	26	* 1.09b Jeff Garzik: Modularize, init cleanup
	27	* 1.09c Jeff Garzik: SMP cleanup
	28	* 1.10 Paul Barton-Davis: add support for async I/O
	29	* 1.10a Andrea Arcangeli: Alpha updates
	30	* 1.10b Andrew Morton: SMP lock fix
	31	* 1.10c Cesar Barros: SMP locking fixes and cleanup
	32	* 1.10d Paul Gortmaker: delete paranoia check in rtc_exit
	33	* 1.10e Maciej W. Rozycki: Handle DECstation's year weirdness.
	34	* 1.11 Takashi Iwai: Kernel access functions
	35	* rtc_register/rtc_unregister/rtc_control
	36	* 1.11a Daniele Bellucci: Audit create_proc_read_entry in rtc_init
	37	* 1.12 Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer
	38	* CONFIG_HPET_EMULATE_RTC
	39	* 1.13 Nobuhiro Iwamatsu: Updata driver.
	40	*/
	41
aa161902 JH	42	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
aa161902 JH	43
e9f2bd81 NI	44	#include <linux/module.h>
	45	#include <linux/err.h>
	46	#include <linux/rtc.h>
	47	#include <linux/platform_device.h>
	48	#include <linux/bcd.h>
	49	#include <linux/delay.h>
91b80e4c	50	#include <linux/io.h>
e9f2bd81 NI	51
e9f2bd81 NI	52	#define DRV_NAME "rs5c313"
e9f2bd81 NI	53
	54	#ifdef CONFIG_SH_LANDISK
	55	/*****************************************************/
	56	/* LANDISK dependence part of RS5C313 */
	57	/*****************************************************/
	58
	59	#define SCSMR1 0xFFE00000
	60	#define SCSCR1 0xFFE00008
	61	#define SCSMR1_CA 0x80
	62	#define SCSCR1_CKE 0x03
	63	#define SCSPTR1 0xFFE0001C
	64	#define SCSPTR1_EIO 0x80
	65	#define SCSPTR1_SPB1IO 0x08
	66	#define SCSPTR1_SPB1DT 0x04
	67	#define SCSPTR1_SPB0IO 0x02
	68	#define SCSPTR1_SPB0DT 0x01
	69
	70	#define SDA_OEN SCSPTR1_SPB1IO
	71	#define SDA SCSPTR1_SPB1DT
	72	#define SCL_OEN SCSPTR1_SPB0IO
	73	#define SCL SCSPTR1_SPB0DT
	74
	75	/* RICOH RS5C313 CE port */
	76	#define RS5C313_CE 0xB0000003
	77
	78	/* RICOH RS5C313 CE port bit */
	79	#define RS5C313_CE_RTCCE 0x02
	80
	81	/* SCSPTR1 data */
	82	unsigned char scsptr1_data;
	83
071a1e33 PM	84	#define RS5C313_CEENABLE __raw_writeb(RS5C313_CE_RTCCE, RS5C313_CE);
	85	#define RS5C313_CEDISABLE __raw_writeb(0x00, RS5C313_CE)
	86	#define RS5C313_MISCOP __raw_writeb(0x02, 0xB0000008)
e9f2bd81 NI	87
	88	static void rs5c313_init_port(void)
	89	{
	90	/* Set SCK as I/O port and Initialize SCSPTR1 data & I/O port. */
071a1e33 PM	91	__raw_writeb(__raw_readb(SCSMR1) & ~SCSMR1_CA, SCSMR1);
071a1e33 PM	92	__raw_writeb(__raw_readb(SCSCR1) & ~SCSCR1_CKE, SCSCR1);
e9f2bd81 NI	93
e9f2bd81 NI	94	/* And Initialize SCL for RS5C313 clock */
071a1e33 PM	95	scsptr1_data = __raw_readb(SCSPTR1) \| SCL; /* SCL:H */
	96	__raw_writeb(scsptr1_data, SCSPTR1);
	97	scsptr1_data = __raw_readb(SCSPTR1) \| SCL_OEN; /* SCL output enable */
	98	__raw_writeb(scsptr1_data, SCSPTR1);
e9f2bd81 NI	99	RS5C313_CEDISABLE; /* CE:L */
	100	}
	101
	102	static void rs5c313_write_data(unsigned char data)
	103	{
	104	int i;
	105
	106	for (i = 0; i < 8; i++) {
	107	/* SDA:Write Data */
	108	scsptr1_data = (scsptr1_data & ~SDA) \|
	109	((((0x80 >> i) & data) >> (7 - i)) << 2);
071a1e33	110	__raw_writeb(scsptr1_data, SCSPTR1);
e9f2bd81 NI	111	if (i == 0) {
e9f2bd81 NI	112	scsptr1_data \|= SDA_OEN; /* SDA:output enable */
071a1e33	113	__raw_writeb(scsptr1_data, SCSPTR1);
e9f2bd81 NI	114	}
	115	ndelay(700);
	116	scsptr1_data &= ~SCL; /* SCL:L */
071a1e33	117	__raw_writeb(scsptr1_data, SCSPTR1);
e9f2bd81 NI	118	ndelay(700);
e9f2bd81 NI	119	scsptr1_data \|= SCL; /* SCL:H */
071a1e33	120	__raw_writeb(scsptr1_data, SCSPTR1);
e9f2bd81 NI	121	}
	122
	123	scsptr1_data &= ~SDA_OEN; /* SDA:output disable */
071a1e33	124	__raw_writeb(scsptr1_data, SCSPTR1);
e9f2bd81 NI	125	}
	126
	127	static unsigned char rs5c313_read_data(void)
	128	{
	129	int i;
9a3f1d53	130	unsigned char data = 0;
e9f2bd81 NI	131
	132	for (i = 0; i < 8; i++) {
	133	ndelay(700);
	134	/* SDA:Read Data */
071a1e33	135	data \|= ((__raw_readb(SCSPTR1) & SDA) >> 2) << (7 - i);
e9f2bd81	136	scsptr1_data &= ~SCL; /* SCL:L */
071a1e33	137	__raw_writeb(scsptr1_data, SCSPTR1);
e9f2bd81 NI	138	ndelay(700);
e9f2bd81 NI	139	scsptr1_data \|= SCL; /* SCL:H */
071a1e33	140	__raw_writeb(scsptr1_data, SCSPTR1);
e9f2bd81 NI	141	}
	142	return data & 0x0F;
	143	}
	144
	145	#endif /* CONFIG_SH_LANDISK */
	146
	147	/*****************************************************/
	148	/* machine independence part of RS5C313 */
	149	/*****************************************************/
	150
	151	/* RICOH RS5C313 address */
	152	#define RS5C313_ADDR_SEC 0x00
	153	#define RS5C313_ADDR_SEC10 0x01
	154	#define RS5C313_ADDR_MIN 0x02
	155	#define RS5C313_ADDR_MIN10 0x03
	156	#define RS5C313_ADDR_HOUR 0x04
	157	#define RS5C313_ADDR_HOUR10 0x05
	158	#define RS5C313_ADDR_WEEK 0x06
	159	#define RS5C313_ADDR_INTINTVREG 0x07
	160	#define RS5C313_ADDR_DAY 0x08
	161	#define RS5C313_ADDR_DAY10 0x09
	162	#define RS5C313_ADDR_MON 0x0A
	163	#define RS5C313_ADDR_MON10 0x0B
	164	#define RS5C313_ADDR_YEAR 0x0C
	165	#define RS5C313_ADDR_YEAR10 0x0D
	166	#define RS5C313_ADDR_CNTREG 0x0E
	167	#define RS5C313_ADDR_TESTREG 0x0F
	168
	169	/* RICOH RS5C313 control register */
	170	#define RS5C313_CNTREG_ADJ_BSY 0x01
	171	#define RS5C313_CNTREG_WTEN_XSTP 0x02
	172	#define RS5C313_CNTREG_12_24 0x04
	173	#define RS5C313_CNTREG_CTFG 0x08
	174
	175	/* RICOH RS5C313 test register */
	176	#define RS5C313_TESTREG_TEST 0x01
	177
	178	/* RICOH RS5C313 control bit */
	179	#define RS5C313_CNTBIT_READ 0x40
	180	#define RS5C313_CNTBIT_AD 0x20
	181	#define RS5C313_CNTBIT_DT 0x10
	182
	183	static unsigned char rs5c313_read_reg(unsigned char addr)
	184	{
	185
	186	rs5c313_write_data(addr \| RS5C313_CNTBIT_READ \| RS5C313_CNTBIT_AD);
	187	return rs5c313_read_data();
	188	}
	189
	190	static void rs5c313_write_reg(unsigned char addr, unsigned char data)
	191	{
	192	data &= 0x0f;
	193	rs5c313_write_data(addr \| RS5C313_CNTBIT_AD);
	194	rs5c313_write_data(data \| RS5C313_CNTBIT_DT);
	195	return;
	196	}
	197
9a3f1d53	198	static inline unsigned char rs5c313_read_cntreg(void)
e9f2bd81 NI	199	{
	200	return rs5c313_read_reg(RS5C313_ADDR_CNTREG);
	201	}
	202
	203	static inline void rs5c313_write_cntreg(unsigned char data)
	204	{
	205	rs5c313_write_reg(RS5C313_ADDR_CNTREG, data);
	206	}
	207
	208	static inline void rs5c313_write_intintvreg(unsigned char data)
	209	{
	210	rs5c313_write_reg(RS5C313_ADDR_INTINTVREG, data);
	211	}
	212
	213	static int rs5c313_rtc_read_time(struct device dev, struct rtc_time tm)
	214	{
	215	int data;
4ac24b3b	216	int cnt;
e9f2bd81	217
4ac24b3b	218	cnt = 0;
e9f2bd81 NI	219	while (1) {
	220	RS5C313_CEENABLE; /* CE:H */
	221
	222	/* Initialize control reg. 24 hour */
	223	rs5c313_write_cntreg(0x04);
	224
	225	if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
	226	break;
	227
	228	RS5C313_CEDISABLE;
	229	ndelay(700); /* CE:L */
	230
4ac24b3b	231	if (cnt++ > 100) {
2a4e2b87	232	dev_err(dev, "%s: timeout error\n", __func__);
4ac24b3b	233	return -EIO;
4ac24b3b	234	}
e9f2bd81 NI	235	}
	236
	237	data = rs5c313_read_reg(RS5C313_ADDR_SEC);
	238	data \|= (rs5c313_read_reg(RS5C313_ADDR_SEC10) << 4);
fe20ba70	239	tm->tm_sec = bcd2bin(data);
e9f2bd81 NI	240
	241	data = rs5c313_read_reg(RS5C313_ADDR_MIN);
	242	data \|= (rs5c313_read_reg(RS5C313_ADDR_MIN10) << 4);
fe20ba70	243	tm->tm_min = bcd2bin(data);
e9f2bd81 NI	244
	245	data = rs5c313_read_reg(RS5C313_ADDR_HOUR);
	246	data \|= (rs5c313_read_reg(RS5C313_ADDR_HOUR10) << 4);
fe20ba70	247	tm->tm_hour = bcd2bin(data);
e9f2bd81 NI	248
	249	data = rs5c313_read_reg(RS5C313_ADDR_DAY);
	250	data \|= (rs5c313_read_reg(RS5C313_ADDR_DAY10) << 4);
fe20ba70	251	tm->tm_mday = bcd2bin(data);
e9f2bd81 NI	252
	253	data = rs5c313_read_reg(RS5C313_ADDR_MON);
	254	data \|= (rs5c313_read_reg(RS5C313_ADDR_MON10) << 4);
fe20ba70	255	tm->tm_mon = bcd2bin(data) - 1;
e9f2bd81 NI	256
	257	data = rs5c313_read_reg(RS5C313_ADDR_YEAR);
	258	data \|= (rs5c313_read_reg(RS5C313_ADDR_YEAR10) << 4);
fe20ba70	259	tm->tm_year = bcd2bin(data);
e9f2bd81 NI	260
	261	if (tm->tm_year < 70)
	262	tm->tm_year += 100;
	263
	264	data = rs5c313_read_reg(RS5C313_ADDR_WEEK);
fe20ba70	265	tm->tm_wday = bcd2bin(data);
e9f2bd81 NI	266
	267	RS5C313_CEDISABLE;
	268	ndelay(700); /* CE:L */
	269
	270	return 0;
	271	}
	272
	273	static int rs5c313_rtc_set_time(struct device dev, struct rtc_time tm)
	274	{
	275	int data;
4ac24b3b	276	int cnt;
e9f2bd81	277
4ac24b3b	278	cnt = 0;
e9f2bd81 NI	279	/* busy check. */
	280	while (1) {
	281	RS5C313_CEENABLE; /* CE:H */
	282
	283	/* Initiatlize control reg. 24 hour */
	284	rs5c313_write_cntreg(0x04);
	285
	286	if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
	287	break;
	288	RS5C313_MISCOP;
	289	RS5C313_CEDISABLE;
	290	ndelay(700); /* CE:L */
4ac24b3b	291
4ac24b3b	292	if (cnt++ > 100) {
2a4e2b87	293	dev_err(dev, "%s: timeout error\n", __func__);
4ac24b3b	294	return -EIO;
4ac24b3b	295	}
e9f2bd81 NI	296	}
e9f2bd81 NI	297
fe20ba70	298	data = bin2bcd(tm->tm_sec);
e9f2bd81 NI	299	rs5c313_write_reg(RS5C313_ADDR_SEC, data);
	300	rs5c313_write_reg(RS5C313_ADDR_SEC10, (data >> 4));
	301
fe20ba70	302	data = bin2bcd(tm->tm_min);
675090fa	303	rs5c313_write_reg(RS5C313_ADDR_MIN, data);
e9f2bd81 NI	304	rs5c313_write_reg(RS5C313_ADDR_MIN10, (data >> 4));
e9f2bd81 NI	305
fe20ba70	306	data = bin2bcd(tm->tm_hour);
e9f2bd81 NI	307	rs5c313_write_reg(RS5C313_ADDR_HOUR, data);
	308	rs5c313_write_reg(RS5C313_ADDR_HOUR10, (data >> 4));
	309
fe20ba70	310	data = bin2bcd(tm->tm_mday);
e9f2bd81	311	rs5c313_write_reg(RS5C313_ADDR_DAY, data);
675090fa	312	rs5c313_write_reg(RS5C313_ADDR_DAY10, (data >> 4));
e9f2bd81	313
fe20ba70	314	data = bin2bcd(tm->tm_mon + 1);
e9f2bd81 NI	315	rs5c313_write_reg(RS5C313_ADDR_MON, data);
	316	rs5c313_write_reg(RS5C313_ADDR_MON10, (data >> 4));
	317
fe20ba70	318	data = bin2bcd(tm->tm_year % 100);
e9f2bd81 NI	319	rs5c313_write_reg(RS5C313_ADDR_YEAR, data);
	320	rs5c313_write_reg(RS5C313_ADDR_YEAR10, (data >> 4));
	321
fe20ba70	322	data = bin2bcd(tm->tm_wday);
e9f2bd81 NI	323	rs5c313_write_reg(RS5C313_ADDR_WEEK, data);
	324
	325	RS5C313_CEDISABLE; /* CE:H */
	326	ndelay(700);
	327
	328	return 0;
	329	}
	330
	331	static void rs5c313_check_xstp_bit(void)
	332	{
	333	struct rtc_time tm;
4ac24b3b	334	int cnt;
e9f2bd81 NI	335
	336	RS5C313_CEENABLE; /* CE:H */
	337	if (rs5c313_read_cntreg() & RS5C313_CNTREG_WTEN_XSTP) {
	338	/* INT interval reg. OFF */
	339	rs5c313_write_intintvreg(0x00);
	340	/* Initialize control reg. 24 hour & adjust */
	341	rs5c313_write_cntreg(0x07);
	342
	343	/* busy check. */
4ac24b3b	344	for (cnt = 0; cnt < 100; cnt++) {
	345	if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
	346	break;
e9f2bd81	347	RS5C313_MISCOP;
4ac24b3b	348	}
e9f2bd81 NI	349
e9f2bd81 NI	350	memset(&tm, 0, sizeof(struct rtc_time));
675090fa SK	351	tm.tm_mday = 1;
	352	tm.tm_mon = 1 - 1;
	353	tm.tm_year = 2000 - 1900;
e9f2bd81 NI	354
e9f2bd81 NI	355	rs5c313_rtc_set_time(NULL, &tm);
aa161902	356	pr_err("invalid value, resetting to 1 Jan 2000\n");
e9f2bd81 NI	357	}
	358	RS5C313_CEDISABLE;
	359	ndelay(700); /* CE:L */
	360	}
	361
	362	static const struct rtc_class_ops rs5c313_rtc_ops = {
	363	.read_time = rs5c313_rtc_read_time,
	364	.set_time = rs5c313_rtc_set_time,
	365	};
	366
	367	static int rs5c313_rtc_probe(struct platform_device *pdev)
	368	{
284e2fa1	369	struct rtc_device *rtc = devm_rtc_device_register(&pdev->dev, "rs5c313",
e9f2bd81 NI	370	&rs5c313_rtc_ops, THIS_MODULE);
	371
	372	if (IS_ERR(rtc))
	373	return PTR_ERR(rtc);
	374
	375	platform_set_drvdata(pdev, rtc);
	376
9a3f1d53	377	return 0;
e9f2bd81 NI	378	}
e9f2bd81 NI	379
e9f2bd81 NI	380	static struct platform_driver rs5c313_rtc_platform_driver = {
	381	.driver = {
	382	.name = DRV_NAME,
e9f2bd81	383	},
675090fa	384	.probe = rs5c313_rtc_probe,
e9f2bd81 NI	385	};
	386
	387	static int __init rs5c313_rtc_init(void)
	388	{
	389	int err;
	390
	391	err = platform_driver_register(&rs5c313_rtc_platform_driver);
	392	if (err)
	393	return err;
	394
	395	rs5c313_init_port();
	396	rs5c313_check_xstp_bit();
	397
	398	return 0;
	399	}
	400
	401	static void __exit rs5c313_rtc_exit(void)
	402	{
675090fa	403	platform_driver_unregister(&rs5c313_rtc_platform_driver);
e9f2bd81 NI	404	}
	405
	406	module_init(rs5c313_rtc_init);
	407	module_exit(rs5c313_rtc_exit);
	408
e9f2bd81 NI	409	MODULE_AUTHOR("kogiidena , Nobuhiro Iwamatsu <[email protected]>");
	410	MODULE_DESCRIPTION("Ricoh RS5C313 RTC device driver");
	411	MODULE_LICENSE("GPL");
ad28a07b	412	MODULE_ALIAS("platform:" DRV_NAME);