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V4L/DVB (6917): ivtv: small textual update
[linux.git] / drivers / serial / crisv10.c
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77accbf5 1/*
1da177e4
LT		 2 * Serial port driver for the ETRAX 100LX chip
3 *
77accbf5 4 * Copyright (C) 1998-2007 Axis Communications AB
1da177e4
LT		 5 *
6 * Many, many authors. Based once upon a time on serial.c for 16x50.
7 *
1da177e4
LT		 8 */
9
10static char *serial_version = "$Revision: 1.25 $";
11
1da177e4
LT		 12#include <linux/types.h>
13#include <linux/errno.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/timer.h>
17#include <linux/interrupt.h>
18#include <linux/tty.h>
19#include <linux/tty_flip.h>
20#include <linux/major.h>
21#include <linux/string.h>
22#include <linux/fcntl.h>
23#include <linux/mm.h>
24#include <linux/slab.h>
25#include <linux/init.h>
26#include <asm/uaccess.h>
27#include <linux/kernel.h>
f392ecfa 28#include <linux/mutex.h>
1977f032 29#include <linux/bitops.h>
1da177e4
LT		 30
31#include <asm/io.h>
32#include <asm/irq.h>
77accbf5 33#include <asm/dma.h>
1da177e4 34#include <asm/system.h>
1da177e4
LT		 35#include <linux/delay.h>
36
37#include <asm/arch/svinto.h>
38
39/* non-arch dependent serial structures are in linux/serial.h */
40#include <linux/serial.h>
41/* while we keep our own stuff (struct e100_serial) in a local .h file */
77accbf5 42#include "crisv10.h"
1da177e4 43#include <asm/fasttimer.h>
77accbf5 44#include <asm/arch/io_interface_mux.h>
1da177e4
LT		 45
46#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
47#ifndef CONFIG_ETRAX_FAST_TIMER
48#error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
49#endif
50#endif
51
52#if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
53 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
54#error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
55#endif
56
57#if defined(CONFIG_ETRAX_RS485_ON_PA) && defined(CONFIG_ETRAX_RS485_ON_PORT_G)
58#error "Disable either CONFIG_ETRAX_RS485_ON_PA or CONFIG_ETRAX_RS485_ON_PORT_G"
59#endif
60
61/*
62 * All of the compatibilty code so we can compile serial.c against
63 * older kernels is hidden in serial_compat.h
64 */
65#if defined(LOCAL_HEADERS)
66#include "serial_compat.h"
67#endif
68
1da177e4
LT		 69struct tty_driver *serial_driver;
70
71/* serial subtype definitions */
72#ifndef SERIAL_TYPE_NORMAL
73#define SERIAL_TYPE_NORMAL 1
74#endif
75
76/* number of characters left in xmit buffer before we ask for more */
77#define WAKEUP_CHARS 256
78
79//#define SERIAL_DEBUG_INTR
80//#define SERIAL_DEBUG_OPEN
81//#define SERIAL_DEBUG_FLOW
82//#define SERIAL_DEBUG_DATA
83//#define SERIAL_DEBUG_THROTTLE
84//#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
85//#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
86
87/* Enable this to use serial interrupts to handle when you
88 expect the first received event on the serial port to
89 be an error, break or similar. Used to be able to flash IRMA
90 from eLinux */
91#define SERIAL_HANDLE_EARLY_ERRORS
92
1da177e4
LT		 93/* Currently 16 descriptors x 128 bytes = 2048 bytes */
94#define SERIAL_DESCR_BUF_SIZE 256
95
96#define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
97#define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
98
99/* We don't want to load the system with massive fast timer interrupt
100 * on high baudrates so limit it to 250 us (4kHz) */
101#define MIN_FLUSH_TIME_USEC 250
102
103/* Add an x here to log a lot of timer stuff */
104#define TIMERD(x)
105/* Debug details of interrupt handling */
106#define DINTR1(x) /* irq on/off, errors */
107#define DINTR2(x) /* tx and rx */
108/* Debug flip buffer stuff */
109#define DFLIP(x)
110/* Debug flow control and overview of data flow */
111#define DFLOW(x)
112#define DBAUD(x)
113#define DLOG_INT_TRIG(x)
114
115//#define DEBUG_LOG_INCLUDED
116#ifndef DEBUG_LOG_INCLUDED
117#define DEBUG_LOG(line, string, value)
118#else
119struct debug_log_info
120{
121 unsigned long time;
122 unsigned long timer_data;
123// int line;
124 const char *string;
125 int value;
126};
127#define DEBUG_LOG_SIZE 4096
128
129struct debug_log_info debug_log[DEBUG_LOG_SIZE];
130int debug_log_pos = 0;
131
132#define DEBUG_LOG(_line, _string, _value) do { \
133 if ((_line) == SERIAL_DEBUG_LINE) {\
134 debug_log_func(_line, _string, _value); \
135 }\
136}while(0)
137
138void debug_log_func(int line, const char *string, int value)
139{
140 if (debug_log_pos < DEBUG_LOG_SIZE) {
141 debug_log[debug_log_pos].time = jiffies;
142 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
143// debug_log[debug_log_pos].line = line;
144 debug_log[debug_log_pos].string = string;
145 debug_log[debug_log_pos].value = value;
146 debug_log_pos++;
147 }
148 /*printk(string, value);*/
149}
150#endif
151
152#ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
153/* Default number of timer ticks before flushing rx fifo
154 * When using "little data, low latency applications: use 0
155 * When using "much data applications (PPP)" use ~5
156 */
157#define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
158#endif
159
160unsigned long timer_data_to_ns(unsigned long timer_data);
161
162static void change_speed(struct e100_serial *info);
163static void rs_throttle(struct tty_struct * tty);
164static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
77accbf5
JN		 165static int rs_write(struct tty_struct *tty,
166 const unsigned char *buf, int count);
1da177e4 167#ifdef CONFIG_ETRAX_RS485
77accbf5
JN		 168static int e100_write_rs485(struct tty_struct *tty,
169 const unsigned char *buf, int count);
1da177e4 170#endif
77accbf5 171static int get_lsr_info(struct e100_serial *info, unsigned int *value);
1da177e4
LT		 172
173
174#define DEF_BAUD 115200 /* 115.2 kbit/s */
175#define STD_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
176#define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
177/* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
178#define DEF_TX 0x80 /* or SERIAL_CTRL_B */
179
180/* offsets from R_SERIALx_CTRL */
181
182#define REG_DATA 0
183#define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
184#define REG_TR_DATA 0
185#define REG_STATUS 1
186#define REG_TR_CTRL 1
187#define REG_REC_CTRL 2
188#define REG_BAUD 3
189#define REG_XOFF 4 /* this is a 32 bit register */
190
191/* The bitfields are the same for all serial ports */
192#define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
193#define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
194#define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
195#define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
196#define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
197
198#define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
199
200/* Values for info->errorcode */
201#define ERRCODE_SET_BREAK (TTY_BREAK)
202#define ERRCODE_INSERT 0x100
203#define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
204
205#define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
206
207/*
208 * General note regarding the use of IO_* macros in this file:
209 *
210 * We will use the bits defined for DMA channel 6 when using various
211 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
212 * the same for all channels (which of course they are).
213 *
214 * We will also use the bits defined for serial port 0 when writing commands
215 * to the different ports, as these bits too are the same for all ports.
216 */
217
218
219/* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
220static const unsigned long e100_ser_int_mask = 0
221#ifdef CONFIG_ETRAX_SERIAL_PORT0
222| IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
223#endif
224#ifdef CONFIG_ETRAX_SERIAL_PORT1
225| IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
226#endif
227#ifdef CONFIG_ETRAX_SERIAL_PORT2
228| IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
229#endif
230#ifdef CONFIG_ETRAX_SERIAL_PORT3
231| IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
232#endif
233;
234unsigned long r_alt_ser_baudrate_shadow = 0;
235
236/* this is the data for the four serial ports in the etrax100 */
237/* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
238/* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
239
240static struct e100_serial rs_table[] = {
241 { .baud = DEF_BAUD,
242 .port = (unsigned char *)R_SERIAL0_CTRL,
243 .irq = 1U << 12, /* uses DMA 6 and 7 */
244 .oclrintradr = R_DMA_CH6_CLR_INTR,
245 .ofirstadr = R_DMA_CH6_FIRST,
246 .ocmdadr = R_DMA_CH6_CMD,
247 .ostatusadr = R_DMA_CH6_STATUS,
248 .iclrintradr = R_DMA_CH7_CLR_INTR,
249 .ifirstadr = R_DMA_CH7_FIRST,
250 .icmdadr = R_DMA_CH7_CMD,
251 .idescradr = R_DMA_CH7_DESCR,
252 .flags = STD_FLAGS,
253 .rx_ctrl = DEF_RX,
254 .tx_ctrl = DEF_TX,
255 .iseteop = 2,
77accbf5
JN		 256 .dma_owner = dma_ser0,
257 .io_if = if_serial_0,
1da177e4
LT		 258#ifdef CONFIG_ETRAX_SERIAL_PORT0
259 .enabled = 1,
260#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
261 .dma_out_enabled = 1,
77accbf5
JN		 262 .dma_out_nbr = SER0_TX_DMA_NBR,
263 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
264 .dma_out_irq_flags = IRQF_DISABLED,
265 .dma_out_irq_description = "serial 0 dma tr",
1da177e4
LT		 266#else
267 .dma_out_enabled = 0,
77accbf5
JN		 268 .dma_out_nbr = UINT_MAX,
269 .dma_out_irq_nbr = 0,
270 .dma_out_irq_flags = 0,
271 .dma_out_irq_description = NULL,
1da177e4
LT		 272#endif
273#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
274 .dma_in_enabled = 1,
77accbf5
JN		 275 .dma_in_nbr = SER0_RX_DMA_NBR,
276 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
277 .dma_in_irq_flags = IRQF_DISABLED,
278 .dma_in_irq_description = "serial 0 dma rec",
1da177e4 279#else
77accbf5
JN		 280 .dma_in_enabled = 0,
281 .dma_in_nbr = UINT_MAX,
282 .dma_in_irq_nbr = 0,
283 .dma_in_irq_flags = 0,
284 .dma_in_irq_description = NULL,
1da177e4
LT		 285#endif
286#else
287 .enabled = 0,
77accbf5 288 .io_if_description = NULL,
1da177e4
LT		 289 .dma_out_enabled = 0,
290 .dma_in_enabled = 0
291#endif
292
293}, /* ttyS0 */
294#ifndef CONFIG_SVINTO_SIM
295 { .baud = DEF_BAUD,
296 .port = (unsigned char *)R_SERIAL1_CTRL,
297 .irq = 1U << 16, /* uses DMA 8 and 9 */
298 .oclrintradr = R_DMA_CH8_CLR_INTR,
299 .ofirstadr = R_DMA_CH8_FIRST,
300 .ocmdadr = R_DMA_CH8_CMD,
301 .ostatusadr = R_DMA_CH8_STATUS,
302 .iclrintradr = R_DMA_CH9_CLR_INTR,
303 .ifirstadr = R_DMA_CH9_FIRST,
304 .icmdadr = R_DMA_CH9_CMD,
305 .idescradr = R_DMA_CH9_DESCR,
306 .flags = STD_FLAGS,
307 .rx_ctrl = DEF_RX,
308 .tx_ctrl = DEF_TX,
309 .iseteop = 3,
77accbf5
JN		 310 .dma_owner = dma_ser1,
311 .io_if = if_serial_1,
1da177e4
LT		 312#ifdef CONFIG_ETRAX_SERIAL_PORT1
313 .enabled = 1,
77accbf5 314 .io_if_description = "ser1",
1da177e4
LT		 315#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
316 .dma_out_enabled = 1,
77accbf5
JN		 317 .dma_out_nbr = SER1_TX_DMA_NBR,
318 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
319 .dma_out_irq_flags = IRQF_DISABLED,
320 .dma_out_irq_description = "serial 1 dma tr",
1da177e4
LT		 321#else
322 .dma_out_enabled = 0,
77accbf5
JN		 323 .dma_out_nbr = UINT_MAX,
324 .dma_out_irq_nbr = 0,
325 .dma_out_irq_flags = 0,
326 .dma_out_irq_description = NULL,
1da177e4
LT		 327#endif
328#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
329 .dma_in_enabled = 1,
77accbf5
JN		 330 .dma_in_nbr = SER1_RX_DMA_NBR,
331 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
332 .dma_in_irq_flags = IRQF_DISABLED,
333 .dma_in_irq_description = "serial 1 dma rec",
1da177e4 334#else
77accbf5
JN		 335 .dma_in_enabled = 0,
336 .dma_in_enabled = 0,
337 .dma_in_nbr = UINT_MAX,
338 .dma_in_irq_nbr = 0,
339 .dma_in_irq_flags = 0,
340 .dma_in_irq_description = NULL,
1da177e4
LT		 341#endif
342#else
343 .enabled = 0,
77accbf5
JN		 344 .io_if_description = NULL,
345 .dma_in_irq_nbr = 0,
1da177e4
LT		 346 .dma_out_enabled = 0,
347 .dma_in_enabled = 0
348#endif
349}, /* ttyS1 */
350
351 { .baud = DEF_BAUD,
352 .port = (unsigned char *)R_SERIAL2_CTRL,
353 .irq = 1U << 4, /* uses DMA 2 and 3 */
354 .oclrintradr = R_DMA_CH2_CLR_INTR,
355 .ofirstadr = R_DMA_CH2_FIRST,
356 .ocmdadr = R_DMA_CH2_CMD,
357 .ostatusadr = R_DMA_CH2_STATUS,
358 .iclrintradr = R_DMA_CH3_CLR_INTR,
359 .ifirstadr = R_DMA_CH3_FIRST,
360 .icmdadr = R_DMA_CH3_CMD,
361 .idescradr = R_DMA_CH3_DESCR,
362 .flags = STD_FLAGS,
363 .rx_ctrl = DEF_RX,
364 .tx_ctrl = DEF_TX,
365 .iseteop = 0,
77accbf5
JN		 366 .dma_owner = dma_ser2,
367 .io_if = if_serial_2,
1da177e4
LT		 368#ifdef CONFIG_ETRAX_SERIAL_PORT2
369 .enabled = 1,
77accbf5 370 .io_if_description = "ser2",
1da177e4
LT		 371#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
372 .dma_out_enabled = 1,
77accbf5
JN		 373 .dma_out_nbr = SER2_TX_DMA_NBR,
374 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
375 .dma_out_irq_flags = IRQF_DISABLED,
376 .dma_out_irq_description = "serial 2 dma tr",
1da177e4
LT		 377#else
378 .dma_out_enabled = 0,
77accbf5
JN		 379 .dma_out_nbr = UINT_MAX,
380 .dma_out_irq_nbr = 0,
381 .dma_out_irq_flags = 0,
382 .dma_out_irq_description = NULL,
1da177e4
LT		 383#endif
384#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
385 .dma_in_enabled = 1,
77accbf5
JN		 386 .dma_in_nbr = SER2_RX_DMA_NBR,
387 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
388 .dma_in_irq_flags = IRQF_DISABLED,
389 .dma_in_irq_description = "serial 2 dma rec",
1da177e4 390#else
77accbf5
JN		 391 .dma_in_enabled = 0,
392 .dma_in_nbr = UINT_MAX,
393 .dma_in_irq_nbr = 0,
394 .dma_in_irq_flags = 0,
395 .dma_in_irq_description = NULL,
1da177e4
LT		 396#endif
397#else
398 .enabled = 0,
77accbf5 399 .io_if_description = NULL,
1da177e4
LT		 400 .dma_out_enabled = 0,
401 .dma_in_enabled = 0
402#endif
403 }, /* ttyS2 */
404
405 { .baud = DEF_BAUD,
406 .port = (unsigned char *)R_SERIAL3_CTRL,
407 .irq = 1U << 8, /* uses DMA 4 and 5 */
408 .oclrintradr = R_DMA_CH4_CLR_INTR,
409 .ofirstadr = R_DMA_CH4_FIRST,
410 .ocmdadr = R_DMA_CH4_CMD,
411 .ostatusadr = R_DMA_CH4_STATUS,
412 .iclrintradr = R_DMA_CH5_CLR_INTR,
413 .ifirstadr = R_DMA_CH5_FIRST,
414 .icmdadr = R_DMA_CH5_CMD,
415 .idescradr = R_DMA_CH5_DESCR,
416 .flags = STD_FLAGS,
417 .rx_ctrl = DEF_RX,
418 .tx_ctrl = DEF_TX,
419 .iseteop = 1,
77accbf5
JN		 420 .dma_owner = dma_ser3,
421 .io_if = if_serial_3,
1da177e4
LT		 422#ifdef CONFIG_ETRAX_SERIAL_PORT3
423 .enabled = 1,
77accbf5 424 .io_if_description = "ser3",
1da177e4
LT		 425#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
426 .dma_out_enabled = 1,
77accbf5
JN		 427 .dma_out_nbr = SER3_TX_DMA_NBR,
428 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
429 .dma_out_irq_flags = IRQF_DISABLED,
430 .dma_out_irq_description = "serial 3 dma tr",
1da177e4
LT		 431#else
432 .dma_out_enabled = 0,
77accbf5
JN		 433 .dma_out_nbr = UINT_MAX,
434 .dma_out_irq_nbr = 0,
435 .dma_out_irq_flags = 0,
436 .dma_out_irq_description = NULL,
1da177e4
LT		 437#endif
438#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
439 .dma_in_enabled = 1,
77accbf5
JN		 440 .dma_in_nbr = SER3_RX_DMA_NBR,
441 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
442 .dma_in_irq_flags = IRQF_DISABLED,
443 .dma_in_irq_description = "serial 3 dma rec",
1da177e4 444#else
77accbf5
JN		 445 .dma_in_enabled = 0,
446 .dma_in_nbr = UINT_MAX,
447 .dma_in_irq_nbr = 0,
448 .dma_in_irq_flags = 0,
449 .dma_in_irq_description = NULL
1da177e4
LT		 450#endif
451#else
452 .enabled = 0,
77accbf5 453 .io_if_description = NULL,
1da177e4
LT		 454 .dma_out_enabled = 0,
455 .dma_in_enabled = 0
456#endif
457 } /* ttyS3 */
458#endif
459};
460
461
462#define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
463
606d099c
AC		 464static struct ktermios *serial_termios[NR_PORTS];
465static struct ktermios *serial_termios_locked[NR_PORTS];
1da177e4
LT		 466#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
467static struct fast_timer fast_timers[NR_PORTS];
468#endif
469
470#ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY
471#define PROCSTAT(x) x
472struct ser_statistics_type {
473 int overrun_cnt;
474 int early_errors_cnt;
475 int ser_ints_ok_cnt;
476 int errors_cnt;
477 unsigned long int processing_flip;
478 unsigned long processing_flip_still_room;
479 unsigned long int timeout_flush_cnt;
480 int rx_dma_ints;
481 int tx_dma_ints;
482 int rx_tot;
483 int tx_tot;
484};
485
486static struct ser_statistics_type ser_stat[NR_PORTS];
487
488#else
489
490#define PROCSTAT(x)
491
492#endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */
493
494/* RS-485 */
495#if defined(CONFIG_ETRAX_RS485)
496#ifdef CONFIG_ETRAX_FAST_TIMER
497static struct fast_timer fast_timers_rs485[NR_PORTS];
498#endif
499#if defined(CONFIG_ETRAX_RS485_ON_PA)
500static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
501#endif
502#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
503static int rs485_port_g_bit = CONFIG_ETRAX_RS485_ON_PORT_G_BIT;
504#endif
505#endif
506
507/* Info and macros needed for each ports extra control/status signals. */
508#define E100_STRUCT_PORT(line, pinname) \
509 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
510 (R_PORT_PA_DATA): ( \
511 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
512 (R_PORT_PB_DATA):&dummy_ser[line]))
513
514#define E100_STRUCT_SHADOW(line, pinname) \
515 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
516 (&port_pa_data_shadow): ( \
517 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
518 (&port_pb_data_shadow):&dummy_ser[line]))
519#define E100_STRUCT_MASK(line, pinname) \
520 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
521 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
522 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
523 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
524
525#define DUMMY_DTR_MASK 1
526#define DUMMY_RI_MASK 2
527#define DUMMY_DSR_MASK 4
528#define DUMMY_CD_MASK 8
529static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
530
531/* If not all status pins are used or disabled, use mixed mode */
532#ifdef CONFIG_ETRAX_SERIAL_PORT0
533
534#define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
535
536#if SER0_PA_BITSUM != -4
537# if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
538# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
539# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
540# endif
541# endif
542# if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
543# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
544# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
545# endif
546# endif
547# if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
548# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
549# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
550# endif
551# endif
552# if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
553# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
554# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
555# endif
556# endif
557#endif
558
559#define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
560
561#if SER0_PB_BITSUM != -4
562# if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
563# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
564# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
565# endif
566# endif
567# if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
568# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
569# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
570# endif
571# endif
572# if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
573# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
574# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
575# endif
576# endif
577# if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
578# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
579# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
580# endif
581# endif
582#endif
583
584#endif /* PORT0 */
585
586
587#ifdef CONFIG_ETRAX_SERIAL_PORT1
588
589#define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
590
591#if SER1_PA_BITSUM != -4
592# if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
593# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
594# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
595# endif
596# endif
597# if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
598# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
599# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
600# endif
601# endif
602# if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
603# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
604# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
605# endif
606# endif
607# if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
608# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
609# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
610# endif
611# endif
612#endif
613
614#define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
615
616#if SER1_PB_BITSUM != -4
617# if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
618# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
619# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
620# endif
621# endif
622# if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
623# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
624# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
625# endif
626# endif
627# if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
628# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
629# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
630# endif
631# endif
632# if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
633# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
634# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
635# endif
636# endif
637#endif
638
639#endif /* PORT1 */
640
641#ifdef CONFIG_ETRAX_SERIAL_PORT2
642
643#define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
644
645#if SER2_PA_BITSUM != -4
646# if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
647# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
648# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
649# endif
650# endif
651# if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
652# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
653# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
654# endif
655# endif
656# if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
657# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
658# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
659# endif
660# endif
661# if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
662# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
663# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
664# endif
665# endif
666#endif
667
668#define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
669
670#if SER2_PB_BITSUM != -4
671# if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
672# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
673# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
674# endif
675# endif
676# if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
677# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
678# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
679# endif
680# endif
681# if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
682# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
683# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
684# endif
685# endif
686# if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
687# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
688# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
689# endif
690# endif
691#endif
692
693#endif /* PORT2 */
694
695#ifdef CONFIG_ETRAX_SERIAL_PORT3
696
697#define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
698
699#if SER3_PA_BITSUM != -4
700# if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
701# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
702# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
703# endif
704# endif
705# if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
706# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
707# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
708# endif
709# endif
710# if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
711# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
712# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
713# endif
714# endif
715# if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
716# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
717# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
718# endif
719# endif
720#endif
721
722#define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
723
724#if SER3_PB_BITSUM != -4
725# if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
726# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
727# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
728# endif
729# endif
730# if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
731# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
732# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
733# endif
734# endif
735# if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
736# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
737# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
738# endif
739# endif
740# if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
741# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
742# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
743# endif
744# endif
745#endif
746
747#endif /* PORT3 */
748
749
750#if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
751 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
752 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
753 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
754#define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
755#endif
756
757#ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
758/* The pins can be mixed on PA and PB */
759#define CONTROL_PINS_PORT_NOT_USED(line) \
760 &dummy_ser[line], &dummy_ser[line], \
761 &dummy_ser[line], &dummy_ser[line], \
762 &dummy_ser[line], &dummy_ser[line], \
763 &dummy_ser[line], &dummy_ser[line], \
764 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
765
766
767struct control_pins
768{
769 volatile unsigned char *dtr_port;
770 unsigned char *dtr_shadow;
771 volatile unsigned char *ri_port;
772 unsigned char *ri_shadow;
773 volatile unsigned char *dsr_port;
774 unsigned char *dsr_shadow;
775 volatile unsigned char *cd_port;
776 unsigned char *cd_shadow;
777
778 unsigned char dtr_mask;
779 unsigned char ri_mask;
780 unsigned char dsr_mask;
781 unsigned char cd_mask;
782};
783
784static const struct control_pins e100_modem_pins[NR_PORTS] =
785{
786 /* Ser 0 */
787 {
788#ifdef CONFIG_ETRAX_SERIAL_PORT0
789 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
790 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
791 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
792 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
793 E100_STRUCT_MASK(0,DTR),
794 E100_STRUCT_MASK(0,RI),
795 E100_STRUCT_MASK(0,DSR),
796 E100_STRUCT_MASK(0,CD)
797#else
798 CONTROL_PINS_PORT_NOT_USED(0)
799#endif
800 },
801
802 /* Ser 1 */
803 {
804#ifdef CONFIG_ETRAX_SERIAL_PORT1
805 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
806 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
807 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
808 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
809 E100_STRUCT_MASK(1,DTR),
810 E100_STRUCT_MASK(1,RI),
811 E100_STRUCT_MASK(1,DSR),
812 E100_STRUCT_MASK(1,CD)
813#else
814 CONTROL_PINS_PORT_NOT_USED(1)
815#endif
816 },
817
818 /* Ser 2 */
819 {
820#ifdef CONFIG_ETRAX_SERIAL_PORT2
821 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
822 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
823 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
824 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
825 E100_STRUCT_MASK(2,DTR),
826 E100_STRUCT_MASK(2,RI),
827 E100_STRUCT_MASK(2,DSR),
828 E100_STRUCT_MASK(2,CD)
829#else
830 CONTROL_PINS_PORT_NOT_USED(2)
831#endif
832 },
833
834 /* Ser 3 */
835 {
836#ifdef CONFIG_ETRAX_SERIAL_PORT3
837 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
838 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
839 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
840 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
841 E100_STRUCT_MASK(3,DTR),
842 E100_STRUCT_MASK(3,RI),
843 E100_STRUCT_MASK(3,DSR),
844 E100_STRUCT_MASK(3,CD)
845#else
846 CONTROL_PINS_PORT_NOT_USED(3)
847#endif
848 }
849};
850#else /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
851
852/* All pins are on either PA or PB for each serial port */
853#define CONTROL_PINS_PORT_NOT_USED(line) \
854 &dummy_ser[line], &dummy_ser[line], \
855 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
856
857
858struct control_pins
859{
860 volatile unsigned char *port;
861 unsigned char *shadow;
862
863 unsigned char dtr_mask;
864 unsigned char ri_mask;
865 unsigned char dsr_mask;
866 unsigned char cd_mask;
867};
868
869#define dtr_port port
870#define dtr_shadow shadow
871#define ri_port port
872#define ri_shadow shadow
873#define dsr_port port
874#define dsr_shadow shadow
875#define cd_port port
876#define cd_shadow shadow
877
878static const struct control_pins e100_modem_pins[NR_PORTS] =
879{
880 /* Ser 0 */
881 {
882#ifdef CONFIG_ETRAX_SERIAL_PORT0
883 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
884 E100_STRUCT_MASK(0,DTR),
885 E100_STRUCT_MASK(0,RI),
886 E100_STRUCT_MASK(0,DSR),
887 E100_STRUCT_MASK(0,CD)
888#else
889 CONTROL_PINS_PORT_NOT_USED(0)
890#endif
891 },
892
893 /* Ser 1 */
894 {
895#ifdef CONFIG_ETRAX_SERIAL_PORT1
896 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
897 E100_STRUCT_MASK(1,DTR),
898 E100_STRUCT_MASK(1,RI),
899 E100_STRUCT_MASK(1,DSR),
900 E100_STRUCT_MASK(1,CD)
901#else
902 CONTROL_PINS_PORT_NOT_USED(1)
903#endif
904 },
905
906 /* Ser 2 */
907 {
908#ifdef CONFIG_ETRAX_SERIAL_PORT2
909 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
910 E100_STRUCT_MASK(2,DTR),
911 E100_STRUCT_MASK(2,RI),
912 E100_STRUCT_MASK(2,DSR),
913 E100_STRUCT_MASK(2,CD)
914#else
915 CONTROL_PINS_PORT_NOT_USED(2)
916#endif
917 },
918
919 /* Ser 3 */
920 {
921#ifdef CONFIG_ETRAX_SERIAL_PORT3
922 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
923 E100_STRUCT_MASK(3,DTR),
924 E100_STRUCT_MASK(3,RI),
925 E100_STRUCT_MASK(3,DSR),
926 E100_STRUCT_MASK(3,CD)
927#else
928 CONTROL_PINS_PORT_NOT_USED(3)
929#endif
930 }
931};
932#endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
933
934#define E100_RTS_MASK 0x20
935#define E100_CTS_MASK 0x40
936
937/* All serial port signals are active low:
938 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
939 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
940 *
941 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
942 */
943
944/* Output */
945#define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
946/* Input */
947#define E100_CTS_GET(info) ((info)->port[REG_STATUS] & E100_CTS_MASK)
948
949/* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
950/* Is an output */
951#define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
952
953/* Normally inputs */
954#define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
955#define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
956
957/* Input */
958#define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
959
960
961/*
962 * tmp_buf is used as a temporary buffer by serial_write. We need to
963 * lock it in case the memcpy_fromfs blocks while swapping in a page,
964 * and some other program tries to do a serial write at the same time.
965 * Since the lock will only come under contention when the system is
966 * swapping and available memory is low, it makes sense to share one
967 * buffer across all the serial ports, since it significantly saves
968 * memory if large numbers of serial ports are open.
969 */
970static unsigned char *tmp_buf;
f392ecfa 971static DEFINE_MUTEX(tmp_buf_mutex);
1da177e4
LT		 972
973/* Calculate the chartime depending on baudrate, numbor of bits etc. */
974static void update_char_time(struct e100_serial * info)
975{
976 tcflag_t cflags = info->tty->termios->c_cflag;
977 int bits;
978
979 /* calc. number of bits / data byte */
980 /* databits + startbit and 1 stopbit */
981 if ((cflags & CSIZE) == CS7)
982 bits = 9;
983 else
984 bits = 10;
985
986 if (cflags & CSTOPB) /* 2 stopbits ? */
987 bits++;
988
989 if (cflags & PARENB) /* parity bit ? */
990 bits++;
991
992 /* calc timeout */
993 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
994 info->flush_time_usec = 4*info->char_time_usec;
995 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
996 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
997
998}
999
1000/*
1001 * This function maps from the Bxxxx defines in asm/termbits.h into real
1002 * baud rates.
1003 */
1004
1005static int
1006cflag_to_baud(unsigned int cflag)
1007{
1008 static int baud_table[] = {
1009 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
1010 4800, 9600, 19200, 38400 };
1011
1012 static int ext_baud_table[] = {
1013 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
1014 0, 0, 0, 0, 0, 0, 0, 0 };
1015
1016 if (cflag & CBAUDEX)
1017 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1018 else
1019 return baud_table[cflag & CBAUD];
1020}
1021
1022/* and this maps to an etrax100 hardware baud constant */
1023
1024static unsigned char
1025cflag_to_etrax_baud(unsigned int cflag)
1026{
1027 char retval;
1028
1029 static char baud_table[] = {
1030 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
1031
1032 static char ext_baud_table[] = {
1033 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
1034
1035 if (cflag & CBAUDEX)
1036 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1037 else
1038 retval = baud_table[cflag & CBAUD];
1039
1040 if (retval < 0) {
1041 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
1042 retval = 5; /* choose default 9600 instead */
1043 }
1044
1045 return retval | (retval << 4); /* choose same for both TX and RX */
1046}
1047
1048
1049/* Various static support functions */
1050
1051/* Functions to set or clear DTR/RTS on the requested line */
1052/* It is complicated by the fact that RTS is a serial port register, while
1053 * DTR might not be implemented in the HW at all, and if it is, it can be on
1054 * any general port.
1055 */
1056
1057
1058static inline void
1059e100_dtr(struct e100_serial *info, int set)
1060{
1061#ifndef CONFIG_SVINTO_SIM
1062 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1063
1064#ifdef SERIAL_DEBUG_IO
1065 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1066 printk("ser%i shadow before 0x%02X get: %i\n",
1067 info->line, *e100_modem_pins[info->line].dtr_shadow,
1068 E100_DTR_GET(info));
1069#endif
1070 /* DTR is active low */
1071 {
1072 unsigned long flags;
1073
77accbf5 1074 local_irq_save(flags);
1da177e4
LT		 1075 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1076 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1077 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
77accbf5 1078 local_irq_restore(flags);
1da177e4
LT		 1079 }
1080
1081#ifdef SERIAL_DEBUG_IO
1082 printk("ser%i shadow after 0x%02X get: %i\n",
1083 info->line, *e100_modem_pins[info->line].dtr_shadow,
1084 E100_DTR_GET(info));
1085#endif
1086#endif
1087}
1088
1089/* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1090 * 0=0V , 1=3.3V
1091 */
1092static inline void
1093e100_rts(struct e100_serial *info, int set)
1094{
1095#ifndef CONFIG_SVINTO_SIM
1096 unsigned long flags;
77accbf5 1097 local_irq_save(flags);
1da177e4
LT		 1098 info->rx_ctrl &= ~E100_RTS_MASK;
1099 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
1100 info->port[REG_REC_CTRL] = info->rx_ctrl;
77accbf5 1101 local_irq_restore(flags);
1da177e4
LT		 1102#ifdef SERIAL_DEBUG_IO
1103 printk("ser%i rts %i\n", info->line, set);
1104#endif
1105#endif
1106}
1107
1108
1109/* If this behaves as a modem, RI and CD is an output */
1110static inline void
1111e100_ri_out(struct e100_serial *info, int set)
1112{
1113#ifndef CONFIG_SVINTO_SIM
1114 /* RI is active low */
1115 {
1116 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1117 unsigned long flags;
1118
77accbf5 1119 local_irq_save(flags);
1da177e4
LT		 1120 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1121 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1122 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
77accbf5 1123 local_irq_restore(flags);
1da177e4
LT		 1124 }
1125#endif
1126}
1127static inline void
1128e100_cd_out(struct e100_serial *info, int set)
1129{
1130#ifndef CONFIG_SVINTO_SIM
1131 /* CD is active low */
1132 {
1133 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1134 unsigned long flags;
1135
77accbf5 1136 local_irq_save(flags);
1da177e4
LT		 1137 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1138 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1139 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
77accbf5 1140 local_irq_restore(flags);
1da177e4
LT		 1141 }
1142#endif
1143}
1144
1145static inline void
1146e100_disable_rx(struct e100_serial *info)
1147{
1148#ifndef CONFIG_SVINTO_SIM
1149 /* disable the receiver */
1150 info->port[REG_REC_CTRL] =
1151 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1152#endif
1153}
1154
1155static inline void
1156e100_enable_rx(struct e100_serial *info)
1157{
1158#ifndef CONFIG_SVINTO_SIM
1159 /* enable the receiver */
1160 info->port[REG_REC_CTRL] =
1161 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1162#endif
1163}
1164
1165/* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1166
1167static inline void
1168e100_disable_rxdma_irq(struct e100_serial *info)
1169{
1170#ifdef SERIAL_DEBUG_INTR
1171 printk("rxdma_irq(%d): 0\n",info->line);
1172#endif
1173 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1174 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1175}
1176
1177static inline void
1178e100_enable_rxdma_irq(struct e100_serial *info)
1179{
1180#ifdef SERIAL_DEBUG_INTR
1181 printk("rxdma_irq(%d): 1\n",info->line);
1182#endif
1183 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1184 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1185}
1186
1187/* the tx DMA uses only dma_descr interrupt */
1188
41c28ff1 1189static void e100_disable_txdma_irq(struct e100_serial *info)
1da177e4
LT		 1190{
1191#ifdef SERIAL_DEBUG_INTR
1192 printk("txdma_irq(%d): 0\n",info->line);
1193#endif
1194 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1195 *R_IRQ_MASK2_CLR = info->irq;
1196}
1197
41c28ff1 1198static void e100_enable_txdma_irq(struct e100_serial *info)
1da177e4
LT		 1199{
1200#ifdef SERIAL_DEBUG_INTR
1201 printk("txdma_irq(%d): 1\n",info->line);
1202#endif
1203 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1204 *R_IRQ_MASK2_SET = info->irq;
1205}
1206
41c28ff1 1207static void e100_disable_txdma_channel(struct e100_serial *info)
1da177e4
LT		 1208{
1209 unsigned long flags;
1210
1211 /* Disable output DMA channel for the serial port in question
1212 * ( set to something other then serialX)
1213 */
77accbf5 1214 local_irq_save(flags);
1da177e4
LT		 1215 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1216 if (info->line == 0) {
1217 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1218 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1219 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1220 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1221 }
1222 } else if (info->line == 1) {
1223 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1224 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1225 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1226 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1227 }
1228 } else if (info->line == 2) {
1229 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1230 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1231 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1232 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1233 }
1234 } else if (info->line == 3) {
1235 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1236 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1237 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1238 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1239 }
1240 }
1241 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1242 local_irq_restore(flags);
1da177e4
LT		 1243}
1244
1245
41c28ff1 1246static void e100_enable_txdma_channel(struct e100_serial *info)
1da177e4
LT		 1247{
1248 unsigned long flags;
1249
77accbf5 1250 local_irq_save(flags);
1da177e4
LT		 1251 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1252 /* Enable output DMA channel for the serial port in question */
1253 if (info->line == 0) {
1254 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1255 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1256 } else if (info->line == 1) {
1257 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1258 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1259 } else if (info->line == 2) {
1260 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1261 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1262 } else if (info->line == 3) {
1263 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1264 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1265 }
1266 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1267 local_irq_restore(flags);
1da177e4
LT		 1268}
1269
41c28ff1 1270static void e100_disable_rxdma_channel(struct e100_serial *info)
1da177e4
LT		 1271{
1272 unsigned long flags;
1273
1274 /* Disable input DMA channel for the serial port in question
1275 * ( set to something other then serialX)
1276 */
77accbf5 1277 local_irq_save(flags);
1da177e4
LT		 1278 if (info->line == 0) {
1279 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1280 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1281 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1282 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1283 }
1284 } else if (info->line == 1) {
1285 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1286 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1287 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1288 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1289 }
1290 } else if (info->line == 2) {
1291 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1292 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1293 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1294 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1295 }
1296 } else if (info->line == 3) {
1297 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1298 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1299 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1300 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1301 }
1302 }
1303 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1304 local_irq_restore(flags);
1da177e4
LT		 1305}
1306
1307
41c28ff1 1308static void e100_enable_rxdma_channel(struct e100_serial *info)
1da177e4
LT		 1309{
1310 unsigned long flags;
1311
77accbf5 1312 local_irq_save(flags);
1da177e4
LT		 1313 /* Enable input DMA channel for the serial port in question */
1314 if (info->line == 0) {
1315 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1316 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1317 } else if (info->line == 1) {
1318 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1319 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1320 } else if (info->line == 2) {
1321 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1322 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1323 } else if (info->line == 3) {
1324 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1325 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1326 }
1327 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1328 local_irq_restore(flags);
1da177e4
LT		 1329}
1330
1331#ifdef SERIAL_HANDLE_EARLY_ERRORS
1332/* in order to detect and fix errors on the first byte
1333 we have to use the serial interrupts as well. */
1334
1335static inline void
1336e100_disable_serial_data_irq(struct e100_serial *info)
1337{
1338#ifdef SERIAL_DEBUG_INTR
1339 printk("ser_irq(%d): 0\n",info->line);
1340#endif
1341 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1342 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1343}
1344
1345static inline void
1346e100_enable_serial_data_irq(struct e100_serial *info)
1347{
1348#ifdef SERIAL_DEBUG_INTR
1349 printk("ser_irq(%d): 1\n",info->line);
1350 printk("**** %d = %d\n",
1351 (8+2*info->line),
1352 (1U << (8+2*info->line)));
1353#endif
1354 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1355 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1356}
1357#endif
1358
1359static inline void
1360e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1361{
1362#ifdef SERIAL_DEBUG_INTR
1363 printk("ser_tx_irq(%d): 0\n",info->line);
1364#endif
1365 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1366 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1367}
1368
1369static inline void
1370e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1371{
1372#ifdef SERIAL_DEBUG_INTR
1373 printk("ser_tx_irq(%d): 1\n",info->line);
1374 printk("**** %d = %d\n",
1375 (8+1+2*info->line),
1376 (1U << (8+1+2*info->line)));
1377#endif
1378 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1379 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1380}
1381
1382static inline void e100_enable_rx_irq(struct e100_serial *info)
1383{
1384 if (info->uses_dma_in)
1385 e100_enable_rxdma_irq(info);
1386 else
1387 e100_enable_serial_data_irq(info);
1388}
1389static inline void e100_disable_rx_irq(struct e100_serial *info)
1390{
1391 if (info->uses_dma_in)
1392 e100_disable_rxdma_irq(info);
1393 else
1394 e100_disable_serial_data_irq(info);
1395}
1396
1397#if defined(CONFIG_ETRAX_RS485)
1398/* Enable RS-485 mode on selected port. This is UGLY. */
1399static int
1400e100_enable_rs485(struct tty_struct *tty,struct rs485_control *r)
1401{
1402 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1403
1404#if defined(CONFIG_ETRAX_RS485_ON_PA)
1405 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1406#endif
1407#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
1408 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1409 rs485_port_g_bit, 1);
1410#endif
1411#if defined(CONFIG_ETRAX_RS485_LTC1387)
1412 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1413 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 1);
1414 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1415 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1);
1416#endif
1417
1418 info->rs485.rts_on_send = 0x01 & r->rts_on_send;
1419 info->rs485.rts_after_sent = 0x01 & r->rts_after_sent;
1420 if (r->delay_rts_before_send >= 1000)
1421 info->rs485.delay_rts_before_send = 1000;
1422 else
1423 info->rs485.delay_rts_before_send = r->delay_rts_before_send;
1424 info->rs485.enabled = r->enabled;
1425/* printk("rts: on send = %i, after = %i, enabled = %i",
1426 info->rs485.rts_on_send,
1427 info->rs485.rts_after_sent,
1428 info->rs485.enabled
1429 );
1430*/
1431 return 0;
1432}
1433
1434static int
77accbf5 1435e100_write_rs485(struct tty_struct *tty,
1da177e4
LT		 1436 const unsigned char *buf, int count)
1437{
1438 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1439 int old_enabled = info->rs485.enabled;
1440
1441 /* rs485 is always implicitly enabled if we're using the ioctl()
1442 * but it doesn't have to be set in the rs485_control
1443 * (to be backward compatible with old apps)
1444 * So we store, set and restore it.
1445 */
1446 info->rs485.enabled = 1;
1447 /* rs_write now deals with RS485 if enabled */
77accbf5 1448 count = rs_write(tty, buf, count);
1da177e4
LT		 1449 info->rs485.enabled = old_enabled;
1450 return count;
1451}
1452
1453#ifdef CONFIG_ETRAX_FAST_TIMER
1454/* Timer function to toggle RTS when using FAST_TIMER */
1455static void rs485_toggle_rts_timer_function(unsigned long data)
1456{
1457 struct e100_serial *info = (struct e100_serial *)data;
1458
1459 fast_timers_rs485[info->line].function = NULL;
1460 e100_rts(info, info->rs485.rts_after_sent);
1461#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1462 e100_enable_rx(info);
1463 e100_enable_rx_irq(info);
1464#endif
1465}
1466#endif
1467#endif /* CONFIG_ETRAX_RS485 */
1468
1469/*
1470 * ------------------------------------------------------------
1471 * rs_stop() and rs_start()
1472 *
1473 * This routines are called before setting or resetting tty->stopped.
1474 * They enable or disable transmitter using the XOFF registers, as necessary.
1475 * ------------------------------------------------------------
1476 */
1477
1478static void
1479rs_stop(struct tty_struct *tty)
1480{
1481 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1482 if (info) {
1483 unsigned long flags;
1484 unsigned long xoff;
1485
77accbf5 1486 local_irq_save(flags);
1da177e4
LT		 1487 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1488 CIRC_CNT(info->xmit.head,
1489 info->xmit.tail,SERIAL_XMIT_SIZE)));
1490
1491 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->tty));
1492 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
1493 if (tty->termios->c_iflag & IXON ) {
1494 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1495 }
1496
1497 *((unsigned long *)&info->port[REG_XOFF]) = xoff;
77accbf5 1498 local_irq_restore(flags);
1da177e4
LT		 1499 }
1500}
1501
1502static void
1503rs_start(struct tty_struct *tty)
1504{
1505 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1506 if (info) {
1507 unsigned long flags;
1508 unsigned long xoff;
1509
77accbf5 1510 local_irq_save(flags);
1da177e4
LT		 1511 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1512 CIRC_CNT(info->xmit.head,
1513 info->xmit.tail,SERIAL_XMIT_SIZE)));
1514 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1515 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
1516 if (tty->termios->c_iflag & IXON ) {
1517 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1518 }
1519
1520 *((unsigned long *)&info->port[REG_XOFF]) = xoff;
1521 if (!info->uses_dma_out &&
1522 info->xmit.head != info->xmit.tail && info->xmit.buf)
1523 e100_enable_serial_tx_ready_irq(info);
1524
77accbf5 1525 local_irq_restore(flags);
1da177e4
LT		 1526 }
1527}
1528
1529/*
1530 * ----------------------------------------------------------------------
1531 *
1532 * Here starts the interrupt handling routines. All of the following
1533 * subroutines are declared as inline and are folded into
1534 * rs_interrupt(). They were separated out for readability's sake.
1535 *
1536 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1537 * runs with interrupts turned off. People who may want to modify
1538 * rs_interrupt() should try to keep the interrupt handler as fast as
1539 * possible. After you are done making modifications, it is not a bad
1540 * idea to do:
1541 *
1542 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1543 *
1544 * and look at the resulting assemble code in serial.s.
1545 *
1546 * - Ted Ts'o ([email protected]), 7-Mar-93
1547 * -----------------------------------------------------------------------
1548 */
1549
1550/*
1551 * This routine is used by the interrupt handler to schedule
1552 * processing in the software interrupt portion of the driver.
1553 */
41c28ff1 1554static void rs_sched_event(struct e100_serial *info, int event)
1da177e4
LT		 1555{
1556 if (info->event & (1 << event))
1557 return;
1558 info->event |= 1 << event;
1559 schedule_work(&info->work);
1560}
1561
1562/* The output DMA channel is free - use it to send as many chars as possible
1563 * NOTES:
1564 * We don't pay attention to info->x_char, which means if the TTY wants to
1565 * use XON/XOFF it will set info->x_char but we won't send any X char!
1566 *
1567 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1568 * buffer containing the X char, and skip updating xmit. We'd also have to
1569 * check if the last sent char was the X char when we enter this function
1570 * the next time, to avoid updating xmit with the sent X value.
1571 */
1572
1573static void
1574transmit_chars_dma(struct e100_serial *info)
1575{
1576 unsigned int c, sentl;
1577 struct etrax_dma_descr *descr;
1578
1579#ifdef CONFIG_SVINTO_SIM
1580 /* This will output too little if tail is not 0 always since
1581 * we don't reloop to send the other part. Anyway this SHOULD be a
1582 * no-op - transmit_chars_dma would never really be called during sim
1583 * since rs_write does not write into the xmit buffer then.
1584 */
1585 if (info->xmit.tail)
1586 printk("Error in serial.c:transmit_chars-dma(), tail!=0\n");
1587 if (info->xmit.head != info->xmit.tail) {
1588 SIMCOUT(info->xmit.buf + info->xmit.tail,
1589 CIRC_CNT(info->xmit.head,
1590 info->xmit.tail,
1591 SERIAL_XMIT_SIZE));
1592 info->xmit.head = info->xmit.tail; /* move back head */
1593 info->tr_running = 0;
1594 }
1595 return;
1596#endif
1597 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1598 *info->oclrintradr =
1599 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1600 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1601
1602#ifdef SERIAL_DEBUG_INTR
1603 if (info->line == SERIAL_DEBUG_LINE)
1604 printk("tc\n");
1605#endif
1606 if (!info->tr_running) {
1607 /* weirdo... we shouldn't get here! */
1608 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1609 return;
1610 }
1611
1612 descr = &info->tr_descr;
1613
1614 /* first get the amount of bytes sent during the last DMA transfer,
1615 and update xmit accordingly */
1616
1617 /* if the stop bit was not set, all data has been sent */
1618 if (!(descr->status & d_stop)) {
1619 sentl = descr->sw_len;
1620 } else
1621 /* otherwise we find the amount of data sent here */
1622 sentl = descr->hw_len;
1623
1624 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1625
1626 /* update stats */
1627 info->icount.tx += sentl;
1628
1629 /* update xmit buffer */
1630 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1631
1632 /* if there is only a few chars left in the buf, wake up the blocked
1633 write if any */
1634 if (CIRC_CNT(info->xmit.head,
1635 info->xmit.tail,
1636 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1637 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1638
1639 /* find out the largest amount of consecutive bytes we want to send now */
1640
1641 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1642
1643 /* Don't send all in one DMA transfer - divide it so we wake up
1644 * application before all is sent
1645 */
1646
1647 if (c >= 4*WAKEUP_CHARS)
1648 c = c/2;
1649
1650 if (c <= 0) {
1651 /* our job here is done, don't schedule any new DMA transfer */
1652 info->tr_running = 0;
1653
1654#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
1655 if (info->rs485.enabled) {
1656 /* Set a short timer to toggle RTS */
1657 start_one_shot_timer(&fast_timers_rs485[info->line],
1658 rs485_toggle_rts_timer_function,
1659 (unsigned long)info,
1660 info->char_time_usec*2,
1661 "RS-485");
1662 }
1663#endif /* RS485 */
1664 return;
1665 }
1666
1667 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1668 /* set up the descriptor correctly for output */
1669 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1670 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1671 descr->sw_len = c;
1672 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1673 descr->status = 0;
1674
1675 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1676 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1677
1678 /* DMA is now running (hopefully) */
1679} /* transmit_chars_dma */
1680
1681static void
1682start_transmit(struct e100_serial *info)
1683{
1684#if 0
1685 if (info->line == SERIAL_DEBUG_LINE)
1686 printk("x\n");
1687#endif
1688
1689 info->tr_descr.sw_len = 0;
1690 info->tr_descr.hw_len = 0;
1691 info->tr_descr.status = 0;
1692 info->tr_running = 1;
1693 if (info->uses_dma_out)
1694 transmit_chars_dma(info);
1695 else
1696 e100_enable_serial_tx_ready_irq(info);
1697} /* start_transmit */
1698
1699#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1700static int serial_fast_timer_started = 0;
1701static int serial_fast_timer_expired = 0;
1702static void flush_timeout_function(unsigned long data);
1703#define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1704 unsigned long timer_flags; \
77accbf5 1705 local_irq_save(timer_flags); \
1da177e4
LT		 1706 if (fast_timers[info->line].function == NULL) { \
1707 serial_fast_timer_started++; \
1708 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1709 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1710 start_one_shot_timer(&fast_timers[info->line], \
1711 flush_timeout_function, \
1712 (unsigned long)info, \
1713 (usec), \
1714 string); \
1715 } \
1716 else { \
1717 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1718 } \
77accbf5 1719 local_irq_restore(timer_flags); \
1da177e4
LT		 1720}
1721#define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1722
1723#else
1724#define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1725#define START_FLUSH_FAST_TIMER(info, string)
1726#endif
1727
1728static struct etrax_recv_buffer *
1729alloc_recv_buffer(unsigned int size)
1730{
1731 struct etrax_recv_buffer *buffer;
1732
1733 if (!(buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC)))
1734 return NULL;
1735
1736 buffer->next = NULL;
1737 buffer->length = 0;
1738 buffer->error = TTY_NORMAL;
1739
1740 return buffer;
1741}
1742
1743static void
1744append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1745{
1746 unsigned long flags;
1747
77accbf5 1748 local_irq_save(flags);
1da177e4
LT		 1749
1750 if (!info->first_recv_buffer)
1751 info->first_recv_buffer = buffer;
1752 else
1753 info->last_recv_buffer->next = buffer;
1754
1755 info->last_recv_buffer = buffer;
1756
1757 info->recv_cnt += buffer->length;
1758 if (info->recv_cnt > info->max_recv_cnt)
1759 info->max_recv_cnt = info->recv_cnt;
1760
77accbf5 1761 local_irq_restore(flags);
1da177e4
LT		 1762}
1763
1764static int
1765add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1766{
1767 struct etrax_recv_buffer *buffer;
1768 if (info->uses_dma_in) {
1769 if (!(buffer = alloc_recv_buffer(4)))
1770 return 0;
1771
1772 buffer->length = 1;
1773 buffer->error = flag;
1774 buffer->buffer[0] = data;
1775
1776 append_recv_buffer(info, buffer);
1777
1778 info->icount.rx++;
1779 } else {
1780 struct tty_struct *tty = info->tty;
77accbf5 1781 tty_insert_flip_char(tty, data, flag);
1da177e4
LT		 1782 info->icount.rx++;
1783 }
1784
1785 return 1;
1786}
1787
41c28ff1
AB		 1788static unsigned int handle_descr_data(struct e100_serial *info,
1789 struct etrax_dma_descr *descr,
1790 unsigned int recvl)
1da177e4
LT		 1791{
1792 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1793
1794 if (info->recv_cnt + recvl > 65536) {
1795 printk(KERN_CRIT
1796 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __FUNCTION__, recvl);
1797 return 0;
1798 }
1799
1800 buffer->length = recvl;
1801
1802 if (info->errorcode == ERRCODE_SET_BREAK)
1803 buffer->error = TTY_BREAK;
1804 info->errorcode = 0;
1805
1806 append_recv_buffer(info, buffer);
1807
1808 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1809 panic("%s: Failed to allocate memory for receive buffer!\n", __FUNCTION__);
1810
1811 descr->buf = virt_to_phys(buffer->buffer);
1812
1813 return recvl;
1814}
1815
41c28ff1 1816static unsigned int handle_all_descr_data(struct e100_serial *info)
1da177e4
LT		 1817{
1818 struct etrax_dma_descr *descr;
1819 unsigned int recvl;
1820 unsigned int ret = 0;
1821
1822 while (1)
1823 {
1824 descr = &info->rec_descr[info->cur_rec_descr];
1825
1826 if (descr == phys_to_virt(*info->idescradr))
1827 break;
1828
1829 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1830 info->cur_rec_descr = 0;
1831
1832 /* find out how many bytes were read */
1833
1834 /* if the eop bit was not set, all data has been received */
1835 if (!(descr->status & d_eop)) {
1836 recvl = descr->sw_len;
1837 } else {
1838 /* otherwise we find the amount of data received here */
1839 recvl = descr->hw_len;
1840 }
1841
1842 /* Reset the status information */
1843 descr->status = 0;
1844
1845 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
1846 if (info->tty->stopped) {
1847 unsigned char *buf = phys_to_virt(descr->buf);
1848 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1849 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1850 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1851 }
1852 );
1853
1854 /* update stats */
1855 info->icount.rx += recvl;
1856
1857 ret += handle_descr_data(info, descr, recvl);
1858 }
1859
1860 return ret;
1861}
1862
41c28ff1 1863static void receive_chars_dma(struct e100_serial *info)
1da177e4
LT		 1864{
1865 struct tty_struct *tty;
1866 unsigned char rstat;
1867
1868#ifdef CONFIG_SVINTO_SIM
1869 /* No receive in the simulator. Will probably be when the rest of
1870 * the serial interface works, and this piece will just be removed.
1871 */
1872 return;
1873#endif
1874
1875 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1876 *info->iclrintradr =
1877 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1878 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1879
1880 tty = info->tty;
1881 if (!tty) /* Something wrong... */
1882 return;
1883
1884#ifdef SERIAL_HANDLE_EARLY_ERRORS
1885 if (info->uses_dma_in)
1886 e100_enable_serial_data_irq(info);
1887#endif
1888
1889 if (info->errorcode == ERRCODE_INSERT_BREAK)
1890 add_char_and_flag(info, '\0', TTY_BREAK);
1891
1892 handle_all_descr_data(info);
1893
1894 /* Read the status register to detect errors */
1895 rstat = info->port[REG_STATUS];
1896 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1897 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1898 }
1899
1900 if (rstat & SER_ERROR_MASK) {
1901 /* If we got an error, we must reset it by reading the
1902 * data_in field
1903 */
1904 unsigned char data = info->port[REG_DATA];
1905
1906 PROCSTAT(ser_stat[info->line].errors_cnt++);
1907 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1908 ((rstat & SER_ERROR_MASK) << 8) | data);
1909
1910 if (rstat & SER_PAR_ERR_MASK)
1911 add_char_and_flag(info, data, TTY_PARITY);
1912 else if (rstat & SER_OVERRUN_MASK)
1913 add_char_and_flag(info, data, TTY_OVERRUN);
1914 else if (rstat & SER_FRAMING_ERR_MASK)
1915 add_char_and_flag(info, data, TTY_FRAME);
1916 }
1917
1918 START_FLUSH_FAST_TIMER(info, "receive_chars");
1919
1920 /* Restart the receiving DMA */
1921 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1922}
1923
41c28ff1 1924static int start_recv_dma(struct e100_serial *info)
1da177e4
LT		 1925{
1926 struct etrax_dma_descr *descr = info->rec_descr;
1927 struct etrax_recv_buffer *buffer;
1928 int i;
1929
1930 /* Set up the receiving descriptors */
1931 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
1932 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1933 panic("%s: Failed to allocate memory for receive buffer!\n", __FUNCTION__);
1934
1935 descr[i].ctrl = d_int;
1936 descr[i].buf = virt_to_phys(buffer->buffer);
1937 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1938 descr[i].hw_len = 0;
1939 descr[i].status = 0;
1940 descr[i].next = virt_to_phys(&descr[i+1]);
1941 }
1942
1943 /* Link the last descriptor to the first */
1944 descr[i-1].next = virt_to_phys(&descr[0]);
1945
1946 /* Start with the first descriptor in the list */
1947 info->cur_rec_descr = 0;
1948
1949 /* Start the DMA */
1950 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1951 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1952
1953 /* Input DMA should be running now */
1954 return 1;
1955}
1956
1957static void
1958start_receive(struct e100_serial *info)
1959{
1960#ifdef CONFIG_SVINTO_SIM
1961 /* No receive in the simulator. Will probably be when the rest of
1962 * the serial interface works, and this piece will just be removed.
1963 */
1964 return;
1965#endif
1da177e4
LT		 1966 if (info->uses_dma_in) {
1967 /* reset the input dma channel to be sure it works */
1968
1969 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1970 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1971 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1972
1973 start_recv_dma(info);
1974 }
1975}
1976
1977
1da177e4
LT		 1978/* the bits in the MASK2 register are laid out like this:
1979 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1980 where I is the input channel and O is the output channel for the port.
1981 info->irq is the bit number for the DMAO_DESCR so to check the others we
1982 shift info->irq to the left.
1983*/
1984
1985/* dma output channel interrupt handler
1986 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1987 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1988*/
1989
1990static irqreturn_t
7d12e780 1991tr_interrupt(int irq, void *dev_id)
1da177e4
LT		 1992{
1993 struct e100_serial *info;
1994 unsigned long ireg;
1995 int i;
1996 int handled = 0;
1997
1998#ifdef CONFIG_SVINTO_SIM
1999 /* No receive in the simulator. Will probably be when the rest of
2000 * the serial interface works, and this piece will just be removed.
2001 */
2002 {
2003 const char *s = "What? tr_interrupt in simulator??\n";
2004 SIMCOUT(s,strlen(s));
2005 }
2006 return IRQ_HANDLED;
2007#endif
2008
2009 /* find out the line that caused this irq and get it from rs_table */
2010
2011 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2012
2013 for (i = 0; i < NR_PORTS; i++) {
2014 info = rs_table + i;
2015 if (!info->enabled || !info->uses_dma_out)
2016 continue;
2017 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
2018 if (ireg & info->irq) {
2019 handled = 1;
2020 /* we can send a new dma bunch. make it so. */
2021 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
2022 /* Read jiffies_usec first,
2023 * we want this time to be as late as possible
2024 */
2025 PROCSTAT(ser_stat[info->line].tx_dma_ints++);
2026 info->last_tx_active_usec = GET_JIFFIES_USEC();
2027 info->last_tx_active = jiffies;
2028 transmit_chars_dma(info);
2029 }
2030
2031 /* FIXME: here we should really check for a change in the
2032 status lines and if so call status_handle(info) */
2033 }
2034 return IRQ_RETVAL(handled);
2035} /* tr_interrupt */
2036
2037/* dma input channel interrupt handler */
2038
2039static irqreturn_t
7d12e780 2040rec_interrupt(int irq, void *dev_id)
1da177e4
LT		 2041{
2042 struct e100_serial *info;
2043 unsigned long ireg;
2044 int i;
2045 int handled = 0;
2046
2047#ifdef CONFIG_SVINTO_SIM
2048 /* No receive in the simulator. Will probably be when the rest of
2049 * the serial interface works, and this piece will just be removed.
2050 */
2051 {
2052 const char *s = "What? rec_interrupt in simulator??\n";
2053 SIMCOUT(s,strlen(s));
2054 }
2055 return IRQ_HANDLED;
2056#endif
2057
2058 /* find out the line that caused this irq and get it from rs_table */
2059
2060 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2061
2062 for (i = 0; i < NR_PORTS; i++) {
2063 info = rs_table + i;
2064 if (!info->enabled || !info->uses_dma_in)
2065 continue;
2066 /* check for both dma_eop and dma_descr for the input dma channel */
2067 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
2068 handled = 1;
2069 /* we have received something */
2070 receive_chars_dma(info);
2071 }
2072
2073 /* FIXME: here we should really check for a change in the
2074 status lines and if so call status_handle(info) */
2075 }
2076 return IRQ_RETVAL(handled);
2077} /* rec_interrupt */
2078
41c28ff1 2079static int force_eop_if_needed(struct e100_serial *info)
1da177e4
LT		 2080{
2081 /* We check data_avail bit to determine if data has
2082 * arrived since last time
2083 */
2084 unsigned char rstat = info->port[REG_STATUS];
2085
2086 /* error or datavail? */
2087 if (rstat & SER_ERROR_MASK) {
2088 /* Some error has occurred. If there has been valid data, an
2089 * EOP interrupt will be made automatically. If no data, the
2090 * normal ser_interrupt should be enabled and handle it.
2091 * So do nothing!
2092 */
2093 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
2094 rstat | (info->line << 8));
2095 return 0;
2096 }
2097
2098 if (rstat & SER_DATA_AVAIL_MASK) {
2099 /* Ok data, no error, count it */
2100 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
2101 rstat | (info->line << 8)));
2102 /* Read data to clear status flags */
2103 (void)info->port[REG_DATA];
2104
2105 info->forced_eop = 0;
2106 START_FLUSH_FAST_TIMER(info, "magic");
2107 return 0;
2108 }
2109
2110 /* hit the timeout, force an EOP for the input
2111 * dma channel if we haven't already
2112 */
2113 if (!info->forced_eop) {
2114 info->forced_eop = 1;
2115 PROCSTAT(ser_stat[info->line].timeout_flush_cnt++);
2116 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
2117 FORCE_EOP(info);
2118 }
2119
2120 return 1;
2121}
2122
41c28ff1 2123static void flush_to_flip_buffer(struct e100_serial *info)
1da177e4
LT		 2124{
2125 struct tty_struct *tty;
2126 struct etrax_recv_buffer *buffer;
1da177e4 2127 unsigned long flags;
1da177e4 2128
77accbf5
JN		 2129 local_irq_save(flags);
2130 tty = info->tty;
1da177e4 2131
77accbf5
JN		 2132 if (!tty) {
2133 local_irq_restore(flags);
1da177e4
LT		 2134 return;
2135 }
2136
2090ab05 2137 while ((buffer = info->first_recv_buffer) != NULL) {
1da177e4
LT		 2138 unsigned int count = buffer->length;
2139
77accbf5 2140 tty_insert_flip_string(tty, buffer->buffer, count);
1da177e4 2141 info->recv_cnt -= count;
1da177e4
LT		 2142
2143 if (count == buffer->length) {
2144 info->first_recv_buffer = buffer->next;
2145 kfree(buffer);
2146 } else {
2147 buffer->length -= count;
2148 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2149 buffer->error = TTY_NORMAL;
2150 }
2151 }
2152
2153 if (!info->first_recv_buffer)
2154 info->last_recv_buffer = NULL;
2155
77accbf5 2156 local_irq_restore(flags);
1da177e4 2157
77accbf5 2158 /* This includes a check for low-latency */
1da177e4
LT		 2159 tty_flip_buffer_push(tty);
2160}
2161
41c28ff1 2162static void check_flush_timeout(struct e100_serial *info)
1da177e4
LT		 2163{
2164 /* Flip what we've got (if we can) */
2165 flush_to_flip_buffer(info);
2166
2167 /* We might need to flip later, but not to fast
2168 * since the system is busy processing input... */
2169 if (info->first_recv_buffer)
2170 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2171
2172 /* Force eop last, since data might have come while we're processing
2173 * and if we started the slow timer above, we won't start a fast
2174 * below.
2175 */
2176 force_eop_if_needed(info);
2177}
2178
2179#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2180static void flush_timeout_function(unsigned long data)
2181{
2182 struct e100_serial *info = (struct e100_serial *)data;
2183
2184 fast_timers[info->line].function = NULL;
2185 serial_fast_timer_expired++;
2186 TIMERD(DEBUG_LOG(info->line, "flush_timout %i ", info->line));
2187 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2188 check_flush_timeout(info);
2189}
2190
2191#else
2192
2193/* dma fifo/buffer timeout handler
2194 forces an end-of-packet for the dma input channel if no chars
2195 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2196*/
2197
2198static struct timer_list flush_timer;
2199
2200static void
2201timed_flush_handler(unsigned long ptr)
2202{
2203 struct e100_serial *info;
2204 int i;
2205
2206#ifdef CONFIG_SVINTO_SIM
2207 return;
2208#endif
2209
2210 for (i = 0; i < NR_PORTS; i++) {
2211 info = rs_table + i;
2212 if (info->uses_dma_in)
2213 check_flush_timeout(info);
2214 }
2215
2216 /* restart flush timer */
2217 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2218}
2219#endif
2220
2221#ifdef SERIAL_HANDLE_EARLY_ERRORS
2222
2223/* If there is an error (ie break) when the DMA is running and
2224 * there are no bytes in the fifo the DMA is stopped and we get no
2225 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2226 * transfer, and if it is without error we can turn the serial
2227 * interrupts off.
2228 */
2229
2230/*
2231BREAK handling on ETRAX 100:
2232ETRAX will generate interrupt although there is no stop bit between the
2233characters.
2234
2235Depending on how long the break sequence is, the end of the breaksequence
2236will look differently:
2237| indicates start/end of a character.
2238
2239B= Break character (0x00) with framing error.
2240E= Error byte with parity error received after B characters.
2241F= "Faked" valid byte received immediately after B characters.
2242V= Valid byte
2243
22441.
2245 B BL ___________________________ V
2246.._|__________|__________| |valid data |
2247
2248Multiple frame errors with data == 0x00 (B),
2249the timing matches up "perfectly" so no extra ending char is detected.
2250The RXD pin is 1 in the last interrupt, in that case
2251we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2252know if another byte will come and this really is case 2. below
2253(e.g F=0xFF or 0xFE)
2254If RXD pin is 0 we can expect another character (see 2. below).
2255
2256
22572.
2258
2259 B B E or F__________________..__ V
2260.._|__________|__________|______ | |valid data
2261 "valid" or
2262 parity error
2263
2264Multiple frame errors with data == 0x00 (B),
2265but the part of the break trigs is interpreted as a start bit (and possibly
2266some 0 bits followed by a number of 1 bits and a stop bit).
2267Depending on parity settings etc. this last character can be either
2268a fake "valid" char (F) or have a parity error (E).
2269
2270If the character is valid it will be put in the buffer,
2271we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2272will set the flags so the tty will handle it,
2273if it's an error byte it will not be put in the buffer
2274and we set info->errorcode = ERRCODE_INSERT_BREAK.
2275
2276To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2277of the last faulty char (B) and compares it with the current time:
2278If the time elapsed time is less then 2*char_time_usec we will assume
2279it's a faked F char and not a Valid char and set
2280info->errorcode = ERRCODE_SET_BREAK.
2281
2282Flaws in the above solution:
2283~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2284We use the timer to distinguish a F character from a V character,
2285if a V character is to close after the break we might make the wrong decision.
2286
2287TODO: The break will be delayed until an F or V character is received.
2288
2289*/
2290
41c28ff1 2291static
1da177e4
LT		 2292struct e100_serial * handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
2293{
2294 unsigned long data_read;
2295 struct tty_struct *tty = info->tty;
2296
2297 if (!tty) {
2298 printk("!NO TTY!\n");
2299 return info;
2300 }
77accbf5 2301
1da177e4
LT		 2302 /* Read data and status at the same time */
2303 data_read = *((unsigned long *)&info->port[REG_DATA_STATUS32]);
2304more_data:
2305 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2306 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2307 }
2308 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2309
2310 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2311 IO_MASK(R_SERIAL0_READ, par_err) |
2312 IO_MASK(R_SERIAL0_READ, overrun) )) {
2313 /* An error */
2314 info->last_rx_active_usec = GET_JIFFIES_USEC();
2315 info->last_rx_active = jiffies;
2316 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2317 DLOG_INT_TRIG(
2318 if (!log_int_trig1_pos) {
2319 log_int_trig1_pos = log_int_pos;
2320 log_int(rdpc(), 0, 0);
2321 }
2322 );
2323
2324
2325 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2326 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2327 /* Most likely a break, but we get interrupts over and
2328 * over again.
2329 */
2330
2331 if (!info->break_detected_cnt) {
2332 DEBUG_LOG(info->line, "#BRK start\n", 0);
2333 }
2334 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2335 /* The RX pin is high now, so the break
2336 * must be over, but....
2337 * we can't really know if we will get another
2338 * last byte ending the break or not.
2339 * And we don't know if the byte (if any) will
2340 * have an error or look valid.
2341 */
2342 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2343 info->errorcode = ERRCODE_INSERT_BREAK;
2344 }
2345 info->break_detected_cnt++;
2346 } else {
2347 /* The error does not look like a break, but could be
2348 * the end of one
2349 */
2350 if (info->break_detected_cnt) {
2351 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2352 info->errorcode = ERRCODE_INSERT_BREAK;
2353 } else {
77accbf5
JN		 2354 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2355 data_in, data_read);
2356 char flag = TTY_NORMAL;
1da177e4 2357 if (info->errorcode == ERRCODE_INSERT_BREAK) {
77accbf5
JN		 2358 struct tty_struct *tty = info->tty;
2359 tty_insert_flip_char(tty, 0, flag);
1da177e4
LT		 2360 info->icount.rx++;
2361 }
1da177e4
LT		 2362
2363 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2364 info->icount.parity++;
77accbf5 2365 flag = TTY_PARITY;
1da177e4
LT		 2366 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2367 info->icount.overrun++;
77accbf5 2368 flag = TTY_OVERRUN;
1da177e4
LT		 2369 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2370 info->icount.frame++;
77accbf5 2371 flag = TTY_FRAME;
1da177e4 2372 }
77accbf5 2373 tty_insert_flip_char(tty, data, flag);
1da177e4
LT		 2374 info->errorcode = 0;
2375 }
2376 info->break_detected_cnt = 0;
2377 }
2378 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2379 /* No error */
2380 DLOG_INT_TRIG(
2381 if (!log_int_trig1_pos) {
2382 if (log_int_pos >= log_int_size) {
2383 log_int_pos = 0;
2384 }
2385 log_int_trig0_pos = log_int_pos;
2386 log_int(rdpc(), 0, 0);
2387 }
2388 );
77accbf5
JN		 2389 tty_insert_flip_char(tty,
2390 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2391 TTY_NORMAL);
1da177e4
LT		 2392 } else {
2393 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2394 }
2395
2396
1da177e4
LT		 2397 info->icount.rx++;
2398 data_read = *((unsigned long *)&info->port[REG_DATA_STATUS32]);
2399 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2400 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2401 goto more_data;
2402 }
2403
2404 tty_flip_buffer_push(info->tty);
2405 return info;
2406}
2407
41c28ff1 2408static struct e100_serial* handle_ser_rx_interrupt(struct e100_serial *info)
1da177e4
LT		 2409{
2410 unsigned char rstat;
2411
2412#ifdef SERIAL_DEBUG_INTR
2413 printk("Interrupt from serport %d\n", i);
2414#endif
2415/* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2416 if (!info->uses_dma_in) {
2417 return handle_ser_rx_interrupt_no_dma(info);
2418 }
2419 /* DMA is used */
2420 rstat = info->port[REG_STATUS];
2421 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2422 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2423 }
2424
2425 if (rstat & SER_ERROR_MASK) {
2426 unsigned char data;
2427
2428 info->last_rx_active_usec = GET_JIFFIES_USEC();
2429 info->last_rx_active = jiffies;
2430 /* If we got an error, we must reset it by reading the
2431 * data_in field
2432 */
2433 data = info->port[REG_DATA];
2434 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2435 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2436 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2437 /* Most likely a break, but we get interrupts over and
2438 * over again.
2439 */
2440
2441 if (!info->break_detected_cnt) {
2442 DEBUG_LOG(info->line, "#BRK start\n", 0);
2443 }
2444 if (rstat & SER_RXD_MASK) {
2445 /* The RX pin is high now, so the break
2446 * must be over, but....
2447 * we can't really know if we will get another
2448 * last byte ending the break or not.
2449 * And we don't know if the byte (if any) will
2450 * have an error or look valid.
2451 */
2452 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2453 info->errorcode = ERRCODE_INSERT_BREAK;
2454 }
2455 info->break_detected_cnt++;
2456 } else {
2457 /* The error does not look like a break, but could be
2458 * the end of one
2459 */
2460 if (info->break_detected_cnt) {
2461 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2462 info->errorcode = ERRCODE_INSERT_BREAK;
2463 } else {
2464 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2465 info->icount.brk++;
2466 add_char_and_flag(info, '\0', TTY_BREAK);
2467 }
2468
2469 if (rstat & SER_PAR_ERR_MASK) {
2470 info->icount.parity++;
2471 add_char_and_flag(info, data, TTY_PARITY);
2472 } else if (rstat & SER_OVERRUN_MASK) {
2473 info->icount.overrun++;
2474 add_char_and_flag(info, data, TTY_OVERRUN);
2475 } else if (rstat & SER_FRAMING_ERR_MASK) {
2476 info->icount.frame++;
2477 add_char_and_flag(info, data, TTY_FRAME);
2478 }
2479
2480 info->errorcode = 0;
2481 }
2482 info->break_detected_cnt = 0;
2483 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2484 ((rstat & SER_ERROR_MASK) << 8) | data);
2485 }
2486 PROCSTAT(ser_stat[info->line].early_errors_cnt++);
2487 } else { /* It was a valid byte, now let the DMA do the rest */
2488 unsigned long curr_time_u = GET_JIFFIES_USEC();
2489 unsigned long curr_time = jiffies;
2490
2491 if (info->break_detected_cnt) {
2492 /* Detect if this character is a new valid char or the
2493 * last char in a break sequence: If LSBits are 0 and
2494 * MSBits are high AND the time is close to the
2495 * previous interrupt we should discard it.
2496 */
2497 long elapsed_usec =
2498 (curr_time - info->last_rx_active) * (1000000/HZ) +
2499 curr_time_u - info->last_rx_active_usec;
2500 if (elapsed_usec < 2*info->char_time_usec) {
2501 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2502 /* Report as BREAK (error) and let
2503 * receive_chars_dma() handle it
2504 */
2505 info->errorcode = ERRCODE_SET_BREAK;
2506 } else {
2507 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2508 }
2509 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2510 }
2511
2512#ifdef SERIAL_DEBUG_INTR
2513 printk("** OK, disabling ser_interrupts\n");
2514#endif
2515 e100_disable_serial_data_irq(info);
2516 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2517 info->break_detected_cnt = 0;
2518
2519 PROCSTAT(ser_stat[info->line].ser_ints_ok_cnt++);
2520 }
2521 /* Restarting the DMA never hurts */
2522 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2523 START_FLUSH_FAST_TIMER(info, "ser_int");
2524 return info;
2525} /* handle_ser_rx_interrupt */
2526
41c28ff1 2527static void handle_ser_tx_interrupt(struct e100_serial *info)
1da177e4
LT		 2528{
2529 unsigned long flags;
2530
2531 if (info->x_char) {
2532 unsigned char rstat;
2533 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
77accbf5 2534 local_irq_save(flags);
1da177e4
LT		 2535 rstat = info->port[REG_STATUS];
2536 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2537
2538 info->port[REG_TR_DATA] = info->x_char;
2539 info->icount.tx++;
2540 info->x_char = 0;
2541 /* We must enable since it is disabled in ser_interrupt */
2542 e100_enable_serial_tx_ready_irq(info);
77accbf5 2543 local_irq_restore(flags);
1da177e4
LT		 2544 return;
2545 }
2546 if (info->uses_dma_out) {
2547 unsigned char rstat;
2548 int i;
2549 /* We only use normal tx interrupt when sending x_char */
2550 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
77accbf5 2551 local_irq_save(flags);
1da177e4
LT		 2552 rstat = info->port[REG_STATUS];
2553 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2554 e100_disable_serial_tx_ready_irq(info);
2555 if (info->tty->stopped)
2556 rs_stop(info->tty);
2557 /* Enable the DMA channel and tell it to continue */
2558 e100_enable_txdma_channel(info);
2559 /* Wait 12 cycles before doing the DMA command */
2560 for(i = 6; i > 0; i--)
2561 nop();
2562
2563 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
77accbf5 2564 local_irq_restore(flags);
1da177e4
LT		 2565 return;
2566 }
2567 /* Normal char-by-char interrupt */
2568 if (info->xmit.head == info->xmit.tail
2569 || info->tty->stopped
2570 || info->tty->hw_stopped) {
2571 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n", info->tty->stopped));
2572 e100_disable_serial_tx_ready_irq(info);
2573 info->tr_running = 0;
2574 return;
2575 }
2576 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2577 /* Send a byte, rs485 timing is critical so turn of ints */
77accbf5 2578 local_irq_save(flags);
1da177e4
LT		 2579 info->port[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
2580 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2581 info->icount.tx++;
2582 if (info->xmit.head == info->xmit.tail) {
2583#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
2584 if (info->rs485.enabled) {
2585 /* Set a short timer to toggle RTS */
2586 start_one_shot_timer(&fast_timers_rs485[info->line],
2587 rs485_toggle_rts_timer_function,
2588 (unsigned long)info,
2589 info->char_time_usec*2,
2590 "RS-485");
2591 }
2592#endif /* RS485 */
2593 info->last_tx_active_usec = GET_JIFFIES_USEC();
2594 info->last_tx_active = jiffies;
2595 e100_disable_serial_tx_ready_irq(info);
2596 info->tr_running = 0;
2597 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2598 } else {
2599 /* We must enable since it is disabled in ser_interrupt */
2600 e100_enable_serial_tx_ready_irq(info);
2601 }
77accbf5 2602 local_irq_restore(flags);
1da177e4
LT		 2603
2604 if (CIRC_CNT(info->xmit.head,
2605 info->xmit.tail,
2606 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2607 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2608
2609} /* handle_ser_tx_interrupt */
2610
2611/* result of time measurements:
2612 * RX duration 54-60 us when doing something, otherwise 6-9 us
2613 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2614 */
2615static irqreturn_t
7d12e780 2616ser_interrupt(int irq, void *dev_id)
1da177e4
LT		 2617{
2618 static volatile int tx_started = 0;
2619 struct e100_serial *info;
2620 int i;
2621 unsigned long flags;
2622 unsigned long irq_mask1_rd;
2623 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2624 int handled = 0;
2625 static volatile unsigned long reentered_ready_mask = 0;
2626
77accbf5 2627 local_irq_save(flags);
1da177e4
LT		 2628 irq_mask1_rd = *R_IRQ_MASK1_RD;
2629 /* First handle all rx interrupts with ints disabled */
2630 info = rs_table;
2631 irq_mask1_rd &= e100_ser_int_mask;
2632 for (i = 0; i < NR_PORTS; i++) {
2633 /* Which line caused the data irq? */
2634 if (irq_mask1_rd & data_mask) {
2635 handled = 1;
2636 handle_ser_rx_interrupt(info);
2637 }
2638 info += 1;
2639 data_mask <<= 2;
2640 }
2641 /* Handle tx interrupts with interrupts enabled so we
2642 * can take care of new data interrupts while transmitting
2643 * We protect the tx part with the tx_started flag.
2644 * We disable the tr_ready interrupts we are about to handle and
2645 * unblock the serial interrupt so new serial interrupts may come.
2646 *
2647 * If we get a new interrupt:
2648 * - it migth be due to synchronous serial ports.
2649 * - serial irq will be blocked by general irq handler.
2650 * - async data will be handled above (sync will be ignored).
2651 * - tx_started flag will prevent us from trying to send again and
2652 * we will exit fast - no need to unblock serial irq.
2653 * - Next (sync) serial interrupt handler will be runned with
2654 * disabled interrupt due to restore_flags() at end of function,
2655 * so sync handler will not be preempted or reentered.
2656 */
2657 if (!tx_started) {
2658 unsigned long ready_mask;
2659 unsigned long
2660 tx_started = 1;
2661 /* Only the tr_ready interrupts left */
2662 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2663 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2664 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2665 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2666 while (irq_mask1_rd) {
2667 /* Disable those we are about to handle */
2668 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2669 /* Unblock the serial interrupt */
2670 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2671
77accbf5 2672 local_irq_enable();
1da177e4
LT		 2673 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2674 info = rs_table;
2675 for (i = 0; i < NR_PORTS; i++) {
2676 /* Which line caused the ready irq? */
2677 if (irq_mask1_rd & ready_mask) {
2678 handled = 1;
2679 handle_ser_tx_interrupt(info);
2680 }
2681 info += 1;
2682 ready_mask <<= 2;
2683 }
2684 /* handle_ser_tx_interrupt enables tr_ready interrupts */
77accbf5 2685 local_irq_disable();
1da177e4
LT		 2686 /* Handle reentered TX interrupt */
2687 irq_mask1_rd = reentered_ready_mask;
2688 }
77accbf5 2689 local_irq_disable();
1da177e4
LT		 2690 tx_started = 0;
2691 } else {
2692 unsigned long ready_mask;
2693 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2694 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2695 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2696 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2697 if (ready_mask) {
2698 reentered_ready_mask |= ready_mask;
2699 /* Disable those we are about to handle */
2700 *R_IRQ_MASK1_CLR = ready_mask;
2701 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2702 }
2703 }
2704
77accbf5 2705 local_irq_restore(flags);
1da177e4
LT		 2706 return IRQ_RETVAL(handled);
2707} /* ser_interrupt */
2708#endif
2709
2710/*
2711 * -------------------------------------------------------------------
2712 * Here ends the serial interrupt routines.
2713 * -------------------------------------------------------------------
2714 */
2715
2716/*
2717 * This routine is used to handle the "bottom half" processing for the
2718 * serial driver, known also the "software interrupt" processing.
2719 * This processing is done at the kernel interrupt level, after the
2720 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2721 * is where time-consuming activities which can not be done in the
2722 * interrupt driver proper are done; the interrupt driver schedules
2723 * them using rs_sched_event(), and they get done here.
2724 */
2725static void
77accbf5 2726do_softint(struct work_struct *work)
1da177e4 2727{
77accbf5 2728 struct e100_serial *info;
1da177e4
LT		 2729 struct tty_struct *tty;
2730
77accbf5
JN		 2731 info = container_of(work, struct e100_serial, work);
2732
1da177e4
LT		 2733 tty = info->tty;
2734 if (!tty)
2735 return;
2736
b963a844
JS		 2737 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2738 tty_wakeup(tty);
1da177e4
LT		 2739}
2740
2741static int
2742startup(struct e100_serial * info)
2743{
2744 unsigned long flags;
2745 unsigned long xmit_page;
2746 int i;
2747
2748 xmit_page = get_zeroed_page(GFP_KERNEL);
2749 if (!xmit_page)
2750 return -ENOMEM;
2751
77accbf5 2752 local_irq_save(flags);
1da177e4
LT		 2753
2754 /* if it was already initialized, skip this */
2755
2756 if (info->flags & ASYNC_INITIALIZED) {
77accbf5 2757 local_irq_restore(flags);
1da177e4
LT		 2758 free_page(xmit_page);
2759 return 0;
2760 }
2761
2762 if (info->xmit.buf)
2763 free_page(xmit_page);
2764 else
2765 info->xmit.buf = (unsigned char *) xmit_page;
2766
2767#ifdef SERIAL_DEBUG_OPEN
2768 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2769#endif
2770
2771#ifdef CONFIG_SVINTO_SIM
2772 /* Bits and pieces collected from below. Better to have them
2773 in one ifdef:ed clause than to mix in a lot of ifdefs,
2774 right? */
2775 if (info->tty)
2776 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2777
2778 info->xmit.head = info->xmit.tail = 0;
2779 info->first_recv_buffer = info->last_recv_buffer = NULL;
2780 info->recv_cnt = info->max_recv_cnt = 0;
2781
2782 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2783 info->rec_descr[i].buf = NULL;
2784
2785 /* No real action in the simulator, but may set info important
2786 to ioctl. */
2787 change_speed(info);
2788#else
2789
2790 /*
2791 * Clear the FIFO buffers and disable them
2792 * (they will be reenabled in change_speed())
2793 */
2794
2795 /*
2796 * Reset the DMA channels and make sure their interrupts are cleared
2797 */
2798
2799 if (info->dma_in_enabled) {
2800 info->uses_dma_in = 1;
2801 e100_enable_rxdma_channel(info);
2802
2803 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2804
2805 /* Wait until reset cycle is complete */
2806 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2807 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2808
2809 /* Make sure the irqs are cleared */
2810 *info->iclrintradr =
2811 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2812 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2813 } else {
2814 e100_disable_rxdma_channel(info);
2815 }
2816
2817 if (info->dma_out_enabled) {
2818 info->uses_dma_out = 1;
2819 e100_enable_txdma_channel(info);
2820 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2821
2822 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2823 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2824
2825 /* Make sure the irqs are cleared */
2826 *info->oclrintradr =
2827 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2828 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2829 } else {
2830 e100_disable_txdma_channel(info);
2831 }
2832
2833 if (info->tty)
2834 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2835
2836 info->xmit.head = info->xmit.tail = 0;
2837 info->first_recv_buffer = info->last_recv_buffer = NULL;
2838 info->recv_cnt = info->max_recv_cnt = 0;
2839
2840 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2841 info->rec_descr[i].buf = 0;
2842
2843 /*
2844 * and set the speed and other flags of the serial port
2845 * this will start the rx/tx as well
2846 */
2847#ifdef SERIAL_HANDLE_EARLY_ERRORS
2848 e100_enable_serial_data_irq(info);
2849#endif
2850 change_speed(info);
2851
2852 /* dummy read to reset any serial errors */
2853
2854 (void)info->port[REG_DATA];
2855
2856 /* enable the interrupts */
2857 if (info->uses_dma_out)
2858 e100_enable_txdma_irq(info);
2859
2860 e100_enable_rx_irq(info);
2861
2862 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2863
2864 /* setup the dma input descriptor and start dma */
2865
2866 start_receive(info);
2867
2868 /* for safety, make sure the descriptors last result is 0 bytes written */
2869
2870 info->tr_descr.sw_len = 0;
2871 info->tr_descr.hw_len = 0;
2872 info->tr_descr.status = 0;
2873
2874 /* enable RTS/DTR last */
2875
2876 e100_rts(info, 1);
2877 e100_dtr(info, 1);
2878
2879#endif /* CONFIG_SVINTO_SIM */
2880
2881 info->flags |= ASYNC_INITIALIZED;
2882
77accbf5 2883 local_irq_restore(flags);
1da177e4
LT		 2884 return 0;
2885}
2886
2887/*
2888 * This routine will shutdown a serial port; interrupts are disabled, and
2889 * DTR is dropped if the hangup on close termio flag is on.
2890 */
2891static void
2892shutdown(struct e100_serial * info)
2893{
2894 unsigned long flags;
2895 struct etrax_dma_descr *descr = info->rec_descr;
2896 struct etrax_recv_buffer *buffer;
2897 int i;
2898
2899#ifndef CONFIG_SVINTO_SIM
2900 /* shut down the transmitter and receiver */
2901 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2902 e100_disable_rx(info);
2903 info->port[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
2904
2905 /* disable interrupts, reset dma channels */
2906 if (info->uses_dma_in) {
2907 e100_disable_rxdma_irq(info);
2908 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2909 info->uses_dma_in = 0;
2910 } else {
2911 e100_disable_serial_data_irq(info);
2912 }
2913
2914 if (info->uses_dma_out) {
2915 e100_disable_txdma_irq(info);
2916 info->tr_running = 0;
2917 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2918 info->uses_dma_out = 0;
2919 } else {
2920 e100_disable_serial_tx_ready_irq(info);
2921 info->tr_running = 0;
2922 }
2923
2924#endif /* CONFIG_SVINTO_SIM */
2925
2926 if (!(info->flags & ASYNC_INITIALIZED))
2927 return;
2928
2929#ifdef SERIAL_DEBUG_OPEN
2930 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2931 info->irq);
2932#endif
2933
77accbf5 2934 local_irq_save(flags);
1da177e4
LT		 2935
2936 if (info->xmit.buf) {
2937 free_page((unsigned long)info->xmit.buf);
2938 info->xmit.buf = NULL;
2939 }
2940
2941 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2942 if (descr[i].buf) {
2943 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2944 kfree(buffer);
2945 descr[i].buf = 0;
2946 }
2947
2948 if (!info->tty || (info->tty->termios->c_cflag & HUPCL)) {
2949 /* hang up DTR and RTS if HUPCL is enabled */
2950 e100_dtr(info, 0);
2951 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2952 }
2953
2954 if (info->tty)
2955 set_bit(TTY_IO_ERROR, &info->tty->flags);
2956
2957 info->flags &= ~ASYNC_INITIALIZED;
77accbf5 2958 local_irq_restore(flags);
1da177e4
LT		 2959}
2960
2961
2962/* change baud rate and other assorted parameters */
2963
2964static void
2965change_speed(struct e100_serial *info)
2966{
2967 unsigned int cflag;
2968 unsigned long xoff;
2969 unsigned long flags;
2970 /* first some safety checks */
2971
2972 if (!info->tty || !info->tty->termios)
2973 return;
2974 if (!info->port)
2975 return;
2976
2977 cflag = info->tty->termios->c_cflag;
2978
2979 /* possibly, the tx/rx should be disabled first to do this safely */
2980
2981 /* change baud-rate and write it to the hardware */
2982 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
2983 /* Special baudrate */
2984 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2985 unsigned long alt_source =
2986 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2987 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2988 /* R_ALT_SER_BAUDRATE selects the source */
2989 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2990 (unsigned long)info->baud_base, info->custom_divisor));
2991 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2992 /* 0, 2-65535 (0=65536) */
2993 u16 divisor = info->custom_divisor;
2994 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2995 /* baudrate is 3.125MHz/custom_divisor */
2996 alt_source =
2997 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2998 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2999 alt_source = 0x11;
3000 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
3001 *R_SERIAL_PRESCALE = divisor;
3002 info->baud = SERIAL_PRESCALE_BASE/divisor;
3003 }
3004#ifdef CONFIG_ETRAX_EXTERN_PB6CLK_ENABLED
3005 else if ((info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8 &&
3006 info->custom_divisor == 1) ||
3007 (info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ &&
3008 info->custom_divisor == 8)) {
3009 /* ext_clk selected */
3010 alt_source =
3011 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, extern) |
3012 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, extern);
3013 DBAUD(printk("using external baudrate: %lu\n", CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8));
3014 info->baud = CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8;
3015 }
1da177e4
LT		 3016#endif
3017 else
3018 {
3019 /* Bad baudbase, we don't support using timer0
3020 * for baudrate.
3021 */
3022 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
3023 (unsigned long)info->baud_base, info->custom_divisor);
3024 }
3025 r_alt_ser_baudrate_shadow &= ~mask;
3026 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3027 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3028 } else {
3029 /* Normal baudrate */
3030 /* Make sure we use normal baudrate */
3031 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
3032 unsigned long alt_source =
3033 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
3034 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
3035 r_alt_ser_baudrate_shadow &= ~mask;
3036 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3037#ifndef CONFIG_SVINTO_SIM
3038 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3039#endif /* CONFIG_SVINTO_SIM */
3040
3041 info->baud = cflag_to_baud(cflag);
3042#ifndef CONFIG_SVINTO_SIM
3043 info->port[REG_BAUD] = cflag_to_etrax_baud(cflag);
3044#endif /* CONFIG_SVINTO_SIM */
3045 }
3046
3047#ifndef CONFIG_SVINTO_SIM
3048 /* start with default settings and then fill in changes */
77accbf5 3049 local_irq_save(flags);
1da177e4
LT		 3050 /* 8 bit, no/even parity */
3051 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
3052 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
3053 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
3054
3055 /* 8 bit, no/even parity, 1 stop bit, no cts */
3056 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
3057 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
3058 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
3059 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
3060 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
3061
3062 if ((cflag & CSIZE) == CS7) {
3063 /* set 7 bit mode */
3064 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
3065 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
3066 }
3067
3068 if (cflag & CSTOPB) {
3069 /* set 2 stop bit mode */
3070 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
3071 }
3072
3073 if (cflag & PARENB) {
3074 /* enable parity */
3075 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
3076 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
3077 }
3078
3079 if (cflag & CMSPAR) {
3080 /* enable stick parity, PARODD mean Mark which matches ETRAX */
3081 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
3082 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
3083 }
3084 if (cflag & PARODD) {
3085 /* set odd parity (or Mark if CMSPAR) */
3086 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
3087 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
3088 }
3089
3090 if (cflag & CRTSCTS) {
3091 /* enable automatic CTS handling */
3092 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
3093 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
3094 }
3095
3096 /* make sure the tx and rx are enabled */
3097
3098 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
3099 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
3100
3101 /* actually write the control regs to the hardware */
3102
3103 info->port[REG_TR_CTRL] = info->tx_ctrl;
3104 info->port[REG_REC_CTRL] = info->rx_ctrl;
3105 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->tty));
3106 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
3107 if (info->tty->termios->c_iflag & IXON ) {
3108 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n", STOP_CHAR(info->tty)));
3109 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
3110 }
3111
3112 *((unsigned long *)&info->port[REG_XOFF]) = xoff;
77accbf5 3113 local_irq_restore(flags);
1da177e4
LT		 3114#endif /* !CONFIG_SVINTO_SIM */
3115
3116 update_char_time(info);
3117
3118} /* change_speed */
3119
3120/* start transmitting chars NOW */
3121
3122static void
3123rs_flush_chars(struct tty_struct *tty)
3124{
3125 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3126 unsigned long flags;
3127
3128 if (info->tr_running ||
3129 info->xmit.head == info->xmit.tail ||
3130 tty->stopped ||
3131 tty->hw_stopped ||
3132 !info->xmit.buf)
3133 return;
3134
3135#ifdef SERIAL_DEBUG_FLOW
3136 printk("rs_flush_chars\n");
3137#endif
3138
3139 /* this protection might not exactly be necessary here */
3140
77accbf5 3141 local_irq_save(flags);
1da177e4 3142 start_transmit(info);
77accbf5 3143 local_irq_restore(flags);
1da177e4
LT		 3144}
3145
77accbf5 3146static int rs_raw_write(struct tty_struct *tty,
41c28ff1 3147 const unsigned char *buf, int count)
1da177e4
LT		 3148{
3149 int c, ret = 0;
3150 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3151 unsigned long flags;
3152
3153 /* first some sanity checks */
3154
3155 if (!tty || !info->xmit.buf || !tmp_buf)
3156 return 0;
3157
3158#ifdef SERIAL_DEBUG_DATA
3159 if (info->line == SERIAL_DEBUG_LINE)
3160 printk("rs_raw_write (%d), status %d\n",
3161 count, info->port[REG_STATUS]);
3162#endif
3163
3164#ifdef CONFIG_SVINTO_SIM
3165 /* Really simple. The output is here and now. */
3166 SIMCOUT(buf, count);
3167 return count;
3168#endif
77accbf5 3169 local_save_flags(flags);
1da177e4
LT		 3170 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
3171 DFLOW(DEBUG_LOG(info->line, "ldisc %i\n", tty->ldisc.chars_in_buffer(tty)));
3172
3173
77accbf5
JN		 3174 /* The local_irq_disable/restore_flags pairs below are needed
3175 * because the DMA interrupt handler moves the info->xmit values.
3176 * the memcpy needs to be in the critical region unfortunately,
3177 * because we need to read xmit values, memcpy, write xmit values
3178 * in one atomic operation... this could perhaps be avoided by
3179 * more clever design.
1da177e4 3180 */
77accbf5 3181 local_irq_disable();
1da177e4
LT		 3182 while (count) {
3183 c = CIRC_SPACE_TO_END(info->xmit.head,
3184 info->xmit.tail,
3185 SERIAL_XMIT_SIZE);
3186
3187 if (count < c)
3188 c = count;
3189 if (c <= 0)
3190 break;
3191
3192 memcpy(info->xmit.buf + info->xmit.head, buf, c);
3193 info->xmit.head = (info->xmit.head + c) &
3194 (SERIAL_XMIT_SIZE-1);
3195 buf += c;
3196 count -= c;
3197 ret += c;
3198 }
77accbf5 3199 local_irq_restore(flags);
1da177e4
LT		 3200
3201 /* enable transmitter if not running, unless the tty is stopped
3202 * this does not need IRQ protection since if tr_running == 0
3203 * the IRQ's are not running anyway for this port.
3204 */
3205 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3206
3207 if (info->xmit.head != info->xmit.tail &&
3208 !tty->stopped &&
3209 !tty->hw_stopped &&
3210 !info->tr_running) {
3211 start_transmit(info);
3212 }
3213
3214 return ret;
3215} /* raw_raw_write() */
3216
3217static int
77accbf5 3218rs_write(struct tty_struct *tty,
1da177e4
LT		 3219 const unsigned char *buf, int count)
3220{
3221#if defined(CONFIG_ETRAX_RS485)
3222 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3223
3224 if (info->rs485.enabled)
3225 {
3226 /* If we are in RS-485 mode, we need to toggle RTS and disable
3227 * the receiver before initiating a DMA transfer
3228 */
3229#ifdef CONFIG_ETRAX_FAST_TIMER
3230 /* Abort any started timer */
3231 fast_timers_rs485[info->line].function = NULL;
3232 del_fast_timer(&fast_timers_rs485[info->line]);
3233#endif
3234 e100_rts(info, info->rs485.rts_on_send);
3235#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3236 e100_disable_rx(info);
3237 e100_enable_rx_irq(info);
3238#endif
3239
3240 if (info->rs485.delay_rts_before_send > 0)
3241 msleep(info->rs485.delay_rts_before_send);
3242 }
3243#endif /* CONFIG_ETRAX_RS485 */
3244
77accbf5 3245 count = rs_raw_write(tty, buf, count);
1da177e4
LT		 3246
3247#if defined(CONFIG_ETRAX_RS485)
3248 if (info->rs485.enabled)
3249 {
3250 unsigned int val;
3251 /* If we are in RS-485 mode the following has to be done:
3252 * wait until DMA is ready
3253 * wait on transmit shift register
3254 * toggle RTS
3255 * enable the receiver
3256 */
3257
3258 /* Sleep until all sent */
3259 tty_wait_until_sent(tty, 0);
3260#ifdef CONFIG_ETRAX_FAST_TIMER
3261 /* Now sleep a little more so that shift register is empty */
3262 schedule_usleep(info->char_time_usec * 2);
3263#endif
3264 /* wait on transmit shift register */
3265 do{
3266 get_lsr_info(info, &val);
3267 }while (!(val & TIOCSER_TEMT));
3268
3269 e100_rts(info, info->rs485.rts_after_sent);
3270
3271#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3272 e100_enable_rx(info);
3273 e100_enable_rxdma_irq(info);
3274#endif
3275 }
3276#endif /* CONFIG_ETRAX_RS485 */
3277
3278 return count;
3279} /* rs_write */
3280
3281
3282/* how much space is available in the xmit buffer? */
3283
3284static int
3285rs_write_room(struct tty_struct *tty)
3286{
3287 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3288
3289 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3290}
3291
3292/* How many chars are in the xmit buffer?
3293 * This does not include any chars in the transmitter FIFO.
3294 * Use wait_until_sent for waiting for FIFO drain.
3295 */
3296
3297static int
3298rs_chars_in_buffer(struct tty_struct *tty)
3299{
3300 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3301
3302 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3303}
3304
3305/* discard everything in the xmit buffer */
3306
3307static void
3308rs_flush_buffer(struct tty_struct *tty)
3309{
3310 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3311 unsigned long flags;
3312
77accbf5 3313 local_irq_save(flags);
1da177e4 3314 info->xmit.head = info->xmit.tail = 0;
77accbf5 3315 local_irq_restore(flags);
1da177e4 3316
b963a844 3317 tty_wakeup(tty);
1da177e4
LT		 3318}
3319
3320/*
3321 * This function is used to send a high-priority XON/XOFF character to
3322 * the device
3323 *
3324 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3325 * but we do it in handle_ser_tx_interrupt().
3326 * We disable DMA channel and enable tx ready interrupt and write the
3327 * character when possible.
3328 */
3329static void rs_send_xchar(struct tty_struct *tty, char ch)
3330{
3331 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3332 unsigned long flags;
77accbf5 3333 local_irq_save(flags);
1da177e4
LT		 3334 if (info->uses_dma_out) {
3335 /* Put the DMA on hold and disable the channel */
3336 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3337 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3338 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3339 e100_disable_txdma_channel(info);
3340 }
3341
3342 /* Must make sure transmitter is not stopped before we can transmit */
3343 if (tty->stopped)
3344 rs_start(tty);
3345
3346 /* Enable manual transmit interrupt and send from there */
3347 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3348 info->x_char = ch;
3349 e100_enable_serial_tx_ready_irq(info);
77accbf5 3350 local_irq_restore(flags);
1da177e4
LT		 3351}
3352
3353/*
3354 * ------------------------------------------------------------
3355 * rs_throttle()
3356 *
3357 * This routine is called by the upper-layer tty layer to signal that
3358 * incoming characters should be throttled.
3359 * ------------------------------------------------------------
3360 */
3361static void
3362rs_throttle(struct tty_struct * tty)
3363{
3364 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3365#ifdef SERIAL_DEBUG_THROTTLE
3366 char buf[64];
3367
3368 printk("throttle %s: %lu....\n", tty_name(tty, buf),
3369 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3370#endif
3371 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty)));
3372
3373 /* Do RTS before XOFF since XOFF might take some time */
3374 if (tty->termios->c_cflag & CRTSCTS) {
3375 /* Turn off RTS line */
3376 e100_rts(info, 0);
3377 }
3378 if (I_IXOFF(tty))
3379 rs_send_xchar(tty, STOP_CHAR(tty));
3380
3381}
3382
3383static void
3384rs_unthrottle(struct tty_struct * tty)
3385{
3386 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3387#ifdef SERIAL_DEBUG_THROTTLE
3388 char buf[64];
3389
3390 printk("unthrottle %s: %lu....\n", tty_name(tty, buf),
3391 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3392#endif
3393 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty)));
3394 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3395 /* Do RTS before XOFF since XOFF might take some time */
3396 if (tty->termios->c_cflag & CRTSCTS) {
3397 /* Assert RTS line */
3398 e100_rts(info, 1);
3399 }
3400
3401 if (I_IXOFF(tty)) {
3402 if (info->x_char)
3403 info->x_char = 0;
3404 else
3405 rs_send_xchar(tty, START_CHAR(tty));
3406 }
3407
3408}
3409
3410/*
3411 * ------------------------------------------------------------
3412 * rs_ioctl() and friends
3413 * ------------------------------------------------------------
3414 */
3415
3416static int
3417get_serial_info(struct e100_serial * info,
3418 struct serial_struct * retinfo)
3419{
3420 struct serial_struct tmp;
3421
3422 /* this is all probably wrong, there are a lot of fields
3423 * here that we don't have in e100_serial and maybe we
3424 * should set them to something else than 0.
3425 */
3426
3427 if (!retinfo)
3428 return -EFAULT;
3429 memset(&tmp, 0, sizeof(tmp));
3430 tmp.type = info->type;
3431 tmp.line = info->line;
3432 tmp.port = (int)info->port;
3433 tmp.irq = info->irq;
3434 tmp.flags = info->flags;
3435 tmp.baud_base = info->baud_base;
3436 tmp.close_delay = info->close_delay;
3437 tmp.closing_wait = info->closing_wait;
3438 tmp.custom_divisor = info->custom_divisor;
3439 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3440 return -EFAULT;
3441 return 0;
3442}
3443
3444static int
3445set_serial_info(struct e100_serial *info,
3446 struct serial_struct *new_info)
3447{
3448 struct serial_struct new_serial;
3449 struct e100_serial old_info;
3450 int retval = 0;
3451
3452 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3453 return -EFAULT;
3454
3455 old_info = *info;
3456
3457 if (!capable(CAP_SYS_ADMIN)) {
3458 if ((new_serial.type != info->type) ||
3459 (new_serial.close_delay != info->close_delay) ||
3460 ((new_serial.flags & ~ASYNC_USR_MASK) !=
3461 (info->flags & ~ASYNC_USR_MASK)))
3462 return -EPERM;
3463 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
3464 (new_serial.flags & ASYNC_USR_MASK));
3465 goto check_and_exit;
3466 }
3467
3468 if (info->count > 1)
3469 return -EBUSY;
3470
3471 /*
3472 * OK, past this point, all the error checking has been done.
3473 * At this point, we start making changes.....
3474 */
3475
3476 info->baud_base = new_serial.baud_base;
3477 info->flags = ((info->flags & ~ASYNC_FLAGS) |
3478 (new_serial.flags & ASYNC_FLAGS));
3479 info->custom_divisor = new_serial.custom_divisor;
3480 info->type = new_serial.type;
3481 info->close_delay = new_serial.close_delay;
3482 info->closing_wait = new_serial.closing_wait;
3483 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3484
3485 check_and_exit:
3486 if (info->flags & ASYNC_INITIALIZED) {
3487 change_speed(info);
3488 } else
3489 retval = startup(info);
3490 return retval;
3491}
3492
3493/*
3494 * get_lsr_info - get line status register info
3495 *
3496 * Purpose: Let user call ioctl() to get info when the UART physically
3497 * is emptied. On bus types like RS485, the transmitter must
3498 * release the bus after transmitting. This must be done when
3499 * the transmit shift register is empty, not be done when the
3500 * transmit holding register is empty. This functionality
3501 * allows an RS485 driver to be written in user space.
3502 */
3503static int
3504get_lsr_info(struct e100_serial * info, unsigned int *value)
3505{
3506 unsigned int result = TIOCSER_TEMT;
3507#ifndef CONFIG_SVINTO_SIM
3508 unsigned long curr_time = jiffies;
3509 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3510 unsigned long elapsed_usec =
3511 (curr_time - info->last_tx_active) * 1000000/HZ +
3512 curr_time_usec - info->last_tx_active_usec;
3513
3514 if (info->xmit.head != info->xmit.tail ||
3515 elapsed_usec < 2*info->char_time_usec) {
3516 result = 0;
3517 }
3518#endif
3519
3520 if (copy_to_user(value, &result, sizeof(int)))
3521 return -EFAULT;
3522 return 0;
3523}
3524
3525#ifdef SERIAL_DEBUG_IO
3526struct state_str
3527{
3528 int state;
3529 const char *str;
3530};
3531
3532const struct state_str control_state_str[] = {
3533 {TIOCM_DTR, "DTR" },
3534 {TIOCM_RTS, "RTS"},
3535 {TIOCM_ST, "ST?" },
3536 {TIOCM_SR, "SR?" },
3537 {TIOCM_CTS, "CTS" },
3538 {TIOCM_CD, "CD" },
3539 {TIOCM_RI, "RI" },
3540 {TIOCM_DSR, "DSR" },
3541 {0, NULL }
3542};
3543
3544char *get_control_state_str(int MLines, char *s)
3545{
3546 int i = 0;
3547
3548 s[0]='\0';
3549 while (control_state_str[i].str != NULL) {
3550 if (MLines & control_state_str[i].state) {
3551 if (s[0] != '\0') {
3552 strcat(s, ", ");
3553 }
3554 strcat(s, control_state_str[i].str);
3555 }
3556 i++;
3557 }
3558 return s;
3559}
3560#endif
3561
77accbf5
JN		 3562static void
3563rs_break(struct tty_struct *tty, int break_state)
3564{
3565 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3566 unsigned long flags;
3567
3568 if (!info->port)
3569 return;
3570
3571 local_irq_save(flags);
3572 if (break_state == -1) {
3573 /* Go to manual mode and set the txd pin to 0 */
3574 /* Clear bit 7 (txd) and 6 (tr_enable) */
3575 info->tx_ctrl &= 0x3F;
3576 } else {
3577 /* Set bit 7 (txd) and 6 (tr_enable) */
3578 info->tx_ctrl |= (0x80 | 0x40);
3579 }
3580 info->port[REG_TR_CTRL] = info->tx_ctrl;
3581 local_irq_restore(flags);
3582}
3583
1da177e4 3584static int
77accbf5
JN		 3585rs_tiocmset(struct tty_struct *tty, struct file *file,
3586 unsigned int set, unsigned int clear)
1da177e4 3587{
77accbf5 3588 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1da177e4 3589
77accbf5
JN		 3590 if (clear & TIOCM_RTS)
3591 e100_rts(info, 0);
3592 if (clear & TIOCM_DTR)
3593 e100_dtr(info, 0);
3594 /* Handle FEMALE behaviour */
3595 if (clear & TIOCM_RI)
3596 e100_ri_out(info, 0);
3597 if (clear & TIOCM_CD)
3598 e100_cd_out(info, 0);
3599
3600 if (set & TIOCM_RTS)
3601 e100_rts(info, 1);
3602 if (set & TIOCM_DTR)
3603 e100_dtr(info, 1);
3604 /* Handle FEMALE behaviour */
3605 if (set & TIOCM_RI)
3606 e100_ri_out(info, 1);
3607 if (set & TIOCM_CD)
3608 e100_cd_out(info, 1);
3609 return 0;
3610}
3611
3612static int
3613rs_tiocmget(struct tty_struct *tty, struct file *file)
3614{
3615 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3616 unsigned int result;
1da177e4
LT		 3617
3618 result =
3619 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3620 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3621 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3622 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3623 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3624 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3625
3626#ifdef SERIAL_DEBUG_IO
77accbf5
JN		 3627 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3628 info->line, result, result);
1da177e4
LT		 3629 {
3630 char s[100];
3631
3632 get_control_state_str(result, s);
77accbf5 3633 printk(KERN_DEBUG "state: %s\n", s);
1da177e4
LT		 3634 }
3635#endif
77accbf5 3636 return result;
1da177e4 3637
1da177e4
LT		 3638}
3639
3640
1da177e4
LT		 3641static int
3642rs_ioctl(struct tty_struct *tty, struct file * file,
3643 unsigned int cmd, unsigned long arg)
3644{
3645 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3646
3647 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3648 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3649 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
3650 if (tty->flags & (1 << TTY_IO_ERROR))
3651 return -EIO;
3652 }
3653
3654 switch (cmd) {
77accbf5
JN		 3655 case TIOCGSERIAL:
3656 return get_serial_info(info,
3657 (struct serial_struct *) arg);
3658 case TIOCSSERIAL:
3659 return set_serial_info(info,
3660 (struct serial_struct *) arg);
3661 case TIOCSERGETLSR: /* Get line status register */
3662 return get_lsr_info(info, (unsigned int *) arg);
3663
3664 case TIOCSERGSTRUCT:
3665 if (copy_to_user((struct e100_serial *) arg,
3666 info, sizeof(struct e100_serial)))
3667 return -EFAULT;
3668 return 0;
1da177e4
LT		 3669
3670#if defined(CONFIG_ETRAX_RS485)
77accbf5
JN		 3671 case TIOCSERSETRS485:
3672 {
3673 struct rs485_control rs485ctrl;
3674 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3675 sizeof(rs485ctrl)))
3676 return -EFAULT;
1da177e4 3677
77accbf5
JN		 3678 return e100_enable_rs485(tty, &rs485ctrl);
3679 }
1da177e4 3680
77accbf5
JN		 3681 case TIOCSERWRRS485:
3682 {
3683 struct rs485_write rs485wr;
3684 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3685 sizeof(rs485wr)))
3686 return -EFAULT;
1da177e4 3687
77accbf5
JN		 3688 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3689 }
1da177e4
LT		 3690#endif
3691
77accbf5
JN		 3692 default:
3693 return -ENOIOCTLCMD;
1da177e4
LT		 3694 }
3695 return 0;
3696}
3697
3698static void
606d099c 3699rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4
LT		 3700{
3701 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3702
3703 if (tty->termios->c_cflag == old_termios->c_cflag &&
3704 tty->termios->c_iflag == old_termios->c_iflag)
3705 return;
3706
3707 change_speed(info);
3708
3709 /* Handle turning off CRTSCTS */
3710 if ((old_termios->c_cflag & CRTSCTS) &&
3711 !(tty->termios->c_cflag & CRTSCTS)) {
3712 tty->hw_stopped = 0;
3713 rs_start(tty);
3714 }
3715
3716}
3717
1da177e4
LT		 3718/*
3719 * ------------------------------------------------------------
3720 * rs_close()
3721 *
3722 * This routine is called when the serial port gets closed. First, we
3723 * wait for the last remaining data to be sent. Then, we unlink its
3724 * S structure from the interrupt chain if necessary, and we free
3725 * that IRQ if nothing is left in the chain.
3726 * ------------------------------------------------------------
3727 */
3728static void
3729rs_close(struct tty_struct *tty, struct file * filp)
3730{
3731 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3732 unsigned long flags;
3733
3734 if (!info)
3735 return;
3736
3737 /* interrupts are disabled for this entire function */
3738
77accbf5 3739 local_irq_save(flags);
1da177e4
LT		 3740
3741 if (tty_hung_up_p(filp)) {
77accbf5 3742 local_irq_restore(flags);
1da177e4
LT		 3743 return;
3744 }
3745
3746#ifdef SERIAL_DEBUG_OPEN
3747 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3748 info->line, info->count);
3749#endif
3750 if ((tty->count == 1) && (info->count != 1)) {
3751 /*
3752 * Uh, oh. tty->count is 1, which means that the tty
3753 * structure will be freed. Info->count should always
3754 * be one in these conditions. If it's greater than
3755 * one, we've got real problems, since it means the
3756 * serial port won't be shutdown.
3757 */
3758 printk(KERN_CRIT
3759 "rs_close: bad serial port count; tty->count is 1, "
3760 "info->count is %d\n", info->count);
3761 info->count = 1;
3762 }
3763 if (--info->count < 0) {
3764 printk(KERN_CRIT "rs_close: bad serial port count for ttyS%d: %d\n",
3765 info->line, info->count);
3766 info->count = 0;
3767 }
3768 if (info->count) {
77accbf5 3769 local_irq_restore(flags);
1da177e4
LT		 3770 return;
3771 }
3772 info->flags |= ASYNC_CLOSING;
3773 /*
3774 * Save the termios structure, since this port may have
3775 * separate termios for callout and dialin.
3776 */
3777 if (info->flags & ASYNC_NORMAL_ACTIVE)
3778 info->normal_termios = *tty->termios;
3779 /*
3780 * Now we wait for the transmit buffer to clear; and we notify
3781 * the line discipline to only process XON/XOFF characters.
3782 */
3783 tty->closing = 1;
3784 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
3785 tty_wait_until_sent(tty, info->closing_wait);
3786 /*
3787 * At this point we stop accepting input. To do this, we
3788 * disable the serial receiver and the DMA receive interrupt.
3789 */
3790#ifdef SERIAL_HANDLE_EARLY_ERRORS
3791 e100_disable_serial_data_irq(info);
3792#endif
3793
3794#ifndef CONFIG_SVINTO_SIM
3795 e100_disable_rx(info);
3796 e100_disable_rx_irq(info);
3797
3798 if (info->flags & ASYNC_INITIALIZED) {
3799 /*
3800 * Before we drop DTR, make sure the UART transmitter
3801 * has completely drained; this is especially
3802 * important as we have a transmit FIFO!
3803 */
3804 rs_wait_until_sent(tty, HZ);
3805 }
3806#endif
3807
3808 shutdown(info);
3809 if (tty->driver->flush_buffer)
3810 tty->driver->flush_buffer(tty);
3811 if (tty->ldisc.flush_buffer)
3812 tty->ldisc.flush_buffer(tty);
3813 tty->closing = 0;
3814 info->event = 0;
3815 info->tty = 0;
3816 if (info->blocked_open) {
3c76bc5b
NA		 3817 if (info->close_delay)
3818 schedule_timeout_interruptible(info->close_delay);
1da177e4
LT		 3819 wake_up_interruptible(&info->open_wait);
3820 }
3821 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3822 wake_up_interruptible(&info->close_wait);
77accbf5 3823 local_irq_restore(flags);
1da177e4
LT		 3824
3825 /* port closed */
3826
3827#if defined(CONFIG_ETRAX_RS485)
3828 if (info->rs485.enabled) {
3829 info->rs485.enabled = 0;
3830#if defined(CONFIG_ETRAX_RS485_ON_PA)
3831 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
3832#endif
3833#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
3834 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3835 rs485_port_g_bit, 0);
3836#endif
3837#if defined(CONFIG_ETRAX_RS485_LTC1387)
3838 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3839 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 0);
3840 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3841 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 0);
3842#endif
3843 }
3844#endif
77accbf5
JN		 3845
3846 /*
3847 * Release any allocated DMA irq's.
3848 */
3849 if (info->dma_in_enabled) {
3850 free_irq(info->dma_in_irq_nbr, info);
3851 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3852 info->uses_dma_in = 0;
3853#ifdef SERIAL_DEBUG_OPEN
3854 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3855 info->dma_in_irq_description);
3856#endif
3857 }
3858 if (info->dma_out_enabled) {
3859 free_irq(info->dma_out_irq_nbr, info);
3860 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3861 info->uses_dma_out = 0;
3862#ifdef SERIAL_DEBUG_OPEN
3863 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3864 info->dma_out_irq_description);
3865#endif
3866 }
1da177e4
LT		 3867}
3868
3869/*
3870 * rs_wait_until_sent() --- wait until the transmitter is empty
3871 */
3872static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3873{
3874 unsigned long orig_jiffies;
3875 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3876 unsigned long curr_time = jiffies;
3877 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3878 long elapsed_usec =
3879 (curr_time - info->last_tx_active) * (1000000/HZ) +
3880 curr_time_usec - info->last_tx_active_usec;
3881
3882 /*
3883 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3884 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3885 */
3886 orig_jiffies = jiffies;
3887 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3888 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3889 (elapsed_usec < 2*info->char_time_usec)) {
3c76bc5b 3890 schedule_timeout_interruptible(1);
1da177e4
LT		 3891 if (signal_pending(current))
3892 break;
3893 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3894 break;
3895 curr_time = jiffies;
3896 curr_time_usec = GET_JIFFIES_USEC();
3897 elapsed_usec =
3898 (curr_time - info->last_tx_active) * (1000000/HZ) +
3899 curr_time_usec - info->last_tx_active_usec;
3900 }
3901 set_current_state(TASK_RUNNING);
3902}
3903
3904/*
3905 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3906 */
3907void
3908rs_hangup(struct tty_struct *tty)
3909{
3910 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3911
3912 rs_flush_buffer(tty);
3913 shutdown(info);
3914 info->event = 0;
3915 info->count = 0;
3916 info->flags &= ~ASYNC_NORMAL_ACTIVE;
3917 info->tty = 0;
3918 wake_up_interruptible(&info->open_wait);
3919}
3920
3921/*
3922 * ------------------------------------------------------------
3923 * rs_open() and friends
3924 * ------------------------------------------------------------
3925 */
3926static int
3927block_til_ready(struct tty_struct *tty, struct file * filp,
3928 struct e100_serial *info)
3929{
3930 DECLARE_WAITQUEUE(wait, current);
3931 unsigned long flags;
3932 int retval;
3933 int do_clocal = 0, extra_count = 0;
3934
3935 /*
3936 * If the device is in the middle of being closed, then block
3937 * until it's done, and then try again.
3938 */
3939 if (tty_hung_up_p(filp) ||
3940 (info->flags & ASYNC_CLOSING)) {
77accbf5
JN		 3941 wait_event_interruptible(info->close_wait,
3942 !(info->flags & ASYNC_CLOSING));
1da177e4
LT		 3943#ifdef SERIAL_DO_RESTART
3944 if (info->flags & ASYNC_HUP_NOTIFY)
3945 return -EAGAIN;
3946 else
3947 return -ERESTARTSYS;
3948#else
3949 return -EAGAIN;
3950#endif
3951 }
3952
3953 /*
3954 * If non-blocking mode is set, or the port is not enabled,
3955 * then make the check up front and then exit.
3956 */
3957 if ((filp->f_flags & O_NONBLOCK) ||
3958 (tty->flags & (1 << TTY_IO_ERROR))) {
3959 info->flags |= ASYNC_NORMAL_ACTIVE;
3960 return 0;
3961 }
3962
3963 if (tty->termios->c_cflag & CLOCAL) {
3964 do_clocal = 1;
3965 }
3966
3967 /*
3968 * Block waiting for the carrier detect and the line to become
3969 * free (i.e., not in use by the callout). While we are in
3970 * this loop, info->count is dropped by one, so that
3971 * rs_close() knows when to free things. We restore it upon
3972 * exit, either normal or abnormal.
3973 */
3974 retval = 0;
3975 add_wait_queue(&info->open_wait, &wait);
3976#ifdef SERIAL_DEBUG_OPEN
3977 printk("block_til_ready before block: ttyS%d, count = %d\n",
3978 info->line, info->count);
3979#endif
77accbf5 3980 local_irq_save(flags);
1da177e4
LT		 3981 if (!tty_hung_up_p(filp)) {
3982 extra_count++;
3983 info->count--;
3984 }
77accbf5 3985 local_irq_restore(flags);
1da177e4
LT		 3986 info->blocked_open++;
3987 while (1) {
77accbf5 3988 local_irq_save(flags);
1da177e4
LT		 3989 /* assert RTS and DTR */
3990 e100_rts(info, 1);
3991 e100_dtr(info, 1);
77accbf5 3992 local_irq_restore(flags);
1da177e4
LT		 3993 set_current_state(TASK_INTERRUPTIBLE);
3994 if (tty_hung_up_p(filp) ||
3995 !(info->flags & ASYNC_INITIALIZED)) {
3996#ifdef SERIAL_DO_RESTART
3997 if (info->flags & ASYNC_HUP_NOTIFY)
3998 retval = -EAGAIN;
3999 else
4000 retval = -ERESTARTSYS;
4001#else
4002 retval = -EAGAIN;
4003#endif
4004 break;
4005 }
4006 if (!(info->flags & ASYNC_CLOSING) && do_clocal)
4007 /* && (do_clocal || DCD_IS_ASSERTED) */
4008 break;
4009 if (signal_pending(current)) {
4010 retval = -ERESTARTSYS;
4011 break;
4012 }
4013#ifdef SERIAL_DEBUG_OPEN
4014 printk("block_til_ready blocking: ttyS%d, count = %d\n",
4015 info->line, info->count);
4016#endif
4017 schedule();
4018 }
4019 set_current_state(TASK_RUNNING);
4020 remove_wait_queue(&info->open_wait, &wait);
4021 if (extra_count)
4022 info->count++;
4023 info->blocked_open--;
4024#ifdef SERIAL_DEBUG_OPEN
4025 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
4026 info->line, info->count);
4027#endif
4028 if (retval)
4029 return retval;
4030 info->flags |= ASYNC_NORMAL_ACTIVE;
4031 return 0;
4032}
4033
77accbf5
JN		 4034static void
4035deinit_port(struct e100_serial *info)
4036{
4037 if (info->dma_out_enabled) {
4038 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
4039 free_irq(info->dma_out_irq_nbr, info);
4040 }
4041 if (info->dma_in_enabled) {
4042 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
4043 free_irq(info->dma_in_irq_nbr, info);
4044 }
4045}
4046
1da177e4
LT		 4047/*
4048 * This routine is called whenever a serial port is opened.
4049 * It performs the serial-specific initialization for the tty structure.
4050 */
4051static int
4052rs_open(struct tty_struct *tty, struct file * filp)
4053{
4054 struct e100_serial *info;
4055 int retval, line;
4056 unsigned long page;
77accbf5 4057 int allocated_resources = 0;
1da177e4
LT		 4058
4059 /* find which port we want to open */
1da177e4
LT		 4060 line = tty->index;
4061
4062 if (line < 0 || line >= NR_PORTS)
4063 return -ENODEV;
4064
4065 /* find the corresponding e100_serial struct in the table */
4066 info = rs_table + line;
4067
4068 /* don't allow the opening of ports that are not enabled in the HW config */
4069 if (!info->enabled)
4070 return -ENODEV;
4071
4072#ifdef SERIAL_DEBUG_OPEN
4073 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
4074 info->count);
4075#endif
4076
4077 info->count++;
4078 tty->driver_data = info;
4079 info->tty = tty;
4080
4081 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
4082
4083 if (!tmp_buf) {
4084 page = get_zeroed_page(GFP_KERNEL);
4085 if (!page) {
4086 return -ENOMEM;
4087 }
4088 if (tmp_buf)
4089 free_page(page);
4090 else
4091 tmp_buf = (unsigned char *) page;
4092 }
4093
4094 /*
4095 * If the port is in the middle of closing, bail out now
4096 */
4097 if (tty_hung_up_p(filp) ||
4098 (info->flags & ASYNC_CLOSING)) {
77accbf5
JN		 4099 wait_event_interruptible(info->close_wait,
4100 !(info->flags & ASYNC_CLOSING));
1da177e4
LT		 4101#ifdef SERIAL_DO_RESTART
4102 return ((info->flags & ASYNC_HUP_NOTIFY) ?
4103 -EAGAIN : -ERESTARTSYS);
4104#else
4105 return -EAGAIN;
4106#endif
4107 }
4108
77accbf5
JN		 4109 /*
4110 * If DMA is enabled try to allocate the irq's.
4111 */
4112 if (info->count == 1) {
4113 allocated_resources = 1;
4114 if (info->dma_in_enabled) {
4115 if (request_irq(info->dma_in_irq_nbr,
4116 rec_interrupt,
4117 info->dma_in_irq_flags,
4118 info->dma_in_irq_description,
4119 info)) {
4120 printk(KERN_WARNING "DMA irq '%s' busy; "
4121 "falling back to non-DMA mode\n",
4122 info->dma_in_irq_description);
4123 /* Make sure we never try to use DMA in */
4124 /* for the port again. */
4125 info->dma_in_enabled = 0;
4126 } else if (cris_request_dma(info->dma_in_nbr,
4127 info->dma_in_irq_description,
4128 DMA_VERBOSE_ON_ERROR,
4129 info->dma_owner)) {
4130 free_irq(info->dma_in_irq_nbr, info);
4131 printk(KERN_WARNING "DMA '%s' busy; "
4132 "falling back to non-DMA mode\n",
4133 info->dma_in_irq_description);
4134 /* Make sure we never try to use DMA in */
4135 /* for the port again. */
4136 info->dma_in_enabled = 0;
4137 }
4138#ifdef SERIAL_DEBUG_OPEN
4139 else
4140 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4141 info->dma_in_irq_description);
4142#endif
4143 }
4144 if (info->dma_out_enabled) {
4145 if (request_irq(info->dma_out_irq_nbr,
4146 tr_interrupt,
4147 info->dma_out_irq_flags,
4148 info->dma_out_irq_description,
4149 info)) {
4150 printk(KERN_WARNING "DMA irq '%s' busy; "
4151 "falling back to non-DMA mode\n",
4152 info->dma_out_irq_description);
4153 /* Make sure we never try to use DMA out */
4154 /* for the port again. */
4155 info->dma_out_enabled = 0;
4156 } else if (cris_request_dma(info->dma_out_nbr,
4157 info->dma_out_irq_description,
4158 DMA_VERBOSE_ON_ERROR,
4159 info->dma_owner)) {
4160 free_irq(info->dma_out_irq_nbr, info);
4161 printk(KERN_WARNING "DMA '%s' busy; "
4162 "falling back to non-DMA mode\n",
4163 info->dma_out_irq_description);
4164 /* Make sure we never try to use DMA out */
4165 /* for the port again. */
4166 info->dma_out_enabled = 0;
4167 }
4168#ifdef SERIAL_DEBUG_OPEN
4169 else
4170 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4171 info->dma_out_irq_description);
4172#endif
4173 }
4174 }
4175
1da177e4
LT		 4176 /*
4177 * Start up the serial port
4178 */
4179
4180 retval = startup(info);
77accbf5
JN		 4181 if (retval) {
4182 if (allocated_resources)
4183 deinit_port(info);
4184
4185 /* FIXME Decrease count info->count here too? */
1da177e4 4186 return retval;
77accbf5
JN		 4187 }
4188
1da177e4
LT		 4189
4190 retval = block_til_ready(tty, filp, info);
4191 if (retval) {
4192#ifdef SERIAL_DEBUG_OPEN
4193 printk("rs_open returning after block_til_ready with %d\n",
4194 retval);
4195#endif
77accbf5
JN		 4196 if (allocated_resources)
4197 deinit_port(info);
4198
1da177e4
LT		 4199 return retval;
4200 }
4201
4202 if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) {
4203 *tty->termios = info->normal_termios;
4204 change_speed(info);
4205 }
4206
4207#ifdef SERIAL_DEBUG_OPEN
4208 printk("rs_open ttyS%d successful...\n", info->line);
4209#endif
4210 DLOG_INT_TRIG( log_int_pos = 0);
4211
4212 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
4213 info->icount.rx = 0;
4214 } );
4215
4216 return 0;
4217}
4218
4219/*
4220 * /proc fs routines....
4221 */
4222
41c28ff1 4223static int line_info(char *buf, struct e100_serial *info)
1da177e4
LT		 4224{
4225 char stat_buf[30];
4226 int ret;
4227 unsigned long tmp;
4228
4229 ret = sprintf(buf, "%d: uart:E100 port:%lX irq:%d",
4230 info->line, (unsigned long)info->port, info->irq);
4231
4232 if (!info->port || (info->type == PORT_UNKNOWN)) {
4233 ret += sprintf(buf+ret, "\n");
4234 return ret;
4235 }
4236
4237 stat_buf[0] = 0;
4238 stat_buf[1] = 0;
4239 if (!E100_RTS_GET(info))
4240 strcat(stat_buf, "|RTS");
4241 if (!E100_CTS_GET(info))
4242 strcat(stat_buf, "|CTS");
4243 if (!E100_DTR_GET(info))
4244 strcat(stat_buf, "|DTR");
4245 if (!E100_DSR_GET(info))
4246 strcat(stat_buf, "|DSR");
4247 if (!E100_CD_GET(info))
4248 strcat(stat_buf, "|CD");
4249 if (!E100_RI_GET(info))
4250 strcat(stat_buf, "|RI");
4251
4252 ret += sprintf(buf+ret, " baud:%d", info->baud);
4253
4254 ret += sprintf(buf+ret, " tx:%lu rx:%lu",
4255 (unsigned long)info->icount.tx,
4256 (unsigned long)info->icount.rx);
4257 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
4258 if (tmp) {
4259 ret += sprintf(buf+ret, " tx_pend:%lu/%lu",
4260 (unsigned long)tmp,
4261 (unsigned long)SERIAL_XMIT_SIZE);
4262 }
4263
4264 ret += sprintf(buf+ret, " rx_pend:%lu/%lu",
4265 (unsigned long)info->recv_cnt,
4266 (unsigned long)info->max_recv_cnt);
4267
4268#if 1
4269 if (info->tty) {
4270
4271 if (info->tty->stopped)
4272 ret += sprintf(buf+ret, " stopped:%i",
4273 (int)info->tty->stopped);
4274 if (info->tty->hw_stopped)
4275 ret += sprintf(buf+ret, " hw_stopped:%i",
4276 (int)info->tty->hw_stopped);
4277 }
4278
4279 {
4280 unsigned char rstat = info->port[REG_STATUS];
4281 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) )
4282 ret += sprintf(buf+ret, " xoff_detect:1");
4283 }
4284
4285#endif
4286
4287
4288
4289
4290 if (info->icount.frame)
4291 ret += sprintf(buf+ret, " fe:%lu",
4292 (unsigned long)info->icount.frame);
4293
4294 if (info->icount.parity)
4295 ret += sprintf(buf+ret, " pe:%lu",
4296 (unsigned long)info->icount.parity);
4297
4298 if (info->icount.brk)
4299 ret += sprintf(buf+ret, " brk:%lu",
4300 (unsigned long)info->icount.brk);
4301
4302 if (info->icount.overrun)
4303 ret += sprintf(buf+ret, " oe:%lu",
4304 (unsigned long)info->icount.overrun);
4305
4306 /*
4307 * Last thing is the RS-232 status lines
4308 */
4309 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
4310 return ret;
4311}
4312
4313int rs_read_proc(char *page, char **start, off_t off, int count,
4314 int *eof, void *data)
4315{
4316 int i, len = 0, l;
4317 off_t begin = 0;
4318
4319 len += sprintf(page, "serinfo:1.0 driver:%s\n",
4320 serial_version);
4321 for (i = 0; i < NR_PORTS && len < 4000; i++) {
4322 if (!rs_table[i].enabled)
4323 continue;
4324 l = line_info(page + len, &rs_table[i]);
4325 len += l;
4326 if (len+begin > off+count)
4327 goto done;
4328 if (len+begin < off) {
4329 begin += len;
4330 len = 0;
4331 }
4332 }
4333#ifdef DEBUG_LOG_INCLUDED
4334 for (i = 0; i < debug_log_pos; i++) {
4335 len += sprintf(page + len, "%-4i %lu.%lu ", i, debug_log[i].time, timer_data_to_ns(debug_log[i].timer_data));
4336 len += sprintf(page + len, debug_log[i].string, debug_log[i].value);
4337 if (len+begin > off+count)
4338 goto done;
4339 if (len+begin < off) {
4340 begin += len;
4341 len = 0;
4342 }
4343 }
4344 len += sprintf(page + len, "debug_log %i/%i %li bytes\n",
4345 i, DEBUG_LOG_SIZE, begin+len);
4346 debug_log_pos = 0;
4347#endif
4348
4349 *eof = 1;
4350done:
4351 if (off >= len+begin)
4352 return 0;
4353 *start = page + (off-begin);
4354 return ((count < begin+len-off) ? count : begin+len-off);
4355}
4356
4357/* Finally, routines used to initialize the serial driver. */
4358
4359static void
4360show_serial_version(void)
4361{
4362 printk(KERN_INFO
4363 "ETRAX 100LX serial-driver %s, (c) 2000-2004 Axis Communications AB\r\n",
4364 &serial_version[11]); /* "$Revision: x.yy" */
4365}
4366
4367/* rs_init inits the driver at boot (using the module_init chain) */
4368
b68e31d0 4369static const struct tty_operations rs_ops = {
1da177e4
LT		 4370 .open = rs_open,
4371 .close = rs_close,
4372 .write = rs_write,
4373 .flush_chars = rs_flush_chars,
4374 .write_room = rs_write_room,
4375 .chars_in_buffer = rs_chars_in_buffer,
4376 .flush_buffer = rs_flush_buffer,
4377 .ioctl = rs_ioctl,
4378 .throttle = rs_throttle,
4379 .unthrottle = rs_unthrottle,
4380 .set_termios = rs_set_termios,
4381 .stop = rs_stop,
4382 .start = rs_start,
4383 .hangup = rs_hangup,
4384 .break_ctl = rs_break,
4385 .send_xchar = rs_send_xchar,
4386 .wait_until_sent = rs_wait_until_sent,
4387 .read_proc = rs_read_proc,
77accbf5
JN		 4388 .tiocmget = rs_tiocmget,
4389 .tiocmset = rs_tiocmset
1da177e4
LT		 4390};
4391
4392static int __init
4393rs_init(void)
4394{
4395 int i;
4396 struct e100_serial *info;
4397 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4398
4399 if (!driver)
4400 return -ENOMEM;
4401
4402 show_serial_version();
4403
4404 /* Setup the timed flush handler system */
4405
4406#if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
77accbf5
JN		 4407 setup_timer(&flush_timer, timed_flush_handler, 0);
4408 mod_timer(&flush_timer, jiffies + 5);
4409#endif
4410
4411#if defined(CONFIG_ETRAX_RS485)
4412#if defined(CONFIG_ETRAX_RS485_ON_PA)
4413 if (cris_io_interface_allocate_pins(if_ser0, 'a', rs485_pa_bit,
4414 rs485_pa_bit)) {
4415 printk(KERN_CRIT "ETRAX100LX serial: Could not allocate "
4416 "RS485 pin\n");
4417 return -EBUSY;
4418 }
4419#endif
4420#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
4421 if (cris_io_interface_allocate_pins(if_ser0, 'g', rs485_pa_bit,
4422 rs485_port_g_bit)) {
4423 printk(KERN_CRIT "ETRAX100LX serial: Could not allocate "
4424 "RS485 pin\n");
4425 return -EBUSY;
4426 }
4427#endif
1da177e4
LT		 4428#endif
4429
4430 /* Initialize the tty_driver structure */
4431
4432 driver->driver_name = "serial";
4433 driver->name = "ttyS";
4434 driver->major = TTY_MAJOR;
4435 driver->minor_start = 64;
4436 driver->type = TTY_DRIVER_TYPE_SERIAL;
4437 driver->subtype = SERIAL_TYPE_NORMAL;
4438 driver->init_termios = tty_std_termios;
4439 driver->init_termios.c_cflag =
4440 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
606d099c
AC		 4441 driver->init_termios.c_ispeed = 115200;
4442 driver->init_termios.c_ospeed = 115200;
331b8319 4443 driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 4444 driver->termios = serial_termios;
4445 driver->termios_locked = serial_termios_locked;
4446
4447 tty_set_operations(driver, &rs_ops);
4448 serial_driver = driver;
4449 if (tty_register_driver(driver))
4450 panic("Couldn't register serial driver\n");
4451 /* do some initializing for the separate ports */
4452
4453 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
77accbf5
JN		 4454 if (info->enabled) {
4455 if (cris_request_io_interface(info->io_if,
4456 info->io_if_description)) {
4457 printk(KERN_CRIT "ETRAX100LX async serial: "
4458 "Could not allocate IO pins for "
4459 "%s, port %d\n",
4460 info->io_if_description, i);
4461 info->enabled = 0;
4462 }
4463 }
1da177e4
LT		 4464 info->uses_dma_in = 0;
4465 info->uses_dma_out = 0;
4466 info->line = i;
4467 info->tty = 0;
4468 info->type = PORT_ETRAX;
4469 info->tr_running = 0;
4470 info->forced_eop = 0;
4471 info->baud_base = DEF_BAUD_BASE;
4472 info->custom_divisor = 0;
4473 info->flags = 0;
4474 info->close_delay = 5*HZ/10;
4475 info->closing_wait = 30*HZ;
4476 info->x_char = 0;
4477 info->event = 0;
4478 info->count = 0;
4479 info->blocked_open = 0;
4480 info->normal_termios = driver->init_termios;
4481 init_waitqueue_head(&info->open_wait);
4482 init_waitqueue_head(&info->close_wait);
4483 info->xmit.buf = NULL;
4484 info->xmit.tail = info->xmit.head = 0;
4485 info->first_recv_buffer = info->last_recv_buffer = NULL;
4486 info->recv_cnt = info->max_recv_cnt = 0;
4487 info->last_tx_active_usec = 0;
4488 info->last_tx_active = 0;
4489
4490#if defined(CONFIG_ETRAX_RS485)
4491 /* Set sane defaults */
4492 info->rs485.rts_on_send = 0;
4493 info->rs485.rts_after_sent = 1;
4494 info->rs485.delay_rts_before_send = 0;
4495 info->rs485.enabled = 0;
4496#endif
77accbf5 4497 INIT_WORK(&info->work, do_softint);
1da177e4
LT		 4498
4499 if (info->enabled) {
4500 printk(KERN_INFO "%s%d at 0x%x is a builtin UART with DMA\n",
4501 serial_driver->name, info->line, (unsigned int)info->port);
4502 }
4503 }
4504#ifdef CONFIG_ETRAX_FAST_TIMER
4505#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4506 memset(fast_timers, 0, sizeof(fast_timers));
4507#endif
4508#ifdef CONFIG_ETRAX_RS485
4509 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4510#endif
4511 fast_timer_init();
4512#endif
4513
4514#ifndef CONFIG_SVINTO_SIM
77accbf5 4515#ifndef CONFIG_ETRAX_KGDB
1da177e4
LT		 4516 /* Not needed in simulator. May only complicate stuff. */
4517 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4518
77accbf5
JN		 4519 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
4520 IRQF_SHARED | IRQF_DISABLED, "serial ", driver))
4521 panic("%s: Failed to request irq8", __FUNCTION__);
1da177e4 4522
1da177e4
LT		 4523#endif
4524#endif /* CONFIG_SVINTO_SIM */
77accbf5 4525
1da177e4
LT		 4526 return 0;
4527}
4528
4529/* this makes sure that rs_init is called during kernel boot */
4530
4531module_init(rs_init);
Empty description
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