[linux.git] / arch / mips / cavium-octeon / serial.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2004-2007 Cavium Networks
 */
#include <linux/console.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/tty.h>
#include <linux/irq.h>

#include <asm/time.h>

#include <asm/octeon/octeon.h>

#define DEBUG_UART 1

unsigned int octeon_serial_in(struct uart_port *up, int offset)
{
	int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
	if (offset == UART_IIR && (rv & 0xf) == 7) {
		/* Busy interrupt, read the USR (39) and try again. */
		cvmx_read_csr((uint64_t)(up->membase + (39 << 3)));
		rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
	}
	return rv;
}

void octeon_serial_out(struct uart_port *up, int offset, int value)
{
	/*
	 * If bits 6 or 7 of the OCTEON UART's LCR are set, it quits
	 * working.
	 */
	if (offset == UART_LCR)
		value &= 0x9f;
	cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
}

static int octeon_serial_probe(struct platform_device *pdev)
{
	int irq, res;
	struct resource *res_mem;
	struct uart_8250_port up;

	/* All adaptors have an irq.  */
	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	memset(&up, 0, sizeof(up));

	up.port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
	up.port.type = PORT_OCTEON;
	up.port.iotype = UPIO_MEM;
	up.port.regshift = 3;
	up.port.dev = &pdev->dev;

	if (octeon_is_simulation())
		/* Make simulator output fast*/
		up.port.uartclk = 115200 * 16;
	else
		up.port.uartclk = octeon_get_io_clock_rate();

	up.port.serial_in = octeon_serial_in;
	up.port.serial_out = octeon_serial_out;
	up.port.irq = irq;

	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res_mem == NULL) {
		dev_err(&pdev->dev, "found no memory resource\n");
		return -ENXIO;
	}
	up.port.mapbase = res_mem->start;
	up.port.membase = ioremap(res_mem->start, resource_size(res_mem));

	res = serial8250_register_8250_port(&up);

	return res >= 0 ? 0 : res;
}

static struct of_device_id octeon_serial_match[] = {
	{
		.compatible = "cavium,octeon-3860-uart",
	},
	{},
};
MODULE_DEVICE_TABLE(of, octeon_serial_match);

static struct platform_driver octeon_serial_driver = {
	.probe		= octeon_serial_probe,
	.driver		= {
		.owner	= THIS_MODULE,
		.name	= "octeon_serial",
		.of_match_table = octeon_serial_match,
	},
};

static int __init octeon_serial_init(void)
{
	return platform_driver_register(&octeon_serial_driver);
}
late_initcall(octeon_serial_init);
Commit	Line	Data
5b3b1688 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2004-2007 Cavium Networks
	7	*/
	8	#include <linux/console.h>
	9	#include <linux/module.h>
	10	#include <linux/init.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/serial.h>
	13	#include <linux/serial_8250.h>
	14	#include <linux/serial_reg.h>
	15	#include <linux/tty.h>
ca4d3e67	16	#include <linux/irq.h>
5b3b1688 DD	17
	18	#include <asm/time.h>
	19
	20	#include <asm/octeon/octeon.h>
	21
5b3b1688	22	#define DEBUG_UART 1
5b3b1688 DD	23
	24	unsigned int octeon_serial_in(struct uart_port *up, int offset)
	25	{
	26	int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
	27	if (offset == UART_IIR && (rv & 0xf) == 7) {
	28	/* Busy interrupt, read the USR (39) and try again. */
	29	cvmx_read_csr((uint64_t)(up->membase + (39 << 3)));
	30	rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
	31	}
	32	return rv;
	33	}
	34
	35	void octeon_serial_out(struct uart_port *up, int offset, int value)
	36	{
	37	/*
	38	* If bits 6 or 7 of the OCTEON UART's LCR are set, it quits
	39	* working.
	40	*/
	41	if (offset == UART_LCR)
	42	value &= 0x9f;
	43	cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
	44	}
	45
28eb0e46	46	static int octeon_serial_probe(struct platform_device *pdev)
5b3b1688	47	{
b59b2841 DD	48	int irq, res;
b59b2841 DD	49	struct resource *res_mem;
640de636	50	struct uart_8250_port up;
b59b2841 DD	51
	52	/* All adaptors have an irq. */
	53	irq = platform_get_irq(pdev, 0);
	54	if (irq < 0)
	55	return irq;
	56
640de636	57	memset(&up, 0, sizeof(up));
b59b2841	58
640de636 DD	59	up.port.flags = ASYNC_SKIP_TEST \| UPF_SHARE_IRQ \| UPF_FIXED_TYPE;
	60	up.port.type = PORT_OCTEON;
	61	up.port.iotype = UPIO_MEM;
	62	up.port.regshift = 3;
	63	up.port.dev = &pdev->dev;
b59b2841	64
606c958e DD	65	if (octeon_is_simulation())
606c958e DD	66	/* Make simulator output fast*/
640de636	67	up.port.uartclk = 115200 * 16;
606c958e	68	else
640de636	69	up.port.uartclk = octeon_get_io_clock_rate();
5b3b1688	70
640de636 DD	71	up.port.serial_in = octeon_serial_in;
	72	up.port.serial_out = octeon_serial_out;
	73	up.port.irq = irq;
5b3b1688	74
b59b2841 DD	75	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	76	if (res_mem == NULL) {
	77	dev_err(&pdev->dev, "found no memory resource\n");
	78	return -ENXIO;
5b3b1688	79	}
640de636 DD	80	up.port.mapbase = res_mem->start;
640de636 DD	81	up.port.membase = ioremap(res_mem->start, resource_size(res_mem));
5b3b1688	82
640de636	83	res = serial8250_register_8250_port(&up);
5b3b1688	84
b59b2841	85	return res >= 0 ? 0 : res;
5b3b1688 DD	86	}
5b3b1688 DD	87
b59b2841 DD	88	static struct of_device_id octeon_serial_match[] = {
	89	{
	90	.compatible = "cavium,octeon-3860-uart",
	91	},
	92	{},
	93	};
	94	MODULE_DEVICE_TABLE(of, octeon_serial_match);
	95
	96	static struct platform_driver octeon_serial_driver = {
	97	.probe = octeon_serial_probe,
	98	.driver = {
	99	.owner = THIS_MODULE,
	100	.name = "octeon_serial",
	101	.of_match_table = octeon_serial_match,
	102	},
	103	};
	104
	105	static int __init octeon_serial_init(void)
	106	{
	107	return platform_driver_register(&octeon_serial_driver);
	108	}
	109	late_initcall(octeon_serial_init);