[linux.git] / arch / mips / cavium-octeon / Kconfig

if CPU_CAVIUM_OCTEON

config CAVIUM_CN63XXP1
	bool "Enable CN63XXP1 errata worarounds"
	default "n"
	help
	  The CN63XXP1 chip requires build time workarounds to
	  function reliably, select this option to enable them.  These
	  workarounds will cause a slight decrease in performance on
	  non-CN63XXP1 hardware, so it is recommended to select "n"
	  unless it is known the workarounds are needed.

config CAVIUM_OCTEON_2ND_KERNEL
	bool "Build the kernel to be used as a 2nd kernel on the same chip"
	default "n"
	help
	  This option configures this kernel to be linked at a different
	  address and use the 2nd uart for output. This allows a kernel built
	  with this option to be run at the same time as one built without this
	  option.

config CAVIUM_OCTEON_HW_FIX_UNALIGNED
	bool "Enable hardware fixups of unaligned loads and stores"
	default "y"
	help
	  Configure the Octeon hardware to automatically fix unaligned loads
	  and stores. Normally unaligned accesses are fixed using a kernel
	  exception handler. This option enables the hardware automatic fixups,
	  which requires only an extra 3 cycles. Disable this option if you
	  are running code that relies on address exceptions on unaligned
	  accesses.

config CAVIUM_OCTEON_CVMSEG_SIZE
	int "Number of L1 cache lines reserved for CVMSEG memory"
	range 0 54
	default 1
	help
	  CVMSEG LM is a segment that accesses portions of the dcache as a
	  local memory; the larger CVMSEG is, the smaller the cache is.
	  This selects the size of CVMSEG LM, which is in cache blocks. The
	  legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
	  between zero and 6192 bytes).

config CAVIUM_OCTEON_LOCK_L2
	bool "Lock often used kernel code in the L2"
	default "y"
	help
	  Enable locking parts of the kernel into the L2 cache.

config CAVIUM_OCTEON_LOCK_L2_TLB
	bool "Lock the TLB handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the low level TLB fast path into L2.

config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
	bool "Lock the exception handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the low level exception handler into L2.

config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
	bool "Lock the interrupt handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the low level interrupt handler into L2.

config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
	bool "Lock the 2nd level interrupt handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the 2nd level interrupt handler in L2.

config CAVIUM_OCTEON_LOCK_L2_MEMCPY
	bool "Lock memcpy() in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the kernel's implementation of memcpy() into L2.

config IOMMU_HELPER
	bool

config NEED_SG_DMA_LENGTH
	bool

config SWIOTLB
	def_bool y
	select IOMMU_HELPER
	select NEED_SG_DMA_LENGTH


config OCTEON_ILM
	tristate "Module to measure interrupt latency using Octeon CIU Timer"
	help
	  This driver is a module to measure interrupt latency using the
	  the CIU Timers on Octeon.

	  To compile this driver as a module, choose M here.  The module
	  will be called octeon-ilm

endif # CPU_CAVIUM_OCTEON
Commit	Line	Data
23a271ec	1	if CPU_CAVIUM_OCTEON
5b3b1688	2
c9941158 DD	3	config CAVIUM_CN63XXP1
c9941158 DD	4	bool "Enable CN63XXP1 errata worarounds"
c9941158 DD	5	default "n"
	6	help
	7	The CN63XXP1 chip requires build time workarounds to
	8	function reliably, select this option to enable them. These
	9	workarounds will cause a slight decrease in performance on
	10	non-CN63XXP1 hardware, so it is recommended to select "n"
	11	unless it is known the workarounds are needed.
	12
5b3b1688 DD	13	config CAVIUM_OCTEON_2ND_KERNEL
5b3b1688 DD	14	bool "Build the kernel to be used as a 2nd kernel on the same chip"
5b3b1688 DD	15	default "n"
	16	help
	17	This option configures this kernel to be linked at a different
	18	address and use the 2nd uart for output. This allows a kernel built
	19	with this option to be run at the same time as one built without this
	20	option.
	21
	22	config CAVIUM_OCTEON_HW_FIX_UNALIGNED
	23	bool "Enable hardware fixups of unaligned loads and stores"
5b3b1688 DD	24	default "y"
	25	help
	26	Configure the Octeon hardware to automatically fix unaligned loads
	27	and stores. Normally unaligned accesses are fixed using a kernel
	28	exception handler. This option enables the hardware automatic fixups,
	29	which requires only an extra 3 cycles. Disable this option if you
	30	are running code that relies on address exceptions on unaligned
	31	accesses.
	32
	33	config CAVIUM_OCTEON_CVMSEG_SIZE
	34	int "Number of L1 cache lines reserved for CVMSEG memory"
5b3b1688 DD	35	range 0 54
	36	default 1
	37	help
	38	CVMSEG LM is a segment that accesses portions of the dcache as a
	39	local memory; the larger CVMSEG is, the smaller the cache is.
	40	This selects the size of CVMSEG LM, which is in cache blocks. The
	41	legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
	42	between zero and 6192 bytes).
	43
	44	config CAVIUM_OCTEON_LOCK_L2
	45	bool "Lock often used kernel code in the L2"
5b3b1688 DD	46	default "y"
	47	help
	48	Enable locking parts of the kernel into the L2 cache.
	49
	50	config CAVIUM_OCTEON_LOCK_L2_TLB
	51	bool "Lock the TLB handler in L2"
	52	depends on CAVIUM_OCTEON_LOCK_L2
	53	default "y"
	54	help
	55	Lock the low level TLB fast path into L2.
	56
	57	config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
	58	bool "Lock the exception handler in L2"
	59	depends on CAVIUM_OCTEON_LOCK_L2
	60	default "y"
	61	help
	62	Lock the low level exception handler into L2.
	63
	64	config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
	65	bool "Lock the interrupt handler in L2"
	66	depends on CAVIUM_OCTEON_LOCK_L2
	67	default "y"
	68	help
	69	Lock the low level interrupt handler into L2.
	70
	71	config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
	72	bool "Lock the 2nd level interrupt handler in L2"
	73	depends on CAVIUM_OCTEON_LOCK_L2
	74	default "y"
	75	help
	76	Lock the 2nd level interrupt handler in L2.
	77
	78	config CAVIUM_OCTEON_LOCK_L2_MEMCPY
	79	bool "Lock memcpy() in L2"
	80	depends on CAVIUM_OCTEON_LOCK_L2
	81	default "y"
	82	help
	83	Lock the kernel's implementation of memcpy() into L2.
	84
b93b2abc DD	85	config IOMMU_HELPER
	86	bool
	87
	88	config NEED_SG_DMA_LENGTH
	89	bool
	90
	91	config SWIOTLB
	92	def_bool y
b93b2abc DD	93	select IOMMU_HELPER
b93b2abc DD	94	select NEED_SG_DMA_LENGTH
23a271ec DD	95
23a271ec DD	96
0e49caf6 VS	97	config OCTEON_ILM
	98	tristate "Module to measure interrupt latency using Octeon CIU Timer"
	99	help
	100	This driver is a module to measure interrupt latency using the
	101	the CIU Timers on Octeon.
	102
	103	To compile this driver as a module, choose M here. The module
	104	will be called octeon-ilm
	105
23a271ec	106	endif # CPU_CAVIUM_OCTEON