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usb: dwc2: gadget: Add checking for g-tx-fifo-size parameter
[linux.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <[email protected]>,
7 * Sebastian Andrzej Siewior <[email protected]>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd
FB		 38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
911f1f88
PZ		 71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
8598bde7
FB		 87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
aee63e3c 93 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
aee63e3c 97 int retries = 10000;
8598bde7
FB		 98 u32 reg;
99
802fde98
PZ		 100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
8598bde7
FB		 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
802fde98
PZ		 124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
8598bde7 131 /* wait for a change in DSTS */
aed430e5 132 retries = 10000;
8598bde7
FB		 133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
8598bde7
FB		 136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
aee63e3c 139 udelay(5);
8598bde7
FB		 140 }
141
8598bde7
FB		 142 return -ETIMEDOUT;
143}
144
dca0119c
JY		 145/**
146 * dwc3_ep_inc_trb() - Increment a TRB index.
147 * @index - Pointer to the TRB index to increment.
148 *
149 * The index should never point to the link TRB. After incrementing,
150 * if it is point to the link TRB, wrap around to the beginning. The
151 * link TRB is always at the last TRB entry.
152 */
153static void dwc3_ep_inc_trb(u8 *index)
457e84b6 154{
dca0119c
JY		 155 (*index)++;
156 if (*index == (DWC3_TRB_NUM - 1))
157 *index = 0;
ef966b9d 158}
457e84b6 159
dca0119c 160static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
ef966b9d 161{
dca0119c 162 dwc3_ep_inc_trb(&dep->trb_enqueue);
ef966b9d 163}
457e84b6 164
dca0119c 165static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
ef966b9d 166{
dca0119c 167 dwc3_ep_inc_trb(&dep->trb_dequeue);
457e84b6
FB		 168}
169
72246da4
FB		 170void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
171 int status)
172{
173 struct dwc3 *dwc = dep->dwc;
174
737f1ae2 175 req->started = false;
72246da4 176 list_del(&req->list);
eeb720fb 177 req->trb = NULL;
e62c5bc5 178 req->remaining = 0;
72246da4
FB		 179
180 if (req->request.status == -EINPROGRESS)
181 req->request.status = status;
182
d6214592 183 if (dwc->ep0_bounced && dep->number <= 1)
0416e494 184 dwc->ep0_bounced = false;
d6214592
FB		 185
186 usb_gadget_unmap_request_by_dev(dwc->sysdev,
187 &req->request, req->direction);
72246da4 188
2c4cbe6e 189 trace_dwc3_gadget_giveback(req);
72246da4
FB		 190
191 spin_unlock(&dwc->lock);
304f7e5e 192 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4 193 spin_lock(&dwc->lock);
fc8bb91b
FB		 194
195 if (dep->number > 1)
196 pm_runtime_put(dwc->dev);
72246da4
FB		 197}
198
3ece0ec4 199int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 200{
201 u32 timeout = 500;
71f7e702 202 int status = 0;
0fe886cd 203 int ret = 0;
b09bb642
FB		 204 u32 reg;
205
206 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
207 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
208
209 do {
210 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
211 if (!(reg & DWC3_DGCMD_CMDACT)) {
71f7e702
FB		 212 status = DWC3_DGCMD_STATUS(reg);
213 if (status)
0fe886cd
FB		 214 ret = -EINVAL;
215 break;
b09bb642 216 }
e3aee486 217 } while (--timeout);
0fe886cd
FB		 218
219 if (!timeout) {
0fe886cd 220 ret = -ETIMEDOUT;
71f7e702 221 status = -ETIMEDOUT;
0fe886cd
FB		 222 }
223
71f7e702
FB		 224 trace_dwc3_gadget_generic_cmd(cmd, param, status);
225
0fe886cd 226 return ret;
b09bb642
FB		 227}
228
c36d8e94
FB		 229static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
230
2cd4718d
FB		 231int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
232 struct dwc3_gadget_ep_cmd_params *params)
72246da4 233{
8897a761 234 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
2cd4718d 235 struct dwc3 *dwc = dep->dwc;
61d58242 236 u32 timeout = 500;
72246da4
FB		 237 u32 reg;
238
0933df15 239 int cmd_status = 0;
2b0f11df 240 int susphy = false;
c0ca324d 241 int ret = -EINVAL;
72246da4 242
2b0f11df
FB		 243 /*
244 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
245 * we're issuing an endpoint command, we must check if
246 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
247 *
248 * We will also set SUSPHY bit to what it was before returning as stated
249 * by the same section on Synopsys databook.
250 */
ab2a92e7
FB		 251 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
252 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
253 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
254 susphy = true;
255 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
256 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
257 }
2b0f11df
FB		 258 }
259
5999914f 260 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
c36d8e94
FB		 261 int needs_wakeup;
262
263 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
264 dwc->link_state == DWC3_LINK_STATE_U2 ||
265 dwc->link_state == DWC3_LINK_STATE_U3);
266
267 if (unlikely(needs_wakeup)) {
268 ret = __dwc3_gadget_wakeup(dwc);
269 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
270 ret);
271 }
272 }
273
2eb88016
FB		 274 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
275 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
276 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
72246da4 277
8897a761
FB		 278 /*
279 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
280 * not relying on XferNotReady, we can make use of a special "No
281 * Response Update Transfer" command where we should clear both CmdAct
282 * and CmdIOC bits.
283 *
284 * With this, we don't need to wait for command completion and can
285 * straight away issue further commands to the endpoint.
286 *
287 * NOTICE: We're making an assumption that control endpoints will never
288 * make use of Update Transfer command. This is a safe assumption
289 * because we can never have more than one request at a time with
290 * Control Endpoints. If anybody changes that assumption, this chunk
291 * needs to be updated accordingly.
292 */
293 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
294 !usb_endpoint_xfer_isoc(desc))
295 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
296 else
297 cmd |= DWC3_DEPCMD_CMDACT;
298
299 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
72246da4 300 do {
2eb88016 301 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
72246da4 302 if (!(reg & DWC3_DEPCMD_CMDACT)) {
0933df15 303 cmd_status = DWC3_DEPCMD_STATUS(reg);
7b9cc7a2 304
7b9cc7a2
KL		 305 switch (cmd_status) {
306 case 0:
307 ret = 0;
308 break;
309 case DEPEVT_TRANSFER_NO_RESOURCE:
7b9cc7a2 310 ret = -EINVAL;
c0ca324d 311 break;
7b9cc7a2
KL		 312 case DEPEVT_TRANSFER_BUS_EXPIRY:
313 /*
314 * SW issues START TRANSFER command to
315 * isochronous ep with future frame interval. If
316 * future interval time has already passed when
317 * core receives the command, it will respond
318 * with an error status of 'Bus Expiry'.
319 *
320 * Instead of always returning -EINVAL, let's
321 * give a hint to the gadget driver that this is
322 * the case by returning -EAGAIN.
323 */
7b9cc7a2
KL		 324 ret = -EAGAIN;
325 break;
326 default:
327 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
328 }
329
c0ca324d 330 break;
72246da4 331 }
f6bb225b 332 } while (--timeout);
72246da4 333
f6bb225b 334 if (timeout == 0) {
f6bb225b 335 ret = -ETIMEDOUT;
0933df15 336 cmd_status = -ETIMEDOUT;
f6bb225b 337 }
c0ca324d 338
0933df15
FB		 339 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
340
6cb2e4e3
FB		 341 if (ret == 0) {
342 switch (DWC3_DEPCMD_CMD(cmd)) {
343 case DWC3_DEPCMD_STARTTRANSFER:
344 dep->flags |= DWC3_EP_TRANSFER_STARTED;
345 break;
346 case DWC3_DEPCMD_ENDTRANSFER:
347 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
348 break;
349 default:
350 /* nothing */
351 break;
352 }
353 }
354
2b0f11df
FB		 355 if (unlikely(susphy)) {
356 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
357 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
358 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
359 }
360
c0ca324d 361 return ret;
72246da4
FB		 362}
363
50c763f8
JY		 364static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
365{
366 struct dwc3 *dwc = dep->dwc;
367 struct dwc3_gadget_ep_cmd_params params;
368 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
369
370 /*
371 * As of core revision 2.60a the recommended programming model
372 * is to set the ClearPendIN bit when issuing a Clear Stall EP
373 * command for IN endpoints. This is to prevent an issue where
374 * some (non-compliant) hosts may not send ACK TPs for pending
375 * IN transfers due to a mishandled error condition. Synopsys
376 * STAR 9000614252.
377 */
5e6c88d2
LB		 378 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
379 (dwc->gadget.speed >= USB_SPEED_SUPER))
50c763f8
JY		 380 cmd |= DWC3_DEPCMD_CLEARPENDIN;
381
382 memset(&params, 0, sizeof(params));
383
2cd4718d 384 return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
50c763f8
JY		 385}
386
72246da4 387static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 388 struct dwc3_trb *trb)
72246da4 389{
c439ef87 390 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 391
392 return dep->trb_pool_dma + offset;
393}
394
395static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
396{
397 struct dwc3 *dwc = dep->dwc;
398
399 if (dep->trb_pool)
400 return 0;
401
d64ff406 402 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
72246da4
FB		 403 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
404 &dep->trb_pool_dma, GFP_KERNEL);
405 if (!dep->trb_pool) {
406 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
407 dep->name);
408 return -ENOMEM;
409 }
410
411 return 0;
412}
413
414static void dwc3_free_trb_pool(struct dwc3_ep *dep)
415{
416 struct dwc3 *dwc = dep->dwc;
417
d64ff406 418 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
72246da4
FB		 419 dep->trb_pool, dep->trb_pool_dma);
420
421 dep->trb_pool = NULL;
422 dep->trb_pool_dma = 0;
423}
424
c4509601
JY		 425static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
426
427/**
428 * dwc3_gadget_start_config - Configure EP resources
429 * @dwc: pointer to our controller context structure
430 * @dep: endpoint that is being enabled
431 *
432 * The assignment of transfer resources cannot perfectly follow the
433 * data book due to the fact that the controller driver does not have
434 * all knowledge of the configuration in advance. It is given this
435 * information piecemeal by the composite gadget framework after every
436 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
437 * programming model in this scenario can cause errors. For two
438 * reasons:
439 *
440 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
441 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
442 * multiple interfaces.
443 *
444 * 2) The databook does not mention doing more DEPXFERCFG for new
445 * endpoint on alt setting (8.1.6).
446 *
447 * The following simplified method is used instead:
448 *
449 * All hardware endpoints can be assigned a transfer resource and this
450 * setting will stay persistent until either a core reset or
451 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
452 * do DEPXFERCFG for every hardware endpoint as well. We are
453 * guaranteed that there are as many transfer resources as endpoints.
454 *
455 * This function is called for each endpoint when it is being enabled
456 * but is triggered only when called for EP0-out, which always happens
457 * first, and which should only happen in one of the above conditions.
458 */
72246da4
FB		 459static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
460{
461 struct dwc3_gadget_ep_cmd_params params;
462 u32 cmd;
c4509601
JY		 463 int i;
464 int ret;
465
466 if (dep->number)
467 return 0;
72246da4
FB		 468
469 memset(&params, 0x00, sizeof(params));
c4509601 470 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 471
2cd4718d 472 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
c4509601
JY		 473 if (ret)
474 return ret;
475
476 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
477 struct dwc3_ep *dep = dwc->eps[i];
72246da4 478
c4509601
JY		 479 if (!dep)
480 continue;
481
482 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
483 if (ret)
484 return ret;
72246da4
FB		 485 }
486
487 return 0;
488}
489
490static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
21e64bf2 491 bool modify, bool restore)
72246da4 492{
39ebb05c
JY		 493 const struct usb_ss_ep_comp_descriptor *comp_desc;
494 const struct usb_endpoint_descriptor *desc;
72246da4
FB		 495 struct dwc3_gadget_ep_cmd_params params;
496
21e64bf2
FB		 497 if (dev_WARN_ONCE(dwc->dev, modify && restore,
498 "Can't modify and restore\n"))
499 return -EINVAL;
500
39ebb05c
JY		 501 comp_desc = dep->endpoint.comp_desc;
502 desc = dep->endpoint.desc;
503
72246da4
FB		 504 memset(&params, 0x00, sizeof(params));
505
dc1c70a7 506 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 507 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
508
509 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 510 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
676e3497 511 u32 burst = dep->endpoint.maxburst;
676e3497 512 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
d2e9a13a 513 }
72246da4 514
21e64bf2
FB		 515 if (modify) {
516 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
517 } else if (restore) {
265b70a7
PZ		 518 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
519 params.param2 |= dep->saved_state;
21e64bf2
FB		 520 } else {
521 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
265b70a7
PZ		 522 }
523
4bc48c97
FB		 524 if (usb_endpoint_xfer_control(desc))
525 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
13fa2e69
FB		 526
527 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
528 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 529
18b7ede5 530 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 531 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
532 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 533 dep->stream_capable = true;
534 }
535
0b93a4c8 536 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 537 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 538
539 /*
540 * We are doing 1:1 mapping for endpoints, meaning
541 * Physical Endpoints 2 maps to Logical Endpoint 2 and
542 * so on. We consider the direction bit as part of the physical
543 * endpoint number. So USB endpoint 0x81 is 0x03.
544 */
dc1c70a7 545 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 546
547 /*
548 * We must use the lower 16 TX FIFOs even though
549 * HW might have more
550 */
551 if (dep->direction)
dc1c70a7 552 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 553
554 if (desc->bInterval) {
dc1c70a7 555 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 556 dep->interval = 1 << (desc->bInterval - 1);
557 }
558
2cd4718d 559 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
72246da4
FB		 560}
561
562static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
563{
564 struct dwc3_gadget_ep_cmd_params params;
565
566 memset(&params, 0x00, sizeof(params));
567
dc1c70a7 568 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4 569
2cd4718d
FB		 570 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
571 &params);
72246da4
FB		 572}
573
574/**
575 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
576 * @dep: endpoint to be initialized
577 * @desc: USB Endpoint Descriptor
578 *
579 * Caller should take care of locking
580 */
581static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
21e64bf2 582 bool modify, bool restore)
72246da4 583{
39ebb05c 584 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
72246da4 585 struct dwc3 *dwc = dep->dwc;
39ebb05c 586
72246da4 587 u32 reg;
b09e99ee 588 int ret;
72246da4
FB		 589
590 if (!(dep->flags & DWC3_EP_ENABLED)) {
591 ret = dwc3_gadget_start_config(dwc, dep);
592 if (ret)
593 return ret;
594 }
595
39ebb05c 596 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
72246da4
FB		 597 if (ret)
598 return ret;
599
600 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 601 struct dwc3_trb *trb_st_hw;
602 struct dwc3_trb *trb_link;
72246da4 603
72246da4
FB		 604 dep->type = usb_endpoint_type(desc);
605 dep->flags |= DWC3_EP_ENABLED;
76a638f8 606 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
72246da4
FB		 607
608 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
609 reg |= DWC3_DALEPENA_EP(dep->number);
610 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
611
76a638f8
BW		 612 init_waitqueue_head(&dep->wait_end_transfer);
613
36b68aae 614 if (usb_endpoint_xfer_control(desc))
2870e501 615 goto out;
72246da4 616
0d25744a
JY		 617 /* Initialize the TRB ring */
618 dep->trb_dequeue = 0;
619 dep->trb_enqueue = 0;
620 memset(dep->trb_pool, 0,
621 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
622
36b68aae 623 /* Link TRB. The HWO bit is never reset */
72246da4
FB		 624 trb_st_hw = &dep->trb_pool[0];
625
f6bafc6a 626 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
f6bafc6a
FB		 627 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
628 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
629 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
630 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 631 }
632
a97ea994
FB		 633 /*
634 * Issue StartTransfer here with no-op TRB so we can always rely on No
635 * Response Update Transfer command.
636 */
637 if (usb_endpoint_xfer_bulk(desc)) {
638 struct dwc3_gadget_ep_cmd_params params;
639 struct dwc3_trb *trb;
640 dma_addr_t trb_dma;
641 u32 cmd;
642
643 memset(&params, 0, sizeof(params));
644 trb = &dep->trb_pool[0];
645 trb_dma = dwc3_trb_dma_offset(dep, trb);
646
647 params.param0 = upper_32_bits(trb_dma);
648 params.param1 = lower_32_bits(trb_dma);
649
650 cmd = DWC3_DEPCMD_STARTTRANSFER;
651
652 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
653 if (ret < 0)
654 return ret;
655
656 dep->flags |= DWC3_EP_BUSY;
657
658 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
659 WARN_ON_ONCE(!dep->resource_index);
660 }
661
2870e501
FB		 662
663out:
664 trace_dwc3_gadget_ep_enable(dep);
665
72246da4
FB		 666 return 0;
667}
668
b992e681 669static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 670static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 671{
672 struct dwc3_request *req;
673
0e146028 674 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 675
0e146028
FB		 676 /* - giveback all requests to gadget driver */
677 while (!list_empty(&dep->started_list)) {
678 req = next_request(&dep->started_list);
1591633e 679
0e146028 680 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
ea53b882
FB		 681 }
682
aa3342c8
FB		 683 while (!list_empty(&dep->pending_list)) {
684 req = next_request(&dep->pending_list);
72246da4 685
624407f9 686 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 687 }
72246da4
FB		 688}
689
690/**
691 * __dwc3_gadget_ep_disable - Disables a HW endpoint
692 * @dep: the endpoint to disable
693 *
624407f9
SAS		 694 * This function also removes requests which are currently processed ny the
695 * hardware and those which are not yet scheduled.
696 * Caller should take care of locking.
72246da4 697 */
72246da4
FB		 698static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
699{
700 struct dwc3 *dwc = dep->dwc;
701 u32 reg;
702
2870e501 703 trace_dwc3_gadget_ep_disable(dep);
7eaeac5c 704
624407f9 705 dwc3_remove_requests(dwc, dep);
72246da4 706
687ef981
FB		 707 /* make sure HW endpoint isn't stalled */
708 if (dep->flags & DWC3_EP_STALL)
7a608559 709 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 710
72246da4
FB		 711 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
712 reg &= ~DWC3_DALEPENA_EP(dep->number);
713 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
714
879631aa 715 dep->stream_capable = false;
72246da4 716 dep->type = 0;
76a638f8 717 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
72246da4 718
39ebb05c
JY		 719 /* Clear out the ep descriptors for non-ep0 */
720 if (dep->number > 1) {
721 dep->endpoint.comp_desc = NULL;
722 dep->endpoint.desc = NULL;
723 }
724
72246da4
FB		 725 return 0;
726}
727
728/* -------------------------------------------------------------------------- */
729
730static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
731 const struct usb_endpoint_descriptor *desc)
732{
733 return -EINVAL;
734}
735
736static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
737{
738 return -EINVAL;
739}
740
741/* -------------------------------------------------------------------------- */
742
743static int dwc3_gadget_ep_enable(struct usb_ep *ep,
744 const struct usb_endpoint_descriptor *desc)
745{
746 struct dwc3_ep *dep;
747 struct dwc3 *dwc;
748 unsigned long flags;
749 int ret;
750
751 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
752 pr_debug("dwc3: invalid parameters\n");
753 return -EINVAL;
754 }
755
756 if (!desc->wMaxPacketSize) {
757 pr_debug("dwc3: missing wMaxPacketSize\n");
758 return -EINVAL;
759 }
760
761 dep = to_dwc3_ep(ep);
762 dwc = dep->dwc;
763
95ca961c
FB		 764 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
765 "%s is already enabled\n",
766 dep->name))
c6f83f38 767 return 0;
c6f83f38 768
72246da4 769 spin_lock_irqsave(&dwc->lock, flags);
39ebb05c 770 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 771 spin_unlock_irqrestore(&dwc->lock, flags);
772
773 return ret;
774}
775
776static int dwc3_gadget_ep_disable(struct usb_ep *ep)
777{
778 struct dwc3_ep *dep;
779 struct dwc3 *dwc;
780 unsigned long flags;
781 int ret;
782
783 if (!ep) {
784 pr_debug("dwc3: invalid parameters\n");
785 return -EINVAL;
786 }
787
788 dep = to_dwc3_ep(ep);
789 dwc = dep->dwc;
790
95ca961c
FB		 791 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
792 "%s is already disabled\n",
793 dep->name))
72246da4 794 return 0;
72246da4 795
72246da4
FB		 796 spin_lock_irqsave(&dwc->lock, flags);
797 ret = __dwc3_gadget_ep_disable(dep);
798 spin_unlock_irqrestore(&dwc->lock, flags);
799
800 return ret;
801}
802
803static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
804 gfp_t gfp_flags)
805{
806 struct dwc3_request *req;
807 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 808
809 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 810 if (!req)
72246da4 811 return NULL;
72246da4
FB		 812
813 req->epnum = dep->number;
814 req->dep = dep;
72246da4 815
68d34c8a
FB		 816 dep->allocated_requests++;
817
2c4cbe6e
FB		 818 trace_dwc3_alloc_request(req);
819
72246da4
FB		 820 return &req->request;
821}
822
823static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
824 struct usb_request *request)
825{
826 struct dwc3_request *req = to_dwc3_request(request);
68d34c8a 827 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4 828
68d34c8a 829 dep->allocated_requests--;
2c4cbe6e 830 trace_dwc3_free_request(req);
72246da4
FB		 831 kfree(req);
832}
833
2c78c029
FB		 834static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
835
e49d3cf4
FB		 836static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
837 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
838 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
c71fc37c 839{
6b9018d4
FB		 840 struct dwc3 *dwc = dep->dwc;
841 struct usb_gadget *gadget = &dwc->gadget;
842 enum usb_device_speed speed = gadget->speed;
c71fc37c 843
ef966b9d 844 dwc3_ep_inc_enq(dep);
e5ba5ec8 845
f6bafc6a
FB		 846 trb->size = DWC3_TRB_SIZE_LENGTH(length);
847 trb->bpl = lower_32_bits(dma);
848 trb->bph = upper_32_bits(dma);
c71fc37c 849
16e78db7 850 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 851 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 852 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 853 break;
854
855 case USB_ENDPOINT_XFER_ISOC:
6b9018d4 856 if (!node) {
e5ba5ec8 857 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
6b9018d4
FB		 858
859 if (speed == USB_SPEED_HIGH) {
860 struct usb_ep *ep = &dep->endpoint;
861 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
862 }
863 } else {
e5ba5ec8 864 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
6b9018d4 865 }
ca4d44ea
FB		 866
867 /* always enable Interrupt on Missed ISOC */
868 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
c71fc37c
FB		 869 break;
870
871 case USB_ENDPOINT_XFER_BULK:
872 case USB_ENDPOINT_XFER_INT:
f6bafc6a 873 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 874 break;
875 default:
876 /*
877 * This is only possible with faulty memory because we
878 * checked it already :)
879 */
0a695d4c
FB		 880 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
881 usb_endpoint_type(dep->endpoint.desc));
c71fc37c
FB		 882 }
883
ca4d44ea 884 /* always enable Continue on Short Packet */
c9508c8c 885 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
58f29034 886 trb->ctrl |= DWC3_TRB_CTRL_CSP;
f3af3651 887
e49d3cf4 888 if (short_not_ok)
c9508c8c
FB		 889 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
890 }
891
e49d3cf4 892 if ((!no_interrupt && !chain) ||
2c78c029 893 (dwc3_calc_trbs_left(dep) == 0))
c9508c8c 894 trb->ctrl |= DWC3_TRB_CTRL_IOC;
f3af3651 895
e5ba5ec8
PA		 896 if (chain)
897 trb->ctrl |= DWC3_TRB_CTRL_CHN;
898
16e78db7 899 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
e49d3cf4 900 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
c71fc37c 901
f6bafc6a 902 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e
FB		 903
904 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 905}
906
e49d3cf4
FB		 907/**
908 * dwc3_prepare_one_trb - setup one TRB from one request
909 * @dep: endpoint for which this request is prepared
910 * @req: dwc3_request pointer
911 * @chain: should this TRB be chained to the next?
912 * @node: only for isochronous endpoints. First TRB needs different type.
913 */
914static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
915 struct dwc3_request *req, unsigned chain, unsigned node)
916{
917 struct dwc3_trb *trb;
918 unsigned length = req->request.length;
919 unsigned stream_id = req->request.stream_id;
920 unsigned short_not_ok = req->request.short_not_ok;
921 unsigned no_interrupt = req->request.no_interrupt;
922 dma_addr_t dma = req->request.dma;
923
924 trb = &dep->trb_pool[dep->trb_enqueue];
925
926 if (!req->trb) {
927 dwc3_gadget_move_started_request(req);
928 req->trb = trb;
929 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
930 dep->queued_requests++;
931 }
932
933 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
934 stream_id, short_not_ok, no_interrupt);
935}
936
361572b5
JY		 937/**
938 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
939 * @dep: The endpoint with the TRB ring
940 * @index: The index of the current TRB in the ring
941 *
942 * Returns the TRB prior to the one pointed to by the index. If the
943 * index is 0, we will wrap backwards, skip the link TRB, and return
944 * the one just before that.
945 */
946static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
947{
45438a0c 948 u8 tmp = index;
361572b5 949
45438a0c
FB		 950 if (!tmp)
951 tmp = DWC3_TRB_NUM - 1;
361572b5 952
45438a0c 953 return &dep->trb_pool[tmp - 1];
361572b5
JY		 954}
955
c4233573
FB		 956static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
957{
958 struct dwc3_trb *tmp;
f2694a93 959 struct dwc3 *dwc = dep->dwc;
32db3d94 960 u8 trbs_left;
c4233573
FB		 961
962 /*
963 * If enqueue & dequeue are equal than it is either full or empty.
964 *
965 * One way to know for sure is if the TRB right before us has HWO bit
966 * set or not. If it has, then we're definitely full and can't fit any
967 * more transfers in our ring.
968 */
969 if (dep->trb_enqueue == dep->trb_dequeue) {
361572b5 970 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
f2694a93
JD		 971 if (dev_WARN_ONCE(dwc->dev, tmp->ctrl & DWC3_TRB_CTRL_HWO,
972 "%s No TRBS left\n", dep->name))
361572b5 973 return 0;
c4233573
FB		 974
975 return DWC3_TRB_NUM - 1;
976 }
977
9d7aba77 978 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
3de2685f 979 trbs_left &= (DWC3_TRB_NUM - 1);
32db3d94 980
9d7aba77
JY		 981 if (dep->trb_dequeue < dep->trb_enqueue)
982 trbs_left--;
983
32db3d94 984 return trbs_left;
c4233573
FB		 985}
986
5ee85d89 987static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
7ae7df49 988 struct dwc3_request *req)
5ee85d89 989{
1f512119 990 struct scatterlist *sg = req->sg;
5ee85d89 991 struct scatterlist *s;
5ee85d89
FB		 992 int i;
993
1f512119 994 for_each_sg(sg, s, req->num_pending_sgs, i) {
c6267a51
FB		 995 unsigned int length = req->request.length;
996 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
997 unsigned int rem = length % maxp;
5ee85d89
FB		 998 unsigned chain = true;
999
4bc48c97 1000 if (sg_is_last(s))
5ee85d89
FB		 1001 chain = false;
1002
c6267a51
FB		 1003 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1004 struct dwc3 *dwc = dep->dwc;
1005 struct dwc3_trb *trb;
1006
1007 req->unaligned = true;
1008
1009 /* prepare normal TRB */
1010 dwc3_prepare_one_trb(dep, req, true, i);
1011
1012 /* Now prepare one extra TRB to align transfer size */
1013 trb = &dep->trb_pool[dep->trb_enqueue];
1014 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1015 maxp - rem, false, 0,
1016 req->request.stream_id,
1017 req->request.short_not_ok,
1018 req->request.no_interrupt);
1019 } else {
1020 dwc3_prepare_one_trb(dep, req, chain, i);
1021 }
5ee85d89 1022
7ae7df49 1023 if (!dwc3_calc_trbs_left(dep))
5ee85d89
FB		 1024 break;
1025 }
1026}
1027
1028static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
7ae7df49 1029 struct dwc3_request *req)
5ee85d89 1030{
c6267a51
FB		 1031 unsigned int length = req->request.length;
1032 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1033 unsigned int rem = length % maxp;
1034
1035 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1036 struct dwc3 *dwc = dep->dwc;
1037 struct dwc3_trb *trb;
1038
1039 req->unaligned = true;
1040
1041 /* prepare normal TRB */
1042 dwc3_prepare_one_trb(dep, req, true, 0);
1043
1044 /* Now prepare one extra TRB to align transfer size */
1045 trb = &dep->trb_pool[dep->trb_enqueue];
1046 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1047 false, 0, req->request.stream_id,
1048 req->request.short_not_ok,
1049 req->request.no_interrupt);
1050 } else {
1051 dwc3_prepare_one_trb(dep, req, false, 0);
1052 }
5ee85d89
FB		 1053}
1054
72246da4
FB		 1055/*
1056 * dwc3_prepare_trbs - setup TRBs from requests
1057 * @dep: endpoint for which requests are being prepared
72246da4 1058 *
1d046793
PZ		 1059 * The function goes through the requests list and sets up TRBs for the
1060 * transfers. The function returns once there are no more TRBs available or
1061 * it runs out of requests.
72246da4 1062 */
c4233573 1063static void dwc3_prepare_trbs(struct dwc3_ep *dep)
72246da4 1064{
68e823e2 1065 struct dwc3_request *req, *n;
72246da4
FB		 1066
1067 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1068
7ae7df49 1069 if (!dwc3_calc_trbs_left(dep))
89bc856e 1070 return;
72246da4 1071
d86c5a67
FB		 1072 /*
1073 * We can get in a situation where there's a request in the started list
1074 * but there weren't enough TRBs to fully kick it in the first time
1075 * around, so it has been waiting for more TRBs to be freed up.
1076 *
1077 * In that case, we should check if we have a request with pending_sgs
1078 * in the started list and prepare TRBs for that request first,
1079 * otherwise we will prepare TRBs completely out of order and that will
1080 * break things.
1081 */
1082 list_for_each_entry(req, &dep->started_list, list) {
1083 if (req->num_pending_sgs > 0)
1084 dwc3_prepare_one_trb_sg(dep, req);
1085
1086 if (!dwc3_calc_trbs_left(dep))
1087 return;
1088 }
1089
aa3342c8 1090 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1f512119 1091 if (req->num_pending_sgs > 0)
7ae7df49 1092 dwc3_prepare_one_trb_sg(dep, req);
5ee85d89 1093 else
7ae7df49 1094 dwc3_prepare_one_trb_linear(dep, req);
72246da4 1095
7ae7df49 1096 if (!dwc3_calc_trbs_left(dep))
5ee85d89 1097 return;
72246da4 1098 }
72246da4
FB		 1099}
1100
4fae2e3e 1101static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
72246da4
FB		 1102{
1103 struct dwc3_gadget_ep_cmd_params params;
1104 struct dwc3_request *req;
4fae2e3e 1105 int starting;
72246da4
FB		 1106 int ret;
1107 u32 cmd;
1108
4fae2e3e 1109 starting = !(dep->flags & DWC3_EP_BUSY);
72246da4 1110
4fae2e3e
FB		 1111 dwc3_prepare_trbs(dep);
1112 req = next_request(&dep->started_list);
72246da4
FB		 1113 if (!req) {
1114 dep->flags |= DWC3_EP_PENDING_REQUEST;
1115 return 0;
1116 }
1117
1118 memset(&params, 0, sizeof(params));
72246da4 1119
4fae2e3e 1120 if (starting) {
1877d6c9
PA		 1121 params.param0 = upper_32_bits(req->trb_dma);
1122 params.param1 = lower_32_bits(req->trb_dma);
b6b1c6db
FB		 1123 cmd = DWC3_DEPCMD_STARTTRANSFER |
1124 DWC3_DEPCMD_PARAM(cmd_param);
1877d6c9 1125 } else {
b6b1c6db
FB		 1126 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1127 DWC3_DEPCMD_PARAM(dep->resource_index);
1877d6c9 1128 }
72246da4 1129
2cd4718d 1130 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
72246da4 1131 if (ret < 0) {
72246da4
FB		 1132 /*
1133 * FIXME we need to iterate over the list of requests
1134 * here and stop, unmap, free and del each of the linked
1d046793 1135 * requests instead of what we do now.
72246da4 1136 */
ce3fc8b3
JD		 1137 if (req->trb)
1138 memset(req->trb, 0, sizeof(struct dwc3_trb));
8ab89da4 1139 dep->queued_requests--;
15b8d933 1140 dwc3_gadget_giveback(dep, req, ret);
72246da4
FB		 1141 return ret;
1142 }
1143
1144 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1145
4fae2e3e 1146 if (starting) {
2eb88016 1147 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
b4996a86 1148 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1149 }
25b8ff68 1150
72246da4
FB		 1151 return 0;
1152}
1153
6cb2e4e3
FB		 1154static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1155{
1156 u32 reg;
1157
1158 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1159 return DWC3_DSTS_SOFFN(reg);
1160}
1161
d6d6ec7b
PA		 1162static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1163 struct dwc3_ep *dep, u32 cur_uf)
1164{
1165 u32 uf;
1166
aa3342c8 1167 if (list_empty(&dep->pending_list)) {
5eb30ced 1168 dev_info(dwc->dev, "%s: ran out of requests\n",
73815280 1169 dep->name);
f4a53c55 1170 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1171 return;
1172 }
1173
1174 /* 4 micro frames in the future */
1175 uf = cur_uf + dep->interval * 4;
1176
4fae2e3e 1177 __dwc3_gadget_kick_transfer(dep, uf);
d6d6ec7b
PA		 1178}
1179
1180static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1181 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1182{
1183 u32 cur_uf, mask;
1184
1185 mask = ~(dep->interval - 1);
1186 cur_uf = event->parameters & mask;
1187
1188 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1189}
1190
72246da4
FB		 1191static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1192{
0fc9a1be
FB		 1193 struct dwc3 *dwc = dep->dwc;
1194 int ret;
1195
bb423984 1196 if (!dep->endpoint.desc) {
5eb30ced
FB		 1197 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1198 dep->name);
bb423984
FB		 1199 return -ESHUTDOWN;
1200 }
1201
1202 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1203 &req->request, req->dep->name)) {
5eb30ced
FB		 1204 dev_err(dwc->dev, "%s: request %p belongs to '%s'\n",
1205 dep->name, &req->request, req->dep->name);
bb423984
FB		 1206 return -EINVAL;
1207 }
1208
fc8bb91b
FB		 1209 pm_runtime_get(dwc->dev);
1210
72246da4
FB		 1211 req->request.actual = 0;
1212 req->request.status = -EINPROGRESS;
1213 req->direction = dep->direction;
1214 req->epnum = dep->number;
1215
fe84f522
FB		 1216 trace_dwc3_ep_queue(req);
1217
d64ff406
AB		 1218 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1219 dep->direction);
0fc9a1be
FB		 1220 if (ret)
1221 return ret;
1222
1f512119
FB		 1223 req->sg = req->request.sg;
1224 req->num_pending_sgs = req->request.num_mapped_sgs;
89185916 1225
aa3342c8 1226 list_add_tail(&req->list, &dep->pending_list);
72246da4 1227
d889c23c
FB		 1228 /*
1229 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1230 * wait for a XferNotReady event so we will know what's the current
1231 * (micro-)frame number.
1232 *
1233 * Without this trick, we are very, very likely gonna get Bus Expiry
1234 * errors which will force us issue EndTransfer command.
1235 */
1236 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
6cb2e4e3
FB		 1237 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1238 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1239 dwc3_stop_active_transfer(dwc, dep->number, true);
1240 dep->flags = DWC3_EP_ENABLED;
1241 } else {
1242 u32 cur_uf;
1243
1244 cur_uf = __dwc3_gadget_get_frame(dwc);
1245 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
87aba106 1246 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
6cb2e4e3 1247 }
08a36b54
FB		 1248 }
1249 return 0;
a0925324 1250 }
72246da4 1251
594e121f
FB		 1252 if (!dwc3_calc_trbs_left(dep))
1253 return 0;
b997ada5 1254
08a36b54 1255 ret = __dwc3_gadget_kick_transfer(dep, 0);
a8f32817
FB		 1256 if (ret == -EBUSY)
1257 ret = 0;
1258
1259 return ret;
72246da4
FB		 1260}
1261
04c03d10
FB		 1262static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1263 struct usb_request *request)
1264{
1265 dwc3_gadget_ep_free_request(ep, request);
1266}
1267
1268static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1269{
1270 struct dwc3_request *req;
1271 struct usb_request *request;
1272 struct usb_ep *ep = &dep->endpoint;
1273
04c03d10
FB		 1274 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1275 if (!request)
1276 return -ENOMEM;
1277
1278 request->length = 0;
1279 request->buf = dwc->zlp_buf;
1280 request->complete = __dwc3_gadget_ep_zlp_complete;
1281
1282 req = to_dwc3_request(request);
1283
1284 return __dwc3_gadget_ep_queue(dep, req);
1285}
1286
72246da4
FB		 1287static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1288 gfp_t gfp_flags)
1289{
1290 struct dwc3_request *req = to_dwc3_request(request);
1291 struct dwc3_ep *dep = to_dwc3_ep(ep);
1292 struct dwc3 *dwc = dep->dwc;
1293
1294 unsigned long flags;
1295
1296 int ret;
1297
fdee4eba 1298 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1299 ret = __dwc3_gadget_ep_queue(dep, req);
04c03d10
FB		 1300
1301 /*
1302 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1303 * setting request->zero, instead of doing magic, we will just queue an
1304 * extra usb_request ourselves so that it gets handled the same way as
1305 * any other request.
1306 */
d9261898
JY		 1307 if (ret == 0 && request->zero && request->length &&
1308 (request->length % ep->maxpacket == 0))
04c03d10
FB		 1309 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1310
72246da4
FB		 1311 spin_unlock_irqrestore(&dwc->lock, flags);
1312
1313 return ret;
1314}
1315
1316static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1317 struct usb_request *request)
1318{
1319 struct dwc3_request *req = to_dwc3_request(request);
1320 struct dwc3_request *r = NULL;
1321
1322 struct dwc3_ep *dep = to_dwc3_ep(ep);
1323 struct dwc3 *dwc = dep->dwc;
1324
1325 unsigned long flags;
1326 int ret = 0;
1327
2c4cbe6e
FB		 1328 trace_dwc3_ep_dequeue(req);
1329
72246da4
FB		 1330 spin_lock_irqsave(&dwc->lock, flags);
1331
aa3342c8 1332 list_for_each_entry(r, &dep->pending_list, list) {
72246da4
FB		 1333 if (r == req)
1334 break;
1335 }
1336
1337 if (r != req) {
aa3342c8 1338 list_for_each_entry(r, &dep->started_list, list) {
72246da4
FB		 1339 if (r == req)
1340 break;
1341 }
1342 if (r == req) {
1343 /* wait until it is processed */
b992e681 1344 dwc3_stop_active_transfer(dwc, dep->number, true);
e8d4e8be 1345 goto out1;
72246da4
FB		 1346 }
1347 dev_err(dwc->dev, "request %p was not queued to %s\n",
1348 request, ep->name);
1349 ret = -EINVAL;
1350 goto out0;
1351 }
1352
e8d4e8be 1353out1:
72246da4
FB		 1354 /* giveback the request */
1355 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1356
1357out0:
1358 spin_unlock_irqrestore(&dwc->lock, flags);
1359
1360 return ret;
1361}
1362
7a608559 1363int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1364{
1365 struct dwc3_gadget_ep_cmd_params params;
1366 struct dwc3 *dwc = dep->dwc;
1367 int ret;
1368
5ad02fb8
FB		 1369 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1370 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1371 return -EINVAL;
1372 }
1373
72246da4
FB		 1374 memset(&params, 0x00, sizeof(params));
1375
1376 if (value) {
69450c4d
FB		 1377 struct dwc3_trb *trb;
1378
1379 unsigned transfer_in_flight;
1380 unsigned started;
1381
ffb80fc6
FB		 1382 if (dep->flags & DWC3_EP_STALL)
1383 return 0;
1384
69450c4d
FB		 1385 if (dep->number > 1)
1386 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1387 else
1388 trb = &dwc->ep0_trb[dep->trb_enqueue];
1389
1390 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1391 started = !list_empty(&dep->started_list);
1392
1393 if (!protocol && ((dep->direction && transfer_in_flight) ||
1394 (!dep->direction && started))) {
7a608559
FB		 1395 return -EAGAIN;
1396 }
1397
2cd4718d
FB		 1398 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1399 &params);
72246da4 1400 if (ret)
3f89204b 1401 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1402 dep->name);
1403 else
1404 dep->flags |= DWC3_EP_STALL;
1405 } else {
ffb80fc6
FB		 1406 if (!(dep->flags & DWC3_EP_STALL))
1407 return 0;
2cd4718d 1408
50c763f8 1409 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4 1410 if (ret)
3f89204b 1411 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1412 dep->name);
1413 else
a535d81c 1414 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1415 }
5275455a 1416
72246da4
FB		 1417 return ret;
1418}
1419
1420static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1421{
1422 struct dwc3_ep *dep = to_dwc3_ep(ep);
1423 struct dwc3 *dwc = dep->dwc;
1424
1425 unsigned long flags;
1426
1427 int ret;
1428
1429 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1430 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1431 spin_unlock_irqrestore(&dwc->lock, flags);
1432
1433 return ret;
1434}
1435
1436static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1437{
1438 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1439 struct dwc3 *dwc = dep->dwc;
1440 unsigned long flags;
95aa4e8d 1441 int ret;
72246da4 1442
249a4569 1443 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1444 dep->flags |= DWC3_EP_WEDGE;
1445
08f0d966 1446 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1447 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1448 else
7a608559 1449 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1450 spin_unlock_irqrestore(&dwc->lock, flags);
1451
1452 return ret;
72246da4
FB		 1453}
1454
1455/* -------------------------------------------------------------------------- */
1456
1457static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1458 .bLength = USB_DT_ENDPOINT_SIZE,
1459 .bDescriptorType = USB_DT_ENDPOINT,
1460 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1461};
1462
1463static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1464 .enable = dwc3_gadget_ep0_enable,
1465 .disable = dwc3_gadget_ep0_disable,
1466 .alloc_request = dwc3_gadget_ep_alloc_request,
1467 .free_request = dwc3_gadget_ep_free_request,
1468 .queue = dwc3_gadget_ep0_queue,
1469 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1470 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1471 .set_wedge = dwc3_gadget_ep_set_wedge,
1472};
1473
1474static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1475 .enable = dwc3_gadget_ep_enable,
1476 .disable = dwc3_gadget_ep_disable,
1477 .alloc_request = dwc3_gadget_ep_alloc_request,
1478 .free_request = dwc3_gadget_ep_free_request,
1479 .queue = dwc3_gadget_ep_queue,
1480 .dequeue = dwc3_gadget_ep_dequeue,
1481 .set_halt = dwc3_gadget_ep_set_halt,
1482 .set_wedge = dwc3_gadget_ep_set_wedge,
1483};
1484
1485/* -------------------------------------------------------------------------- */
1486
1487static int dwc3_gadget_get_frame(struct usb_gadget *g)
1488{
1489 struct dwc3 *dwc = gadget_to_dwc(g);
72246da4 1490
6cb2e4e3 1491 return __dwc3_gadget_get_frame(dwc);
72246da4
FB		 1492}
1493
218ef7b6 1494static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
72246da4 1495{
d6011f6f 1496 int retries;
72246da4 1497
218ef7b6 1498 int ret;
72246da4
FB		 1499 u32 reg;
1500
72246da4
FB		 1501 u8 link_state;
1502 u8 speed;
1503
72246da4
FB		 1504 /*
1505 * According to the Databook Remote wakeup request should
1506 * be issued only when the device is in early suspend state.
1507 *
1508 * We can check that via USB Link State bits in DSTS register.
1509 */
1510 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1511
1512 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c 1513 if ((speed == DWC3_DSTS_SUPERSPEED) ||
5eb30ced 1514 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
6b742899 1515 return 0;
72246da4
FB		 1516
1517 link_state = DWC3_DSTS_USBLNKST(reg);
1518
1519 switch (link_state) {
1520 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1521 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1522 break;
1523 default:
218ef7b6 1524 return -EINVAL;
72246da4
FB		 1525 }
1526
8598bde7
FB		 1527 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1528 if (ret < 0) {
1529 dev_err(dwc->dev, "failed to put link in Recovery\n");
218ef7b6 1530 return ret;
8598bde7 1531 }
72246da4 1532
802fde98
PZ		 1533 /* Recent versions do this automatically */
1534 if (dwc->revision < DWC3_REVISION_194A) {
1535 /* write zeroes to Link Change Request */
fcc023c7 1536 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1537 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1538 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1539 }
72246da4 1540
1d046793 1541 /* poll until Link State changes to ON */
d6011f6f 1542 retries = 20000;
72246da4 1543
d6011f6f 1544 while (retries--) {
72246da4
FB		 1545 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1546
1547 /* in HS, means ON */
1548 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1549 break;
1550 }
1551
1552 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1553 dev_err(dwc->dev, "failed to send remote wakeup\n");
218ef7b6 1554 return -EINVAL;
72246da4
FB		 1555 }
1556
218ef7b6
FB		 1557 return 0;
1558}
1559
1560static int dwc3_gadget_wakeup(struct usb_gadget *g)
1561{
1562 struct dwc3 *dwc = gadget_to_dwc(g);
1563 unsigned long flags;
1564 int ret;
1565
1566 spin_lock_irqsave(&dwc->lock, flags);
1567 ret = __dwc3_gadget_wakeup(dwc);
72246da4
FB		 1568 spin_unlock_irqrestore(&dwc->lock, flags);
1569
1570 return ret;
1571}
1572
1573static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1574 int is_selfpowered)
1575{
1576 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1577 unsigned long flags;
72246da4 1578
249a4569 1579 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1580 g->is_selfpowered = !!is_selfpowered;
249a4569 1581 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1582
1583 return 0;
1584}
1585
7b2a0368 1586static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1587{
1588 u32 reg;
61d58242 1589 u32 timeout = 500;
72246da4 1590
fc8bb91b
FB		 1591 if (pm_runtime_suspended(dwc->dev))
1592 return 0;
1593
72246da4 1594 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1595 if (is_on) {
802fde98
PZ		 1596 if (dwc->revision <= DWC3_REVISION_187A) {
1597 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1598 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1599 }
1600
1601 if (dwc->revision >= DWC3_REVISION_194A)
1602 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1603 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1604
1605 if (dwc->has_hibernation)
1606 reg |= DWC3_DCTL_KEEP_CONNECT;
1607
9fcb3bd8 1608 dwc->pullups_connected = true;
8db7ed15 1609 } else {
72246da4 1610 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1611
1612 if (dwc->has_hibernation && !suspend)
1613 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1614
9fcb3bd8 1615 dwc->pullups_connected = false;
8db7ed15 1616 }
72246da4
FB		 1617
1618 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1619
1620 do {
1621 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
b6d4e16e
FB		 1622 reg &= DWC3_DSTS_DEVCTRLHLT;
1623 } while (--timeout && !(!is_on ^ !reg));
f2df679b
FB		 1624
1625 if (!timeout)
1626 return -ETIMEDOUT;
72246da4 1627
6f17f74b 1628 return 0;
72246da4
FB		 1629}
1630
1631static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1632{
1633 struct dwc3 *dwc = gadget_to_dwc(g);
1634 unsigned long flags;
6f17f74b 1635 int ret;
72246da4
FB		 1636
1637 is_on = !!is_on;
1638
bb014736
BW		 1639 /*
1640 * Per databook, when we want to stop the gadget, if a control transfer
1641 * is still in process, complete it and get the core into setup phase.
1642 */
1643 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1644 reinit_completion(&dwc->ep0_in_setup);
1645
1646 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1647 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1648 if (ret == 0) {
1649 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1650 return -ETIMEDOUT;
1651 }
1652 }
1653
72246da4 1654 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1655 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1656 spin_unlock_irqrestore(&dwc->lock, flags);
1657
6f17f74b 1658 return ret;
72246da4
FB		 1659}
1660
8698e2ac
FB		 1661static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1662{
1663 u32 reg;
1664
1665 /* Enable all but Start and End of Frame IRQs */
1666 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1667 DWC3_DEVTEN_EVNTOVERFLOWEN |
1668 DWC3_DEVTEN_CMDCMPLTEN |
1669 DWC3_DEVTEN_ERRTICERREN |
1670 DWC3_DEVTEN_WKUPEVTEN |
8698e2ac
FB		 1671 DWC3_DEVTEN_CONNECTDONEEN |
1672 DWC3_DEVTEN_USBRSTEN |
1673 DWC3_DEVTEN_DISCONNEVTEN);
1674
799e9dc8
FB		 1675 if (dwc->revision < DWC3_REVISION_250A)
1676 reg |= DWC3_DEVTEN_ULSTCNGEN;
1677
8698e2ac
FB		 1678 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1679}
1680
1681static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1682{
1683 /* mask all interrupts */
1684 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1685}
1686
1687static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1688static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1689
4e99472b
FB		 1690/**
1691 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1692 * dwc: pointer to our context structure
1693 *
1694 * The following looks like complex but it's actually very simple. In order to
1695 * calculate the number of packets we can burst at once on OUT transfers, we're
1696 * gonna use RxFIFO size.
1697 *
1698 * To calculate RxFIFO size we need two numbers:
1699 * MDWIDTH = size, in bits, of the internal memory bus
1700 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1701 *
1702 * Given these two numbers, the formula is simple:
1703 *
1704 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1705 *
1706 * 24 bytes is for 3x SETUP packets
1707 * 16 bytes is a clock domain crossing tolerance
1708 *
1709 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1710 */
1711static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1712{
1713 u32 ram2_depth;
1714 u32 mdwidth;
1715 u32 nump;
1716 u32 reg;
1717
1718 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1719 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1720
1721 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1722 nump = min_t(u32, nump, 16);
1723
1724 /* update NumP */
1725 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1726 reg &= ~DWC3_DCFG_NUMP_MASK;
1727 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1728 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1729}
1730
d7be2952 1731static int __dwc3_gadget_start(struct dwc3 *dwc)
72246da4 1732{
72246da4 1733 struct dwc3_ep *dep;
72246da4
FB		 1734 int ret = 0;
1735 u32 reg;
1736
cf40b86b
JY		 1737 /*
1738 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1739 * the core supports IMOD, disable it.
1740 */
1741 if (dwc->imod_interval) {
1742 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1743 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1744 } else if (dwc3_has_imod(dwc)) {
1745 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1746 }
1747
72246da4
FB		 1748 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1749 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1750
1751 /**
1752 * WORKAROUND: DWC3 revision < 2.20a have an issue
1753 * which would cause metastability state on Run/Stop
1754 * bit if we try to force the IP to USB2-only mode.
1755 *
1756 * Because of that, we cannot configure the IP to any
1757 * speed other than the SuperSpeed
1758 *
1759 * Refers to:
1760 *
1761 * STAR#9000525659: Clock Domain Crossing on DCTL in
1762 * USB 2.0 Mode
1763 */
f7e846f0 1764 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1765 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1766 } else {
1767 switch (dwc->maximum_speed) {
1768 case USB_SPEED_LOW:
2da9ad76 1769 reg |= DWC3_DCFG_LOWSPEED;
f7e846f0
FB		 1770 break;
1771 case USB_SPEED_FULL:
9418ee15 1772 reg |= DWC3_DCFG_FULLSPEED;
f7e846f0
FB		 1773 break;
1774 case USB_SPEED_HIGH:
2da9ad76 1775 reg |= DWC3_DCFG_HIGHSPEED;
f7e846f0 1776 break;
7580862b 1777 case USB_SPEED_SUPER_PLUS:
2da9ad76 1778 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
7580862b 1779 break;
f7e846f0 1780 default:
77966eb8
JY		 1781 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1782 dwc->maximum_speed);
1783 /* fall through */
1784 case USB_SPEED_SUPER:
1785 reg |= DWC3_DCFG_SUPERSPEED;
1786 break;
f7e846f0
FB		 1787 }
1788 }
72246da4
FB		 1789 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1790
2a58f9c1
FB		 1791 /*
1792 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1793 * field instead of letting dwc3 itself calculate that automatically.
1794 *
1795 * This way, we maximize the chances that we'll be able to get several
1796 * bursts of data without going through any sort of endpoint throttling.
1797 */
1798 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1799 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1800 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1801
4e99472b
FB		 1802 dwc3_gadget_setup_nump(dwc);
1803
72246da4
FB		 1804 /* Start with SuperSpeed Default */
1805 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1806
1807 dep = dwc->eps[0];
39ebb05c 1808 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1809 if (ret) {
1810 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1811 goto err0;
72246da4
FB		 1812 }
1813
1814 dep = dwc->eps[1];
39ebb05c 1815 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1816 if (ret) {
1817 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1818 goto err1;
72246da4
FB		 1819 }
1820
1821 /* begin to receive SETUP packets */
c7fcdeb2 1822 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1823 dwc3_ep0_out_start(dwc);
1824
8698e2ac
FB		 1825 dwc3_gadget_enable_irq(dwc);
1826
72246da4
FB		 1827 return 0;
1828
b0d7ffd4 1829err1:
d7be2952 1830 __dwc3_gadget_ep_disable(dwc->eps[0]);
b0d7ffd4
FB		 1831
1832err0:
72246da4
FB		 1833 return ret;
1834}
1835
d7be2952
FB		 1836static int dwc3_gadget_start(struct usb_gadget *g,
1837 struct usb_gadget_driver *driver)
72246da4
FB		 1838{
1839 struct dwc3 *dwc = gadget_to_dwc(g);
1840 unsigned long flags;
d7be2952 1841 int ret = 0;
8698e2ac 1842 int irq;
72246da4 1843
9522def4 1844 irq = dwc->irq_gadget;
d7be2952
FB		 1845 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1846 IRQF_SHARED, "dwc3", dwc->ev_buf);
1847 if (ret) {
1848 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1849 irq, ret);
1850 goto err0;
1851 }
1852
72246da4 1853 spin_lock_irqsave(&dwc->lock, flags);
d7be2952
FB		 1854 if (dwc->gadget_driver) {
1855 dev_err(dwc->dev, "%s is already bound to %s\n",
1856 dwc->gadget.name,
1857 dwc->gadget_driver->driver.name);
1858 ret = -EBUSY;
1859 goto err1;
1860 }
1861
1862 dwc->gadget_driver = driver;
1863
fc8bb91b
FB		 1864 if (pm_runtime_active(dwc->dev))
1865 __dwc3_gadget_start(dwc);
1866
d7be2952
FB		 1867 spin_unlock_irqrestore(&dwc->lock, flags);
1868
1869 return 0;
1870
1871err1:
1872 spin_unlock_irqrestore(&dwc->lock, flags);
1873 free_irq(irq, dwc);
1874
1875err0:
1876 return ret;
1877}
72246da4 1878
d7be2952
FB		 1879static void __dwc3_gadget_stop(struct dwc3 *dwc)
1880{
8698e2ac 1881 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1882 __dwc3_gadget_ep_disable(dwc->eps[0]);
1883 __dwc3_gadget_ep_disable(dwc->eps[1]);
d7be2952 1884}
72246da4 1885
d7be2952
FB		 1886static int dwc3_gadget_stop(struct usb_gadget *g)
1887{
1888 struct dwc3 *dwc = gadget_to_dwc(g);
1889 unsigned long flags;
76a638f8 1890 int epnum;
72246da4 1891
d7be2952 1892 spin_lock_irqsave(&dwc->lock, flags);
76a638f8
BW		 1893
1894 if (pm_runtime_suspended(dwc->dev))
1895 goto out;
1896
d7be2952 1897 __dwc3_gadget_stop(dwc);
76a638f8
BW		 1898
1899 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1900 struct dwc3_ep *dep = dwc->eps[epnum];
1901
1902 if (!dep)
1903 continue;
1904
1905 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1906 continue;
1907
1908 wait_event_lock_irq(dep->wait_end_transfer,
1909 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1910 dwc->lock);
1911 }
1912
1913out:
d7be2952 1914 dwc->gadget_driver = NULL;
72246da4
FB		 1915 spin_unlock_irqrestore(&dwc->lock, flags);
1916
3f308d17 1917 free_irq(dwc->irq_gadget, dwc->ev_buf);
b0d7ffd4 1918
72246da4
FB		 1919 return 0;
1920}
802fde98 1921
72246da4
FB		 1922static const struct usb_gadget_ops dwc3_gadget_ops = {
1923 .get_frame = dwc3_gadget_get_frame,
1924 .wakeup = dwc3_gadget_wakeup,
1925 .set_selfpowered = dwc3_gadget_set_selfpowered,
1926 .pullup = dwc3_gadget_pullup,
1927 .udc_start = dwc3_gadget_start,
1928 .udc_stop = dwc3_gadget_stop,
1929};
1930
1931/* -------------------------------------------------------------------------- */
1932
6a1e3ef4
FB		 1933static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1934 u8 num, u32 direction)
72246da4
FB		 1935{
1936 struct dwc3_ep *dep;
6a1e3ef4 1937 u8 i;
72246da4 1938
6a1e3ef4 1939 for (i = 0; i < num; i++) {
d07fa665 1940 u8 epnum = (i << 1) | (direction ? 1 : 0);
72246da4 1941
72246da4 1942 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 1943 if (!dep)
72246da4 1944 return -ENOMEM;
72246da4
FB		 1945
1946 dep->dwc = dwc;
1947 dep->number = epnum;
9aa62ae4 1948 dep->direction = !!direction;
2eb88016 1949 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
72246da4
FB		 1950 dwc->eps[epnum] = dep;
1951
1952 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1953 (epnum & 1) ? "in" : "out");
6a1e3ef4 1954
72246da4 1955 dep->endpoint.name = dep->name;
39ebb05c
JY		 1956
1957 if (!(dep->number > 1)) {
1958 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
1959 dep->endpoint.comp_desc = NULL;
1960 }
1961
74674cbf 1962 spin_lock_init(&dep->lock);
72246da4
FB		 1963
1964 if (epnum == 0 || epnum == 1) {
e117e742 1965 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 1966 dep->endpoint.maxburst = 1;
72246da4
FB		 1967 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1968 if (!epnum)
1969 dwc->gadget.ep0 = &dep->endpoint;
1970 } else {
1971 int ret;
1972
e117e742 1973 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 1974 dep->endpoint.max_streams = 15;
72246da4
FB		 1975 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1976 list_add_tail(&dep->endpoint.ep_list,
1977 &dwc->gadget.ep_list);
1978
1979 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1980 if (ret)
72246da4 1981 return ret;
72246da4 1982 }
25b8ff68 1983
a474d3b7
RB		 1984 if (epnum == 0 || epnum == 1) {
1985 dep->endpoint.caps.type_control = true;
1986 } else {
1987 dep->endpoint.caps.type_iso = true;
1988 dep->endpoint.caps.type_bulk = true;
1989 dep->endpoint.caps.type_int = true;
1990 }
1991
1992 dep->endpoint.caps.dir_in = !!direction;
1993 dep->endpoint.caps.dir_out = !direction;
1994
aa3342c8
FB		 1995 INIT_LIST_HEAD(&dep->pending_list);
1996 INIT_LIST_HEAD(&dep->started_list);
72246da4
FB		 1997 }
1998
1999 return 0;
2000}
2001
6a1e3ef4
FB		 2002static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
2003{
2004 int ret;
2005
2006 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2007
2008 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
2009 if (ret < 0) {
5eb30ced 2010 dev_err(dwc->dev, "failed to initialize OUT endpoints\n");
6a1e3ef4
FB		 2011 return ret;
2012 }
2013
2014 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
2015 if (ret < 0) {
5eb30ced 2016 dev_err(dwc->dev, "failed to initialize IN endpoints\n");
6a1e3ef4
FB		 2017 return ret;
2018 }
2019
2020 return 0;
2021}
2022
72246da4
FB		 2023static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2024{
2025 struct dwc3_ep *dep;
2026 u8 epnum;
2027
2028 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2029 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2030 if (!dep)
2031 continue;
5bf8fae3
GC		 2032 /*
2033 * Physical endpoints 0 and 1 are special; they form the
2034 * bi-directional USB endpoint 0.
2035 *
2036 * For those two physical endpoints, we don't allocate a TRB
2037 * pool nor do we add them the endpoints list. Due to that, we
2038 * shouldn't do these two operations otherwise we would end up
2039 * with all sorts of bugs when removing dwc3.ko.
2040 */
2041 if (epnum != 0 && epnum != 1) {
2042 dwc3_free_trb_pool(dep);
72246da4 2043 list_del(&dep->endpoint.ep_list);
5bf8fae3 2044 }
72246da4
FB		 2045
2046 kfree(dep);
2047 }
2048}
2049
72246da4 2050/* -------------------------------------------------------------------------- */
e5caff68 2051
e5ba5ec8
PA		 2052static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2053 struct dwc3_request *req, struct dwc3_trb *trb,
e5b36ae2
FB		 2054 const struct dwc3_event_depevt *event, int status,
2055 int chain)
72246da4 2056{
72246da4
FB		 2057 unsigned int count;
2058 unsigned int s_pkt = 0;
d6d6ec7b 2059 unsigned int trb_status;
72246da4 2060
dc55c67e 2061 dwc3_ep_inc_deq(dep);
a9c3ca5f
FB		 2062
2063 if (req->trb == trb)
2064 dep->queued_requests--;
2065
2c4cbe6e
FB		 2066 trace_dwc3_complete_trb(dep, trb);
2067
e5b36ae2
FB		 2068 /*
2069 * If we're in the middle of series of chained TRBs and we
2070 * receive a short transfer along the way, DWC3 will skip
2071 * through all TRBs including the last TRB in the chain (the
2072 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2073 * bit and SW has to do it manually.
2074 *
2075 * We're going to do that here to avoid problems of HW trying
2076 * to use bogus TRBs for transfers.
2077 */
2078 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2079 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2080
c6267a51
FB		 2081 /*
2082 * If we're dealing with unaligned size OUT transfer, we will be left
2083 * with one TRB pending in the ring. We need to manually clear HWO bit
2084 * from that TRB.
2085 */
2086 if (req->unaligned && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
2087 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2088 return 1;
2089 }
2090
e5ba5ec8 2091 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
a0ad85ae 2092 return 1;
e5b36ae2 2093
e5ba5ec8 2094 count = trb->size & DWC3_TRB_SIZE_MASK;
e62c5bc5 2095 req->remaining += count;
e5ba5ec8
PA		 2096
2097 if (dep->direction) {
2098 if (count) {
2099 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2100 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
e5ba5ec8
PA		 2101 /*
2102 * If missed isoc occurred and there is
2103 * no request queued then issue END
2104 * TRANSFER, so that core generates
2105 * next xfernotready and we will issue
2106 * a fresh START TRANSFER.
2107 * If there are still queued request
2108 * then wait, do not issue either END
2109 * or UPDATE TRANSFER, just attach next
aa3342c8 2110 * request in pending_list during
e5ba5ec8
PA		 2111 * giveback.If any future queued request
2112 * is successfully transferred then we
2113 * will issue UPDATE TRANSFER for all
aa3342c8 2114 * request in the pending_list.
e5ba5ec8
PA		 2115 */
2116 dep->flags |= DWC3_EP_MISSED_ISOC;
2117 } else {
2118 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2119 dep->name);
2120 status = -ECONNRESET;
2121 }
2122 } else {
2123 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2124 }
2125 } else {
2126 if (count && (event->status & DEPEVT_STATUS_SHORT))
2127 s_pkt = 1;
2128 }
2129
7c705dfe 2130 if (s_pkt && !chain)
e5ba5ec8 2131 return 1;
f99f53f2 2132
e5ba5ec8
PA		 2133 if ((event->status & DEPEVT_STATUS_IOC) &&
2134 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2135 return 1;
f99f53f2 2136
e5ba5ec8
PA		 2137 return 0;
2138}
2139
2140static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2141 const struct dwc3_event_depevt *event, int status)
2142{
31162af4 2143 struct dwc3_request *req, *n;
e5ba5ec8 2144 struct dwc3_trb *trb;
d6e10bf2 2145 bool ioc = false;
e62c5bc5 2146 int ret = 0;
e5ba5ec8 2147
31162af4 2148 list_for_each_entry_safe(req, n, &dep->started_list, list) {
1f512119 2149 unsigned length;
e5b36ae2
FB		 2150 int chain;
2151
1f512119
FB		 2152 length = req->request.length;
2153 chain = req->num_pending_sgs > 0;
31162af4 2154 if (chain) {
1f512119 2155 struct scatterlist *sg = req->sg;
31162af4 2156 struct scatterlist *s;
1f512119 2157 unsigned int pending = req->num_pending_sgs;
31162af4 2158 unsigned int i;
c7de5734 2159
1f512119 2160 for_each_sg(sg, s, pending, i) {
31162af4 2161 trb = &dep->trb_pool[dep->trb_dequeue];
31162af4 2162
7282c4ef
FB		 2163 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2164 break;
2165
1f512119
FB		 2166 req->sg = sg_next(s);
2167 req->num_pending_sgs--;
2168
31162af4
FB		 2169 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2170 event, status, chain);
1f512119
FB		 2171 if (ret)
2172 break;
31162af4
FB		 2173 }
2174 } else {
737f1ae2 2175 trb = &dep->trb_pool[dep->trb_dequeue];
d115d705 2176 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
e5b36ae2 2177 event, status, chain);
31162af4 2178 }
d115d705 2179
c6267a51
FB		 2180 if (req->unaligned) {
2181 trb = &dep->trb_pool[dep->trb_dequeue];
2182 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2183 event, status, false);
2184 req->unaligned = false;
2185 }
2186
e62c5bc5 2187 req->request.actual = length - req->remaining;
1f512119 2188
ff377ae4 2189 if ((req->request.actual < length) && req->num_pending_sgs)
1f512119
FB		 2190 return __dwc3_gadget_kick_transfer(dep, 0);
2191
d115d705 2192 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8 2193
d6e10bf2
AB		 2194 if (ret) {
2195 if ((event->status & DEPEVT_STATUS_IOC) &&
2196 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2197 ioc = true;
72246da4 2198 break;
d6e10bf2 2199 }
31162af4 2200 }
72246da4 2201
4cb42217
FB		 2202 /*
2203 * Our endpoint might get disabled by another thread during
2204 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2205 * early on so DWC3_EP_BUSY flag gets cleared
2206 */
2207 if (!dep->endpoint.desc)
2208 return 1;
2209
cdc359dd 2210 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
aa3342c8
FB		 2211 list_empty(&dep->started_list)) {
2212 if (list_empty(&dep->pending_list)) {
cdc359dd
PA		 2213 /*
2214 * If there is no entry in request list then do
2215 * not issue END TRANSFER now. Just set PENDING
2216 * flag, so that END TRANSFER is issued when an
2217 * entry is added into request list.
2218 */
2219 dep->flags = DWC3_EP_PENDING_REQUEST;
2220 } else {
b992e681 2221 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 2222 dep->flags = DWC3_EP_ENABLED;
2223 }
7efea86c
PA		 2224 return 1;
2225 }
2226
d6e10bf2
AB		 2227 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2228 return 0;
2229
72246da4
FB		 2230 return 1;
2231}
2232
2233static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 2234 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 2235{
2236 unsigned status = 0;
2237 int clean_busy;
e18b7975
FB		 2238 u32 is_xfer_complete;
2239
2240 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 2241
2242 if (event->status & DEPEVT_STATUS_BUSERR)
2243 status = -ECONNRESET;
2244
1d046793 2245 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
4cb42217 2246 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
e18b7975 2247 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 2248 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 2249
2250 /*
2251 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2252 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2253 */
2254 if (dwc->revision < DWC3_REVISION_183A) {
2255 u32 reg;
2256 int i;
2257
2258 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 2259 dep = dwc->eps[i];
fae2b904
FB		 2260
2261 if (!(dep->flags & DWC3_EP_ENABLED))
2262 continue;
2263
aa3342c8 2264 if (!list_empty(&dep->started_list))
fae2b904
FB		 2265 return;
2266 }
2267
2268 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2269 reg |= dwc->u1u2;
2270 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2271
2272 dwc->u1u2 = 0;
2273 }
8a1a9c9e 2274
4cb42217
FB		 2275 /*
2276 * Our endpoint might get disabled by another thread during
2277 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2278 * early on so DWC3_EP_BUSY flag gets cleared
2279 */
2280 if (!dep->endpoint.desc)
2281 return;
2282
e6e709b7 2283 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2284 int ret;
2285
4fae2e3e 2286 ret = __dwc3_gadget_kick_transfer(dep, 0);
8a1a9c9e
FB		 2287 if (!ret || ret == -EBUSY)
2288 return;
2289 }
72246da4
FB		 2290}
2291
72246da4
FB		 2292static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2293 const struct dwc3_event_depevt *event)
2294{
2295 struct dwc3_ep *dep;
2296 u8 epnum = event->endpoint_number;
76a638f8 2297 u8 cmd;
72246da4
FB		 2298
2299 dep = dwc->eps[epnum];
2300
d7fd41c6
JD		 2301 if (!(dep->flags & DWC3_EP_ENABLED)) {
2302 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2303 return;
2304
2305 /* Handle only EPCMDCMPLT when EP disabled */
2306 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2307 return;
2308 }
3336abb5 2309
72246da4
FB		 2310 if (epnum == 0 || epnum == 1) {
2311 dwc3_ep0_interrupt(dwc, event);
2312 return;
2313 }
2314
2315 switch (event->endpoint_event) {
2316 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2317 dep->resource_index = 0;
c2df85ca 2318
16e78db7 2319 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8566cd1a 2320 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
72246da4
FB		 2321 return;
2322 }
2323
029d97ff 2324 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2325 break;
2326 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2327 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2328 break;
2329 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2330 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2331 dwc3_gadget_start_isoc(dwc, dep, event);
2332 } else {
2333 int ret;
2334
4fae2e3e 2335 ret = __dwc3_gadget_kick_transfer(dep, 0);
72246da4
FB		 2336 if (!ret || ret == -EBUSY)
2337 return;
72246da4
FB		 2338 }
2339
879631aa
FB		 2340 break;
2341 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2342 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2343 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2344 dep->name);
2345 return;
2346 }
72246da4 2347 break;
72246da4 2348 case DWC3_DEPEVT_EPCMDCMPLT:
76a638f8
BW		 2349 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2350
2351 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2352 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2353 wake_up(&dep->wait_end_transfer);
2354 }
2355 break;
2356 case DWC3_DEPEVT_RXTXFIFOEVT:
72246da4
FB		 2357 break;
2358 }
2359}
2360
2361static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2362{
2363 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2364 spin_unlock(&dwc->lock);
2365 dwc->gadget_driver->disconnect(&dwc->gadget);
2366 spin_lock(&dwc->lock);
2367 }
2368}
2369
bc5ba2e0
FB		 2370static void dwc3_suspend_gadget(struct dwc3 *dwc)
2371{
73a30bfc 2372 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2373 spin_unlock(&dwc->lock);
2374 dwc->gadget_driver->suspend(&dwc->gadget);
2375 spin_lock(&dwc->lock);
2376 }
2377}
2378
2379static void dwc3_resume_gadget(struct dwc3 *dwc)
2380{
73a30bfc 2381 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2382 spin_unlock(&dwc->lock);
2383 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2384 spin_lock(&dwc->lock);
8e74475b
FB		 2385 }
2386}
2387
2388static void dwc3_reset_gadget(struct dwc3 *dwc)
2389{
2390 if (!dwc->gadget_driver)
2391 return;
2392
2393 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2394 spin_unlock(&dwc->lock);
2395 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2396 spin_lock(&dwc->lock);
2397 }
2398}
2399
b992e681 2400static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2401{
2402 struct dwc3_ep *dep;
2403 struct dwc3_gadget_ep_cmd_params params;
2404 u32 cmd;
2405 int ret;
2406
2407 dep = dwc->eps[epnum];
2408
76a638f8
BW		 2409 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2410 !dep->resource_index)
3daf74d7
PA		 2411 return;
2412
57911504
PA		 2413 /*
2414 * NOTICE: We are violating what the Databook says about the
2415 * EndTransfer command. Ideally we would _always_ wait for the
2416 * EndTransfer Command Completion IRQ, but that's causing too
2417 * much trouble synchronizing between us and gadget driver.
2418 *
2419 * We have discussed this with the IP Provider and it was
2420 * suggested to giveback all requests here, but give HW some
2421 * extra time to synchronize with the interconnect. We're using
dc93b41a 2422 * an arbitrary 100us delay for that.
57911504
PA		 2423 *
2424 * Note also that a similar handling was tested by Synopsys
2425 * (thanks a lot Paul) and nothing bad has come out of it.
2426 * In short, what we're doing is:
2427 *
2428 * - Issue EndTransfer WITH CMDIOC bit set
2429 * - Wait 100us
06281d46
JY		 2430 *
2431 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2432 * supports a mode to work around the above limitation. The
2433 * software can poll the CMDACT bit in the DEPCMD register
2434 * after issuing a EndTransfer command. This mode is enabled
2435 * by writing GUCTL2[14]. This polling is already done in the
2436 * dwc3_send_gadget_ep_cmd() function so if the mode is
2437 * enabled, the EndTransfer command will have completed upon
2438 * returning from this function and we don't need to delay for
2439 * 100us.
2440 *
2441 * This mode is NOT available on the DWC_usb31 IP.
57911504
PA		 2442 */
2443
3daf74d7 2444 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2445 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2446 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2447 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7 2448 memset(&params, 0, sizeof(params));
2cd4718d 2449 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3daf74d7 2450 WARN_ON_ONCE(ret);
b4996a86 2451 dep->resource_index = 0;
041d81f4 2452 dep->flags &= ~DWC3_EP_BUSY;
06281d46 2453
76a638f8
BW		 2454 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2455 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
06281d46 2456 udelay(100);
76a638f8 2457 }
72246da4
FB		 2458}
2459
72246da4
FB		 2460static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2461{
2462 u32 epnum;
2463
2464 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2465 struct dwc3_ep *dep;
72246da4
FB		 2466 int ret;
2467
2468 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2469 if (!dep)
2470 continue;
72246da4
FB		 2471
2472 if (!(dep->flags & DWC3_EP_STALL))
2473 continue;
2474
2475 dep->flags &= ~DWC3_EP_STALL;
2476
50c763f8 2477 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4
FB		 2478 WARN_ON_ONCE(ret);
2479 }
2480}
2481
2482static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2483{
c4430a26
FB		 2484 int reg;
2485
72246da4
FB		 2486 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2487 reg &= ~DWC3_DCTL_INITU1ENA;
2488 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2489
2490 reg &= ~DWC3_DCTL_INITU2ENA;
2491 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2492
72246da4
FB		 2493 dwc3_disconnect_gadget(dwc);
2494
2495 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2496 dwc->setup_packet_pending = false;
06a374ed 2497 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
fc8bb91b
FB		 2498
2499 dwc->connected = false;
72246da4
FB		 2500}
2501
72246da4
FB		 2502static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2503{
2504 u32 reg;
2505
fc8bb91b
FB		 2506 dwc->connected = true;
2507
df62df56
FB		 2508 /*
2509 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2510 * would cause a missing Disconnect Event if there's a
2511 * pending Setup Packet in the FIFO.
2512 *
2513 * There's no suggested workaround on the official Bug
2514 * report, which states that "unless the driver/application
2515 * is doing any special handling of a disconnect event,
2516 * there is no functional issue".
2517 *
2518 * Unfortunately, it turns out that we _do_ some special
2519 * handling of a disconnect event, namely complete all
2520 * pending transfers, notify gadget driver of the
2521 * disconnection, and so on.
2522 *
2523 * Our suggested workaround is to follow the Disconnect
2524 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2525 * flag. Such flag gets set whenever we have a SETUP_PENDING
2526 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2527 * same endpoint.
2528 *
2529 * Refers to:
2530 *
2531 * STAR#9000466709: RTL: Device : Disconnect event not
2532 * generated if setup packet pending in FIFO
2533 */
2534 if (dwc->revision < DWC3_REVISION_188A) {
2535 if (dwc->setup_packet_pending)
2536 dwc3_gadget_disconnect_interrupt(dwc);
2537 }
2538
8e74475b 2539 dwc3_reset_gadget(dwc);
72246da4
FB		 2540
2541 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2542 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2543 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2544 dwc->test_mode = false;
72246da4
FB		 2545 dwc3_clear_stall_all_ep(dwc);
2546
2547 /* Reset device address to zero */
2548 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2549 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2550 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2551}
2552
72246da4
FB		 2553static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2554{
72246da4
FB		 2555 struct dwc3_ep *dep;
2556 int ret;
2557 u32 reg;
2558 u8 speed;
2559
72246da4
FB		 2560 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2561 speed = reg & DWC3_DSTS_CONNECTSPD;
2562 dwc->speed = speed;
2563
5fb6fdaf
JY		 2564 /*
2565 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2566 * each time on Connect Done.
2567 *
2568 * Currently we always use the reset value. If any platform
2569 * wants to set this to a different value, we need to add a
2570 * setting and update GCTL.RAMCLKSEL here.
2571 */
72246da4
FB		 2572
2573 switch (speed) {
2da9ad76 2574 case DWC3_DSTS_SUPERSPEED_PLUS:
7580862b
JY		 2575 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2576 dwc->gadget.ep0->maxpacket = 512;
2577 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2578 break;
2da9ad76 2579 case DWC3_DSTS_SUPERSPEED:
05870c5b
FB		 2580 /*
2581 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2582 * would cause a missing USB3 Reset event.
2583 *
2584 * In such situations, we should force a USB3 Reset
2585 * event by calling our dwc3_gadget_reset_interrupt()
2586 * routine.
2587 *
2588 * Refers to:
2589 *
2590 * STAR#9000483510: RTL: SS : USB3 reset event may
2591 * not be generated always when the link enters poll
2592 */
2593 if (dwc->revision < DWC3_REVISION_190A)
2594 dwc3_gadget_reset_interrupt(dwc);
2595
72246da4
FB		 2596 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2597 dwc->gadget.ep0->maxpacket = 512;
2598 dwc->gadget.speed = USB_SPEED_SUPER;
2599 break;
2da9ad76 2600 case DWC3_DSTS_HIGHSPEED:
72246da4
FB		 2601 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2602 dwc->gadget.ep0->maxpacket = 64;
2603 dwc->gadget.speed = USB_SPEED_HIGH;
2604 break;
9418ee15 2605 case DWC3_DSTS_FULLSPEED:
72246da4
FB		 2606 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2607 dwc->gadget.ep0->maxpacket = 64;
2608 dwc->gadget.speed = USB_SPEED_FULL;
2609 break;
2da9ad76 2610 case DWC3_DSTS_LOWSPEED:
72246da4
FB		 2611 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2612 dwc->gadget.ep0->maxpacket = 8;
2613 dwc->gadget.speed = USB_SPEED_LOW;
2614 break;
2615 }
2616
2b758350
PA		 2617 /* Enable USB2 LPM Capability */
2618
ee5cd41c 2619 if ((dwc->revision > DWC3_REVISION_194A) &&
2da9ad76
JY		 2620 (speed != DWC3_DSTS_SUPERSPEED) &&
2621 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2b758350
PA		 2622 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2623 reg |= DWC3_DCFG_LPM_CAP;
2624 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2625
2626 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2627 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2628
460d098c 2629 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2630
80caf7d2
HR		 2631 /*
2632 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2633 * DCFG.LPMCap is set, core responses with an ACK and the
2634 * BESL value in the LPM token is less than or equal to LPM
2635 * NYET threshold.
2636 */
2637 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2638 && dwc->has_lpm_erratum,
9165dabb 2639 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
80caf7d2
HR		 2640
2641 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2642 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2643
356363bf
FB		 2644 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2645 } else {
2646 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2647 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2648 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2649 }
2650
72246da4 2651 dep = dwc->eps[0];
39ebb05c 2652 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2653 if (ret) {
2654 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2655 return;
2656 }
2657
2658 dep = dwc->eps[1];
39ebb05c 2659 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2660 if (ret) {
2661 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2662 return;
2663 }
2664
2665 /*
2666 * Configure PHY via GUSB3PIPECTLn if required.
2667 *
2668 * Update GTXFIFOSIZn
2669 *
2670 * In both cases reset values should be sufficient.
2671 */
2672}
2673
2674static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2675{
72246da4
FB		 2676 /*
2677 * TODO take core out of low power mode when that's
2678 * implemented.
2679 */
2680
ad14d4e0
JL		 2681 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2682 spin_unlock(&dwc->lock);
2683 dwc->gadget_driver->resume(&dwc->gadget);
2684 spin_lock(&dwc->lock);
2685 }
72246da4
FB		 2686}
2687
2688static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2689 unsigned int evtinfo)
2690{
fae2b904 2691 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2692 unsigned int pwropt;
2693
2694 /*
2695 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2696 * Hibernation mode enabled which would show up when device detects
2697 * host-initiated U3 exit.
2698 *
2699 * In that case, device will generate a Link State Change Interrupt
2700 * from U3 to RESUME which is only necessary if Hibernation is
2701 * configured in.
2702 *
2703 * There are no functional changes due to such spurious event and we
2704 * just need to ignore it.
2705 *
2706 * Refers to:
2707 *
2708 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2709 * operational mode
2710 */
2711 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2712 if ((dwc->revision < DWC3_REVISION_250A) &&
2713 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2714 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2715 (next == DWC3_LINK_STATE_RESUME)) {
0b0cc1cd
FB		 2716 return;
2717 }
2718 }
fae2b904
FB		 2719
2720 /*
2721 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2722 * on the link partner, the USB session might do multiple entry/exit
2723 * of low power states before a transfer takes place.
2724 *
2725 * Due to this problem, we might experience lower throughput. The
2726 * suggested workaround is to disable DCTL[12:9] bits if we're
2727 * transitioning from U1/U2 to U0 and enable those bits again
2728 * after a transfer completes and there are no pending transfers
2729 * on any of the enabled endpoints.
2730 *
2731 * This is the first half of that workaround.
2732 *
2733 * Refers to:
2734 *
2735 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2736 * core send LGO_Ux entering U0
2737 */
2738 if (dwc->revision < DWC3_REVISION_183A) {
2739 if (next == DWC3_LINK_STATE_U0) {
2740 u32 u1u2;
2741 u32 reg;
2742
2743 switch (dwc->link_state) {
2744 case DWC3_LINK_STATE_U1:
2745 case DWC3_LINK_STATE_U2:
2746 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2747 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2748 | DWC3_DCTL_ACCEPTU2ENA
2749 | DWC3_DCTL_INITU1ENA
2750 | DWC3_DCTL_ACCEPTU1ENA);
2751
2752 if (!dwc->u1u2)
2753 dwc->u1u2 = reg & u1u2;
2754
2755 reg &= ~u1u2;
2756
2757 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2758 break;
2759 default:
2760 /* do nothing */
2761 break;
2762 }
2763 }
2764 }
2765
bc5ba2e0
FB		 2766 switch (next) {
2767 case DWC3_LINK_STATE_U1:
2768 if (dwc->speed == USB_SPEED_SUPER)
2769 dwc3_suspend_gadget(dwc);
2770 break;
2771 case DWC3_LINK_STATE_U2:
2772 case DWC3_LINK_STATE_U3:
2773 dwc3_suspend_gadget(dwc);
2774 break;
2775 case DWC3_LINK_STATE_RESUME:
2776 dwc3_resume_gadget(dwc);
2777 break;
2778 default:
2779 /* do nothing */
2780 break;
2781 }
2782
e57ebc1d 2783 dwc->link_state = next;
72246da4
FB		 2784}
2785
72704f87
BW		 2786static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2787 unsigned int evtinfo)
2788{
2789 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2790
2791 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2792 dwc3_suspend_gadget(dwc);
2793
2794 dwc->link_state = next;
2795}
2796
e1dadd3b
FB		 2797static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2798 unsigned int evtinfo)
2799{
2800 unsigned int is_ss = evtinfo & BIT(4);
2801
2802 /**
2803 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2804 * have a known issue which can cause USB CV TD.9.23 to fail
2805 * randomly.
2806 *
2807 * Because of this issue, core could generate bogus hibernation
2808 * events which SW needs to ignore.
2809 *
2810 * Refers to:
2811 *
2812 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2813 * Device Fallback from SuperSpeed
2814 */
2815 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2816 return;
2817
2818 /* enter hibernation here */
2819}
2820
72246da4
FB		 2821static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2822 const struct dwc3_event_devt *event)
2823{
2824 switch (event->type) {
2825 case DWC3_DEVICE_EVENT_DISCONNECT:
2826 dwc3_gadget_disconnect_interrupt(dwc);
2827 break;
2828 case DWC3_DEVICE_EVENT_RESET:
2829 dwc3_gadget_reset_interrupt(dwc);
2830 break;
2831 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2832 dwc3_gadget_conndone_interrupt(dwc);
2833 break;
2834 case DWC3_DEVICE_EVENT_WAKEUP:
2835 dwc3_gadget_wakeup_interrupt(dwc);
2836 break;
e1dadd3b
FB		 2837 case DWC3_DEVICE_EVENT_HIBER_REQ:
2838 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2839 "unexpected hibernation event\n"))
2840 break;
2841
2842 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2843 break;
72246da4
FB		 2844 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2845 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2846 break;
2847 case DWC3_DEVICE_EVENT_EOPF:
72704f87 2848 /* It changed to be suspend event for version 2.30a and above */
5eb30ced 2849 if (dwc->revision >= DWC3_REVISION_230A) {
72704f87
BW		 2850 /*
2851 * Ignore suspend event until the gadget enters into
2852 * USB_STATE_CONFIGURED state.
2853 */
2854 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2855 dwc3_gadget_suspend_interrupt(dwc,
2856 event->event_info);
2857 }
72246da4
FB		 2858 break;
2859 case DWC3_DEVICE_EVENT_SOF:
72246da4 2860 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
72246da4 2861 case DWC3_DEVICE_EVENT_CMD_CMPL:
72246da4 2862 case DWC3_DEVICE_EVENT_OVERFLOW:
72246da4
FB		 2863 break;
2864 default:
e9f2aa87 2865 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2866 }
2867}
2868
2869static void dwc3_process_event_entry(struct dwc3 *dwc,
2870 const union dwc3_event *event)
2871{
43c96be1 2872 trace_dwc3_event(event->raw, dwc);
2c4cbe6e 2873
72246da4
FB		 2874 /* Endpoint IRQ, handle it and return early */
2875 if (event->type.is_devspec == 0) {
2876 /* depevt */
2877 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2878 }
2879
2880 switch (event->type.type) {
2881 case DWC3_EVENT_TYPE_DEV:
2882 dwc3_gadget_interrupt(dwc, &event->devt);
2883 break;
2884 /* REVISIT what to do with Carkit and I2C events ? */
2885 default:
2886 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2887 }
2888}
2889
dea520a4 2890static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
b15a762f 2891{
dea520a4 2892 struct dwc3 *dwc = evt->dwc;
b15a762f 2893 irqreturn_t ret = IRQ_NONE;
f42f2447 2894 int left;
e8adfc30 2895 u32 reg;
b15a762f 2896
f42f2447 2897 left = evt->count;
b15a762f 2898
f42f2447
FB		 2899 if (!(evt->flags & DWC3_EVENT_PENDING))
2900 return IRQ_NONE;
b15a762f 2901
f42f2447
FB		 2902 while (left > 0) {
2903 union dwc3_event event;
b15a762f 2904
ebbb2d59 2905 event.raw = *(u32 *) (evt->cache + evt->lpos);
b15a762f 2906
f42f2447 2907 dwc3_process_event_entry(dwc, &event);
b15a762f 2908
f42f2447
FB		 2909 /*
2910 * FIXME we wrap around correctly to the next entry as
2911 * almost all entries are 4 bytes in size. There is one
2912 * entry which has 12 bytes which is a regular entry
2913 * followed by 8 bytes data. ATM I don't know how
2914 * things are organized if we get next to the a
2915 * boundary so I worry about that once we try to handle
2916 * that.
2917 */
caefe6c7 2918 evt->lpos = (evt->lpos + 4) % evt->length;
f42f2447 2919 left -= 4;
f42f2447 2920 }
b15a762f 2921
f42f2447
FB		 2922 evt->count = 0;
2923 evt->flags &= ~DWC3_EVENT_PENDING;
2924 ret = IRQ_HANDLED;
b15a762f 2925
f42f2447 2926 /* Unmask interrupt */
660e9bde 2927 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
f42f2447 2928 reg &= ~DWC3_GEVNTSIZ_INTMASK;
660e9bde 2929 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
b15a762f 2930
cf40b86b
JY		 2931 if (dwc->imod_interval) {
2932 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2933 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2934 }
2935
f42f2447
FB		 2936 return ret;
2937}
e8adfc30 2938
dea520a4 2939static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
f42f2447 2940{
dea520a4
FB		 2941 struct dwc3_event_buffer *evt = _evt;
2942 struct dwc3 *dwc = evt->dwc;
e5f68b4a 2943 unsigned long flags;
f42f2447 2944 irqreturn_t ret = IRQ_NONE;
f42f2447 2945
e5f68b4a 2946 spin_lock_irqsave(&dwc->lock, flags);
dea520a4 2947 ret = dwc3_process_event_buf(evt);
e5f68b4a 2948 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 2949
2950 return ret;
2951}
2952
dea520a4 2953static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
72246da4 2954{
dea520a4 2955 struct dwc3 *dwc = evt->dwc;
ebbb2d59 2956 u32 amount;
72246da4 2957 u32 count;
e8adfc30 2958 u32 reg;
72246da4 2959
fc8bb91b
FB		 2960 if (pm_runtime_suspended(dwc->dev)) {
2961 pm_runtime_get(dwc->dev);
2962 disable_irq_nosync(dwc->irq_gadget);
2963 dwc->pending_events = true;
2964 return IRQ_HANDLED;
2965 }
2966
660e9bde 2967 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
72246da4
FB		 2968 count &= DWC3_GEVNTCOUNT_MASK;
2969 if (!count)
2970 return IRQ_NONE;
2971
b15a762f
FB		 2972 evt->count = count;
2973 evt->flags |= DWC3_EVENT_PENDING;
72246da4 2974
e8adfc30 2975 /* Mask interrupt */
660e9bde 2976 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
e8adfc30 2977 reg |= DWC3_GEVNTSIZ_INTMASK;
660e9bde 2978 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
e8adfc30 2979
ebbb2d59
JY		 2980 amount = min(count, evt->length - evt->lpos);
2981 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
2982
2983 if (amount < count)
2984 memcpy(evt->cache, evt->buf, count - amount);
2985
65aca320
JY		 2986 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
2987
b15a762f 2988 return IRQ_WAKE_THREAD;
72246da4
FB		 2989}
2990
dea520a4 2991static irqreturn_t dwc3_interrupt(int irq, void *_evt)
72246da4 2992{
dea520a4 2993 struct dwc3_event_buffer *evt = _evt;
72246da4 2994
dea520a4 2995 return dwc3_check_event_buf(evt);
72246da4
FB		 2996}
2997
6db3812e
FB		 2998static int dwc3_gadget_get_irq(struct dwc3 *dwc)
2999{
3000 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3001 int irq;
3002
3003 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3004 if (irq > 0)
3005 goto out;
3006
3007 if (irq == -EPROBE_DEFER)
3008 goto out;
3009
3010 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3011 if (irq > 0)
3012 goto out;
3013
3014 if (irq == -EPROBE_DEFER)
3015 goto out;
3016
3017 irq = platform_get_irq(dwc3_pdev, 0);
3018 if (irq > 0)
3019 goto out;
3020
3021 if (irq != -EPROBE_DEFER)
3022 dev_err(dwc->dev, "missing peripheral IRQ\n");
3023
3024 if (!irq)
3025 irq = -EINVAL;
3026
3027out:
3028 return irq;
3029}
3030
72246da4
FB		 3031/**
3032 * dwc3_gadget_init - Initializes gadget related registers
1d046793 3033 * @dwc: pointer to our controller context structure
72246da4
FB		 3034 *
3035 * Returns 0 on success otherwise negative errno.
3036 */
41ac7b3a 3037int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 3038{
6db3812e
FB		 3039 int ret;
3040 int irq;
9522def4 3041
6db3812e
FB		 3042 irq = dwc3_gadget_get_irq(dwc);
3043 if (irq < 0) {
3044 ret = irq;
3045 goto err0;
9522def4
RQ		 3046 }
3047
3048 dwc->irq_gadget = irq;
72246da4 3049
d64ff406 3050 dwc->ctrl_req = dma_alloc_coherent(dwc->sysdev, sizeof(*dwc->ctrl_req),
72246da4
FB		 3051 &dwc->ctrl_req_addr, GFP_KERNEL);
3052 if (!dwc->ctrl_req) {
3053 dev_err(dwc->dev, "failed to allocate ctrl request\n");
3054 ret = -ENOMEM;
3055 goto err0;
3056 }
3057
d64ff406
AB		 3058 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3059 sizeof(*dwc->ep0_trb) * 2,
3060 &dwc->ep0_trb_addr, GFP_KERNEL);
72246da4
FB		 3061 if (!dwc->ep0_trb) {
3062 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3063 ret = -ENOMEM;
3064 goto err1;
3065 }
3066
3ef35faf 3067 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4 3068 if (!dwc->setup_buf) {
72246da4
FB		 3069 ret = -ENOMEM;
3070 goto err2;
3071 }
3072
d64ff406 3073 dwc->ep0_bounce = dma_alloc_coherent(dwc->sysdev,
3ef35faf
FB		 3074 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
3075 GFP_KERNEL);
5812b1c2
FB		 3076 if (!dwc->ep0_bounce) {
3077 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
3078 ret = -ENOMEM;
3079 goto err3;
3080 }
3081
04c03d10
FB		 3082 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
3083 if (!dwc->zlp_buf) {
3084 ret = -ENOMEM;
3085 goto err4;
3086 }
3087
905dc04e
FB		 3088 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3089 &dwc->bounce_addr, GFP_KERNEL);
3090 if (!dwc->bounce) {
3091 ret = -ENOMEM;
3092 goto err5;
3093 }
3094
bb014736
BW		 3095 init_completion(&dwc->ep0_in_setup);
3096
72246da4 3097 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 3098 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 3099 dwc->gadget.sg_supported = true;
72246da4 3100 dwc->gadget.name = "dwc3-gadget";
6a4290cc 3101 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 3102
b9e51b2b
BM		 3103 /*
3104 * FIXME We might be setting max_speed to <SUPER, however versions
3105 * <2.20a of dwc3 have an issue with metastability (documented
3106 * elsewhere in this driver) which tells us we can't set max speed to
3107 * anything lower than SUPER.
3108 *
3109 * Because gadget.max_speed is only used by composite.c and function
3110 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3111 * to happen so we avoid sending SuperSpeed Capability descriptor
3112 * together with our BOS descriptor as that could confuse host into
3113 * thinking we can handle super speed.
3114 *
3115 * Note that, in fact, we won't even support GetBOS requests when speed
3116 * is less than super speed because we don't have means, yet, to tell
3117 * composite.c that we are USB 2.0 + LPM ECN.
3118 */
3119 if (dwc->revision < DWC3_REVISION_220A)
5eb30ced 3120 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
b9e51b2b
BM		 3121 dwc->revision);
3122
3123 dwc->gadget.max_speed = dwc->maximum_speed;
3124
72246da4
FB		 3125 /*
3126 * REVISIT: Here we should clear all pending IRQs to be
3127 * sure we're starting from a well known location.
3128 */
3129
3130 ret = dwc3_gadget_init_endpoints(dwc);
3131 if (ret)
905dc04e 3132 goto err6;
72246da4 3133
72246da4
FB		 3134 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3135 if (ret) {
3136 dev_err(dwc->dev, "failed to register udc\n");
905dc04e 3137 goto err6;
72246da4
FB		 3138 }
3139
3140 return 0;
905dc04e
FB		 3141err6:
3142 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3143 dwc->bounce_addr);
72246da4 3144
04c03d10
FB		 3145err5:
3146 kfree(dwc->zlp_buf);
3147
5812b1c2 3148err4:
e1f80467 3149 dwc3_gadget_free_endpoints(dwc);
d64ff406 3150 dma_free_coherent(dwc->sysdev, DWC3_EP0_BOUNCE_SIZE,
3ef35faf 3151 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 3152
72246da4 3153err3:
0fc9a1be 3154 kfree(dwc->setup_buf);
72246da4
FB		 3155
3156err2:
d64ff406 3157 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3158 dwc->ep0_trb, dwc->ep0_trb_addr);
3159
3160err1:
d64ff406 3161 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ctrl_req),
72246da4
FB		 3162 dwc->ctrl_req, dwc->ctrl_req_addr);
3163
3164err0:
3165 return ret;
3166}
3167
7415f17c
FB		 3168/* -------------------------------------------------------------------------- */
3169
72246da4
FB		 3170void dwc3_gadget_exit(struct dwc3 *dwc)
3171{
72246da4 3172 usb_del_gadget_udc(&dwc->gadget);
72246da4 3173
72246da4
FB		 3174 dwc3_gadget_free_endpoints(dwc);
3175
905dc04e
FB		 3176 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3177 dwc->bounce_addr);
d64ff406 3178 dma_free_coherent(dwc->sysdev, DWC3_EP0_BOUNCE_SIZE,
3ef35faf 3179 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 3180
0fc9a1be 3181 kfree(dwc->setup_buf);
04c03d10 3182 kfree(dwc->zlp_buf);
72246da4 3183
d64ff406 3184 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3185 dwc->ep0_trb, dwc->ep0_trb_addr);
3186
d64ff406 3187 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ctrl_req),
72246da4 3188 dwc->ctrl_req, dwc->ctrl_req_addr);
72246da4 3189}
7415f17c 3190
0b0231aa 3191int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 3192{
9f8a67b6
FB		 3193 int ret;
3194
9772b47a
RQ		 3195 if (!dwc->gadget_driver)
3196 return 0;
3197
9f8a67b6
FB		 3198 ret = dwc3_gadget_run_stop(dwc, false, false);
3199 if (ret < 0)
3200 return ret;
7415f17c 3201
9f8a67b6
FB		 3202 dwc3_disconnect_gadget(dwc);
3203 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3204
3205 return 0;
3206}
3207
3208int dwc3_gadget_resume(struct dwc3 *dwc)
3209{
7415f17c
FB		 3210 int ret;
3211
9772b47a
RQ		 3212 if (!dwc->gadget_driver)
3213 return 0;
3214
9f8a67b6
FB		 3215 ret = __dwc3_gadget_start(dwc);
3216 if (ret < 0)
7415f17c
FB		 3217 goto err0;
3218
9f8a67b6
FB		 3219 ret = dwc3_gadget_run_stop(dwc, true, false);
3220 if (ret < 0)
7415f17c
FB		 3221 goto err1;
3222
7415f17c
FB		 3223 return 0;
3224
3225err1:
9f8a67b6 3226 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3227
3228err0:
3229 return ret;
3230}
fc8bb91b
FB		 3231
3232void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3233{
3234 if (dwc->pending_events) {
3235 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3236 dwc->pending_events = false;
3237 enable_irq(dwc->irq_gadget);
3238 }
3239}
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