[linux.git] / include / linux / coresight.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
 */

#ifndef _LINUX_CORESIGHT_H
#define _LINUX_CORESIGHT_H

#include <linux/device.h>
#include <linux/perf_event.h>
#include <linux/sched.h>

/* Peripheral id registers (0xFD0-0xFEC) */
#define CORESIGHT_PERIPHIDR4	0xfd0
#define CORESIGHT_PERIPHIDR5	0xfd4
#define CORESIGHT_PERIPHIDR6	0xfd8
#define CORESIGHT_PERIPHIDR7	0xfdC
#define CORESIGHT_PERIPHIDR0	0xfe0
#define CORESIGHT_PERIPHIDR1	0xfe4
#define CORESIGHT_PERIPHIDR2	0xfe8
#define CORESIGHT_PERIPHIDR3	0xfeC
/* Component id registers (0xFF0-0xFFC) */
#define CORESIGHT_COMPIDR0	0xff0
#define CORESIGHT_COMPIDR1	0xff4
#define CORESIGHT_COMPIDR2	0xff8
#define CORESIGHT_COMPIDR3	0xffC

#define ETM_ARCH_V3_3		0x23
#define ETM_ARCH_V3_5		0x25
#define PFT_ARCH_V1_0		0x30
#define PFT_ARCH_V1_1		0x31

#define CORESIGHT_UNLOCK	0xc5acce55

extern struct bus_type coresight_bustype;

enum coresight_dev_type {
	CORESIGHT_DEV_TYPE_NONE,
	CORESIGHT_DEV_TYPE_SINK,
	CORESIGHT_DEV_TYPE_LINK,
	CORESIGHT_DEV_TYPE_LINKSINK,
	CORESIGHT_DEV_TYPE_SOURCE,
	CORESIGHT_DEV_TYPE_HELPER,
	CORESIGHT_DEV_TYPE_ECT,
};

enum coresight_dev_subtype_sink {
	CORESIGHT_DEV_SUBTYPE_SINK_NONE,
	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
	CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
};

enum coresight_dev_subtype_link {
	CORESIGHT_DEV_SUBTYPE_LINK_NONE,
	CORESIGHT_DEV_SUBTYPE_LINK_MERG,
	CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
	CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
};

enum coresight_dev_subtype_source {
	CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
	CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
	CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
	CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
};

enum coresight_dev_subtype_helper {
	CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
	CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
};

/* Embedded Cross Trigger (ECT) sub-types */
enum coresight_dev_subtype_ect {
	CORESIGHT_DEV_SUBTYPE_ECT_NONE,
	CORESIGHT_DEV_SUBTYPE_ECT_CTI,
};

/**
 * union coresight_dev_subtype - further characterisation of a type
 * @sink_subtype:	type of sink this component is, as defined
 *			by @coresight_dev_subtype_sink.
 * @link_subtype:	type of link this component is, as defined
 *			by @coresight_dev_subtype_link.
 * @source_subtype:	type of source this component is, as defined
 *			by @coresight_dev_subtype_source.
 * @helper_subtype:	type of helper this component is, as defined
 *			by @coresight_dev_subtype_helper.
 * @ect_subtype:        type of cross trigger this component is, as
 *			defined by @coresight_dev_subtype_ect
 */
union coresight_dev_subtype {
	/* We have some devices which acts as LINK and SINK */
	struct {
		enum coresight_dev_subtype_sink sink_subtype;
		enum coresight_dev_subtype_link link_subtype;
	};
	enum coresight_dev_subtype_source source_subtype;
	enum coresight_dev_subtype_helper helper_subtype;
	enum coresight_dev_subtype_ect ect_subtype;
};

/**
 * struct coresight_platform_data - data harvested from the firmware
 * specification.
 *
 * @nr_inport:	Number of elements for the input connections.
 * @nr_outport:	Number of elements for the output connections.
 * @conns:	Sparse array of nr_outport connections from this component.
 */
struct coresight_platform_data {
	int nr_inport;
	int nr_outport;
	struct coresight_connection *conns;
};

/**
 * struct coresight_desc - description of a component required from drivers
 * @type:	as defined by @coresight_dev_type.
 * @subtype:	as defined by @coresight_dev_subtype.
 * @ops:	generic operations for this component, as defined
 *		by @coresight_ops.
 * @pdata:	platform data collected from DT.
 * @dev:	The device entity associated to this component.
 * @groups:	operations specific to this component. These will end up
 *		in the component's sysfs sub-directory.
 * @name:	name for the coresight device, also shown under sysfs.
 */
struct coresight_desc {
	enum coresight_dev_type type;
	union coresight_dev_subtype subtype;
	const struct coresight_ops *ops;
	struct coresight_platform_data *pdata;
	struct device *dev;
	const struct attribute_group **groups;
	const char *name;
};

/**
 * struct coresight_connection - representation of a single connection
 * @outport:	a connection's output port number.
 * @child_port:	remote component's port number @output is connected to.
 * @chid_fwnode: remote component's fwnode handle.
 * @child_dev:	a @coresight_device representation of the component
		connected to @outport.
 * @link: Representation of the connection as a sysfs link.
 */
struct coresight_connection {
	int outport;
	int child_port;
	struct fwnode_handle *child_fwnode;
	struct coresight_device *child_dev;
	struct coresight_sysfs_link *link;
};

/**
 * struct coresight_sysfs_link - representation of a connection in sysfs.
 * @orig:		Originating (master) coresight device for the link.
 * @orig_name:		Name to use for the link orig->target.
 * @target:		Target (slave) coresight device for the link.
 * @target_name:	Name to use for the link target->orig.
 */
struct coresight_sysfs_link {
	struct coresight_device *orig;
	const char *orig_name;
	struct coresight_device *target;
	const char *target_name;
};

/**
 * struct coresight_device - representation of a device as used by the framework
 * @pdata:	Platform data with device connections associated to this device.
 * @type:	as defined by @coresight_dev_type.
 * @subtype:	as defined by @coresight_dev_subtype.
 * @ops:	generic operations for this component, as defined
		by @coresight_ops.
 * @dev:	The device entity associated to this component.
 * @refcnt:	keep track of what is in use.
 * @orphan:	true if the component has connections that haven't been linked.
 * @enable:	'true' if component is currently part of an active path.
 * @activated:	'true' only if a _sink_ has been activated.  A sink can be
 *		activated but not yet enabled.  Enabling for a _sink_
 *		happens when a source has been selected and a path is enabled
 *		from source to that sink.
 * @ea:		Device attribute for sink representation under PMU directory.
 * @def_sink:	cached reference to default sink found for this device.
 * @ect_dev:	Associated cross trigger device. Not part of the trace data
 *		path or connections.
 * @nr_links:   number of sysfs links created to other components from this
 *		device. These will appear in the "connections" group.
 * @has_conns_grp: Have added a "connections" group for sysfs links.
 */
struct coresight_device {
	struct coresight_platform_data *pdata;
	enum coresight_dev_type type;
	union coresight_dev_subtype subtype;
	const struct coresight_ops *ops;
	struct device dev;
	atomic_t *refcnt;
	bool orphan;
	bool enable;	/* true only if configured as part of a path */
	/* sink specific fields */
	bool activated;	/* true only if a sink is part of a path */
	struct dev_ext_attribute *ea;
	struct coresight_device *def_sink;
	/* cross trigger handling */
	struct coresight_device *ect_dev;
	/* sysfs links between components */
	int nr_links;
	bool has_conns_grp;
	bool ect_enabled; /* true only if associated ect device is enabled */
};

/*
 * coresight_dev_list - Mapping for devices to "name" index for device
 * names.
 *
 * @nr_idx:		Number of entries already allocated.
 * @pfx:		Prefix pattern for device name.
 * @fwnode_list:	Array of fwnode_handles associated with each allocated
 *			index, upto nr_idx entries.
 */
struct coresight_dev_list {
	int			nr_idx;
	const char		*pfx;
	struct fwnode_handle	**fwnode_list;
};

#define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx)				\
static struct coresight_dev_list (var) = {				\
						.pfx = dev_pfx,		\
						.nr_idx = 0,		\
						.fwnode_list = NULL,	\
}

#define to_coresight_device(d) container_of(d, struct coresight_device, dev)

#define source_ops(csdev)	csdev->ops->source_ops
#define sink_ops(csdev)		csdev->ops->sink_ops
#define link_ops(csdev)		csdev->ops->link_ops
#define helper_ops(csdev)	csdev->ops->helper_ops
#define ect_ops(csdev)		csdev->ops->ect_ops

/**
 * struct coresight_ops_sink - basic operations for a sink
 * Operations available for sinks
 * @enable:		enables the sink.
 * @disable:		disables the sink.
 * @alloc_buffer:	initialises perf's ring buffer for trace collection.
 * @free_buffer:	release memory allocated in @get_config.
 * @update_buffer:	update buffer pointers after a trace session.
 */
struct coresight_ops_sink {
	int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
	int (*disable)(struct coresight_device *csdev);
	void *(*alloc_buffer)(struct coresight_device *csdev,
			      struct perf_event *event, void **pages,
			      int nr_pages, bool overwrite);
	void (*free_buffer)(void *config);
	unsigned long (*update_buffer)(struct coresight_device *csdev,
			      struct perf_output_handle *handle,
			      void *sink_config);
};

/**
 * struct coresight_ops_link - basic operations for a link
 * Operations available for links.
 * @enable:	enables flow between iport and oport.
 * @disable:	disables flow between iport and oport.
 */
struct coresight_ops_link {
	int (*enable)(struct coresight_device *csdev, int iport, int oport);
	void (*disable)(struct coresight_device *csdev, int iport, int oport);
};

/**
 * struct coresight_ops_source - basic operations for a source
 * Operations available for sources.
 * @cpu_id:	returns the value of the CPU number this component
 *		is associated to.
 * @trace_id:	returns the value of the component's trace ID as known
 *		to the HW.
 * @enable:	enables tracing for a source.
 * @disable:	disables tracing for a source.
 */
struct coresight_ops_source {
	int (*cpu_id)(struct coresight_device *csdev);
	int (*trace_id)(struct coresight_device *csdev);
	int (*enable)(struct coresight_device *csdev,
		      struct perf_event *event,  u32 mode);
	void (*disable)(struct coresight_device *csdev,
			struct perf_event *event);
};

/**
 * struct coresight_ops_helper - Operations for a helper device.
 *
 * All operations could pass in a device specific data, which could
 * help the helper device to determine what to do.
 *
 * @enable	: Enable the device
 * @disable	: Disable the device
 */
struct coresight_ops_helper {
	int (*enable)(struct coresight_device *csdev, void *data);
	int (*disable)(struct coresight_device *csdev, void *data);
};

/**
 * struct coresight_ops_ect - Ops for an embedded cross trigger device
 *
 * @enable	: Enable the device
 * @disable	: Disable the device
 */
struct coresight_ops_ect {
	int (*enable)(struct coresight_device *csdev);
	int (*disable)(struct coresight_device *csdev);
};

struct coresight_ops {
	const struct coresight_ops_sink *sink_ops;
	const struct coresight_ops_link *link_ops;
	const struct coresight_ops_source *source_ops;
	const struct coresight_ops_helper *helper_ops;
	const struct coresight_ops_ect *ect_ops;
};

#if IS_ENABLED(CONFIG_CORESIGHT)
extern struct coresight_device *
coresight_register(struct coresight_desc *desc);
extern void coresight_unregister(struct coresight_device *csdev);
extern int coresight_enable(struct coresight_device *csdev);
extern void coresight_disable(struct coresight_device *csdev);
extern int coresight_timeout(void __iomem *addr, u32 offset,
			     int position, int value);

extern int coresight_claim_device(void __iomem *base);
extern int coresight_claim_device_unlocked(void __iomem *base);

extern void coresight_disclaim_device(void __iomem *base);
extern void coresight_disclaim_device_unlocked(void __iomem *base);
extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
					 struct device *dev);

extern bool coresight_loses_context_with_cpu(struct device *dev);
#else
static inline struct coresight_device *
coresight_register(struct coresight_desc *desc) { return NULL; }
static inline void coresight_unregister(struct coresight_device *csdev) {}
static inline int
coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
static inline void coresight_disable(struct coresight_device *csdev) {}
static inline int coresight_timeout(void __iomem *addr, u32 offset,
				     int position, int value) { return 1; }
static inline int coresight_claim_device_unlocked(void __iomem *base)
{
	return -EINVAL;
}

static inline int coresight_claim_device(void __iomem *base)
{
	return -EINVAL;
}

static inline void coresight_disclaim_device(void __iomem *base) {}
static inline void coresight_disclaim_device_unlocked(void __iomem *base) {}

static inline bool coresight_loses_context_with_cpu(struct device *dev)
{
	return false;
}
#endif

extern int coresight_get_cpu(struct device *dev);

struct coresight_platform_data *coresight_get_platform_data(struct device *dev);

#endif
Commit	Line	Data
ad0dfdfd MP	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2012, The Linux Foundation. All rights reserved.
a06ae860 PP	4	*/
	5
	6	#ifndef _LINUX_CORESIGHT_H
	7	#define _LINUX_CORESIGHT_H
	8
	9	#include <linux/device.h>
882d5e11	10	#include <linux/perf_event.h>
ff63ec13	11	#include <linux/sched.h>
a06ae860 PP	12
	13	/* Peripheral id registers (0xFD0-0xFEC) */
	14	#define CORESIGHT_PERIPHIDR4 0xfd0
	15	#define CORESIGHT_PERIPHIDR5 0xfd4
	16	#define CORESIGHT_PERIPHIDR6 0xfd8
	17	#define CORESIGHT_PERIPHIDR7 0xfdC
	18	#define CORESIGHT_PERIPHIDR0 0xfe0
	19	#define CORESIGHT_PERIPHIDR1 0xfe4
	20	#define CORESIGHT_PERIPHIDR2 0xfe8
	21	#define CORESIGHT_PERIPHIDR3 0xfeC
	22	/* Component id registers (0xFF0-0xFFC) */
	23	#define CORESIGHT_COMPIDR0 0xff0
	24	#define CORESIGHT_COMPIDR1 0xff4
	25	#define CORESIGHT_COMPIDR2 0xff8
	26	#define CORESIGHT_COMPIDR3 0xffC
	27
	28	#define ETM_ARCH_V3_3 0x23
	29	#define ETM_ARCH_V3_5 0x25
	30	#define PFT_ARCH_V1_0 0x30
	31	#define PFT_ARCH_V1_1 0x31
	32
	33	#define CORESIGHT_UNLOCK 0xc5acce55
	34
	35	extern struct bus_type coresight_bustype;
	36
	37	enum coresight_dev_type {
	38	CORESIGHT_DEV_TYPE_NONE,
	39	CORESIGHT_DEV_TYPE_SINK,
	40	CORESIGHT_DEV_TYPE_LINK,
	41	CORESIGHT_DEV_TYPE_LINKSINK,
	42	CORESIGHT_DEV_TYPE_SOURCE,
8a091d84	43	CORESIGHT_DEV_TYPE_HELPER,
835d722b	44	CORESIGHT_DEV_TYPE_ECT,
a06ae860 PP	45	};
	46
	47	enum coresight_dev_subtype_sink {
	48	CORESIGHT_DEV_SUBTYPE_SINK_NONE,
	49	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
	50	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
0336bdfd	51	CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
a06ae860 PP	52	};
	53
	54	enum coresight_dev_subtype_link {
	55	CORESIGHT_DEV_SUBTYPE_LINK_NONE,
	56	CORESIGHT_DEV_SUBTYPE_LINK_MERG,
	57	CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
	58	CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
	59	};
	60
	61	enum coresight_dev_subtype_source {
	62	CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
	63	CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
	64	CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
	65	CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
	66	};
	67
8a091d84 SP	68	enum coresight_dev_subtype_helper {
8a091d84 SP	69	CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
fcacb5c1	70	CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
8a091d84 SP	71	};
8a091d84 SP	72
835d722b ML	73	/* Embedded Cross Trigger (ECT) sub-types */
	74	enum coresight_dev_subtype_ect {
	75	CORESIGHT_DEV_SUBTYPE_ECT_NONE,
	76	CORESIGHT_DEV_SUBTYPE_ECT_CTI,
	77	};
	78
a06ae860	79	/**
00b78e8b	80	* union coresight_dev_subtype - further characterisation of a type
a06ae860	81	* @sink_subtype: type of sink this component is, as defined
00b78e8b	82	* by @coresight_dev_subtype_sink.
a06ae860	83	* @link_subtype: type of link this component is, as defined
00b78e8b	84	* by @coresight_dev_subtype_link.
a06ae860	85	* @source_subtype: type of source this component is, as defined
00b78e8b	86	* by @coresight_dev_subtype_source.
8a091d84 SP	87	* @helper_subtype: type of helper this component is, as defined
8a091d84 SP	88	* by @coresight_dev_subtype_helper.
835d722b ML	89	* @ect_subtype: type of cross trigger this component is, as
835d722b ML	90	* defined by @coresight_dev_subtype_ect
a06ae860	91	*/
00b78e8b SP	92	union coresight_dev_subtype {
	93	/* We have some devices which acts as LINK and SINK */
	94	struct {
	95	enum coresight_dev_subtype_sink sink_subtype;
	96	enum coresight_dev_subtype_link link_subtype;
	97	};
a06ae860	98	enum coresight_dev_subtype_source source_subtype;
8a091d84	99	enum coresight_dev_subtype_helper helper_subtype;
835d722b	100	enum coresight_dev_subtype_ect ect_subtype;
a06ae860 PP	101	};
	102
	103	/**
d375b356 SP	104	* struct coresight_platform_data - data harvested from the firmware
	105	* specification.
	106	*
	107	* @nr_inport: Number of elements for the input connections.
	108	* @nr_outport: Number of elements for the output connections.
	109	* @conns: Sparse array of nr_outport connections from this component.
a06ae860 PP	110	*/
a06ae860 PP	111	struct coresight_platform_data {
a06ae860	112	int nr_inport;
a06ae860	113	int nr_outport;
c2c72941	114	struct coresight_connection *conns;
a06ae860 PP	115	};
	116
	117	/**
	118	* struct coresight_desc - description of a component required from drivers
	119	* @type: as defined by @coresight_dev_type.
	120	* @subtype: as defined by @coresight_dev_subtype.
	121	* @ops: generic operations for this component, as defined
2ede79a6	122	* by @coresight_ops.
a06ae860 PP	123	* @pdata: platform data collected from DT.
a06ae860 PP	124	* @dev: The device entity associated to this component.
8ee885a9	125	* @groups: operations specific to this component. These will end up
2ede79a6 SP	126	* in the component's sysfs sub-directory.
2ede79a6 SP	127	* @name: name for the coresight device, also shown under sysfs.
a06ae860 PP	128	*/
	129	struct coresight_desc {
	130	enum coresight_dev_type type;
00b78e8b	131	union coresight_dev_subtype subtype;
a06ae860 PP	132	const struct coresight_ops *ops;
	133	struct coresight_platform_data *pdata;
	134	struct device *dev;
	135	const struct attribute_group **groups;
2ede79a6	136	const char *name;
a06ae860 PP	137	};
	138
	139	/**
	140	* struct coresight_connection - representation of a single connection
a06ae860	141	* @outport: a connection's output port number.
a06ae860	142	* @child_port: remote component's port number @output is connected to.
37ea1ffd	143	* @chid_fwnode: remote component's fwnode handle.
a06ae860 PP	144	* @child_dev: a @coresight_device representation of the component
a06ae860 PP	145	connected to @outport.
8a7365c2	146	* @link: Representation of the connection as a sysfs link.
a06ae860 PP	147	*/
	148	struct coresight_connection {
	149	int outport;
a06ae860	150	int child_port;
37ea1ffd	151	struct fwnode_handle *child_fwnode;
a06ae860	152	struct coresight_device *child_dev;
8a7365c2	153	struct coresight_sysfs_link *link;
a06ae860 PP	154	};
a06ae860 PP	155
80961525 ML	156	/**
	157	* struct coresight_sysfs_link - representation of a connection in sysfs.
	158	* @orig: Originating (master) coresight device for the link.
	159	* @orig_name: Name to use for the link orig->target.
	160	* @target: Target (slave) coresight device for the link.
	161	* @target_name: Name to use for the link target->orig.
	162	*/
	163	struct coresight_sysfs_link {
	164	struct coresight_device *orig;
	165	const char *orig_name;
	166	struct coresight_device *target;
	167	const char *target_name;
	168	};
	169
a06ae860 PP	170	/**
a06ae860 PP	171	* struct coresight_device - representation of a device as used by the framework
b77e3ed0	172	* @pdata: Platform data with device connections associated to this device.
a06ae860 PP	173	* @type: as defined by @coresight_dev_type.
	174	* @subtype: as defined by @coresight_dev_subtype.
	175	* @ops: generic operations for this component, as defined
	176	by @coresight_ops.
	177	* @dev: The device entity associated to this component.
	178	* @refcnt: keep track of what is in use.
a06ae860 PP	179	* @orphan: true if the component has connections that haven't been linked.
	180	* @enable: 'true' if component is currently part of an active path.
	181	* @activated: 'true' only if a _sink_ has been activated. A sink can be
bb8e370b	182	* activated but not yet enabled. Enabling for a _sink_
d061cd73 ML	183	* happens when a source has been selected and a path is enabled
d061cd73 ML	184	* from source to that sink.
bb8e370b	185	* @ea: Device attribute for sink representation under PMU directory.
0336bdfd	186	* @def_sink: cached reference to default sink found for this device.
177af828 ML	187	* @ect_dev: Associated cross trigger device. Not part of the trace data
177af828 ML	188	* path or connections.
80961525 ML	189	* @nr_links: number of sysfs links created to other components from this
	190	* device. These will appear in the "connections" group.
	191	* @has_conns_grp: Have added a "connections" group for sysfs links.
a06ae860 PP	192	*/
a06ae860 PP	193	struct coresight_device {
b77e3ed0	194	struct coresight_platform_data *pdata;
a06ae860	195	enum coresight_dev_type type;
00b78e8b	196	union coresight_dev_subtype subtype;
a06ae860 PP	197	const struct coresight_ops *ops;
	198	struct device dev;
	199	atomic_t *refcnt;
a06ae860 PP	200	bool orphan;
a06ae860 PP	201	bool enable; /* true only if configured as part of a path */
bb8e370b	202	/* sink specific fields */
a06ae860	203	bool activated; /* true only if a sink is part of a path */
bb8e370b	204	struct dev_ext_attribute *ea;
0336bdfd	205	struct coresight_device *def_sink;
177af828 ML	206	/* cross trigger handling */
177af828 ML	207	struct coresight_device *ect_dev;
80961525 ML	208	/* sysfs links between components */
	209	int nr_links;
	210	bool has_conns_grp;
f2ccc7b7	211	bool ect_enabled; /* true only if associated ect device is enabled */
a06ae860 PP	212	};
a06ae860 PP	213
0f5f9b6b SP	214	/*
	215	* coresight_dev_list - Mapping for devices to "name" index for device
	216	* names.
	217	*
	218	* @nr_idx: Number of entries already allocated.
	219	* @pfx: Prefix pattern for device name.
	220	* @fwnode_list: Array of fwnode_handles associated with each allocated
	221	* index, upto nr_idx entries.
	222	*/
	223	struct coresight_dev_list {
	224	int nr_idx;
	225	const char *pfx;
	226	struct fwnode_handle **fwnode_list;
	227	};
	228
	229	#define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \
	230	static struct coresight_dev_list (var) = { \
	231	.pfx = dev_pfx, \
	232	.nr_idx = 0, \
	233	.fwnode_list = NULL, \
	234	}
	235
a06ae860 PP	236	#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
	237
	238	#define source_ops(csdev) csdev->ops->source_ops
	239	#define sink_ops(csdev) csdev->ops->sink_ops
	240	#define link_ops(csdev) csdev->ops->link_ops
8a091d84	241	#define helper_ops(csdev) csdev->ops->helper_ops
835d722b	242	#define ect_ops(csdev) csdev->ops->ect_ops
a06ae860	243
a06ae860 PP	244	/**
	245	* struct coresight_ops_sink - basic operations for a sink
	246	* Operations available for sinks
2997aa40 MP	247	* @enable: enables the sink.
	248	* @disable: disables the sink.
	249	* @alloc_buffer: initialises perf's ring buffer for trace collection.
	250	* @free_buffer: release memory allocated in @get_config.
2997aa40	251	* @update_buffer: update buffer pointers after a trace session.
a06ae860 PP	252	*/
a06ae860 PP	253	struct coresight_ops_sink {
3d6e8935	254	int (enable)(struct coresight_device csdev, u32 mode, void *data);
6c817a95	255	int (disable)(struct coresight_device csdev);
a0f08a6a MP	256	void (alloc_buffer)(struct coresight_device *csdev,
	257	struct perf_event event, void *pages,
	258	int nr_pages, bool overwrite);
2997aa40	259	void (free_buffer)(void config);
7ec786ad	260	unsigned long (update_buffer)(struct coresight_device csdev,
2997aa40 MP	261	struct perf_output_handle *handle,
2997aa40 MP	262	void *sink_config);
a06ae860 PP	263	};
	264
	265	/**
	266	* struct coresight_ops_link - basic operations for a link
	267	* Operations available for links.
	268	* @enable: enables flow between iport and oport.
	269	* @disable: disables flow between iport and oport.
	270	*/
	271	struct coresight_ops_link {
	272	int (enable)(struct coresight_device csdev, int iport, int oport);
	273	void (disable)(struct coresight_device csdev, int iport, int oport);
	274	};
	275
	276	/**
	277	* struct coresight_ops_source - basic operations for a source
	278	* Operations available for sources.
52210c87 MP	279	* @cpu_id: returns the value of the CPU number this component
52210c87 MP	280	* is associated to.
a06ae860	281	* @trace_id: returns the value of the component's trace ID as known
882d5e11	282	* to the HW.
1d27ff5a	283	* @enable: enables tracing for a source.
a06ae860 PP	284	* @disable: disables tracing for a source.
	285	*/
	286	struct coresight_ops_source {
52210c87	287	int (cpu_id)(struct coresight_device csdev);
a06ae860	288	int (trace_id)(struct coresight_device csdev);
882d5e11	289	int (enable)(struct coresight_device csdev,
68905d73 MP	290	struct perf_event *event, u32 mode);
	291	void (disable)(struct coresight_device csdev,
	292	struct perf_event *event);
a06ae860 PP	293	};
a06ae860 PP	294
8a091d84 SP	295	/**
	296	* struct coresight_ops_helper - Operations for a helper device.
	297	*
	298	* All operations could pass in a device specific data, which could
	299	* help the helper device to determine what to do.
	300	*
	301	* @enable : Enable the device
	302	* @disable : Disable the device
	303	*/
	304	struct coresight_ops_helper {
	305	int (enable)(struct coresight_device csdev, void *data);
	306	int (disable)(struct coresight_device csdev, void *data);
	307	};
	308
835d722b ML	309	/**
	310	* struct coresight_ops_ect - Ops for an embedded cross trigger device
	311	*
	312	* @enable : Enable the device
	313	* @disable : Disable the device
	314	*/
	315	struct coresight_ops_ect {
	316	int (enable)(struct coresight_device csdev);
	317	int (disable)(struct coresight_device csdev);
	318	};
	319
a06ae860 PP	320	struct coresight_ops {
	321	const struct coresight_ops_sink *sink_ops;
	322	const struct coresight_ops_link *link_ops;
	323	const struct coresight_ops_source *source_ops;
8a091d84	324	const struct coresight_ops_helper *helper_ops;
835d722b	325	const struct coresight_ops_ect *ect_ops;
a06ae860 PP	326	};
a06ae860 PP	327
b8127113	328	#if IS_ENABLED(CONFIG_CORESIGHT)
a06ae860 PP	329	extern struct coresight_device *
	330	coresight_register(struct coresight_desc *desc);
	331	extern void coresight_unregister(struct coresight_device *csdev);
	332	extern int coresight_enable(struct coresight_device *csdev);
	333	extern void coresight_disable(struct coresight_device *csdev);
a06ae860 PP	334	extern int coresight_timeout(void __iomem *addr, u32 offset,
a06ae860 PP	335	int position, int value);
2478a6ae SP	336
	337	extern int coresight_claim_device(void __iomem *base);
	338	extern int coresight_claim_device_unlocked(void __iomem *base);
	339
	340	extern void coresight_disclaim_device(void __iomem *base);
	341	extern void coresight_disclaim_device_unlocked(void __iomem *base);
0f5f9b6b SP	342	extern char coresight_alloc_device_name(struct coresight_dev_list devs,
0f5f9b6b SP	343	struct device *dev);
f188b5e7 AM	344
f188b5e7 AM	345	extern bool coresight_loses_context_with_cpu(struct device *dev);
a06ae860 PP	346	#else
	347	static inline struct coresight_device *
	348	coresight_register(struct coresight_desc *desc) { return NULL; }
	349	static inline void coresight_unregister(struct coresight_device *csdev) {}
	350	static inline int
	351	coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
	352	static inline void coresight_disable(struct coresight_device *csdev) {}
a06ae860 PP	353	static inline int coresight_timeout(void __iomem *addr, u32 offset,
a06ae860 PP	354	int position, int value) { return 1; }
2478a6ae SP	355	static inline int coresight_claim_device_unlocked(void __iomem *base)
	356	{
	357	return -EINVAL;
	358	}
	359
	360	static inline int coresight_claim_device(void __iomem *base)
	361	{
	362	return -EINVAL;
	363	}
	364
	365	static inline void coresight_disclaim_device(void __iomem *base) {}
	366	static inline void coresight_disclaim_device_unlocked(void __iomem *base) {}
	367
f188b5e7 AM	368	static inline bool coresight_loses_context_with_cpu(struct device *dev)
	369	{
	370	return false;
	371	}
c61c4b5d MP	372	#endif
c61c4b5d MP	373
91824db2	374	extern int coresight_get_cpu(struct device *dev);
a06ae860	375
f03631da SP	376	struct coresight_platform_data coresight_get_platform_data(struct device dev);
f03631da SP	377
a06ae860	378	#endif