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[PATCH] Fix swsusp with PNP BIOS
[linux.git] / drivers / net / smc91x.h
CommitLineData
1da177e4
LT		 1/*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <[email protected]>
30 . Daris A Nevil <[email protected]>
31 . Nicolas Pitre <[email protected]>
32 .
33 ---------------------------------------------------------------------------*/
34#ifndef _SMC91X_H_
35#define _SMC91X_H_
36
37
38/*
39 * Define your architecture specific bus configuration parameters here.
40 */
41
42#if defined(CONFIG_ARCH_LUBBOCK)
43
44/* We can only do 16-bit reads and writes in the static memory space. */
45#define SMC_CAN_USE_8BIT 0
46#define SMC_CAN_USE_16BIT 1
47#define SMC_CAN_USE_32BIT 0
48#define SMC_NOWAIT 1
49
50/* The first two address lines aren't connected... */
51#define SMC_IO_SHIFT 2
52
53#define SMC_inw(a, r) readw((a) + (r))
54#define SMC_outw(v, a, r) writew(v, (a) + (r))
55#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
57
58#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
59
60/* We can only do 16-bit reads and writes in the static memory space. */
61#define SMC_CAN_USE_8BIT 0
62#define SMC_CAN_USE_16BIT 1
63#define SMC_CAN_USE_32BIT 0
64#define SMC_NOWAIT 1
65
66#define SMC_IO_SHIFT 0
67
68#define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
69#define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
70#define SMC_insw(a, r, p, l) \
71 do { \
72 unsigned long __port = (a) + (r); \
73 u16 *__p = (u16 *)(p); \
74 int __l = (l); \
75 insw(__port, __p, __l); \
76 while (__l > 0) { \
77 *__p = swab16(*__p); \
78 __p++; \
79 __l--; \
80 } \
81 } while (0)
82#define SMC_outsw(a, r, p, l) \
83 do { \
84 unsigned long __port = (a) + (r); \
85 u16 *__p = (u16 *)(p); \
86 int __l = (l); \
87 while (__l > 0) { \
88 /* Believe it or not, the swab isn't needed. */ \
89 outw( /* swab16 */ (*__p++), __port); \
90 __l--; \
91 } \
92 } while (0)
9ded96f2 93#define SMC_IRQ_FLAGS (0)
1da177e4
LT		 94
95#elif defined(CONFIG_SA1100_PLEB)
96/* We can only do 16-bit reads and writes in the static memory space. */
97#define SMC_CAN_USE_8BIT 1
98#define SMC_CAN_USE_16BIT 1
99#define SMC_CAN_USE_32BIT 0
100#define SMC_IO_SHIFT 0
101#define SMC_NOWAIT 1
102
1cf99be5
RK		 103#define SMC_inb(a, r) readb((a) + (r))
104#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
105#define SMC_inw(a, r) readw((a) + (r))
106#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
107#define SMC_outb(v, a, r) writeb(v, (a) + (r))
108#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
109#define SMC_outw(v, a, r) writew(v, (a) + (r))
110#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
1da177e4 111
9ded96f2 112#define SMC_IRQ_FLAGS (0)
1da177e4
LT		 113
114#elif defined(CONFIG_SA1100_ASSABET)
115
116#include <asm/arch/neponset.h>
117
118/* We can only do 8-bit reads and writes in the static memory space. */
119#define SMC_CAN_USE_8BIT 1
120#define SMC_CAN_USE_16BIT 0
121#define SMC_CAN_USE_32BIT 0
122#define SMC_NOWAIT 1
123
124/* The first two address lines aren't connected... */
125#define SMC_IO_SHIFT 2
126
127#define SMC_inb(a, r) readb((a) + (r))
128#define SMC_outb(v, a, r) writeb(v, (a) + (r))
129#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
130#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
131
b0348b90
LB		 132#elif defined(CONFIG_MACH_LOGICPD_PXA270)
133
134#define SMC_CAN_USE_8BIT 0
135#define SMC_CAN_USE_16BIT 1
136#define SMC_CAN_USE_32BIT 0
137#define SMC_IO_SHIFT 0
138#define SMC_NOWAIT 1
139#define SMC_USE_PXA_DMA 1
140
141#define SMC_inb(a, r) readb((a) + (r))
142#define SMC_inw(a, r) readw((a) + (r))
143#define SMC_inl(a, r) readl((a) + (r))
144#define SMC_outb(v, a, r) writeb(v, (a) + (r))
145#define SMC_outw(v, a, r) writew(v, (a) + (r))
146#define SMC_outl(v, a, r) writel(v, (a) + (r))
147#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
148#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
149
1da177e4
LT		 150#elif defined(CONFIG_ARCH_INNOKOM) || \
151 defined(CONFIG_MACH_MAINSTONE) || \
152 defined(CONFIG_ARCH_PXA_IDP) || \
153 defined(CONFIG_ARCH_RAMSES)
154
155#define SMC_CAN_USE_8BIT 1
156#define SMC_CAN_USE_16BIT 1
157#define SMC_CAN_USE_32BIT 1
158#define SMC_IO_SHIFT 0
159#define SMC_NOWAIT 1
160#define SMC_USE_PXA_DMA 1
161
162#define SMC_inb(a, r) readb((a) + (r))
163#define SMC_inw(a, r) readw((a) + (r))
164#define SMC_inl(a, r) readl((a) + (r))
165#define SMC_outb(v, a, r) writeb(v, (a) + (r))
166#define SMC_outl(v, a, r) writel(v, (a) + (r))
167#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
168#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
169
170/* We actually can't write halfwords properly if not word aligned */
171static inline void
eb1d6988 172SMC_outw(u16 val, void __iomem *ioaddr, int reg)
1da177e4
LT		 173{
174 if (reg & 2) {
175 unsigned int v = val << 16;
176 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
177 writel(v, ioaddr + (reg & ~2));
178 } else {
179 writew(val, ioaddr + reg);
180 }
181}
182
183#elif defined(CONFIG_ARCH_OMAP)
184
185/* We can only do 16-bit reads and writes in the static memory space. */
186#define SMC_CAN_USE_8BIT 0
187#define SMC_CAN_USE_16BIT 1
188#define SMC_CAN_USE_32BIT 0
189#define SMC_IO_SHIFT 0
190#define SMC_NOWAIT 1
191
192#define SMC_inb(a, r) readb((a) + (r))
193#define SMC_outb(v, a, r) writeb(v, (a) + (r))
194#define SMC_inw(a, r) readw((a) + (r))
195#define SMC_outw(v, a, r) writew(v, (a) + (r))
196#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
197#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
198#define SMC_inl(a, r) readl((a) + (r))
199#define SMC_outl(v, a, r) writel(v, (a) + (r))
200#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
201#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
202
5f13e7ec
DB		 203#include <asm/mach-types.h>
204#include <asm/arch/cpu.h>
205
9ded96f2 206#define SMC_IRQ_FLAGS (( \
5f13e7ec
DB		 207 machine_is_omap_h2() \
208 || machine_is_omap_h3() \
af44f5bf 209 || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
1fb9df5d 210 ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)
5f13e7ec
DB		 211
212
1da177e4
LT		 213#elif defined(CONFIG_SH_SH4202_MICRODEV)
214
215#define SMC_CAN_USE_8BIT 0
216#define SMC_CAN_USE_16BIT 1
217#define SMC_CAN_USE_32BIT 0
218
219#define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
220#define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
221#define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
222#define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
223#define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
224#define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
225#define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
226#define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
227#define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
228#define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
229
9ded96f2 230#define SMC_IRQ_FLAGS (0)
1da177e4
LT		 231
232#elif defined(CONFIG_ISA)
233
234#define SMC_CAN_USE_8BIT 1
235#define SMC_CAN_USE_16BIT 1
236#define SMC_CAN_USE_32BIT 0
237
238#define SMC_inb(a, r) inb((a) + (r))
239#define SMC_inw(a, r) inw((a) + (r))
240#define SMC_outb(v, a, r) outb(v, (a) + (r))
241#define SMC_outw(v, a, r) outw(v, (a) + (r))
242#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
243#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
244
245#elif defined(CONFIG_M32R)
246
247#define SMC_CAN_USE_8BIT 0
248#define SMC_CAN_USE_16BIT 1
249#define SMC_CAN_USE_32BIT 0
250
f3ac9fbf
HT		 251#define SMC_inb(a, r) inb((u32)a) + (r))
252#define SMC_inw(a, r) inw(((u32)a) + (r))
253#define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
254#define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
255#define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
256#define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
1da177e4 257
9ded96f2 258#define SMC_IRQ_FLAGS (0)
1da177e4
LT		 259
260#define RPC_LSA_DEFAULT RPC_LED_TX_RX
261#define RPC_LSB_DEFAULT RPC_LED_100_10
262
d4adcffb
MS		 263#elif defined(CONFIG_MACH_LPD79520) \
264 || defined(CONFIG_MACH_LPD7A400) \
265 || defined(CONFIG_MACH_LPD7A404)
1da177e4 266
d4adcffb
MS		 267/* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
268 * way that the CPU handles chip selects and the way that the SMC chip
269 * expects the chip select to operate. Refer to
1da177e4 270 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
d4adcffb
MS		 271 * IOBARRIER is a byte, in order that we read the least-common
272 * denominator. It would be wasteful to read 32 bits from an 8-bit
273 * accessible region.
1da177e4
LT		 274 *
275 * There is no explicit protection against interrupts intervening
276 * between the writew and the IOBARRIER. In SMC ISR there is a
277 * preamble that performs an IOBARRIER in the extremely unlikely event
278 * that the driver interrupts itself between a writew to the chip an
279 * the IOBARRIER that follows *and* the cache is large enough that the
280 * first off-chip access while handing the interrupt is to the SMC
281 * chip. Other devices in the same address space as the SMC chip must
282 * be aware of the potential for trouble and perform a similar
283 * IOBARRIER on entry to their ISR.
284 */
285
286#include <asm/arch/constants.h> /* IOBARRIER_VIRT */
287
288#define SMC_CAN_USE_8BIT 0
289#define SMC_CAN_USE_16BIT 1
290#define SMC_CAN_USE_32BIT 0
291#define SMC_NOWAIT 0
d4adcffb 292#define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
1da177e4 293
d4adcffb
MS		 294#define SMC_inw(a,r)\
295 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
296#define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
1da177e4 297
d4adcffb
MS		 298#define SMC_insw LPD7_SMC_insw
299static inline void LPD7_SMC_insw (unsigned char* a, int r,
300 unsigned char* p, int l)
301{
302 unsigned short* ps = (unsigned short*) p;
303 while (l-- > 0) {
304 *ps++ = readw (a + r);
305 LPD7X_IOBARRIER;
306 }
307}
09779c6d 308
d4adcffb
MS		 309#define SMC_outsw LPD7_SMC_outsw
310static inline void LPD7_SMC_outsw (unsigned char* a, int r,
311 unsigned char* p, int l)
1da177e4
LT		 312{
313 unsigned short* ps = (unsigned short*) p;
314 while (l-- > 0) {
315 writew (*ps++, a + r);
d4adcffb 316 LPD7X_IOBARRIER;
1da177e4
LT		 317 }
318}
319
d4adcffb 320#define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
1da177e4
LT		 321
322#define RPC_LSA_DEFAULT RPC_LED_TX_RX
323#define RPC_LSB_DEFAULT RPC_LED_100_10
324
55793455
PP		 325#elif defined(CONFIG_SOC_AU1X00)
326
327#include <au1xxx.h>
328
329/* We can only do 16-bit reads and writes in the static memory space. */
330#define SMC_CAN_USE_8BIT 0
331#define SMC_CAN_USE_16BIT 1
332#define SMC_CAN_USE_32BIT 0
333#define SMC_IO_SHIFT 0
334#define SMC_NOWAIT 1
335
336#define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
337#define SMC_insw(a, r, p, l) \
338 do { \
339 unsigned long _a = (unsigned long)((a) + (r)); \
340 int _l = (l); \
341 u16 *_p = (u16 *)(p); \
342 while (_l-- > 0) \
343 *_p++ = au_readw(_a); \
344 } while(0)
345#define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
346#define SMC_outsw(a, r, p, l) \
347 do { \
348 unsigned long _a = (unsigned long)((a) + (r)); \
349 int _l = (l); \
350 const u16 *_p = (const u16 *)(p); \
351 while (_l-- > 0) \
352 au_writew(*_p++ , _a); \
353 } while(0)
354
9ded96f2 355#define SMC_IRQ_FLAGS (0)
55793455 356
8431adfd
DS		 357#elif defined(CONFIG_ARCH_VERSATILE)
358
359#define SMC_CAN_USE_8BIT 1
360#define SMC_CAN_USE_16BIT 1
361#define SMC_CAN_USE_32BIT 1
362#define SMC_NOWAIT 1
363
364#define SMC_inb(a, r) readb((a) + (r))
365#define SMC_inw(a, r) readw((a) + (r))
366#define SMC_inl(a, r) readl((a) + (r))
367#define SMC_outb(v, a, r) writeb(v, (a) + (r))
368#define SMC_outw(v, a, r) writew(v, (a) + (r))
369#define SMC_outl(v, a, r) writel(v, (a) + (r))
370#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
371#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
372
373#define SMC_IRQ_FLAGS (0)
374
1da177e4
LT		 375#else
376
377#define SMC_CAN_USE_8BIT 1
378#define SMC_CAN_USE_16BIT 1
379#define SMC_CAN_USE_32BIT 1
380#define SMC_NOWAIT 1
381
382#define SMC_inb(a, r) readb((a) + (r))
383#define SMC_inw(a, r) readw((a) + (r))
384#define SMC_inl(a, r) readl((a) + (r))
385#define SMC_outb(v, a, r) writeb(v, (a) + (r))
386#define SMC_outw(v, a, r) writew(v, (a) + (r))
387#define SMC_outl(v, a, r) writel(v, (a) + (r))
388#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
389#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
390
391#define RPC_LSA_DEFAULT RPC_LED_100_10
392#define RPC_LSB_DEFAULT RPC_LED_TX_RX
393
394#endif
395
1da177e4
LT		 396#ifdef SMC_USE_PXA_DMA
397/*
398 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
399 * always happening in irq context so no need to worry about races. TX is
400 * different and probably not worth it for that reason, and not as critical
401 * as RX which can overrun memory and lose packets.
402 */
403#include <linux/dma-mapping.h>
404#include <asm/dma.h>
405#include <asm/arch/pxa-regs.h>
406
407#ifdef SMC_insl
408#undef SMC_insl
409#define SMC_insl(a, r, p, l) \
410 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
411static inline void
eb1d6988 412smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
1da177e4
LT		 413 u_char *buf, int len)
414{
415 dma_addr_t dmabuf;
416
417 /* fallback if no DMA available */
418 if (dma == (unsigned char)-1) {
419 readsl(ioaddr + reg, buf, len);
420 return;
421 }
422
423 /* 64 bit alignment is required for memory to memory DMA */
424 if ((long)buf & 4) {
425 *((u32 *)buf) = SMC_inl(ioaddr, reg);
426 buf += 4;
427 len--;
428 }
429
430 len *= 4;
431 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
432 DCSR(dma) = DCSR_NODESC;
433 DTADR(dma) = dmabuf;
434 DSADR(dma) = physaddr + reg;
435 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
436 DCMD_WIDTH4 | (DCMD_LENGTH & len));
437 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
438 while (!(DCSR(dma) & DCSR_STOPSTATE))
439 cpu_relax();
440 DCSR(dma) = 0;
441 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
442}
443#endif
444
445#ifdef SMC_insw
446#undef SMC_insw
447#define SMC_insw(a, r, p, l) \
448 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
449static inline void
eb1d6988 450smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
1da177e4
LT		 451 u_char *buf, int len)
452{
453 dma_addr_t dmabuf;
454
455 /* fallback if no DMA available */
456 if (dma == (unsigned char)-1) {
457 readsw(ioaddr + reg, buf, len);
458 return;
459 }
460
461 /* 64 bit alignment is required for memory to memory DMA */
462 while ((long)buf & 6) {
463 *((u16 *)buf) = SMC_inw(ioaddr, reg);
464 buf += 2;
465 len--;
466 }
467
468 len *= 2;
469 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
470 DCSR(dma) = DCSR_NODESC;
471 DTADR(dma) = dmabuf;
472 DSADR(dma) = physaddr + reg;
473 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
474 DCMD_WIDTH2 | (DCMD_LENGTH & len));
475 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
476 while (!(DCSR(dma) & DCSR_STOPSTATE))
477 cpu_relax();
478 DCSR(dma) = 0;
479 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
480}
481#endif
482
483static void
484smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs)
485{
486 DCSR(dma) = 0;
487}
488#endif /* SMC_USE_PXA_DMA */
489
490
09779c6d
NP		 491/*
492 * Everything a particular hardware setup needs should have been defined
493 * at this point. Add stubs for the undefined cases, mainly to avoid
494 * compilation warnings since they'll be optimized away, or to prevent buggy
495 * use of them.
496 */
497
498#if ! SMC_CAN_USE_32BIT
499#define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
500#define SMC_outl(x, ioaddr, reg) BUG()
501#define SMC_insl(a, r, p, l) BUG()
502#define SMC_outsl(a, r, p, l) BUG()
503#endif
504
505#if !defined(SMC_insl) || !defined(SMC_outsl)
506#define SMC_insl(a, r, p, l) BUG()
507#define SMC_outsl(a, r, p, l) BUG()
508#endif
509
510#if ! SMC_CAN_USE_16BIT
511
512/*
513 * Any 16-bit access is performed with two 8-bit accesses if the hardware
514 * can't do it directly. Most registers are 16-bit so those are mandatory.
515 */
516#define SMC_outw(x, ioaddr, reg) \
517 do { \
518 unsigned int __val16 = (x); \
519 SMC_outb( __val16, ioaddr, reg ); \
520 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
521 } while (0)
522#define SMC_inw(ioaddr, reg) \
523 ({ \
524 unsigned int __val16; \
525 __val16 = SMC_inb( ioaddr, reg ); \
526 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
527 __val16; \
528 })
529
530#define SMC_insw(a, r, p, l) BUG()
531#define SMC_outsw(a, r, p, l) BUG()
532
533#endif
534
535#if !defined(SMC_insw) || !defined(SMC_outsw)
536#define SMC_insw(a, r, p, l) BUG()
537#define SMC_outsw(a, r, p, l) BUG()
538#endif
539
540#if ! SMC_CAN_USE_8BIT
541#define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
542#define SMC_outb(x, ioaddr, reg) BUG()
543#define SMC_insb(a, r, p, l) BUG()
544#define SMC_outsb(a, r, p, l) BUG()
545#endif
546
547#if !defined(SMC_insb) || !defined(SMC_outsb)
548#define SMC_insb(a, r, p, l) BUG()
549#define SMC_outsb(a, r, p, l) BUG()
550#endif
551
552#ifndef SMC_CAN_USE_DATACS
553#define SMC_CAN_USE_DATACS 0
554#endif
555
1da177e4
LT		 556#ifndef SMC_IO_SHIFT
557#define SMC_IO_SHIFT 0
558#endif
09779c6d
NP		 559
560#ifndef SMC_IRQ_FLAGS
1fb9df5d 561#define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
09779c6d
NP		 562#endif
563
564#ifndef SMC_INTERRUPT_PREAMBLE
565#define SMC_INTERRUPT_PREAMBLE
566#endif
567
568
569/* Because of bank switching, the LAN91x uses only 16 I/O ports */
1da177e4
LT		 570#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
571#define SMC_DATA_EXTENT (4)
572
573/*
574 . Bank Select Register:
575 .
576 . yyyy yyyy 0000 00xx
577 . xx = bank number
578 . yyyy yyyy = 0x33, for identification purposes.
579*/
580#define BANK_SELECT (14 << SMC_IO_SHIFT)
581
582
583// Transmit Control Register
584/* BANK 0 */
585#define TCR_REG SMC_REG(0x0000, 0)
586#define TCR_ENABLE 0x0001 // When 1 we can transmit
587#define TCR_LOOP 0x0002 // Controls output pin LBK
588#define TCR_FORCOL 0x0004 // When 1 will force a collision
589#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
590#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
591#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
592#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
593#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
594#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
595#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
596
597#define TCR_CLEAR 0 /* do NOTHING */
598/* the default settings for the TCR register : */
599#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
600
601
602// EPH Status Register
603/* BANK 0 */
604#define EPH_STATUS_REG SMC_REG(0x0002, 0)
605#define ES_TX_SUC 0x0001 // Last TX was successful
606#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
607#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
608#define ES_LTX_MULT 0x0008 // Last tx was a multicast
609#define ES_16COL 0x0010 // 16 Collisions Reached
610#define ES_SQET 0x0020 // Signal Quality Error Test
611#define ES_LTXBRD 0x0040 // Last tx was a broadcast
612#define ES_TXDEFR 0x0080 // Transmit Deferred
613#define ES_LATCOL 0x0200 // Late collision detected on last tx
614#define ES_LOSTCARR 0x0400 // Lost Carrier Sense
615#define ES_EXC_DEF 0x0800 // Excessive Deferral
616#define ES_CTR_ROL 0x1000 // Counter Roll Over indication
617#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
618#define ES_TXUNRN 0x8000 // Tx Underrun
619
620
621// Receive Control Register
622/* BANK 0 */
623#define RCR_REG SMC_REG(0x0004, 0)
624#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
625#define RCR_PRMS 0x0002 // Enable promiscuous mode
626#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
627#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
628#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
629#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
630#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
631#define RCR_SOFTRST 0x8000 // resets the chip
632
633/* the normal settings for the RCR register : */
634#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
635#define RCR_CLEAR 0x0 // set it to a base state
636
637
638// Counter Register
639/* BANK 0 */
640#define COUNTER_REG SMC_REG(0x0006, 0)
641
642
643// Memory Information Register
644/* BANK 0 */
645#define MIR_REG SMC_REG(0x0008, 0)
646
647
648// Receive/Phy Control Register
649/* BANK 0 */
650#define RPC_REG SMC_REG(0x000A, 0)
651#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
652#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
653#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
654#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
655#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
656#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
657#define RPC_LED_RES (0x01) // LED = Reserved
658#define RPC_LED_10 (0x02) // LED = 10Mbps link detect
659#define RPC_LED_FD (0x03) // LED = Full Duplex Mode
660#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
661#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
662#define RPC_LED_TX (0x06) // LED = TX packet occurred
663#define RPC_LED_RX (0x07) // LED = RX packet occurred
664
665#ifndef RPC_LSA_DEFAULT
666#define RPC_LSA_DEFAULT RPC_LED_100
667#endif
668#ifndef RPC_LSB_DEFAULT
669#define RPC_LSB_DEFAULT RPC_LED_FD
670#endif
671
672#define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
673
674
675/* Bank 0 0x0C is reserved */
676
677// Bank Select Register
678/* All Banks */
679#define BSR_REG 0x000E
680
681
682// Configuration Reg
683/* BANK 1 */
684#define CONFIG_REG SMC_REG(0x0000, 1)
685#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
686#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
687#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
688#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
689
690// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
691#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
692
693
694// Base Address Register
695/* BANK 1 */
696#define BASE_REG SMC_REG(0x0002, 1)
697
698
699// Individual Address Registers
700/* BANK 1 */
701#define ADDR0_REG SMC_REG(0x0004, 1)
702#define ADDR1_REG SMC_REG(0x0006, 1)
703#define ADDR2_REG SMC_REG(0x0008, 1)
704
705
706// General Purpose Register
707/* BANK 1 */
708#define GP_REG SMC_REG(0x000A, 1)
709
710
711// Control Register
712/* BANK 1 */
713#define CTL_REG SMC_REG(0x000C, 1)
714#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
715#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
716#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
717#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
718#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
719#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
720#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
721#define CTL_STORE 0x0001 // When set stores registers into EEPROM
722
723
724// MMU Command Register
725/* BANK 2 */
726#define MMU_CMD_REG SMC_REG(0x0000, 2)
727#define MC_BUSY 1 // When 1 the last release has not completed
728#define MC_NOP (0<<5) // No Op
729#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
730#define MC_RESET (2<<5) // Reset MMU to initial state
731#define MC_REMOVE (3<<5) // Remove the current rx packet
732#define MC_RELEASE (4<<5) // Remove and release the current rx packet
733#define MC_FREEPKT (5<<5) // Release packet in PNR register
734#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
735#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
736
737
738// Packet Number Register
739/* BANK 2 */
740#define PN_REG SMC_REG(0x0002, 2)
741
742
743// Allocation Result Register
744/* BANK 2 */
745#define AR_REG SMC_REG(0x0003, 2)
746#define AR_FAILED 0x80 // Alocation Failed
747
748
749// TX FIFO Ports Register
750/* BANK 2 */
751#define TXFIFO_REG SMC_REG(0x0004, 2)
752#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
753
754// RX FIFO Ports Register
755/* BANK 2 */
756#define RXFIFO_REG SMC_REG(0x0005, 2)
757#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
758
759#define FIFO_REG SMC_REG(0x0004, 2)
760
761// Pointer Register
762/* BANK 2 */
763#define PTR_REG SMC_REG(0x0006, 2)
764#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
765#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
766#define PTR_READ 0x2000 // When 1 the operation is a read
767
768
769// Data Register
770/* BANK 2 */
771#define DATA_REG SMC_REG(0x0008, 2)
772
773
774// Interrupt Status/Acknowledge Register
775/* BANK 2 */
776#define INT_REG SMC_REG(0x000C, 2)
777
778
779// Interrupt Mask Register
780/* BANK 2 */
781#define IM_REG SMC_REG(0x000D, 2)
782#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
783#define IM_ERCV_INT 0x40 // Early Receive Interrupt
784#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
785#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
786#define IM_ALLOC_INT 0x08 // Set when allocation request is completed
787#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
788#define IM_TX_INT 0x02 // Transmit Interrupt
789#define IM_RCV_INT 0x01 // Receive Interrupt
790
791
792// Multicast Table Registers
793/* BANK 3 */
794#define MCAST_REG1 SMC_REG(0x0000, 3)
795#define MCAST_REG2 SMC_REG(0x0002, 3)
796#define MCAST_REG3 SMC_REG(0x0004, 3)
797#define MCAST_REG4 SMC_REG(0x0006, 3)
798
799
800// Management Interface Register (MII)
801/* BANK 3 */
802#define MII_REG SMC_REG(0x0008, 3)
803#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
804#define MII_MDOE 0x0008 // MII Output Enable
805#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
806#define MII_MDI 0x0002 // MII Input, pin MDI
807#define MII_MDO 0x0001 // MII Output, pin MDO
808
809
810// Revision Register
811/* BANK 3 */
812/* ( hi: chip id low: rev # ) */
813#define REV_REG SMC_REG(0x000A, 3)
814
815
816// Early RCV Register
817/* BANK 3 */
818/* this is NOT on SMC9192 */
819#define ERCV_REG SMC_REG(0x000C, 3)
820#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
821#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
822
823
824// External Register
825/* BANK 7 */
826#define EXT_REG SMC_REG(0x0000, 7)
827
828
829#define CHIP_9192 3
830#define CHIP_9194 4
831#define CHIP_9195 5
832#define CHIP_9196 6
833#define CHIP_91100 7
834#define CHIP_91100FD 8
835#define CHIP_91111FD 9
836
837static const char * chip_ids[ 16 ] = {
838 NULL, NULL, NULL,
839 /* 3 */ "SMC91C90/91C92",
840 /* 4 */ "SMC91C94",
841 /* 5 */ "SMC91C95",
842 /* 6 */ "SMC91C96",
843 /* 7 */ "SMC91C100",
844 /* 8 */ "SMC91C100FD",
845 /* 9 */ "SMC91C11xFD",
846 NULL, NULL, NULL,
847 NULL, NULL, NULL};
848
849
1da177e4
LT		 850/*
851 . Receive status bits
852*/
853#define RS_ALGNERR 0x8000
854#define RS_BRODCAST 0x4000
855#define RS_BADCRC 0x2000
856#define RS_ODDFRAME 0x1000
857#define RS_TOOLONG 0x0800
858#define RS_TOOSHORT 0x0400
859#define RS_MULTICAST 0x0001
860#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
861
862
863/*
864 * PHY IDs
865 * LAN83C183 == LAN91C111 Internal PHY
866 */
867#define PHY_LAN83C183 0x0016f840
868#define PHY_LAN83C180 0x02821c50
869
870/*
871 * PHY Register Addresses (LAN91C111 Internal PHY)
872 *
873 * Generic PHY registers can be found in <linux/mii.h>
874 *
875 * These phy registers are specific to our on-board phy.
876 */
877
878// PHY Configuration Register 1
879#define PHY_CFG1_REG 0x10
880#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
881#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
882#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
883#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
884#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
885#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
886#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
887#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
888#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
889#define PHY_CFG1_TLVL_MASK 0x003C
890#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
891
892
893// PHY Configuration Register 2
894#define PHY_CFG2_REG 0x11
895#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
896#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
897#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
898#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
899
900// PHY Status Output (and Interrupt status) Register
901#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
902#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
903#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
904#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
905#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
906#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
907#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
908#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
909#define PHY_INT_JAB 0x0100 // 1=Jabber detected
910#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
911#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
912
913// PHY Interrupt/Status Mask Register
914#define PHY_MASK_REG 0x13 // Interrupt Mask
915// Uses the same bit definitions as PHY_INT_REG
916
917
918/*
919 * SMC91C96 ethernet config and status registers.
920 * These are in the "attribute" space.
921 */
922#define ECOR 0x8000
923#define ECOR_RESET 0x80
924#define ECOR_LEVEL_IRQ 0x40
925#define ECOR_WR_ATTRIB 0x04
926#define ECOR_ENABLE 0x01
927
928#define ECSR 0x8002
929#define ECSR_IOIS8 0x20
930#define ECSR_PWRDWN 0x04
931#define ECSR_INT 0x02
932
933#define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
934
935
936/*
937 * Macros to abstract register access according to the data bus
938 * capabilities. Please use those and not the in/out primitives.
939 * Note: the following macros do *not* select the bank -- this must
940 * be done separately as needed in the main code. The SMC_REG() macro
941 * only uses the bank argument for debugging purposes (when enabled).
09779c6d
NP		 942 *
943 * Note: despite inline functions being safer, everything leading to this
944 * should preferably be macros to let BUG() display the line number in
945 * the core source code since we're interested in the top call site
946 * not in any inline function location.
1da177e4
LT		 947 */
948
949#if SMC_DEBUG > 0
950#define SMC_REG(reg, bank) \
951 ({ \
952 int __b = SMC_CURRENT_BANK(); \
953 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
954 printk( "%s: bank reg screwed (0x%04x)\n", \
955 CARDNAME, __b ); \
956 BUG(); \
957 } \
958 reg<<SMC_IO_SHIFT; \
959 })
960#else
961#define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
962#endif
963
09779c6d
NP		 964/*
965 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
966 * aligned to a 32 bit boundary. I tell you that does exist!
967 * Fortunately the affected register accesses can be easily worked around
968 * since we can write zeroes to the preceeding 16 bits without adverse
969 * effects and use a 32-bit access.
970 *
971 * Enforce it on any 32-bit capable setup for now.
972 */
973#define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
974
975#define SMC_GET_PN() \
976 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
977 : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
978
979#define SMC_SET_PN(x) \
980 do { \
981 if (SMC_MUST_ALIGN_WRITE) \
982 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
983 else if (SMC_CAN_USE_8BIT) \
984 SMC_outb(x, ioaddr, PN_REG); \
985 else \
986 SMC_outw(x, ioaddr, PN_REG); \
987 } while (0)
988
989#define SMC_GET_AR() \
990 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
991 : (SMC_inw(ioaddr, PN_REG) >> 8) )
992
993#define SMC_GET_TXFIFO() \
994 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
995 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
996
997#define SMC_GET_RXFIFO() \
998 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
999 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
1000
1001#define SMC_GET_INT() \
1002 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
1003 : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
1004
1da177e4
LT		 1005#define SMC_ACK_INT(x) \
1006 do { \
09779c6d
NP		 1007 if (SMC_CAN_USE_8BIT) \
1008 SMC_outb(x, ioaddr, INT_REG); \
1009 else { \
1010 unsigned long __flags; \
1011 int __mask; \
1012 local_irq_save(__flags); \
1013 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
1014 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
1015 local_irq_restore(__flags); \
1016 } \
1017 } while (0)
1018
1019#define SMC_GET_INT_MASK() \
1020 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
1021 : (SMC_inw( ioaddr, INT_REG ) >> 8) )
1022
1023#define SMC_SET_INT_MASK(x) \
1024 do { \
1025 if (SMC_CAN_USE_8BIT) \
1026 SMC_outb(x, ioaddr, IM_REG); \
1027 else \
1028 SMC_outw((x) << 8, ioaddr, INT_REG); \
1029 } while (0)
1030
1031#define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
1032
1033#define SMC_SELECT_BANK(x) \
1034 do { \
1035 if (SMC_MUST_ALIGN_WRITE) \
1036 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1037 else \
1038 SMC_outw(x, ioaddr, BANK_SELECT); \
1039 } while (0)
1040
1041#define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
1042
1043#define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
1044
1045#define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
1046
1047#define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
1048
1049#define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
1050
1051#define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
1052
1053#define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
1054
1055#define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
1056
1057#define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
1058
1059#define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
1060
1061#define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
1062
1063#define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
1064
1065#define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
1066
1067#define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
1068
1069#define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
1070
1071#define SMC_SET_PTR(x) \
1072 do { \
1073 if (SMC_MUST_ALIGN_WRITE) \
1074 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
1075 else \
1076 SMC_outw(x, ioaddr, PTR_REG); \
1da177e4 1077 } while (0)
1da177e4 1078
09779c6d
NP		 1079#define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
1080
1081#define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
1082
1083#define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
1084
1085#define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
1086
1087#define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
1088
1089#define SMC_SET_RPC(x) \
1090 do { \
1091 if (SMC_MUST_ALIGN_WRITE) \
1092 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
1093 else \
1094 SMC_outw(x, ioaddr, RPC_REG); \
1095 } while (0)
1096
1097#define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
1098
1099#define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
1da177e4
LT		 1100
1101#ifndef SMC_GET_MAC_ADDR
1102#define SMC_GET_MAC_ADDR(addr) \
1103 do { \
1104 unsigned int __v; \
1105 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1106 addr[0] = __v; addr[1] = __v >> 8; \
1107 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1108 addr[2] = __v; addr[3] = __v >> 8; \
1109 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1110 addr[4] = __v; addr[5] = __v >> 8; \
1111 } while (0)
1112#endif
1113
1114#define SMC_SET_MAC_ADDR(addr) \
1115 do { \
1116 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1117 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1118 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1119 } while (0)
1120
1121#define SMC_SET_MCAST(x) \
1122 do { \
1123 const unsigned char *mt = (x); \
1124 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1125 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1126 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1127 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
1128 } while (0)
1129
1da177e4
LT		 1130#define SMC_PUT_PKT_HDR(status, length) \
1131 do { \
09779c6d
NP		 1132 if (SMC_CAN_USE_32BIT) \
1133 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
1134 else { \
1135 SMC_outw(status, ioaddr, DATA_REG); \
1136 SMC_outw(length, ioaddr, DATA_REG); \
1137 } \
1da177e4 1138 } while (0)
1da177e4 1139
09779c6d 1140#define SMC_GET_PKT_HDR(status, length) \
1da177e4 1141 do { \
09779c6d
NP		 1142 if (SMC_CAN_USE_32BIT) { \
1143 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
1144 (status) = __val & 0xffff; \
1145 (length) = __val >> 16; \
1146 } else { \
1147 (status) = SMC_inw(ioaddr, DATA_REG); \
1148 (length) = SMC_inw(ioaddr, DATA_REG); \
1da177e4
LT		 1149 } \
1150 } while (0)
1da177e4 1151
09779c6d 1152#define SMC_PUSH_DATA(p, l) \
1da177e4 1153 do { \
09779c6d
NP		 1154 if (SMC_CAN_USE_32BIT) { \
1155 void *__ptr = (p); \
1156 int __len = (l); \
1157 void *__ioaddr = ioaddr; \
1158 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1159 __len -= 2; \
1160 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
1161 __ptr += 2; \
1162 } \
1163 if (SMC_CAN_USE_DATACS && lp->datacs) \
1164 __ioaddr = lp->datacs; \
1165 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1166 if (__len & 2) { \
1167 __ptr += (__len & ~3); \
1168 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
1169 } \
1170 } else if (SMC_CAN_USE_16BIT) \
1171 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
1172 else if (SMC_CAN_USE_8BIT) \
1173 SMC_outsb(ioaddr, DATA_REG, p, l); \
1da177e4 1174 } while (0)
1da177e4
LT		 1175
1176#define SMC_PULL_DATA(p, l) \
09779c6d
NP		 1177 do { \
1178 if (SMC_CAN_USE_32BIT) { \
1179 void *__ptr = (p); \
1180 int __len = (l); \
1181 void *__ioaddr = ioaddr; \
1182 if ((unsigned long)__ptr & 2) { \
1183 /* \
1184 * We want 32bit alignment here. \
1185 * Since some buses perform a full \
1186 * 32bit fetch even for 16bit data \
1187 * we can't use SMC_inw() here. \
1188 * Back both source (on-chip) and \
1189 * destination pointers of 2 bytes. \
1190 * This is possible since the call to \
1191 * SMC_GET_PKT_HDR() already advanced \
1192 * the source pointer of 4 bytes, and \
1193 * the skb_reserve(skb, 2) advanced \
1194 * the destination pointer of 2 bytes. \
1195 */ \
1196 __ptr -= 2; \
1197 __len += 2; \
1198 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1199 } \
1200 if (SMC_CAN_USE_DATACS && lp->datacs) \
1201 __ioaddr = lp->datacs; \
1da177e4 1202 __len += 2; \
09779c6d
NP		 1203 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1204 } else if (SMC_CAN_USE_16BIT) \
1205 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
1206 else if (SMC_CAN_USE_8BIT) \
1207 SMC_insb(ioaddr, DATA_REG, p, l); \
1208 } while (0)
1da177e4
LT		 1209
1210#endif /* _SMC91X_H_ */
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