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[linux.git] / drivers / net / r8169.c
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1da177e4
LT		 1/*
2=========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <[email protected]>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 2004 - Massive updates. See kernel SCM system for details.
10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
14
15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
21
22 2. Support TBI mode.
23=========================================================================
24VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP).
29
30VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/pci.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/delay.h>
59#include <linux/ethtool.h>
60#include <linux/mii.h>
61#include <linux/if_vlan.h>
62#include <linux/crc32.h>
63#include <linux/in.h>
64#include <linux/ip.h>
65#include <linux/tcp.h>
66#include <linux/init.h>
67#include <linux/dma-mapping.h>
68
69#include <asm/io.h>
70#include <asm/irq.h>
71
f7ccf420
SH		 72#ifdef CONFIG_R8169_NAPI
73#define NAPI_SUFFIX "-NAPI"
74#else
75#define NAPI_SUFFIX ""
76#endif
77
78#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 79#define MODULENAME "r8169"
80#define PFX MODULENAME ": "
81
82#ifdef RTL8169_DEBUG
83#define assert(expr) \
84 if(!(expr)) { \
85 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
86 #expr,__FILE__,__FUNCTION__,__LINE__); \
87 }
88#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
89#else
90#define assert(expr) do {} while (0)
91#define dprintk(fmt, args...) do {} while (0)
92#endif /* RTL8169_DEBUG */
93
b57b7e5a 94#define R8169_MSG_DEFAULT \
f0e837d9 95 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 96
1da177e4
LT		 97#define TX_BUFFS_AVAIL(tp) \
98 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
99
100#ifdef CONFIG_R8169_NAPI
101#define rtl8169_rx_skb netif_receive_skb
0b50f81d 102#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 103#define rtl8169_rx_quota(count, quota) min(count, quota)
104#else
105#define rtl8169_rx_skb netif_rx
0b50f81d 106#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 107#define rtl8169_rx_quota(count, quota) count
108#endif
109
110/* media options */
111#define MAX_UNITS 8
112static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
113static int num_media = 0;
114
115/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 116static const int max_interrupt_work = 20;
1da177e4
LT		 117
118/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
119 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 120static const int multicast_filter_limit = 32;
1da177e4
LT		 121
122/* MAC address length */
123#define MAC_ADDR_LEN 6
124
125#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
126#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
129#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
130#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
131#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
132
133#define R8169_REGS_SIZE 256
134#define R8169_NAPI_WEIGHT 64
135#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
136#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
137#define RX_BUF_SIZE 1536 /* Rx Buffer size */
138#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
139#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
140
141#define RTL8169_TX_TIMEOUT (6*HZ)
142#define RTL8169_PHY_TIMEOUT (10*HZ)
143
144/* write/read MMIO register */
145#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
146#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
147#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
148#define RTL_R8(reg) readb (ioaddr + (reg))
149#define RTL_R16(reg) readw (ioaddr + (reg))
150#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
151
152enum mac_version {
153 RTL_GIGA_MAC_VER_B = 0x00,
154 /* RTL_GIGA_MAC_VER_C = 0x03, */
155 RTL_GIGA_MAC_VER_D = 0x01,
156 RTL_GIGA_MAC_VER_E = 0x02,
157 RTL_GIGA_MAC_VER_X = 0x04 /* Greater than RTL_GIGA_MAC_VER_E */
158};
159
160enum phy_version {
161 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
162 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
163 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
164 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
165 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
166 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
167};
168
169
170#define _R(NAME,MAC,MASK) \
171 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
172
3c6bee1d 173static const struct {
1da177e4
LT		 174 const char *name;
175 u8 mac_version;
176 u32 RxConfigMask; /* Clears the bits supported by this chip */
177} rtl_chip_info[] = {
178 _R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880),
179 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880),
180 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880),
181 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_X, 0xff7e1880),
182};
183#undef _R
184
185static struct pci_device_id rtl8169_pci_tbl[] = {
53456f60 186 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), },
de1e938e 187 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), },
53456f60
FR		 188 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), },
189 { PCI_DEVICE(0x16ec, 0x0116), },
86f0cd50 190 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024, },
1da177e4
LT		 191 {0,},
192};
193
194MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
195
196static int rx_copybreak = 200;
197static int use_dac;
b57b7e5a
SH		 198static struct {
199 u32 msg_enable;
200} debug = { -1 };
1da177e4
LT		 201
202enum RTL8169_registers {
203 MAC0 = 0, /* Ethernet hardware address. */
204 MAR0 = 8, /* Multicast filter. */
d4a3a0fc
SH		 205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
1da177e4
LT		 207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
211 FLASH = 0x30,
212 ERSR = 0x36,
213 ChipCmd = 0x37,
214 TxPoll = 0x38,
215 IntrMask = 0x3C,
216 IntrStatus = 0x3E,
217 TxConfig = 0x40,
218 RxConfig = 0x44,
219 RxMissed = 0x4C,
220 Cfg9346 = 0x50,
221 Config0 = 0x51,
222 Config1 = 0x52,
223 Config2 = 0x53,
224 Config3 = 0x54,
225 Config4 = 0x55,
226 Config5 = 0x56,
227 MultiIntr = 0x5C,
228 PHYAR = 0x60,
229 TBICSR = 0x64,
230 TBI_ANAR = 0x68,
231 TBI_LPAR = 0x6A,
232 PHYstatus = 0x6C,
233 RxMaxSize = 0xDA,
234 CPlusCmd = 0xE0,
235 IntrMitigate = 0xE2,
236 RxDescAddrLow = 0xE4,
237 RxDescAddrHigh = 0xE8,
238 EarlyTxThres = 0xEC,
239 FuncEvent = 0xF0,
240 FuncEventMask = 0xF4,
241 FuncPresetState = 0xF8,
242 FuncForceEvent = 0xFC,
243};
244
245enum RTL8169_register_content {
246 /* InterruptStatusBits */
247 SYSErr = 0x8000,
248 PCSTimeout = 0x4000,
249 SWInt = 0x0100,
250 TxDescUnavail = 0x80,
251 RxFIFOOver = 0x40,
252 LinkChg = 0x20,
253 RxOverflow = 0x10,
254 TxErr = 0x08,
255 TxOK = 0x04,
256 RxErr = 0x02,
257 RxOK = 0x01,
258
259 /* RxStatusDesc */
260 RxRES = 0x00200000,
261 RxCRC = 0x00080000,
262 RxRUNT = 0x00100000,
263 RxRWT = 0x00400000,
264
265 /* ChipCmdBits */
266 CmdReset = 0x10,
267 CmdRxEnb = 0x08,
268 CmdTxEnb = 0x04,
269 RxBufEmpty = 0x01,
270
271 /* Cfg9346Bits */
272 Cfg9346_Lock = 0x00,
273 Cfg9346_Unlock = 0xC0,
274
275 /* rx_mode_bits */
276 AcceptErr = 0x20,
277 AcceptRunt = 0x10,
278 AcceptBroadcast = 0x08,
279 AcceptMulticast = 0x04,
280 AcceptMyPhys = 0x02,
281 AcceptAllPhys = 0x01,
282
283 /* RxConfigBits */
284 RxCfgFIFOShift = 13,
285 RxCfgDMAShift = 8,
286
287 /* TxConfigBits */
288 TxInterFrameGapShift = 24,
289 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
290
5d06a99f
FR		 291 /* Config1 register p.24 */
292 PMEnable = (1 << 0), /* Power Management Enable */
293
61a4dcc2
FR		 294 /* Config3 register p.25 */
295 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
296 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
297
5d06a99f 298 /* Config5 register p.27 */
61a4dcc2
FR		 299 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
300 MWF = (1 << 5), /* Accept Multicast wakeup frame */
301 UWF = (1 << 4), /* Accept Unicast wakeup frame */
302 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 303 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
304
1da177e4
LT		 305 /* TBICSR p.28 */
306 TBIReset = 0x80000000,
307 TBILoopback = 0x40000000,
308 TBINwEnable = 0x20000000,
309 TBINwRestart = 0x10000000,
310 TBILinkOk = 0x02000000,
311 TBINwComplete = 0x01000000,
312
313 /* CPlusCmd p.31 */
314 RxVlan = (1 << 6),
315 RxChkSum = (1 << 5),
316 PCIDAC = (1 << 4),
317 PCIMulRW = (1 << 3),
318
319 /* rtl8169_PHYstatus */
320 TBI_Enable = 0x80,
321 TxFlowCtrl = 0x40,
322 RxFlowCtrl = 0x20,
323 _1000bpsF = 0x10,
324 _100bps = 0x08,
325 _10bps = 0x04,
326 LinkStatus = 0x02,
327 FullDup = 0x01,
328
329 /* GIGABIT_PHY_registers */
330 PHY_CTRL_REG = 0,
331 PHY_STAT_REG = 1,
332 PHY_AUTO_NEGO_REG = 4,
333 PHY_1000_CTRL_REG = 9,
334
335 /* GIGABIT_PHY_REG_BIT */
336 PHY_Restart_Auto_Nego = 0x0200,
337 PHY_Enable_Auto_Nego = 0x1000,
338
339 /* PHY_STAT_REG = 1 */
340 PHY_Auto_Neco_Comp = 0x0020,
341
342 /* PHY_AUTO_NEGO_REG = 4 */
343 PHY_Cap_10_Half = 0x0020,
344 PHY_Cap_10_Full = 0x0040,
345 PHY_Cap_100_Half = 0x0080,
346 PHY_Cap_100_Full = 0x0100,
347
348 /* PHY_1000_CTRL_REG = 9 */
349 PHY_Cap_1000_Full = 0x0200,
350
351 PHY_Cap_Null = 0x0,
352
353 /* _MediaType */
354 _10_Half = 0x01,
355 _10_Full = 0x02,
356 _100_Half = 0x04,
357 _100_Full = 0x08,
358 _1000_Full = 0x10,
359
360 /* _TBICSRBit */
361 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 362
363 /* DumpCounterCommand */
364 CounterDump = 0x8,
1da177e4
LT		 365};
366
367enum _DescStatusBit {
368 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
369 RingEnd = (1 << 30), /* End of descriptor ring */
370 FirstFrag = (1 << 29), /* First segment of a packet */
371 LastFrag = (1 << 28), /* Final segment of a packet */
372
373 /* Tx private */
374 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
375 MSSShift = 16, /* MSS value position */
376 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
377 IPCS = (1 << 18), /* Calculate IP checksum */
378 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
379 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
380 TxVlanTag = (1 << 17), /* Add VLAN tag */
381
382 /* Rx private */
383 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
384 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
385
386#define RxProtoUDP (PID1)
387#define RxProtoTCP (PID0)
388#define RxProtoIP (PID1 | PID0)
389#define RxProtoMask RxProtoIP
390
391 IPFail = (1 << 16), /* IP checksum failed */
392 UDPFail = (1 << 15), /* UDP/IP checksum failed */
393 TCPFail = (1 << 14), /* TCP/IP checksum failed */
394 RxVlanTag = (1 << 16), /* VLAN tag available */
395};
396
397#define RsvdMask 0x3fffc000
398
399struct TxDesc {
400 u32 opts1;
401 u32 opts2;
402 u64 addr;
403};
404
405struct RxDesc {
406 u32 opts1;
407 u32 opts2;
408 u64 addr;
409};
410
411struct ring_info {
412 struct sk_buff *skb;
413 u32 len;
414 u8 __pad[sizeof(void *) - sizeof(u32)];
415};
416
417struct rtl8169_private {
418 void __iomem *mmio_addr; /* memory map physical address */
419 struct pci_dev *pci_dev; /* Index of PCI device */
420 struct net_device_stats stats; /* statistics of net device */
421 spinlock_t lock; /* spin lock flag */
b57b7e5a 422 u32 msg_enable;
1da177e4
LT		 423 int chipset;
424 int mac_version;
425 int phy_version;
426 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
427 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
428 u32 dirty_rx;
429 u32 dirty_tx;
430 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
431 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
432 dma_addr_t TxPhyAddr;
433 dma_addr_t RxPhyAddr;
434 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
435 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
436 unsigned rx_buf_sz;
437 struct timer_list timer;
438 u16 cp_cmd;
439 u16 intr_mask;
440 int phy_auto_nego_reg;
441 int phy_1000_ctrl_reg;
442#ifdef CONFIG_R8169_VLAN
443 struct vlan_group *vlgrp;
444#endif
445 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
446 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
447 void (*phy_reset_enable)(void __iomem *);
448 unsigned int (*phy_reset_pending)(void __iomem *);
449 unsigned int (*link_ok)(void __iomem *);
450 struct work_struct task;
61a4dcc2 451 unsigned wol_enabled : 1;
1da177e4
LT		 452};
453
979b6c13 454MODULE_AUTHOR("Realtek and the Linux r8169 crew <[email protected]>");
1da177e4
LT		 455MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
456module_param_array(media, int, &num_media, 0);
df0a1bf6 457MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
1da177e4 458module_param(rx_copybreak, int, 0);
1b7efd58 459MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 460module_param(use_dac, int, 0);
461MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 462module_param_named(debug, debug.msg_enable, int, 0);
463MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 464MODULE_LICENSE("GPL");
465MODULE_VERSION(RTL8169_VERSION);
466
467static int rtl8169_open(struct net_device *dev);
468static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
469static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
470 struct pt_regs *regs);
471static int rtl8169_init_ring(struct net_device *dev);
472static void rtl8169_hw_start(struct net_device *dev);
473static int rtl8169_close(struct net_device *dev);
474static void rtl8169_set_rx_mode(struct net_device *dev);
475static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 476static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4
LT		 477static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
478 void __iomem *);
4dcb7d33 479static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4
LT		 480static void rtl8169_down(struct net_device *dev);
481
482#ifdef CONFIG_R8169_NAPI
483static int rtl8169_poll(struct net_device *dev, int *budget);
484#endif
485
486static const u16 rtl8169_intr_mask =
487 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
488static const u16 rtl8169_napi_event =
489 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
490static const unsigned int rtl8169_rx_config =
491 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
492
493#define PHY_Cap_10_Half_Or_Less PHY_Cap_10_Half
494#define PHY_Cap_10_Full_Or_Less PHY_Cap_10_Full | PHY_Cap_10_Half_Or_Less
495#define PHY_Cap_100_Half_Or_Less PHY_Cap_100_Half | PHY_Cap_10_Full_Or_Less
496#define PHY_Cap_100_Full_Or_Less PHY_Cap_100_Full | PHY_Cap_100_Half_Or_Less
497
498static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
499{
500 int i;
501
502 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
1da177e4 503
2371408c 504 for (i = 20; i > 0; i--) {
1da177e4
LT		 505 /* Check if the RTL8169 has completed writing to the specified MII register */
506 if (!(RTL_R32(PHYAR) & 0x80000000))
507 break;
2371408c 508 udelay(25);
1da177e4
LT		 509 }
510}
511
512static int mdio_read(void __iomem *ioaddr, int RegAddr)
513{
514 int i, value = -1;
515
516 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
1da177e4 517
2371408c 518 for (i = 20; i > 0; i--) {
1da177e4
LT		 519 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
520 if (RTL_R32(PHYAR) & 0x80000000) {
521 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
522 break;
523 }
2371408c 524 udelay(25);
1da177e4
LT		 525 }
526 return value;
527}
528
529static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
530{
531 RTL_W16(IntrMask, 0x0000);
532
533 RTL_W16(IntrStatus, 0xffff);
534}
535
536static void rtl8169_asic_down(void __iomem *ioaddr)
537{
538 RTL_W8(ChipCmd, 0x00);
539 rtl8169_irq_mask_and_ack(ioaddr);
540 RTL_R16(CPlusCmd);
541}
542
543static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
544{
545 return RTL_R32(TBICSR) & TBIReset;
546}
547
548static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
549{
550 return mdio_read(ioaddr, 0) & 0x8000;
551}
552
553static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
554{
555 return RTL_R32(TBICSR) & TBILinkOk;
556}
557
558static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
559{
560 return RTL_R8(PHYstatus) & LinkStatus;
561}
562
563static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
564{
565 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
566}
567
568static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
569{
570 unsigned int val;
571
572 val = (mdio_read(ioaddr, PHY_CTRL_REG) | 0x8000) & 0xffff;
573 mdio_write(ioaddr, PHY_CTRL_REG, val);
574}
575
576static void rtl8169_check_link_status(struct net_device *dev,
577 struct rtl8169_private *tp, void __iomem *ioaddr)
578{
579 unsigned long flags;
580
581 spin_lock_irqsave(&tp->lock, flags);
582 if (tp->link_ok(ioaddr)) {
583 netif_carrier_on(dev);
b57b7e5a
SH		 584 if (netif_msg_ifup(tp))
585 printk(KERN_INFO PFX "%s: link up\n", dev->name);
586 } else {
587 if (netif_msg_ifdown(tp))
588 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 589 netif_carrier_off(dev);
b57b7e5a 590 }
1da177e4
LT		 591 spin_unlock_irqrestore(&tp->lock, flags);
592}
593
594static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
595{
596 struct {
597 u16 speed;
598 u8 duplex;
599 u8 autoneg;
600 u8 media;
601 } link_settings[] = {
602 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
603 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
604 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
605 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
606 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
607 /* Make TBI happy */
608 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
609 }, *p;
610 unsigned char option;
611
612 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
613
b57b7e5a 614 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
1da177e4
LT		 615 printk(KERN_WARNING PFX "media option is deprecated.\n");
616
617 for (p = link_settings; p->media != 0xff; p++) {
618 if (p->media == option)
619 break;
620 }
621 *autoneg = p->autoneg;
622 *speed = p->speed;
623 *duplex = p->duplex;
624}
625
61a4dcc2
FR		 626static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
627{
628 struct rtl8169_private *tp = netdev_priv(dev);
629 void __iomem *ioaddr = tp->mmio_addr;
630 u8 options;
631
632 wol->wolopts = 0;
633
634#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
635 wol->supported = WAKE_ANY;
636
637 spin_lock_irq(&tp->lock);
638
639 options = RTL_R8(Config1);
640 if (!(options & PMEnable))
641 goto out_unlock;
642
643 options = RTL_R8(Config3);
644 if (options & LinkUp)
645 wol->wolopts |= WAKE_PHY;
646 if (options & MagicPacket)
647 wol->wolopts |= WAKE_MAGIC;
648
649 options = RTL_R8(Config5);
650 if (options & UWF)
651 wol->wolopts |= WAKE_UCAST;
652 if (options & BWF)
653 wol->wolopts |= WAKE_BCAST;
654 if (options & MWF)
655 wol->wolopts |= WAKE_MCAST;
656
657out_unlock:
658 spin_unlock_irq(&tp->lock);
659}
660
661static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
662{
663 struct rtl8169_private *tp = netdev_priv(dev);
664 void __iomem *ioaddr = tp->mmio_addr;
665 int i;
666 static struct {
667 u32 opt;
668 u16 reg;
669 u8 mask;
670 } cfg[] = {
671 { WAKE_ANY, Config1, PMEnable },
672 { WAKE_PHY, Config3, LinkUp },
673 { WAKE_MAGIC, Config3, MagicPacket },
674 { WAKE_UCAST, Config5, UWF },
675 { WAKE_BCAST, Config5, BWF },
676 { WAKE_MCAST, Config5, MWF },
677 { WAKE_ANY, Config5, LanWake }
678 };
679
680 spin_lock_irq(&tp->lock);
681
682 RTL_W8(Cfg9346, Cfg9346_Unlock);
683
684 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
685 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
686 if (wol->wolopts & cfg[i].opt)
687 options |= cfg[i].mask;
688 RTL_W8(cfg[i].reg, options);
689 }
690
691 RTL_W8(Cfg9346, Cfg9346_Lock);
692
693 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
694
695 spin_unlock_irq(&tp->lock);
696
697 return 0;
698}
699
1da177e4
LT		 700static void rtl8169_get_drvinfo(struct net_device *dev,
701 struct ethtool_drvinfo *info)
702{
703 struct rtl8169_private *tp = netdev_priv(dev);
704
705 strcpy(info->driver, MODULENAME);
706 strcpy(info->version, RTL8169_VERSION);
707 strcpy(info->bus_info, pci_name(tp->pci_dev));
708}
709
710static int rtl8169_get_regs_len(struct net_device *dev)
711{
712 return R8169_REGS_SIZE;
713}
714
715static int rtl8169_set_speed_tbi(struct net_device *dev,
716 u8 autoneg, u16 speed, u8 duplex)
717{
718 struct rtl8169_private *tp = netdev_priv(dev);
719 void __iomem *ioaddr = tp->mmio_addr;
720 int ret = 0;
721 u32 reg;
722
723 reg = RTL_R32(TBICSR);
724 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
725 (duplex == DUPLEX_FULL)) {
726 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
727 } else if (autoneg == AUTONEG_ENABLE)
728 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
729 else {
b57b7e5a
SH		 730 if (netif_msg_link(tp)) {
731 printk(KERN_WARNING "%s: "
732 "incorrect speed setting refused in TBI mode\n",
733 dev->name);
734 }
1da177e4
LT		 735 ret = -EOPNOTSUPP;
736 }
737
738 return ret;
739}
740
741static int rtl8169_set_speed_xmii(struct net_device *dev,
742 u8 autoneg, u16 speed, u8 duplex)
743{
744 struct rtl8169_private *tp = netdev_priv(dev);
745 void __iomem *ioaddr = tp->mmio_addr;
746 int auto_nego, giga_ctrl;
747
748 auto_nego = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
749 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full |
750 PHY_Cap_100_Half | PHY_Cap_100_Full);
751 giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG);
752 giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_Null);
753
754 if (autoneg == AUTONEG_ENABLE) {
755 auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full |
756 PHY_Cap_100_Half | PHY_Cap_100_Full);
757 giga_ctrl |= PHY_Cap_1000_Full;
758 } else {
759 if (speed == SPEED_10)
760 auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full;
761 else if (speed == SPEED_100)
762 auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full;
763 else if (speed == SPEED_1000)
764 giga_ctrl |= PHY_Cap_1000_Full;
765
766 if (duplex == DUPLEX_HALF)
767 auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);
726ecdcf
AG		 768
769 if (duplex == DUPLEX_FULL)
770 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_100_Half);
1da177e4
LT		 771 }
772
773 tp->phy_auto_nego_reg = auto_nego;
774 tp->phy_1000_ctrl_reg = giga_ctrl;
775
776 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, auto_nego);
777 mdio_write(ioaddr, PHY_1000_CTRL_REG, giga_ctrl);
778 mdio_write(ioaddr, PHY_CTRL_REG, PHY_Enable_Auto_Nego |
779 PHY_Restart_Auto_Nego);
780 return 0;
781}
782
783static int rtl8169_set_speed(struct net_device *dev,
784 u8 autoneg, u16 speed, u8 duplex)
785{
786 struct rtl8169_private *tp = netdev_priv(dev);
787 int ret;
788
789 ret = tp->set_speed(dev, autoneg, speed, duplex);
790
791 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
792 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
793
794 return ret;
795}
796
797static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
798{
799 struct rtl8169_private *tp = netdev_priv(dev);
800 unsigned long flags;
801 int ret;
802
803 spin_lock_irqsave(&tp->lock, flags);
804 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
805 spin_unlock_irqrestore(&tp->lock, flags);
806
807 return ret;
808}
809
810static u32 rtl8169_get_rx_csum(struct net_device *dev)
811{
812 struct rtl8169_private *tp = netdev_priv(dev);
813
814 return tp->cp_cmd & RxChkSum;
815}
816
817static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
818{
819 struct rtl8169_private *tp = netdev_priv(dev);
820 void __iomem *ioaddr = tp->mmio_addr;
821 unsigned long flags;
822
823 spin_lock_irqsave(&tp->lock, flags);
824
825 if (data)
826 tp->cp_cmd |= RxChkSum;
827 else
828 tp->cp_cmd &= ~RxChkSum;
829
830 RTL_W16(CPlusCmd, tp->cp_cmd);
831 RTL_R16(CPlusCmd);
832
833 spin_unlock_irqrestore(&tp->lock, flags);
834
835 return 0;
836}
837
838#ifdef CONFIG_R8169_VLAN
839
840static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
841 struct sk_buff *skb)
842{
843 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
844 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
845}
846
847static void rtl8169_vlan_rx_register(struct net_device *dev,
848 struct vlan_group *grp)
849{
850 struct rtl8169_private *tp = netdev_priv(dev);
851 void __iomem *ioaddr = tp->mmio_addr;
852 unsigned long flags;
853
854 spin_lock_irqsave(&tp->lock, flags);
855 tp->vlgrp = grp;
856 if (tp->vlgrp)
857 tp->cp_cmd |= RxVlan;
858 else
859 tp->cp_cmd &= ~RxVlan;
860 RTL_W16(CPlusCmd, tp->cp_cmd);
861 RTL_R16(CPlusCmd);
862 spin_unlock_irqrestore(&tp->lock, flags);
863}
864
865static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
866{
867 struct rtl8169_private *tp = netdev_priv(dev);
868 unsigned long flags;
869
870 spin_lock_irqsave(&tp->lock, flags);
871 if (tp->vlgrp)
872 tp->vlgrp->vlan_devices[vid] = NULL;
873 spin_unlock_irqrestore(&tp->lock, flags);
874}
875
876static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
877 struct sk_buff *skb)
878{
879 u32 opts2 = le32_to_cpu(desc->opts2);
880 int ret;
881
882 if (tp->vlgrp && (opts2 & RxVlanTag)) {
883 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
884 swab16(opts2 & 0xffff));
885 ret = 0;
886 } else
887 ret = -1;
888 desc->opts2 = 0;
889 return ret;
890}
891
892#else /* !CONFIG_R8169_VLAN */
893
894static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
895 struct sk_buff *skb)
896{
897 return 0;
898}
899
900static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
901 struct sk_buff *skb)
902{
903 return -1;
904}
905
906#endif
907
908static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
909{
910 struct rtl8169_private *tp = netdev_priv(dev);
911 void __iomem *ioaddr = tp->mmio_addr;
912 u32 status;
913
914 cmd->supported =
915 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
916 cmd->port = PORT_FIBRE;
917 cmd->transceiver = XCVR_INTERNAL;
918
919 status = RTL_R32(TBICSR);
920 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
921 cmd->autoneg = !!(status & TBINwEnable);
922
923 cmd->speed = SPEED_1000;
924 cmd->duplex = DUPLEX_FULL; /* Always set */
925}
926
927static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
928{
929 struct rtl8169_private *tp = netdev_priv(dev);
930 void __iomem *ioaddr = tp->mmio_addr;
931 u8 status;
932
933 cmd->supported = SUPPORTED_10baseT_Half |
934 SUPPORTED_10baseT_Full |
935 SUPPORTED_100baseT_Half |
936 SUPPORTED_100baseT_Full |
937 SUPPORTED_1000baseT_Full |
938 SUPPORTED_Autoneg |
939 SUPPORTED_TP;
940
941 cmd->autoneg = 1;
942 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
943
944 if (tp->phy_auto_nego_reg & PHY_Cap_10_Half)
945 cmd->advertising |= ADVERTISED_10baseT_Half;
946 if (tp->phy_auto_nego_reg & PHY_Cap_10_Full)
947 cmd->advertising |= ADVERTISED_10baseT_Full;
948 if (tp->phy_auto_nego_reg & PHY_Cap_100_Half)
949 cmd->advertising |= ADVERTISED_100baseT_Half;
950 if (tp->phy_auto_nego_reg & PHY_Cap_100_Full)
951 cmd->advertising |= ADVERTISED_100baseT_Full;
952 if (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)
953 cmd->advertising |= ADVERTISED_1000baseT_Full;
954
955 status = RTL_R8(PHYstatus);
956
957 if (status & _1000bpsF)
958 cmd->speed = SPEED_1000;
959 else if (status & _100bps)
960 cmd->speed = SPEED_100;
961 else if (status & _10bps)
962 cmd->speed = SPEED_10;
963
964 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
965 DUPLEX_FULL : DUPLEX_HALF;
966}
967
968static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
969{
970 struct rtl8169_private *tp = netdev_priv(dev);
971 unsigned long flags;
972
973 spin_lock_irqsave(&tp->lock, flags);
974
975 tp->get_settings(dev, cmd);
976
977 spin_unlock_irqrestore(&tp->lock, flags);
978 return 0;
979}
980
981static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
982 void *p)
983{
984 struct rtl8169_private *tp = netdev_priv(dev);
985 unsigned long flags;
986
987 if (regs->len > R8169_REGS_SIZE)
988 regs->len = R8169_REGS_SIZE;
989
990 spin_lock_irqsave(&tp->lock, flags);
991 memcpy_fromio(p, tp->mmio_addr, regs->len);
992 spin_unlock_irqrestore(&tp->lock, flags);
993}
994
b57b7e5a
SH		 995static u32 rtl8169_get_msglevel(struct net_device *dev)
996{
997 struct rtl8169_private *tp = netdev_priv(dev);
998
999 return tp->msg_enable;
1000}
1001
1002static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1003{
1004 struct rtl8169_private *tp = netdev_priv(dev);
1005
1006 tp->msg_enable = value;
1007}
1008
d4a3a0fc
SH		 1009static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1010 "tx_packets",
1011 "rx_packets",
1012 "tx_errors",
1013 "rx_errors",
1014 "rx_missed",
1015 "align_errors",
1016 "tx_single_collisions",
1017 "tx_multi_collisions",
1018 "unicast",
1019 "broadcast",
1020 "multicast",
1021 "tx_aborted",
1022 "tx_underrun",
1023};
1024
1025struct rtl8169_counters {
1026 u64 tx_packets;
1027 u64 rx_packets;
1028 u64 tx_errors;
1029 u32 rx_errors;
1030 u16 rx_missed;
1031 u16 align_errors;
1032 u32 tx_one_collision;
1033 u32 tx_multi_collision;
1034 u64 rx_unicast;
1035 u64 rx_broadcast;
1036 u32 rx_multicast;
1037 u16 tx_aborted;
1038 u16 tx_underun;
1039};
1040
1041static int rtl8169_get_stats_count(struct net_device *dev)
1042{
1043 return ARRAY_SIZE(rtl8169_gstrings);
1044}
1045
1046static void rtl8169_get_ethtool_stats(struct net_device *dev,
1047 struct ethtool_stats *stats, u64 *data)
1048{
1049 struct rtl8169_private *tp = netdev_priv(dev);
1050 void __iomem *ioaddr = tp->mmio_addr;
1051 struct rtl8169_counters *counters;
1052 dma_addr_t paddr;
1053 u32 cmd;
1054
1055 ASSERT_RTNL();
1056
1057 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1058 if (!counters)
1059 return;
1060
1061 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1062 cmd = (u64)paddr & DMA_32BIT_MASK;
1063 RTL_W32(CounterAddrLow, cmd);
1064 RTL_W32(CounterAddrLow, cmd | CounterDump);
1065
1066 while (RTL_R32(CounterAddrLow) & CounterDump) {
1067 if (msleep_interruptible(1))
1068 break;
1069 }
1070
1071 RTL_W32(CounterAddrLow, 0);
1072 RTL_W32(CounterAddrHigh, 0);
1073
1074 data[0] = le64_to_cpu(counters->tx_packets);
1075 data[1] = le64_to_cpu(counters->rx_packets);
1076 data[2] = le64_to_cpu(counters->tx_errors);
1077 data[3] = le32_to_cpu(counters->rx_errors);
1078 data[4] = le16_to_cpu(counters->rx_missed);
1079 data[5] = le16_to_cpu(counters->align_errors);
1080 data[6] = le32_to_cpu(counters->tx_one_collision);
1081 data[7] = le32_to_cpu(counters->tx_multi_collision);
1082 data[8] = le64_to_cpu(counters->rx_unicast);
1083 data[9] = le64_to_cpu(counters->rx_broadcast);
1084 data[10] = le32_to_cpu(counters->rx_multicast);
1085 data[11] = le16_to_cpu(counters->tx_aborted);
1086 data[12] = le16_to_cpu(counters->tx_underun);
1087
1088 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1089}
1090
1091static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1092{
1093 switch(stringset) {
1094 case ETH_SS_STATS:
1095 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1096 break;
1097 }
1098}
1099
1100
1da177e4
LT		 1101static struct ethtool_ops rtl8169_ethtool_ops = {
1102 .get_drvinfo = rtl8169_get_drvinfo,
1103 .get_regs_len = rtl8169_get_regs_len,
1104 .get_link = ethtool_op_get_link,
1105 .get_settings = rtl8169_get_settings,
1106 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1107 .get_msglevel = rtl8169_get_msglevel,
1108 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1109 .get_rx_csum = rtl8169_get_rx_csum,
1110 .set_rx_csum = rtl8169_set_rx_csum,
1111 .get_tx_csum = ethtool_op_get_tx_csum,
1112 .set_tx_csum = ethtool_op_set_tx_csum,
1113 .get_sg = ethtool_op_get_sg,
1114 .set_sg = ethtool_op_set_sg,
1115 .get_tso = ethtool_op_get_tso,
1116 .set_tso = ethtool_op_set_tso,
1117 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1118 .get_wol = rtl8169_get_wol,
1119 .set_wol = rtl8169_set_wol,
d4a3a0fc
SH		 1120 .get_strings = rtl8169_get_strings,
1121 .get_stats_count = rtl8169_get_stats_count,
1122 .get_ethtool_stats = rtl8169_get_ethtool_stats,
6d6525b7 1123 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1124};
1125
1126static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1127 int bitval)
1128{
1129 int val;
1130
1131 val = mdio_read(ioaddr, reg);
1132 val = (bitval == 1) ?
1133 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1134 mdio_write(ioaddr, reg, val & 0xffff);
1135}
1136
1137static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1138{
1139 const struct {
1140 u32 mask;
1141 int mac_version;
1142 } mac_info[] = {
1143 { 0x1 << 28, RTL_GIGA_MAC_VER_X },
1144 { 0x1 << 26, RTL_GIGA_MAC_VER_E },
1145 { 0x1 << 23, RTL_GIGA_MAC_VER_D },
1146 { 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */
1147 }, *p = mac_info;
1148 u32 reg;
1149
1150 reg = RTL_R32(TxConfig) & 0x7c800000;
1151 while ((reg & p->mask) != p->mask)
1152 p++;
1153 tp->mac_version = p->mac_version;
1154}
1155
1156static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1157{
1158 struct {
1159 int version;
1160 char *msg;
1161 } mac_print[] = {
1162 { RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
1163 { RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
1164 { RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
1165 { 0, NULL }
1166 }, *p;
1167
1168 for (p = mac_print; p->msg; p++) {
1169 if (tp->mac_version == p->version) {
1170 dprintk("mac_version == %s (%04d)\n", p->msg,
1171 p->version);
1172 return;
1173 }
1174 }
1175 dprintk("mac_version == Unknown\n");
1176}
1177
1178static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1179{
1180 const struct {
1181 u16 mask;
1182 u16 set;
1183 int phy_version;
1184 } phy_info[] = {
1185 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1186 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1187 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1188 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1189 }, *p = phy_info;
1190 u16 reg;
1191
1192 reg = mdio_read(ioaddr, 3) & 0xffff;
1193 while ((reg & p->mask) != p->set)
1194 p++;
1195 tp->phy_version = p->phy_version;
1196}
1197
1198static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1199{
1200 struct {
1201 int version;
1202 char *msg;
1203 u32 reg;
1204 } phy_print[] = {
1205 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1206 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1207 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1208 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1209 { 0, NULL, 0x0000 }
1210 }, *p;
1211
1212 for (p = phy_print; p->msg; p++) {
1213 if (tp->phy_version == p->version) {
1214 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1215 return;
1216 }
1217 }
1218 dprintk("phy_version == Unknown\n");
1219}
1220
1221static void rtl8169_hw_phy_config(struct net_device *dev)
1222{
1223 struct rtl8169_private *tp = netdev_priv(dev);
1224 void __iomem *ioaddr = tp->mmio_addr;
1225 struct {
1226 u16 regs[5]; /* Beware of bit-sign propagation */
1227 } phy_magic[5] = { {
1228 { 0x0000, //w 4 15 12 0
1229 0x00a1, //w 3 15 0 00a1
1230 0x0008, //w 2 15 0 0008
1231 0x1020, //w 1 15 0 1020
1232 0x1000 } },{ //w 0 15 0 1000
1233 { 0x7000, //w 4 15 12 7
1234 0xff41, //w 3 15 0 ff41
1235 0xde60, //w 2 15 0 de60
1236 0x0140, //w 1 15 0 0140
1237 0x0077 } },{ //w 0 15 0 0077
1238 { 0xa000, //w 4 15 12 a
1239 0xdf01, //w 3 15 0 df01
1240 0xdf20, //w 2 15 0 df20
1241 0xff95, //w 1 15 0 ff95
1242 0xfa00 } },{ //w 0 15 0 fa00
1243 { 0xb000, //w 4 15 12 b
1244 0xff41, //w 3 15 0 ff41
1245 0xde20, //w 2 15 0 de20
1246 0x0140, //w 1 15 0 0140
1247 0x00bb } },{ //w 0 15 0 00bb
1248 { 0xf000, //w 4 15 12 f
1249 0xdf01, //w 3 15 0 df01
1250 0xdf20, //w 2 15 0 df20
1251 0xff95, //w 1 15 0 ff95
1252 0xbf00 } //w 0 15 0 bf00
1253 }
1254 }, *p = phy_magic;
1255 int i;
1256
1257 rtl8169_print_mac_version(tp);
1258 rtl8169_print_phy_version(tp);
1259
1260 if (tp->mac_version <= RTL_GIGA_MAC_VER_B)
1261 return;
1262 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1263 return;
1264
1265 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1266 dprintk("Do final_reg2.cfg\n");
1267
1268 /* Shazam ! */
1269
1270 if (tp->mac_version == RTL_GIGA_MAC_VER_X) {
1271 mdio_write(ioaddr, 31, 0x0001);
1272 mdio_write(ioaddr, 9, 0x273a);
1273 mdio_write(ioaddr, 14, 0x7bfb);
1274 mdio_write(ioaddr, 27, 0x841e);
1275
1276 mdio_write(ioaddr, 31, 0x0002);
1277 mdio_write(ioaddr, 1, 0x90d0);
1278 mdio_write(ioaddr, 31, 0x0000);
1279 return;
1280 }
1281
1282 /* phy config for RTL8169s mac_version C chip */
1283 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1284 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1285 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1286 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1287
1288 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1289 int val, pos = 4;
1290
1291 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1292 mdio_write(ioaddr, pos, val);
1293 while (--pos >= 0)
1294 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1295 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1296 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1297 }
1298 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1299}
1300
1301static void rtl8169_phy_timer(unsigned long __opaque)
1302{
1303 struct net_device *dev = (struct net_device *)__opaque;
1304 struct rtl8169_private *tp = netdev_priv(dev);
1305 struct timer_list *timer = &tp->timer;
1306 void __iomem *ioaddr = tp->mmio_addr;
1307 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1308
1309 assert(tp->mac_version > RTL_GIGA_MAC_VER_B);
1310 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1311
1312 if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
1313 return;
1314
1315 spin_lock_irq(&tp->lock);
1316
1317 if (tp->phy_reset_pending(ioaddr)) {
1318 /*
1319 * A busy loop could burn quite a few cycles on nowadays CPU.
1320 * Let's delay the execution of the timer for a few ticks.
1321 */
1322 timeout = HZ/10;
1323 goto out_mod_timer;
1324 }
1325
1326 if (tp->link_ok(ioaddr))
1327 goto out_unlock;
1328
b57b7e5a
SH		 1329 if (netif_msg_link(tp))
1330 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1331
1332 tp->phy_reset_enable(ioaddr);
1333
1334out_mod_timer:
1335 mod_timer(timer, jiffies + timeout);
1336out_unlock:
1337 spin_unlock_irq(&tp->lock);
1338}
1339
1340static inline void rtl8169_delete_timer(struct net_device *dev)
1341{
1342 struct rtl8169_private *tp = netdev_priv(dev);
1343 struct timer_list *timer = &tp->timer;
1344
1345 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1346 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1347 return;
1348
1349 del_timer_sync(timer);
1350}
1351
1352static inline void rtl8169_request_timer(struct net_device *dev)
1353{
1354 struct rtl8169_private *tp = netdev_priv(dev);
1355 struct timer_list *timer = &tp->timer;
1356
1357 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1358 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1359 return;
1360
1361 init_timer(timer);
1362 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
1363 timer->data = (unsigned long)(dev);
1364 timer->function = rtl8169_phy_timer;
1365 add_timer(timer);
1366}
1367
1368#ifdef CONFIG_NET_POLL_CONTROLLER
1369/*
1370 * Polling 'interrupt' - used by things like netconsole to send skbs
1371 * without having to re-enable interrupts. It's not called while
1372 * the interrupt routine is executing.
1373 */
1374static void rtl8169_netpoll(struct net_device *dev)
1375{
1376 struct rtl8169_private *tp = netdev_priv(dev);
1377 struct pci_dev *pdev = tp->pci_dev;
1378
1379 disable_irq(pdev->irq);
1380 rtl8169_interrupt(pdev->irq, dev, NULL);
1381 enable_irq(pdev->irq);
1382}
1383#endif
1384
1385static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1386 void __iomem *ioaddr)
1387{
1388 iounmap(ioaddr);
1389 pci_release_regions(pdev);
1390 pci_disable_device(pdev);
1391 free_netdev(dev);
1392}
1393
1394static int __devinit
1395rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1396 void __iomem **ioaddr_out)
1397{
1398 void __iomem *ioaddr;
1399 struct net_device *dev;
1400 struct rtl8169_private *tp;
1401 int rc = -ENOMEM, i, acpi_idle_state = 0, pm_cap;
1402
1403 assert(ioaddr_out != NULL);
1404
1405 /* dev zeroed in alloc_etherdev */
1406 dev = alloc_etherdev(sizeof (*tp));
1407 if (dev == NULL) {
b57b7e5a 1408 if (netif_msg_drv(&debug))
9b91cf9d 1409 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1da177e4
LT		 1410 goto err_out;
1411 }
1412
1413 SET_MODULE_OWNER(dev);
1414 SET_NETDEV_DEV(dev, &pdev->dev);
1415 tp = netdev_priv(dev);
b57b7e5a 1416 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1417
1418 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1419 rc = pci_enable_device(pdev);
b57b7e5a 1420 if (rc < 0) {
2e8a538d 1421 if (netif_msg_probe(tp))
9b91cf9d 1422 dev_err(&pdev->dev, "enable failure\n");
1da177e4
LT		 1423 goto err_out_free_dev;
1424 }
1425
1426 rc = pci_set_mwi(pdev);
1427 if (rc < 0)
1428 goto err_out_disable;
1429
1430 /* save power state before pci_enable_device overwrites it */
1431 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1432 if (pm_cap) {
1433 u16 pwr_command;
1434
1435 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1436 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1437 } else {
2e8a538d 1438 if (netif_msg_probe(tp))
9b91cf9d 1439 dev_err(&pdev->dev,
e53091fa 1440 "PowerManagement capability not found.\n");
1da177e4
LT		 1441 }
1442
1443 /* make sure PCI base addr 1 is MMIO */
1444 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2e8a538d 1445 if (netif_msg_probe(tp))
9b91cf9d 1446 dev_err(&pdev->dev,
b57b7e5a 1447 "region #1 not an MMIO resource, aborting\n");
1da177e4
LT		 1448 rc = -ENODEV;
1449 goto err_out_mwi;
1450 }
1451 /* check for weird/broken PCI region reporting */
1452 if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) {
2e8a538d 1453 if (netif_msg_probe(tp))
9b91cf9d 1454 dev_err(&pdev->dev,
b57b7e5a 1455 "Invalid PCI region size(s), aborting\n");
1da177e4
LT		 1456 rc = -ENODEV;
1457 goto err_out_mwi;
1458 }
1459
1460 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1461 if (rc < 0) {
2e8a538d 1462 if (netif_msg_probe(tp))
9b91cf9d 1463 dev_err(&pdev->dev, "could not request regions.\n");
1da177e4
LT		 1464 goto err_out_mwi;
1465 }
1466
1467 tp->cp_cmd = PCIMulRW | RxChkSum;
1468
1469 if ((sizeof(dma_addr_t) > 4) &&
1470 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1471 tp->cp_cmd |= PCIDAC;
1472 dev->features |= NETIF_F_HIGHDMA;
1473 } else {
1474 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1475 if (rc < 0) {
2e8a538d 1476 if (netif_msg_probe(tp))
9b91cf9d 1477 dev_err(&pdev->dev,
b57b7e5a 1478 "DMA configuration failed.\n");
1da177e4
LT		 1479 goto err_out_free_res;
1480 }
1481 }
1482
1483 pci_set_master(pdev);
1484
1485 /* ioremap MMIO region */
1486 ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE);
1487 if (ioaddr == NULL) {
b57b7e5a 1488 if (netif_msg_probe(tp))
9b91cf9d 1489 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4
LT		 1490 rc = -EIO;
1491 goto err_out_free_res;
1492 }
1493
1494 /* Unneeded ? Don't mess with Mrs. Murphy. */
1495 rtl8169_irq_mask_and_ack(ioaddr);
1496
1497 /* Soft reset the chip. */
1498 RTL_W8(ChipCmd, CmdReset);
1499
1500 /* Check that the chip has finished the reset. */
1501 for (i = 1000; i > 0; i--) {
1502 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1503 break;
1504 udelay(10);
1505 }
1506
1507 /* Identify chip attached to board */
1508 rtl8169_get_mac_version(tp, ioaddr);
1509 rtl8169_get_phy_version(tp, ioaddr);
1510
1511 rtl8169_print_mac_version(tp);
1512 rtl8169_print_phy_version(tp);
1513
1514 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1515 if (tp->mac_version == rtl_chip_info[i].mac_version)
1516 break;
1517 }
1518 if (i < 0) {
1519 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1520 if (netif_msg_probe(tp)) {
2e8a538d 1521 dev_printk(KERN_DEBUG, &pdev->dev,
b57b7e5a 1522 "unknown chip version, assuming %s\n",
2e8a538d 1523 rtl_chip_info[0].name);
b57b7e5a 1524 }
1da177e4
LT		 1525 i++;
1526 }
1527 tp->chipset = i;
1528
5d06a99f
FR		 1529 RTL_W8(Cfg9346, Cfg9346_Unlock);
1530 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1531 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1532 RTL_W8(Cfg9346, Cfg9346_Lock);
1533
1da177e4
LT		 1534 *ioaddr_out = ioaddr;
1535 *dev_out = dev;
1536out:
1537 return rc;
1538
1539err_out_free_res:
1540 pci_release_regions(pdev);
1541
1542err_out_mwi:
1543 pci_clear_mwi(pdev);
1544
1545err_out_disable:
1546 pci_disable_device(pdev);
1547
1548err_out_free_dev:
1549 free_netdev(dev);
1550err_out:
1551 *ioaddr_out = NULL;
1552 *dev_out = NULL;
1553 goto out;
1554}
1555
1556static int __devinit
1557rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1558{
1559 struct net_device *dev = NULL;
1560 struct rtl8169_private *tp;
1561 void __iomem *ioaddr = NULL;
1562 static int board_idx = -1;
1da177e4
LT		 1563 u8 autoneg, duplex;
1564 u16 speed;
1565 int i, rc;
1566
1567 assert(pdev != NULL);
1568 assert(ent != NULL);
1569
1570 board_idx++;
1571
b57b7e5a 1572 if (netif_msg_drv(&debug)) {
1da177e4
LT		 1573 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1574 MODULENAME, RTL8169_VERSION);
1da177e4
LT		 1575 }
1576
1577 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
1578 if (rc)
1579 return rc;
1580
1581 tp = netdev_priv(dev);
1582 assert(ioaddr != NULL);
1583
1584 if (RTL_R8(PHYstatus) & TBI_Enable) {
1585 tp->set_speed = rtl8169_set_speed_tbi;
1586 tp->get_settings = rtl8169_gset_tbi;
1587 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1588 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1589 tp->link_ok = rtl8169_tbi_link_ok;
1590
1591 tp->phy_1000_ctrl_reg = PHY_Cap_1000_Full; /* Implied by TBI */
1592 } else {
1593 tp->set_speed = rtl8169_set_speed_xmii;
1594 tp->get_settings = rtl8169_gset_xmii;
1595 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1596 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1597 tp->link_ok = rtl8169_xmii_link_ok;
1598 }
1599
1600 /* Get MAC address. FIXME: read EEPROM */
1601 for (i = 0; i < MAC_ADDR_LEN; i++)
1602 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1603 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1604
1605 dev->open = rtl8169_open;
1606 dev->hard_start_xmit = rtl8169_start_xmit;
1607 dev->get_stats = rtl8169_get_stats;
1608 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1609 dev->stop = rtl8169_close;
1610 dev->tx_timeout = rtl8169_tx_timeout;
1611 dev->set_multicast_list = rtl8169_set_rx_mode;
1612 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1613 dev->irq = pdev->irq;
1614 dev->base_addr = (unsigned long) ioaddr;
1615 dev->change_mtu = rtl8169_change_mtu;
1616
1617#ifdef CONFIG_R8169_NAPI
1618 dev->poll = rtl8169_poll;
1619 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1620#endif
1621
1622#ifdef CONFIG_R8169_VLAN
1623 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1624 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1625 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
1626#endif
1627
1628#ifdef CONFIG_NET_POLL_CONTROLLER
1629 dev->poll_controller = rtl8169_netpoll;
1630#endif
1631
1632 tp->intr_mask = 0xffff;
1633 tp->pci_dev = pdev;
1634 tp->mmio_addr = ioaddr;
1635
1636 spin_lock_init(&tp->lock);
1637
1638 rc = register_netdev(dev);
1639 if (rc) {
1640 rtl8169_release_board(pdev, dev, ioaddr);
1641 return rc;
1642 }
1643
b57b7e5a
SH		 1644 if (netif_msg_probe(tp)) {
1645 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n",
1646 dev->name, rtl_chip_info[tp->chipset].name);
1647 }
1da177e4
LT		 1648
1649 pci_set_drvdata(pdev, dev);
1650
b57b7e5a
SH		 1651 if (netif_msg_probe(tp)) {
1652 printk(KERN_INFO "%s: %s at 0x%lx, "
1653 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1654 "IRQ %d\n",
1655 dev->name,
1656 rtl_chip_info[ent->driver_data].name,
1657 dev->base_addr,
1658 dev->dev_addr[0], dev->dev_addr[1],
1659 dev->dev_addr[2], dev->dev_addr[3],
1660 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1661 }
1da177e4
LT		 1662
1663 rtl8169_hw_phy_config(dev);
1664
1665 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1666 RTL_W8(0x82, 0x01);
1667
1668 if (tp->mac_version < RTL_GIGA_MAC_VER_E) {
1669 dprintk("Set PCI Latency=0x40\n");
1670 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
1671 }
1672
1673 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1674 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1675 RTL_W8(0x82, 0x01);
1676 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1677 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1678 }
1679
1680 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1681
1682 rtl8169_set_speed(dev, autoneg, speed, duplex);
1683
b57b7e5a 1684 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1da177e4
LT		 1685 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1686
1687 return 0;
1688}
1689
1690static void __devexit
1691rtl8169_remove_one(struct pci_dev *pdev)
1692{
1693 struct net_device *dev = pci_get_drvdata(pdev);
1694 struct rtl8169_private *tp = netdev_priv(dev);
1695
1696 assert(dev != NULL);
1697 assert(tp != NULL);
1698
1699 unregister_netdev(dev);
1700 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1701 pci_set_drvdata(pdev, NULL);
1702}
1703
1da177e4
LT		 1704static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1705 struct net_device *dev)
1706{
1707 unsigned int mtu = dev->mtu;
1708
1709 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1710}
1711
1712static int rtl8169_open(struct net_device *dev)
1713{
1714 struct rtl8169_private *tp = netdev_priv(dev);
1715 struct pci_dev *pdev = tp->pci_dev;
1716 int retval;
1717
1718 rtl8169_set_rxbufsize(tp, dev);
1719
1720 retval =
1fb9df5d 1721 request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1722 if (retval < 0)
1723 goto out;
1724
1725 retval = -ENOMEM;
1726
1727 /*
1728 * Rx and Tx desscriptors needs 256 bytes alignment.
1729 * pci_alloc_consistent provides more.
1730 */
1731 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1732 &tp->TxPhyAddr);
1733 if (!tp->TxDescArray)
1734 goto err_free_irq;
1735
1736 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1737 &tp->RxPhyAddr);
1738 if (!tp->RxDescArray)
1739 goto err_free_tx;
1740
1741 retval = rtl8169_init_ring(dev);
1742 if (retval < 0)
1743 goto err_free_rx;
1744
1745 INIT_WORK(&tp->task, NULL, dev);
1746
1747 rtl8169_hw_start(dev);
1748
1749 rtl8169_request_timer(dev);
1750
1751 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1752out:
1753 return retval;
1754
1755err_free_rx:
1756 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1757 tp->RxPhyAddr);
1758err_free_tx:
1759 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1760 tp->TxPhyAddr);
1761err_free_irq:
1762 free_irq(dev->irq, dev);
1763 goto out;
1764}
1765
1766static void rtl8169_hw_reset(void __iomem *ioaddr)
1767{
1768 /* Disable interrupts */
1769 rtl8169_irq_mask_and_ack(ioaddr);
1770
1771 /* Reset the chipset */
1772 RTL_W8(ChipCmd, CmdReset);
1773
1774 /* PCI commit */
1775 RTL_R8(ChipCmd);
1776}
1777
1778static void
1779rtl8169_hw_start(struct net_device *dev)
1780{
1781 struct rtl8169_private *tp = netdev_priv(dev);
1782 void __iomem *ioaddr = tp->mmio_addr;
1783 u32 i;
1784
1785 /* Soft reset the chip. */
1786 RTL_W8(ChipCmd, CmdReset);
1787
1788 /* Check that the chip has finished the reset. */
1789 for (i = 1000; i > 0; i--) {
1790 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1791 break;
1792 udelay(10);
1793 }
1794
1795 RTL_W8(Cfg9346, Cfg9346_Unlock);
1796 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1797 RTL_W8(EarlyTxThres, EarlyTxThld);
1798
126fa4b9
FR		 1799 /* Low hurts. Let's disable the filtering. */
1800 RTL_W16(RxMaxSize, 16383);
1da177e4
LT		 1801
1802 /* Set Rx Config register */
1803 i = rtl8169_rx_config |
1804 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1805 RTL_W32(RxConfig, i);
1806
1807 /* Set DMA burst size and Interframe Gap Time */
1808 RTL_W32(TxConfig,
1809 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
1810 TxInterFrameGapShift));
1811 tp->cp_cmd |= RTL_R16(CPlusCmd);
1812 RTL_W16(CPlusCmd, tp->cp_cmd);
1813
1814 if ((tp->mac_version == RTL_GIGA_MAC_VER_D) ||
1815 (tp->mac_version == RTL_GIGA_MAC_VER_E)) {
1816 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1817 "Bit-3 and bit-14 MUST be 1\n");
1818 tp->cp_cmd |= (1 << 14) | PCIMulRW;
1819 RTL_W16(CPlusCmd, tp->cp_cmd);
1820 }
1821
1822 /*
1823 * Undocumented corner. Supposedly:
1824 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1825 */
1826 RTL_W16(IntrMitigate, 0x0000);
1827
1828 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1829 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1830 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1831 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1832 RTL_W8(Cfg9346, Cfg9346_Lock);
1833 udelay(10);
1834
1835 RTL_W32(RxMissed, 0);
1836
1837 rtl8169_set_rx_mode(dev);
1838
1839 /* no early-rx interrupts */
1840 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1841
1842 /* Enable all known interrupts by setting the interrupt mask. */
1843 RTL_W16(IntrMask, rtl8169_intr_mask);
1844
1845 netif_start_queue(dev);
1846}
1847
1848static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1849{
1850 struct rtl8169_private *tp = netdev_priv(dev);
1851 int ret = 0;
1852
1853 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
1854 return -EINVAL;
1855
1856 dev->mtu = new_mtu;
1857
1858 if (!netif_running(dev))
1859 goto out;
1860
1861 rtl8169_down(dev);
1862
1863 rtl8169_set_rxbufsize(tp, dev);
1864
1865 ret = rtl8169_init_ring(dev);
1866 if (ret < 0)
1867 goto out;
1868
1869 netif_poll_enable(dev);
1870
1871 rtl8169_hw_start(dev);
1872
1873 rtl8169_request_timer(dev);
1874
1875out:
1876 return ret;
1877}
1878
1879static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1880{
1881 desc->addr = 0x0badbadbadbadbadull;
1882 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
1883}
1884
1885static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
1886 struct sk_buff **sk_buff, struct RxDesc *desc)
1887{
1888 struct pci_dev *pdev = tp->pci_dev;
1889
1890 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1891 PCI_DMA_FROMDEVICE);
1892 dev_kfree_skb(*sk_buff);
1893 *sk_buff = NULL;
1894 rtl8169_make_unusable_by_asic(desc);
1895}
1896
1897static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
1898{
1899 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
1900
1901 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
1902}
1903
1904static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
1905 u32 rx_buf_sz)
1906{
1907 desc->addr = cpu_to_le64(mapping);
1908 wmb();
1909 rtl8169_mark_to_asic(desc, rx_buf_sz);
1910}
1911
1912static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1913 struct RxDesc *desc, int rx_buf_sz)
1914{
1915 struct sk_buff *skb;
1916 dma_addr_t mapping;
1917 int ret = 0;
1918
1919 skb = dev_alloc_skb(rx_buf_sz + NET_IP_ALIGN);
1920 if (!skb)
1921 goto err_out;
1922
1923 skb_reserve(skb, NET_IP_ALIGN);
1924 *sk_buff = skb;
1925
689be439 1926 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 1927 PCI_DMA_FROMDEVICE);
1928
1929 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1930
1931out:
1932 return ret;
1933
1934err_out:
1935 ret = -ENOMEM;
1936 rtl8169_make_unusable_by_asic(desc);
1937 goto out;
1938}
1939
1940static void rtl8169_rx_clear(struct rtl8169_private *tp)
1941{
1942 int i;
1943
1944 for (i = 0; i < NUM_RX_DESC; i++) {
1945 if (tp->Rx_skbuff[i]) {
1946 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
1947 tp->RxDescArray + i);
1948 }
1949 }
1950}
1951
1952static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
1953 u32 start, u32 end)
1954{
1955 u32 cur;
1956
1957 for (cur = start; end - cur > 0; cur++) {
1958 int ret, i = cur % NUM_RX_DESC;
1959
1960 if (tp->Rx_skbuff[i])
1961 continue;
1962
1963 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
1964 tp->RxDescArray + i, tp->rx_buf_sz);
1965 if (ret < 0)
1966 break;
1967 }
1968 return cur - start;
1969}
1970
1971static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1972{
1973 desc->opts1 |= cpu_to_le32(RingEnd);
1974}
1975
1976static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
1977{
1978 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
1979}
1980
1981static int rtl8169_init_ring(struct net_device *dev)
1982{
1983 struct rtl8169_private *tp = netdev_priv(dev);
1984
1985 rtl8169_init_ring_indexes(tp);
1986
1987 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
1988 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
1989
1990 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
1991 goto err_out;
1992
1993 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
1994
1995 return 0;
1996
1997err_out:
1998 rtl8169_rx_clear(tp);
1999 return -ENOMEM;
2000}
2001
2002static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2003 struct TxDesc *desc)
2004{
2005 unsigned int len = tx_skb->len;
2006
2007 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2008 desc->opts1 = 0x00;
2009 desc->opts2 = 0x00;
2010 desc->addr = 0x00;
2011 tx_skb->len = 0;
2012}
2013
2014static void rtl8169_tx_clear(struct rtl8169_private *tp)
2015{
2016 unsigned int i;
2017
2018 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2019 unsigned int entry = i % NUM_TX_DESC;
2020 struct ring_info *tx_skb = tp->tx_skb + entry;
2021 unsigned int len = tx_skb->len;
2022
2023 if (len) {
2024 struct sk_buff *skb = tx_skb->skb;
2025
2026 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2027 tp->TxDescArray + entry);
2028 if (skb) {
2029 dev_kfree_skb(skb);
2030 tx_skb->skb = NULL;
2031 }
2032 tp->stats.tx_dropped++;
2033 }
2034 }
2035 tp->cur_tx = tp->dirty_tx = 0;
2036}
2037
2038static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
2039{
2040 struct rtl8169_private *tp = netdev_priv(dev);
2041
2042 PREPARE_WORK(&tp->task, task, dev);
2043 schedule_delayed_work(&tp->task, 4);
2044}
2045
2046static void rtl8169_wait_for_quiescence(struct net_device *dev)
2047{
2048 struct rtl8169_private *tp = netdev_priv(dev);
2049 void __iomem *ioaddr = tp->mmio_addr;
2050
2051 synchronize_irq(dev->irq);
2052
2053 /* Wait for any pending NAPI task to complete */
2054 netif_poll_disable(dev);
2055
2056 rtl8169_irq_mask_and_ack(ioaddr);
2057
2058 netif_poll_enable(dev);
2059}
2060
2061static void rtl8169_reinit_task(void *_data)
2062{
2063 struct net_device *dev = _data;
2064 int ret;
2065
2066 if (netif_running(dev)) {
2067 rtl8169_wait_for_quiescence(dev);
2068 rtl8169_close(dev);
2069 }
2070
2071 ret = rtl8169_open(dev);
2072 if (unlikely(ret < 0)) {
2073 if (net_ratelimit()) {
b57b7e5a
SH		 2074 struct rtl8169_private *tp = netdev_priv(dev);
2075
2076 if (netif_msg_drv(tp)) {
2077 printk(PFX KERN_ERR
2078 "%s: reinit failure (status = %d)."
2079 " Rescheduling.\n", dev->name, ret);
2080 }
1da177e4
LT		 2081 }
2082 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2083 }
2084}
2085
2086static void rtl8169_reset_task(void *_data)
2087{
2088 struct net_device *dev = _data;
2089 struct rtl8169_private *tp = netdev_priv(dev);
2090
2091 if (!netif_running(dev))
2092 return;
2093
2094 rtl8169_wait_for_quiescence(dev);
2095
2096 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2097 rtl8169_tx_clear(tp);
2098
2099 if (tp->dirty_rx == tp->cur_rx) {
2100 rtl8169_init_ring_indexes(tp);
2101 rtl8169_hw_start(dev);
2102 netif_wake_queue(dev);
2103 } else {
2104 if (net_ratelimit()) {
b57b7e5a
SH		 2105 struct rtl8169_private *tp = netdev_priv(dev);
2106
2107 if (netif_msg_intr(tp)) {
2108 printk(PFX KERN_EMERG
2109 "%s: Rx buffers shortage\n", dev->name);
2110 }
1da177e4
LT		 2111 }
2112 rtl8169_schedule_work(dev, rtl8169_reset_task);
2113 }
2114}
2115
2116static void rtl8169_tx_timeout(struct net_device *dev)
2117{
2118 struct rtl8169_private *tp = netdev_priv(dev);
2119
2120 rtl8169_hw_reset(tp->mmio_addr);
2121
2122 /* Let's wait a bit while any (async) irq lands on */
2123 rtl8169_schedule_work(dev, rtl8169_reset_task);
2124}
2125
2126static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2127 u32 opts1)
2128{
2129 struct skb_shared_info *info = skb_shinfo(skb);
2130 unsigned int cur_frag, entry;
2131 struct TxDesc *txd;
2132
2133 entry = tp->cur_tx;
2134 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2135 skb_frag_t *frag = info->frags + cur_frag;
2136 dma_addr_t mapping;
2137 u32 status, len;
2138 void *addr;
2139
2140 entry = (entry + 1) % NUM_TX_DESC;
2141
2142 txd = tp->TxDescArray + entry;
2143 len = frag->size;
2144 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2145 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2146
2147 /* anti gcc 2.95.3 bugware (sic) */
2148 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2149
2150 txd->opts1 = cpu_to_le32(status);
2151 txd->addr = cpu_to_le64(mapping);
2152
2153 tp->tx_skb[entry].len = len;
2154 }
2155
2156 if (cur_frag) {
2157 tp->tx_skb[entry].skb = skb;
2158 txd->opts1 |= cpu_to_le32(LastFrag);
2159 }
2160
2161 return cur_frag;
2162}
2163
2164static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2165{
2166 if (dev->features & NETIF_F_TSO) {
7967168c 2167 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2168
2169 if (mss)
2170 return LargeSend | ((mss & MSSMask) << MSSShift);
2171 }
2172 if (skb->ip_summed == CHECKSUM_HW) {
2173 const struct iphdr *ip = skb->nh.iph;
2174
2175 if (ip->protocol == IPPROTO_TCP)
2176 return IPCS | TCPCS;
2177 else if (ip->protocol == IPPROTO_UDP)
2178 return IPCS | UDPCS;
2179 WARN_ON(1); /* we need a WARN() */
2180 }
2181 return 0;
2182}
2183
2184static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2185{
2186 struct rtl8169_private *tp = netdev_priv(dev);
2187 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2188 struct TxDesc *txd = tp->TxDescArray + entry;
2189 void __iomem *ioaddr = tp->mmio_addr;
2190 dma_addr_t mapping;
2191 u32 status, len;
2192 u32 opts1;
2193 int ret = 0;
2194
2195 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2196 if (netif_msg_drv(tp)) {
2197 printk(KERN_ERR
2198 "%s: BUG! Tx Ring full when queue awake!\n",
2199 dev->name);
2200 }
1da177e4
LT		 2201 goto err_stop;
2202 }
2203
2204 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2205 goto err_stop;
2206
2207 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2208
2209 frags = rtl8169_xmit_frags(tp, skb, opts1);
2210 if (frags) {
2211 len = skb_headlen(skb);
2212 opts1 |= FirstFrag;
2213 } else {
2214 len = skb->len;
2215
2216 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2217 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2218 goto err_update_stats;
2219 len = ETH_ZLEN;
2220 }
2221
2222 opts1 |= FirstFrag | LastFrag;
2223 tp->tx_skb[entry].skb = skb;
2224 }
2225
2226 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2227
2228 tp->tx_skb[entry].len = len;
2229 txd->addr = cpu_to_le64(mapping);
2230 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2231
2232 wmb();
2233
2234 /* anti gcc 2.95.3 bugware (sic) */
2235 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2236 txd->opts1 = cpu_to_le32(status);
2237
2238 dev->trans_start = jiffies;
2239
2240 tp->cur_tx += frags + 1;
2241
2242 smp_wmb();
2243
2244 RTL_W8(TxPoll, 0x40); /* set polling bit */
2245
2246 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2247 netif_stop_queue(dev);
2248 smp_rmb();
2249 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2250 netif_wake_queue(dev);
2251 }
2252
2253out:
2254 return ret;
2255
2256err_stop:
2257 netif_stop_queue(dev);
2258 ret = 1;
2259err_update_stats:
2260 tp->stats.tx_dropped++;
2261 goto out;
2262}
2263
2264static void rtl8169_pcierr_interrupt(struct net_device *dev)
2265{
2266 struct rtl8169_private *tp = netdev_priv(dev);
2267 struct pci_dev *pdev = tp->pci_dev;
2268 void __iomem *ioaddr = tp->mmio_addr;
2269 u16 pci_status, pci_cmd;
2270
2271 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2272 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2273
b57b7e5a
SH		 2274 if (netif_msg_intr(tp)) {
2275 printk(KERN_ERR
2276 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2277 dev->name, pci_cmd, pci_status);
2278 }
1da177e4
LT		 2279
2280 /*
2281 * The recovery sequence below admits a very elaborated explanation:
2282 * - it seems to work;
2283 * - I did not see what else could be done.
2284 *
2285 * Feel free to adjust to your needs.
2286 */
2287 pci_write_config_word(pdev, PCI_COMMAND,
2288 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2289
2290 pci_write_config_word(pdev, PCI_STATUS,
2291 pci_status & (PCI_STATUS_DETECTED_PARITY |
2292 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2293 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2294
2295 /* The infamous DAC f*ckup only happens at boot time */
2296 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2297 if (netif_msg_intr(tp))
2298 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2299 tp->cp_cmd &= ~PCIDAC;
2300 RTL_W16(CPlusCmd, tp->cp_cmd);
2301 dev->features &= ~NETIF_F_HIGHDMA;
2302 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2303 }
2304
2305 rtl8169_hw_reset(ioaddr);
2306}
2307
2308static void
2309rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2310 void __iomem *ioaddr)
2311{
2312 unsigned int dirty_tx, tx_left;
2313
2314 assert(dev != NULL);
2315 assert(tp != NULL);
2316 assert(ioaddr != NULL);
2317
2318 dirty_tx = tp->dirty_tx;
2319 smp_rmb();
2320 tx_left = tp->cur_tx - dirty_tx;
2321
2322 while (tx_left > 0) {
2323 unsigned int entry = dirty_tx % NUM_TX_DESC;
2324 struct ring_info *tx_skb = tp->tx_skb + entry;
2325 u32 len = tx_skb->len;
2326 u32 status;
2327
2328 rmb();
2329 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2330 if (status & DescOwn)
2331 break;
2332
2333 tp->stats.tx_bytes += len;
2334 tp->stats.tx_packets++;
2335
2336 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2337
2338 if (status & LastFrag) {
2339 dev_kfree_skb_irq(tx_skb->skb);
2340 tx_skb->skb = NULL;
2341 }
2342 dirty_tx++;
2343 tx_left--;
2344 }
2345
2346 if (tp->dirty_tx != dirty_tx) {
2347 tp->dirty_tx = dirty_tx;
2348 smp_wmb();
2349 if (netif_queue_stopped(dev) &&
2350 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2351 netif_wake_queue(dev);
2352 }
2353 }
2354}
2355
126fa4b9
FR		 2356static inline int rtl8169_fragmented_frame(u32 status)
2357{
2358 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2359}
2360
1da177e4
LT		 2361static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2362{
2363 u32 opts1 = le32_to_cpu(desc->opts1);
2364 u32 status = opts1 & RxProtoMask;
2365
2366 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2367 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2368 ((status == RxProtoIP) && !(opts1 & IPFail)))
2369 skb->ip_summed = CHECKSUM_UNNECESSARY;
2370 else
2371 skb->ip_summed = CHECKSUM_NONE;
2372}
2373
2374static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
2375 struct RxDesc *desc, int rx_buf_sz)
2376{
2377 int ret = -1;
2378
2379 if (pkt_size < rx_copybreak) {
2380 struct sk_buff *skb;
2381
2382 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
2383 if (skb) {
2384 skb_reserve(skb, NET_IP_ALIGN);
689be439 2385 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
1da177e4
LT		 2386 *sk_buff = skb;
2387 rtl8169_mark_to_asic(desc, rx_buf_sz);
2388 ret = 0;
2389 }
2390 }
2391 return ret;
2392}
2393
2394static int
2395rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2396 void __iomem *ioaddr)
2397{
2398 unsigned int cur_rx, rx_left;
2399 unsigned int delta, count;
2400
2401 assert(dev != NULL);
2402 assert(tp != NULL);
2403 assert(ioaddr != NULL);
2404
2405 cur_rx = tp->cur_rx;
2406 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2407 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2408
4dcb7d33 2409 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2410 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2411 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2412 u32 status;
2413
2414 rmb();
126fa4b9 2415 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2416
2417 if (status & DescOwn)
2418 break;
4dcb7d33 2419 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2420 if (netif_msg_rx_err(tp)) {
2421 printk(KERN_INFO
2422 "%s: Rx ERROR. status = %08x\n",
2423 dev->name, status);
2424 }
1da177e4
LT		 2425 tp->stats.rx_errors++;
2426 if (status & (RxRWT | RxRUNT))
2427 tp->stats.rx_length_errors++;
2428 if (status & RxCRC)
2429 tp->stats.rx_crc_errors++;
126fa4b9 2430 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2431 } else {
1da177e4
LT		 2432 struct sk_buff *skb = tp->Rx_skbuff[entry];
2433 int pkt_size = (status & 0x00001FFF) - 4;
2434 void (*pci_action)(struct pci_dev *, dma_addr_t,
2435 size_t, int) = pci_dma_sync_single_for_device;
2436
126fa4b9
FR		 2437 /*
2438 * The driver does not support incoming fragmented
2439 * frames. They are seen as a symptom of over-mtu
2440 * sized frames.
2441 */
2442 if (unlikely(rtl8169_fragmented_frame(status))) {
2443 tp->stats.rx_dropped++;
2444 tp->stats.rx_length_errors++;
2445 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2446 continue;
126fa4b9
FR		 2447 }
2448
1da177e4
LT		 2449 rtl8169_rx_csum(skb, desc);
2450
2451 pci_dma_sync_single_for_cpu(tp->pci_dev,
2452 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2453 PCI_DMA_FROMDEVICE);
2454
2455 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
2456 tp->rx_buf_sz)) {
2457 pci_action = pci_unmap_single;
2458 tp->Rx_skbuff[entry] = NULL;
2459 }
2460
2461 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2462 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2463
2464 skb->dev = dev;
2465 skb_put(skb, pkt_size);
2466 skb->protocol = eth_type_trans(skb, dev);
2467
2468 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2469 rtl8169_rx_skb(skb);
2470
2471 dev->last_rx = jiffies;
2472 tp->stats.rx_bytes += pkt_size;
2473 tp->stats.rx_packets++;
2474 }
1da177e4
LT		 2475 }
2476
2477 count = cur_rx - tp->cur_rx;
2478 tp->cur_rx = cur_rx;
2479
2480 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2481 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2482 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2483 tp->dirty_rx += delta;
2484
2485 /*
2486 * FIXME: until there is periodic timer to try and refill the ring,
2487 * a temporary shortage may definitely kill the Rx process.
2488 * - disable the asic to try and avoid an overflow and kick it again
2489 * after refill ?
2490 * - how do others driver handle this condition (Uh oh...).
2491 */
b57b7e5a 2492 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2493 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2494
2495 return count;
2496}
2497
2498/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2499static irqreturn_t
2500rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
2501{
2502 struct net_device *dev = (struct net_device *) dev_instance;
2503 struct rtl8169_private *tp = netdev_priv(dev);
2504 int boguscnt = max_interrupt_work;
2505 void __iomem *ioaddr = tp->mmio_addr;
2506 int status;
2507 int handled = 0;
2508
2509 do {
2510 status = RTL_R16(IntrStatus);
2511
2512 /* hotplug/major error/no more work/shared irq */
2513 if ((status == 0xFFFF) || !status)
2514 break;
2515
2516 handled = 1;
2517
2518 if (unlikely(!netif_running(dev))) {
2519 rtl8169_asic_down(ioaddr);
2520 goto out;
2521 }
2522
2523 status &= tp->intr_mask;
2524 RTL_W16(IntrStatus,
2525 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2526
2527 if (!(status & rtl8169_intr_mask))
2528 break;
2529
2530 if (unlikely(status & SYSErr)) {
2531 rtl8169_pcierr_interrupt(dev);
2532 break;
2533 }
2534
2535 if (status & LinkChg)
2536 rtl8169_check_link_status(dev, tp, ioaddr);
2537
2538#ifdef CONFIG_R8169_NAPI
2539 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2540 tp->intr_mask = ~rtl8169_napi_event;
2541
2542 if (likely(netif_rx_schedule_prep(dev)))
2543 __netif_rx_schedule(dev);
b57b7e5a 2544 else if (netif_msg_intr(tp)) {
1da177e4
LT		 2545 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2546 dev->name, status);
2547 }
2548 break;
2549#else
2550 /* Rx interrupt */
2551 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2552 rtl8169_rx_interrupt(dev, tp, ioaddr);
2553 }
2554 /* Tx interrupt */
2555 if (status & (TxOK | TxErr))
2556 rtl8169_tx_interrupt(dev, tp, ioaddr);
2557#endif
2558
2559 boguscnt--;
2560 } while (boguscnt > 0);
2561
2562 if (boguscnt <= 0) {
7c8b2eb4 2563 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2564 printk(KERN_WARNING
2565 "%s: Too much work at interrupt!\n", dev->name);
2566 }
1da177e4
LT		 2567 /* Clear all interrupt sources. */
2568 RTL_W16(IntrStatus, 0xffff);
2569 }
2570out:
2571 return IRQ_RETVAL(handled);
2572}
2573
2574#ifdef CONFIG_R8169_NAPI
2575static int rtl8169_poll(struct net_device *dev, int *budget)
2576{
2577 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2578 struct rtl8169_private *tp = netdev_priv(dev);
2579 void __iomem *ioaddr = tp->mmio_addr;
2580
2581 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2582 rtl8169_tx_interrupt(dev, tp, ioaddr);
2583
2584 *budget -= work_done;
2585 dev->quota -= work_done;
2586
2587 if (work_done < work_to_do) {
2588 netif_rx_complete(dev);
2589 tp->intr_mask = 0xffff;
2590 /*
2591 * 20040426: the barrier is not strictly required but the
2592 * behavior of the irq handler could be less predictable
2593 * without it. Btw, the lack of flush for the posted pci
2594 * write is safe - FR
2595 */
2596 smp_wmb();
2597 RTL_W16(IntrMask, rtl8169_intr_mask);
2598 }
2599
2600 return (work_done >= work_to_do);
2601}
2602#endif
2603
2604static void rtl8169_down(struct net_device *dev)
2605{
2606 struct rtl8169_private *tp = netdev_priv(dev);
2607 void __iomem *ioaddr = tp->mmio_addr;
2608 unsigned int poll_locked = 0;
2609
2610 rtl8169_delete_timer(dev);
2611
2612 netif_stop_queue(dev);
2613
2614 flush_scheduled_work();
2615
2616core_down:
2617 spin_lock_irq(&tp->lock);
2618
2619 rtl8169_asic_down(ioaddr);
2620
2621 /* Update the error counts. */
2622 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2623 RTL_W32(RxMissed, 0);
2624
2625 spin_unlock_irq(&tp->lock);
2626
2627 synchronize_irq(dev->irq);
2628
2629 if (!poll_locked) {
2630 netif_poll_disable(dev);
2631 poll_locked++;
2632 }
2633
2634 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2635 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2636
2637 /*
2638 * And now for the 50k$ question: are IRQ disabled or not ?
2639 *
2640 * Two paths lead here:
2641 * 1) dev->close
2642 * -> netif_running() is available to sync the current code and the
2643 * IRQ handler. See rtl8169_interrupt for details.
2644 * 2) dev->change_mtu
2645 * -> rtl8169_poll can not be issued again and re-enable the
2646 * interruptions. Let's simply issue the IRQ down sequence again.
2647 */
2648 if (RTL_R16(IntrMask))
2649 goto core_down;
2650
2651 rtl8169_tx_clear(tp);
2652
2653 rtl8169_rx_clear(tp);
2654}
2655
2656static int rtl8169_close(struct net_device *dev)
2657{
2658 struct rtl8169_private *tp = netdev_priv(dev);
2659 struct pci_dev *pdev = tp->pci_dev;
2660
2661 rtl8169_down(dev);
2662
2663 free_irq(dev->irq, dev);
2664
2665 netif_poll_enable(dev);
2666
2667 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2668 tp->RxPhyAddr);
2669 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2670 tp->TxPhyAddr);
2671 tp->TxDescArray = NULL;
2672 tp->RxDescArray = NULL;
2673
2674 return 0;
2675}
2676
2677static void
2678rtl8169_set_rx_mode(struct net_device *dev)
2679{
2680 struct rtl8169_private *tp = netdev_priv(dev);
2681 void __iomem *ioaddr = tp->mmio_addr;
2682 unsigned long flags;
2683 u32 mc_filter[2]; /* Multicast hash filter */
2684 int i, rx_mode;
2685 u32 tmp = 0;
2686
2687 if (dev->flags & IFF_PROMISC) {
2688 /* Unconditionally log net taps. */
b57b7e5a
SH		 2689 if (netif_msg_link(tp)) {
2690 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2691 dev->name);
2692 }
1da177e4
LT		 2693 rx_mode =
2694 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2695 AcceptAllPhys;
2696 mc_filter[1] = mc_filter[0] = 0xffffffff;
2697 } else if ((dev->mc_count > multicast_filter_limit)
2698 || (dev->flags & IFF_ALLMULTI)) {
2699 /* Too many to filter perfectly -- accept all multicasts. */
2700 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2701 mc_filter[1] = mc_filter[0] = 0xffffffff;
2702 } else {
2703 struct dev_mc_list *mclist;
2704 rx_mode = AcceptBroadcast | AcceptMyPhys;
2705 mc_filter[1] = mc_filter[0] = 0;
2706 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2707 i++, mclist = mclist->next) {
2708 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2709 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2710 rx_mode |= AcceptMulticast;
2711 }
2712 }
2713
2714 spin_lock_irqsave(&tp->lock, flags);
2715
2716 tmp = rtl8169_rx_config | rx_mode |
2717 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2718
2719 RTL_W32(RxConfig, tmp);
2720 RTL_W32(MAR0 + 0, mc_filter[0]);
2721 RTL_W32(MAR0 + 4, mc_filter[1]);
2722
2723 spin_unlock_irqrestore(&tp->lock, flags);
2724}
2725
2726/**
2727 * rtl8169_get_stats - Get rtl8169 read/write statistics
2728 * @dev: The Ethernet Device to get statistics for
2729 *
2730 * Get TX/RX statistics for rtl8169
2731 */
2732static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2733{
2734 struct rtl8169_private *tp = netdev_priv(dev);
2735 void __iomem *ioaddr = tp->mmio_addr;
2736 unsigned long flags;
2737
2738 if (netif_running(dev)) {
2739 spin_lock_irqsave(&tp->lock, flags);
2740 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2741 RTL_W32(RxMissed, 0);
2742 spin_unlock_irqrestore(&tp->lock, flags);
2743 }
2744
2745 return &tp->stats;
2746}
2747
5d06a99f
FR		 2748#ifdef CONFIG_PM
2749
2750static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2751{
2752 struct net_device *dev = pci_get_drvdata(pdev);
2753 struct rtl8169_private *tp = netdev_priv(dev);
2754 void __iomem *ioaddr = tp->mmio_addr;
2755
2756 if (!netif_running(dev))
2757 goto out;
2758
2759 netif_device_detach(dev);
2760 netif_stop_queue(dev);
2761
2762 spin_lock_irq(&tp->lock);
2763
2764 rtl8169_asic_down(ioaddr);
2765
2766 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2767 RTL_W32(RxMissed, 0);
2768
2769 spin_unlock_irq(&tp->lock);
2770
2771 pci_save_state(pdev);
61a4dcc2 2772 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
5d06a99f
FR		 2773 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2774out:
2775 return 0;
2776}
2777
2778static int rtl8169_resume(struct pci_dev *pdev)
2779{
2780 struct net_device *dev = pci_get_drvdata(pdev);
2781
2782 if (!netif_running(dev))
2783 goto out;
2784
2785 netif_device_attach(dev);
2786
2787 pci_set_power_state(pdev, PCI_D0);
2788 pci_restore_state(pdev);
61a4dcc2 2789 pci_enable_wake(pdev, PCI_D0, 0);
5d06a99f
FR		 2790
2791 rtl8169_schedule_work(dev, rtl8169_reset_task);
2792out:
2793 return 0;
2794}
2795
2796#endif /* CONFIG_PM */
2797
1da177e4
LT		 2798static struct pci_driver rtl8169_pci_driver = {
2799 .name = MODULENAME,
2800 .id_table = rtl8169_pci_tbl,
2801 .probe = rtl8169_init_one,
2802 .remove = __devexit_p(rtl8169_remove_one),
2803#ifdef CONFIG_PM
2804 .suspend = rtl8169_suspend,
2805 .resume = rtl8169_resume,
2806#endif
2807};
2808
2809static int __init
2810rtl8169_init_module(void)
2811{
2812 return pci_module_init(&rtl8169_pci_driver);
2813}
2814
2815static void __exit
2816rtl8169_cleanup_module(void)
2817{
2818 pci_unregister_driver(&rtl8169_pci_driver);
2819}
2820
2821module_init(rtl8169_init_module);
2822module_exit(rtl8169_cleanup_module);
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