[linux.git] / drivers / net / wireless / wl12xx / wl1251.h

/*
 * This file is part of wl1251
 *
 * Copyright (c) 1998-2007 Texas Instruments Incorporated
 * Copyright (C) 2008-2009 Nokia Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#ifndef __WL1251_H__
#define __WL1251_H__

#include <linux/mutex.h>
#include <linux/list.h>
#include <linux/bitops.h>
#include <net/mac80211.h>

#define DRIVER_NAME "wl1251"
#define DRIVER_PREFIX DRIVER_NAME ": "

enum {
	DEBUG_NONE	= 0,
	DEBUG_IRQ	= BIT(0),
	DEBUG_SPI	= BIT(1),
	DEBUG_BOOT	= BIT(2),
	DEBUG_MAILBOX	= BIT(3),
	DEBUG_NETLINK	= BIT(4),
	DEBUG_EVENT	= BIT(5),
	DEBUG_TX	= BIT(6),
	DEBUG_RX	= BIT(7),
	DEBUG_SCAN	= BIT(8),
	DEBUG_CRYPT	= BIT(9),
	DEBUG_PSM	= BIT(10),
	DEBUG_MAC80211	= BIT(11),
	DEBUG_CMD	= BIT(12),
	DEBUG_ACX	= BIT(13),
	DEBUG_ALL	= ~0,
};

#define DEBUG_LEVEL (DEBUG_NONE)

#define DEBUG_DUMP_LIMIT 1024

#define wl1251_error(fmt, arg...) \
	printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg)

#define wl1251_warning(fmt, arg...) \
	printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg)

#define wl1251_notice(fmt, arg...) \
	printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg)

#define wl1251_info(fmt, arg...) \
	printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg)

#define wl1251_debug(level, fmt, arg...) \
	do { \
		if (level & DEBUG_LEVEL) \
			printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \
	} while (0)

#define wl1251_dump(level, prefix, buf, len)	\
	do { \
		if (level & DEBUG_LEVEL) \
			print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
				       DUMP_PREFIX_OFFSET, 16, 1,	\
				       buf,				\
				       min_t(size_t, len, DEBUG_DUMP_LIMIT), \
				       0);				\
	} while (0)

#define wl1251_dump_ascii(level, prefix, buf, len)	\
	do { \
		if (level & DEBUG_LEVEL) \
			print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
				       DUMP_PREFIX_OFFSET, 16, 1,	\
				       buf,				\
				       min_t(size_t, len, DEBUG_DUMP_LIMIT), \
				       true);				\
	} while (0)

#define WL1251_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN |	\
				  CFG_BSSID_FILTER_EN)

#define WL1251_DEFAULT_RX_FILTER (CFG_RX_PRSP_EN |  \
				  CFG_RX_MGMT_EN |  \
				  CFG_RX_DATA_EN |  \
				  CFG_RX_CTL_EN |   \
				  CFG_RX_BCN_EN |   \
				  CFG_RX_AUTH_EN |  \
				  CFG_RX_ASSOC_EN)

#define WL1251_BUSY_WORD_LEN 8

struct boot_attr {
	u32 radio_type;
	u8 mac_clock;
	u8 arm_clock;
	int firmware_debug;
	u32 minor;
	u32 major;
	u32 bugfix;
};

enum wl1251_state {
	WL1251_STATE_OFF,
	WL1251_STATE_ON,
	WL1251_STATE_PLT,
};

enum wl1251_partition_type {
	PART_DOWN,
	PART_WORK,
	PART_DRPW,

	PART_TABLE_LEN
};

struct wl1251_partition {
	u32 size;
	u32 start;
};

struct wl1251_partition_set {
	struct wl1251_partition mem;
	struct wl1251_partition reg;
};

struct wl1251;

struct wl1251_stats {
	struct acx_statistics *fw_stats;
	unsigned long fw_stats_update;

	unsigned int retry_count;
	unsigned int excessive_retries;
};

struct wl1251_debugfs {
	struct dentry *rootdir;
	struct dentry *fw_statistics;

	struct dentry *tx_internal_desc_overflow;

	struct dentry *rx_out_of_mem;
	struct dentry *rx_hdr_overflow;
	struct dentry *rx_hw_stuck;
	struct dentry *rx_dropped;
	struct dentry *rx_fcs_err;
	struct dentry *rx_xfr_hint_trig;
	struct dentry *rx_path_reset;
	struct dentry *rx_reset_counter;

	struct dentry *dma_rx_requested;
	struct dentry *dma_rx_errors;
	struct dentry *dma_tx_requested;
	struct dentry *dma_tx_errors;

	struct dentry *isr_cmd_cmplt;
	struct dentry *isr_fiqs;
	struct dentry *isr_rx_headers;
	struct dentry *isr_rx_mem_overflow;
	struct dentry *isr_rx_rdys;
	struct dentry *isr_irqs;
	struct dentry *isr_tx_procs;
	struct dentry *isr_decrypt_done;
	struct dentry *isr_dma0_done;
	struct dentry *isr_dma1_done;
	struct dentry *isr_tx_exch_complete;
	struct dentry *isr_commands;
	struct dentry *isr_rx_procs;
	struct dentry *isr_hw_pm_mode_changes;
	struct dentry *isr_host_acknowledges;
	struct dentry *isr_pci_pm;
	struct dentry *isr_wakeups;
	struct dentry *isr_low_rssi;

	struct dentry *wep_addr_key_count;
	struct dentry *wep_default_key_count;
	/* skipping wep.reserved */
	struct dentry *wep_key_not_found;
	struct dentry *wep_decrypt_fail;
	struct dentry *wep_packets;
	struct dentry *wep_interrupt;

	struct dentry *pwr_ps_enter;
	struct dentry *pwr_elp_enter;
	struct dentry *pwr_missing_bcns;
	struct dentry *pwr_wake_on_host;
	struct dentry *pwr_wake_on_timer_exp;
	struct dentry *pwr_tx_with_ps;
	struct dentry *pwr_tx_without_ps;
	struct dentry *pwr_rcvd_beacons;
	struct dentry *pwr_power_save_off;
	struct dentry *pwr_enable_ps;
	struct dentry *pwr_disable_ps;
	struct dentry *pwr_fix_tsf_ps;
	/* skipping cont_miss_bcns_spread for now */
	struct dentry *pwr_rcvd_awake_beacons;

	struct dentry *mic_rx_pkts;
	struct dentry *mic_calc_failure;

	struct dentry *aes_encrypt_fail;
	struct dentry *aes_decrypt_fail;
	struct dentry *aes_encrypt_packets;
	struct dentry *aes_decrypt_packets;
	struct dentry *aes_encrypt_interrupt;
	struct dentry *aes_decrypt_interrupt;

	struct dentry *event_heart_beat;
	struct dentry *event_calibration;
	struct dentry *event_rx_mismatch;
	struct dentry *event_rx_mem_empty;
	struct dentry *event_rx_pool;
	struct dentry *event_oom_late;
	struct dentry *event_phy_transmit_error;
	struct dentry *event_tx_stuck;

	struct dentry *ps_pspoll_timeouts;
	struct dentry *ps_upsd_timeouts;
	struct dentry *ps_upsd_max_sptime;
	struct dentry *ps_upsd_max_apturn;
	struct dentry *ps_pspoll_max_apturn;
	struct dentry *ps_pspoll_utilization;
	struct dentry *ps_upsd_utilization;

	struct dentry *rxpipe_rx_prep_beacon_drop;
	struct dentry *rxpipe_descr_host_int_trig_rx_data;
	struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data;
	struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data;
	struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data;

	struct dentry *tx_queue_len;
	struct dentry *tx_queue_status;

	struct dentry *retry_count;
	struct dentry *excessive_retries;
};

struct wl1251_if_operations {
	void (*read)(struct wl1251 *wl, int addr, void *buf, size_t len);
	void (*write)(struct wl1251 *wl, int addr, void *buf, size_t len);
	void (*read_elp)(struct wl1251 *wl, int addr, u32 *val);
	void (*write_elp)(struct wl1251 *wl, int addr, u32 val);
	void (*reset)(struct wl1251 *wl);
	void (*enable_irq)(struct wl1251 *wl);
	void (*disable_irq)(struct wl1251 *wl);
};

struct wl1251 {
	struct ieee80211_hw *hw;
	bool mac80211_registered;

	void *if_priv;
	const struct wl1251_if_operations *if_ops;

	void (*set_power)(bool enable);
	int irq;
	bool use_eeprom;

	enum wl1251_state state;
	struct mutex mutex;

	int physical_mem_addr;
	int physical_reg_addr;
	int virtual_mem_addr;
	int virtual_reg_addr;

	int cmd_box_addr;
	int event_box_addr;
	struct boot_attr boot_attr;

	u8 *fw;
	size_t fw_len;
	u8 *nvs;
	size_t nvs_len;

	u8 bssid[ETH_ALEN];
	u8 mac_addr[ETH_ALEN];
	u8 bss_type;
	u8 listen_int;
	int channel;

	void *target_mem_map;
	struct acx_data_path_params_resp *data_path;

	/* Number of TX packets transferred to the FW, modulo 16 */
	u32 data_in_count;

	/* Frames scheduled for transmission, not handled yet */
	struct sk_buff_head tx_queue;
	bool tx_queue_stopped;

	struct work_struct tx_work;
	struct work_struct filter_work;

	/* Pending TX frames */
	struct sk_buff *tx_frames[16];

	/*
	 * Index pointing to the next TX complete entry
	 * in the cyclic XT complete array we get from
	 * the FW.
	 */
	u32 next_tx_complete;

	/* FW Rx counter */
	u32 rx_counter;

	/* Rx frames handled */
	u32 rx_handled;

	/* Current double buffer */
	u32 rx_current_buffer;
	u32 rx_last_id;

	/* The target interrupt mask */
	u32 intr_mask;
	struct work_struct irq_work;

	/* The mbox event mask */
	u32 event_mask;

	/* Mailbox pointers */
	u32 mbox_ptr[2];

	/* Are we currently scanning */
	bool scanning;

	/* Default key (for WEP) */
	u32 default_key;

	unsigned int tx_mgmt_frm_rate;
	unsigned int tx_mgmt_frm_mod;

	unsigned int rx_config;
	unsigned int rx_filter;

	/* is firmware in elp mode */
	bool elp;

	struct delayed_work elp_work;

	/* we can be in psm, but not in elp, we have to differentiate */
	bool psm;

	/* PSM mode requested */
	bool psm_requested;

	u16 beacon_int;
	u8 dtim_period;

	/* in dBm */
	int power_level;

	struct wl1251_stats stats;
	struct wl1251_debugfs debugfs;

	u32 buffer_32;
	u32 buffer_cmd;
	u8 buffer_busyword[WL1251_BUSY_WORD_LEN];
	struct wl1251_rx_descriptor *rx_descriptor;

	struct ieee80211_vif *vif;

	u32 chip_id;
	char fw_ver[21];

	/* Most recently reported noise in dBm */
	s8 noise;
};

int wl1251_plt_start(struct wl1251 *wl);
int wl1251_plt_stop(struct wl1251 *wl);

struct ieee80211_hw *wl1251_alloc_hw(void);
int wl1251_free_hw(struct wl1251 *wl);
int wl1251_init_ieee80211(struct wl1251 *wl);
void wl1251_enable_interrupts(struct wl1251 *wl);
void wl1251_disable_interrupts(struct wl1251 *wl);

#define DEFAULT_HW_GEN_MODULATION_TYPE    CCK_LONG /* Long Preamble */
#define DEFAULT_HW_GEN_TX_RATE          RATE_2MBPS
#define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */

#define WL1251_DEFAULT_POWER_LEVEL 20

#define WL1251_TX_QUEUE_MAX_LENGTH 20

#define WL1251_DEFAULT_BEACON_INT 100
#define WL1251_DEFAULT_DTIM_PERIOD 1

#define WL1251_DEFAULT_CHANNEL 0

#define CHIP_ID_1251_PG10	           (0x7010101)
#define CHIP_ID_1251_PG11	           (0x7020101)
#define CHIP_ID_1251_PG12	           (0x7030101)
#define CHIP_ID_1271_PG10	           (0x4030101)
#define CHIP_ID_1271_PG20	           (0x4030111)

#define WL1251_FW_NAME "wl1251-fw.bin"
#define WL1251_NVS_NAME "wl1251-nvs.bin"

#define WL1251_POWER_ON_SLEEP 10 /* in miliseconds */

#define WL1251_PART_DOWN_MEM_START	0x0
#define WL1251_PART_DOWN_MEM_SIZE	0x16800
#define WL1251_PART_DOWN_REG_START	REGISTERS_BASE
#define WL1251_PART_DOWN_REG_SIZE	REGISTERS_DOWN_SIZE

#define WL1251_PART_WORK_MEM_START	0x28000
#define WL1251_PART_WORK_MEM_SIZE	0x14000
#define WL1251_PART_WORK_REG_START	REGISTERS_BASE
#define WL1251_PART_WORK_REG_SIZE	REGISTERS_WORK_SIZE

#endif
Commit	Line	Data
2f01a1f5	1	/*
80301cdc	2	* This file is part of wl1251
2f01a1f5 KV	3	*
	4	* Copyright (c) 1998-2007 Texas Instruments Incorporated
	5	* Copyright (C) 2008-2009 Nokia Corporation
	6	*
2f01a1f5 KV	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* version 2 as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	19	* 02110-1301 USA
	20	*
	21	*/
	22
80301cdc KV	23	#ifndef __WL1251_H__
80301cdc KV	24	#define __WL1251_H__
2f01a1f5 KV	25
	26	#include <linux/mutex.h>
	27	#include <linux/list.h>
	28	#include <linux/bitops.h>
	29	#include <net/mac80211.h>
	30
80301cdc	31	#define DRIVER_NAME "wl1251"
2f01a1f5 KV	32	#define DRIVER_PREFIX DRIVER_NAME ": "
	33
	34	enum {
	35	DEBUG_NONE = 0,
	36	DEBUG_IRQ = BIT(0),
	37	DEBUG_SPI = BIT(1),
	38	DEBUG_BOOT = BIT(2),
	39	DEBUG_MAILBOX = BIT(3),
	40	DEBUG_NETLINK = BIT(4),
	41	DEBUG_EVENT = BIT(5),
	42	DEBUG_TX = BIT(6),
	43	DEBUG_RX = BIT(7),
	44	DEBUG_SCAN = BIT(8),
	45	DEBUG_CRYPT = BIT(9),
	46	DEBUG_PSM = BIT(10),
	47	DEBUG_MAC80211 = BIT(11),
	48	DEBUG_CMD = BIT(12),
	49	DEBUG_ACX = BIT(13),
	50	DEBUG_ALL = ~0,
	51	};
	52
	53	#define DEBUG_LEVEL (DEBUG_NONE)
	54
	55	#define DEBUG_DUMP_LIMIT 1024
	56
80301cdc	57	#define wl1251_error(fmt, arg...) \
2f01a1f5 KV	58	printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg)
2f01a1f5 KV	59
80301cdc	60	#define wl1251_warning(fmt, arg...) \
2f01a1f5 KV	61	printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg)
2f01a1f5 KV	62
80301cdc	63	#define wl1251_notice(fmt, arg...) \
2f01a1f5 KV	64	printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg)
2f01a1f5 KV	65
80301cdc	66	#define wl1251_info(fmt, arg...) \
2f01a1f5 KV	67	printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg)
2f01a1f5 KV	68
80301cdc	69	#define wl1251_debug(level, fmt, arg...) \
2f01a1f5 KV	70	do { \
	71	if (level & DEBUG_LEVEL) \
	72	printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \
	73	} while (0)
	74
80301cdc	75	#define wl1251_dump(level, prefix, buf, len) \
2f01a1f5 KV	76	do { \
	77	if (level & DEBUG_LEVEL) \
	78	print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
	79	DUMP_PREFIX_OFFSET, 16, 1, \
	80	buf, \
	81	min_t(size_t, len, DEBUG_DUMP_LIMIT), \
	82	0); \
	83	} while (0)
	84
80301cdc	85	#define wl1251_dump_ascii(level, prefix, buf, len) \
2f01a1f5 KV	86	do { \
	87	if (level & DEBUG_LEVEL) \
	88	print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
	89	DUMP_PREFIX_OFFSET, 16, 1, \
	90	buf, \
	91	min_t(size_t, len, DEBUG_DUMP_LIMIT), \
	92	true); \
	93	} while (0)
	94
80301cdc	95	#define WL1251_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN \| \
2f01a1f5 KV	96	CFG_BSSID_FILTER_EN)
2f01a1f5 KV	97
80301cdc	98	#define WL1251_DEFAULT_RX_FILTER (CFG_RX_PRSP_EN \| \
2f01a1f5 KV	99	CFG_RX_MGMT_EN \| \
	100	CFG_RX_DATA_EN \| \
	101	CFG_RX_CTL_EN \| \
	102	CFG_RX_BCN_EN \| \
	103	CFG_RX_AUTH_EN \| \
	104	CFG_RX_ASSOC_EN)
	105
80301cdc	106	#define WL1251_BUSY_WORD_LEN 8
2f01a1f5 KV	107
	108	struct boot_attr {
	109	u32 radio_type;
	110	u8 mac_clock;
	111	u8 arm_clock;
	112	int firmware_debug;
	113	u32 minor;
	114	u32 major;
	115	u32 bugfix;
	116	};
	117
80301cdc KV	118	enum wl1251_state {
	119	WL1251_STATE_OFF,
	120	WL1251_STATE_ON,
	121	WL1251_STATE_PLT,
2f01a1f5 KV	122	};
2f01a1f5 KV	123
80301cdc	124	enum wl1251_partition_type {
2f01a1f5 KV	125	PART_DOWN,
	126	PART_WORK,
	127	PART_DRPW,
	128
	129	PART_TABLE_LEN
	130	};
	131
80301cdc	132	struct wl1251_partition {
2f01a1f5 KV	133	u32 size;
	134	u32 start;
	135	};
	136
80301cdc KV	137	struct wl1251_partition_set {
	138	struct wl1251_partition mem;
	139	struct wl1251_partition reg;
2f01a1f5 KV	140	};
2f01a1f5 KV	141
80301cdc	142	struct wl1251;
2f01a1f5	143
80301cdc	144	struct wl1251_stats {
2f01a1f5 KV	145	struct acx_statistics *fw_stats;
	146	unsigned long fw_stats_update;
	147
	148	unsigned int retry_count;
	149	unsigned int excessive_retries;
	150	};
	151
80301cdc	152	struct wl1251_debugfs {
2f01a1f5 KV	153	struct dentry *rootdir;
	154	struct dentry *fw_statistics;
	155
	156	struct dentry *tx_internal_desc_overflow;
	157
	158	struct dentry *rx_out_of_mem;
	159	struct dentry *rx_hdr_overflow;
	160	struct dentry *rx_hw_stuck;
	161	struct dentry *rx_dropped;
	162	struct dentry *rx_fcs_err;
	163	struct dentry *rx_xfr_hint_trig;
	164	struct dentry *rx_path_reset;
	165	struct dentry *rx_reset_counter;
	166
	167	struct dentry *dma_rx_requested;
	168	struct dentry *dma_rx_errors;
	169	struct dentry *dma_tx_requested;
	170	struct dentry *dma_tx_errors;
	171
	172	struct dentry *isr_cmd_cmplt;
	173	struct dentry *isr_fiqs;
	174	struct dentry *isr_rx_headers;
	175	struct dentry *isr_rx_mem_overflow;
	176	struct dentry *isr_rx_rdys;
	177	struct dentry *isr_irqs;
	178	struct dentry *isr_tx_procs;
	179	struct dentry *isr_decrypt_done;
	180	struct dentry *isr_dma0_done;
	181	struct dentry *isr_dma1_done;
	182	struct dentry *isr_tx_exch_complete;
	183	struct dentry *isr_commands;
	184	struct dentry *isr_rx_procs;
	185	struct dentry *isr_hw_pm_mode_changes;
	186	struct dentry *isr_host_acknowledges;
	187	struct dentry *isr_pci_pm;
	188	struct dentry *isr_wakeups;
	189	struct dentry *isr_low_rssi;
	190
	191	struct dentry *wep_addr_key_count;
	192	struct dentry *wep_default_key_count;
	193	/* skipping wep.reserved */
	194	struct dentry *wep_key_not_found;
	195	struct dentry *wep_decrypt_fail;
	196	struct dentry *wep_packets;
	197	struct dentry *wep_interrupt;
	198
	199	struct dentry *pwr_ps_enter;
	200	struct dentry *pwr_elp_enter;
	201	struct dentry *pwr_missing_bcns;
	202	struct dentry *pwr_wake_on_host;
	203	struct dentry *pwr_wake_on_timer_exp;
	204	struct dentry *pwr_tx_with_ps;
	205	struct dentry *pwr_tx_without_ps;
	206	struct dentry *pwr_rcvd_beacons;
	207	struct dentry *pwr_power_save_off;
	208	struct dentry *pwr_enable_ps;
	209	struct dentry *pwr_disable_ps;
	210	struct dentry *pwr_fix_tsf_ps;
	211	/* skipping cont_miss_bcns_spread for now */
	212	struct dentry *pwr_rcvd_awake_beacons;
	213
	214	struct dentry *mic_rx_pkts;
	215	struct dentry *mic_calc_failure;
	216
217	struct dentry *aes_encrypt_fail;
218	struct dentry *aes_decrypt_fail;
219	struct dentry *aes_encrypt_packets;
220	struct dentry *aes_decrypt_packets;
221	struct dentry *aes_encrypt_interrupt;
222	struct dentry *aes_decrypt_interrupt;
223
224	struct dentry *event_heart_beat;
225	struct dentry *event_calibration;
226	struct dentry *event_rx_mismatch;
227	struct dentry *event_rx_mem_empty;
228	struct dentry *event_rx_pool;
229	struct dentry *event_oom_late;
230	struct dentry *event_phy_transmit_error;
231	struct dentry *event_tx_stuck;
232
233	struct dentry *ps_pspoll_timeouts;
234	struct dentry *ps_upsd_timeouts;
235	struct dentry *ps_upsd_max_sptime;
236	struct dentry *ps_upsd_max_apturn;
237	struct dentry *ps_pspoll_max_apturn;
238	struct dentry *ps_pspoll_utilization;
239	struct dentry *ps_upsd_utilization;
240
241	struct dentry *rxpipe_rx_prep_beacon_drop;
242	struct dentry *rxpipe_descr_host_int_trig_rx_data;
243	struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data;
244	struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data;
245	struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data;
246
247	struct dentry *tx_queue_len;
b7339b1d	248	struct dentry *tx_queue_status;
2f01a1f5 KV	249
	250	struct dentry *retry_count;
	251	struct dentry *excessive_retries;
	252	};
	253
08d9f572 BC	254	struct wl1251_if_operations {
	255	void (read)(struct wl1251 wl, int addr, void *buf, size_t len);
	256	void (write)(struct wl1251 wl, int addr, void *buf, size_t len);
3f9e750d GI	257	void (read_elp)(struct wl1251 wl, int addr, u32 *val);
3f9e750d GI	258	void (write_elp)(struct wl1251 wl, int addr, u32 val);
08d9f572	259	void (reset)(struct wl1251 wl);
b5ed9c1b BC	260	void (enable_irq)(struct wl1251 wl);
b5ed9c1b BC	261	void (disable_irq)(struct wl1251 wl);
08d9f572 BC	262	};
08d9f572 BC	263
80301cdc	264	struct wl1251 {
2f01a1f5 KV	265	struct ieee80211_hw *hw;
	266	bool mac80211_registered;
	267
af8c78eb	268	void *if_priv;
8e639c06	269	const struct wl1251_if_operations *if_ops;
2f01a1f5 KV	270
	271	void (*set_power)(bool enable);
	272	int irq;
c95cf3d0	273	bool use_eeprom;
2f01a1f5	274
80301cdc	275	enum wl1251_state state;
2f01a1f5 KV	276	struct mutex mutex;
	277
	278	int physical_mem_addr;
	279	int physical_reg_addr;
	280	int virtual_mem_addr;
	281	int virtual_reg_addr;
	282
2f01a1f5 KV	283	int cmd_box_addr;
	284	int event_box_addr;
	285	struct boot_attr boot_attr;
	286
	287	u8 *fw;
	288	size_t fw_len;
	289	u8 *nvs;
	290	size_t nvs_len;
	291
	292	u8 bssid[ETH_ALEN];
	293	u8 mac_addr[ETH_ALEN];
	294	u8 bss_type;
	295	u8 listen_int;
	296	int channel;
	297
	298	void *target_mem_map;
	299	struct acx_data_path_params_resp *data_path;
	300
	301	/* Number of TX packets transferred to the FW, modulo 16 */
	302	u32 data_in_count;
	303
	304	/* Frames scheduled for transmission, not handled yet */
	305	struct sk_buff_head tx_queue;
	306	bool tx_queue_stopped;
	307
	308	struct work_struct tx_work;
	309	struct work_struct filter_work;
	310
	311	/* Pending TX frames */
	312	struct sk_buff *tx_frames[16];
	313
	314	/*
	315	* Index pointing to the next TX complete entry
	316	* in the cyclic XT complete array we get from
	317	* the FW.
	318	*/
	319	u32 next_tx_complete;
	320
	321	/* FW Rx counter */
	322	u32 rx_counter;
	323
	324	/* Rx frames handled */
	325	u32 rx_handled;
	326
	327	/* Current double buffer */
	328	u32 rx_current_buffer;
	329	u32 rx_last_id;
	330
	331	/* The target interrupt mask */
	332	u32 intr_mask;
	333	struct work_struct irq_work;
	334
	335	/* The mbox event mask */
	336	u32 event_mask;
	337
	338	/* Mailbox pointers */
	339	u32 mbox_ptr[2];
	340
	341	/* Are we currently scanning */
	342	bool scanning;
	343
2f01a1f5 KV	344	/* Default key (for WEP) */
	345	u32 default_key;
	346
	347	unsigned int tx_mgmt_frm_rate;
	348	unsigned int tx_mgmt_frm_mod;
	349
	350	unsigned int rx_config;
	351	unsigned int rx_filter;
	352
	353	/* is firmware in elp mode */
	354	bool elp;
	355
d5da79ac JO	356	struct delayed_work elp_work;
d5da79ac JO	357
2f01a1f5 KV	358	/* we can be in psm, but not in elp, we have to differentiate */
	359	bool psm;
	360
	361	/* PSM mode requested */
	362	bool psm_requested;
	363
e2fd4611 KV	364	u16 beacon_int;
	365	u8 dtim_period;
	366
2f01a1f5 KV	367	/* in dBm */
	368	int power_level;
	369
80301cdc KV	370	struct wl1251_stats stats;
80301cdc KV	371	struct wl1251_debugfs debugfs;
1d3b8130 KV	372
1d3b8130 KV	373	u32 buffer_32;
56343a3c	374	u32 buffer_cmd;
80301cdc KV	375	u8 buffer_busyword[WL1251_BUSY_WORD_LEN];
80301cdc KV	376	struct wl1251_rx_descriptor *rx_descriptor;
0e71bb08	377
287f6f96 JO	378	struct ieee80211_vif *vif;
287f6f96 JO	379
0e71bb08 KV	380	u32 chip_id;
0e71bb08 KV	381	char fw_ver[21];
19434148 JL	382
	383	/* Most recently reported noise in dBm */
	384	s8 noise;
2f01a1f5 KV	385	};
2f01a1f5 KV	386
80301cdc KV	387	int wl1251_plt_start(struct wl1251 *wl);
80301cdc KV	388	int wl1251_plt_stop(struct wl1251 *wl);
2f01a1f5	389
8e639c06 BC	390	struct ieee80211_hw *wl1251_alloc_hw(void);
	391	int wl1251_free_hw(struct wl1251 *wl);
	392	int wl1251_init_ieee80211(struct wl1251 *wl);
b5ed9c1b BC	393	void wl1251_enable_interrupts(struct wl1251 *wl);
b5ed9c1b BC	394	void wl1251_disable_interrupts(struct wl1251 *wl);
8e639c06	395
2f01a1f5 KV	396	#define DEFAULT_HW_GEN_MODULATION_TYPE CCK_LONG /* Long Preamble */
	397	#define DEFAULT_HW_GEN_TX_RATE RATE_2MBPS
	398	#define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */
	399
80301cdc	400	#define WL1251_DEFAULT_POWER_LEVEL 20
2f01a1f5	401
80301cdc	402	#define WL1251_TX_QUEUE_MAX_LENGTH 20
2f01a1f5	403
e2fd4611 KV	404	#define WL1251_DEFAULT_BEACON_INT 100
	405	#define WL1251_DEFAULT_DTIM_PERIOD 1
	406
9780279c KV	407	#define WL1251_DEFAULT_CHANNEL 0
9780279c KV	408
2f01a1f5 KV	409	#define CHIP_ID_1251_PG10 (0x7010101)
	410	#define CHIP_ID_1251_PG11 (0x7020101)
	411	#define CHIP_ID_1251_PG12 (0x7030101)
	412	#define CHIP_ID_1271_PG10 (0x4030101)
27797d68	413	#define CHIP_ID_1271_PG20 (0x4030111)
2f01a1f5	414
0e71bb08 KV	415	#define WL1251_FW_NAME "wl1251-fw.bin"
	416	#define WL1251_NVS_NAME "wl1251-nvs.bin"
	417
	418	#define WL1251_POWER_ON_SLEEP 10 /* in miliseconds */
	419
	420	#define WL1251_PART_DOWN_MEM_START 0x0
	421	#define WL1251_PART_DOWN_MEM_SIZE 0x16800
	422	#define WL1251_PART_DOWN_REG_START REGISTERS_BASE
	423	#define WL1251_PART_DOWN_REG_SIZE REGISTERS_DOWN_SIZE
	424
	425	#define WL1251_PART_WORK_MEM_START 0x28000
	426	#define WL1251_PART_WORK_MEM_SIZE 0x14000
	427	#define WL1251_PART_WORK_REG_START REGISTERS_BASE
	428	#define WL1251_PART_WORK_REG_SIZE REGISTERS_WORK_SIZE
	429
2f01a1f5	430	#endif