[linux.git] / include / asm-mips / mach-au1x00 / au1xxx_ide.h

/*
 * include/asm-mips/mach-au1x00/au1xxx_ide.h  version 01.30.00   Aug. 02 2005
 *
 * BRIEF MODULE DESCRIPTION
 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
 *
 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
 *
 * This program is free software; you can redistribute it and/or modify it under
 * the terms of the GNU General Public License as published by the Free Software
 * Foundation; either version 2 of the License, or (at your option) any later
 * version.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
 *       Interface and Linux Device Driver" Application Note.
 */

#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
        #define DMA_WAIT_TIMEOUT        100
        #define NUM_DESCRIPTORS         PRD_ENTRIES
#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
        #define NUM_DESCRIPTORS         2
#endif

#ifndef AU1XXX_ATA_RQSIZE
        #define AU1XXX_ATA_RQSIZE       128
#endif

/* Disable Burstable-Support for DBDMA */
#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
        #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON  0
#endif

#ifdef CONFIG_PM
/*
* This will enable the device to be powered up when write() or read()
* is called. If this is not defined, the driver will return -EBUSY.
*/
#define WAKE_ON_ACCESS 1

typedef struct
{
        spinlock_t         lock;       /* Used to block on state transitions */
        au1xxx_power_dev_t *dev;       /* Power Managers device structure */
        unsigned	   stopped;    /* USed to signaling device is stopped */
} pm_state;
#endif


typedef struct
{
        u32                     tx_dev_id, rx_dev_id, target_dev_id;
        u32                     tx_chan, rx_chan;
        void                    *tx_desc_head, *rx_desc_head;
        ide_hwif_t              *hwif;
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
        ide_drive_t             *drive;
        u8                      white_list, black_list;
        struct dbdma_cmd        *dma_table_cpu;
        dma_addr_t              dma_table_dma;
#endif
        struct device           *dev;
	int			irq;
	u32			regbase;
#ifdef CONFIG_PM
        pm_state                pm;
#endif
} _auide_hwif;

#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
/* HD white list */
static const struct drive_list_entry dma_white_list [] = {
/*
 * Hitachi
 */
        { "HITACHI_DK14FA-20"    ,       "ALL"           },
        { "HTS726060M9AT00"      ,       "ALL"           },
/*
 * Maxtor
 */
        { "Maxtor 6E040L0"      ,       "ALL"           },
        { "Maxtor 6Y080P0"      ,       "ALL"           },
        { "Maxtor 6Y160P0"      ,       "ALL"           },
/*
 * Seagate
 */
        { "ST3120026A"          ,       "ALL"           },
        { "ST320014A"           ,       "ALL"           },
        { "ST94011A"            ,       "ALL"           },
        { "ST340016A"           ,       "ALL"           },
/*
 * Western Digital
 */
        { "WDC WD400UE-00HCT0"  ,       "ALL"           },
        { "WDC WD400JB-00JJC0"  ,       "ALL"           },
        { NULL                  ,       NULL            }
};

/* HD black list */
static const struct drive_list_entry dma_black_list [] = {
/*
 * Western Digital
 */
        { "WDC WD100EB-00CGH0"  ,       "ALL"           },
        { "WDC WD200BB-00AUA1"  ,       "ALL"           },
        { "WDC AC24300L"        ,       "ALL"           },
        { NULL                  ,       NULL            }
};
#endif

/* function prototyping */
u8 auide_inb(unsigned long port);
u16 auide_inw(unsigned long port);
u32 auide_inl(unsigned long port);
void auide_insw(unsigned long port, void *addr, u32 count);
void auide_insl(unsigned long port, void *addr, u32 count);
void auide_outb(u8 addr, unsigned long port);
void auide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port);
void auide_outw(u16 addr, unsigned long port);
void auide_outl(u32 addr, unsigned long port);
void auide_outsw(unsigned long port, void *addr, u32 count);
void auide_outsl(unsigned long port, void *addr, u32 count);
static void auide_tune_drive(ide_drive_t *drive, byte pio);
static int auide_tune_chipset (ide_drive_t *drive, u8 speed);
static int auide_ddma_init( _auide_hwif *auide );
static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif);
int __init auide_probe(void);

/*******************************************************************************
* PIO Mode timing calculation :                                                *
*                                                                              *
* Static Bus Spec   ATA Spec                                                   *
*      Tcsoe      =   t1                                                       *
*      Toecs      =   t9                                                       *
*      Twcs       =   t9                                                       *
*      Tcsh       =   t2i | t2                                                 *
*      Tcsoff     =   t2i | t2                                                 *
*      Twp        =   t2                                                       *
*      Tcsw       =   t1                                                       *
*      Tpm        =   0                                                        *
*      Ta         =   t1+t2                                                    *
*******************************************************************************/

#define TCSOE_MASK            (0x07<<29)
#define TOECS_MASK            (0x07<<26)
#define TWCS_MASK             (0x07<<28)
#define TCSH_MASK             (0x0F<<24)
#define TCSOFF_MASK           (0x07<<20)
#define TWP_MASK              (0x3F<<14)
#define TCSW_MASK             (0x0F<<10)
#define TPM_MASK              (0x0F<<6)
#define TA_MASK               (0x3F<<0)
#define TS_MASK               (1<<8)

/* Timing parameters PIO mode 0 */
#define SBC_IDE_PIO0_TCSOE    (0x04<<29)
#define SBC_IDE_PIO0_TOECS    (0x01<<26)
#define SBC_IDE_PIO0_TWCS     (0x02<<28)
#define SBC_IDE_PIO0_TCSH     (0x08<<24)
#define SBC_IDE_PIO0_TCSOFF   (0x07<<20)
#define SBC_IDE_PIO0_TWP      (0x10<<14)
#define SBC_IDE_PIO0_TCSW     (0x04<<10)
#define SBC_IDE_PIO0_TPM      (0x0<<6)
#define SBC_IDE_PIO0_TA       (0x15<<0)
/* Timing parameters PIO mode 1 */
#define SBC_IDE_PIO1_TCSOE    (0x03<<29)
#define SBC_IDE_PIO1_TOECS    (0x01<<26)
#define SBC_IDE_PIO1_TWCS     (0x01<<28)
#define SBC_IDE_PIO1_TCSH     (0x06<<24)
#define SBC_IDE_PIO1_TCSOFF   (0x06<<20)
#define SBC_IDE_PIO1_TWP      (0x08<<14)
#define SBC_IDE_PIO1_TCSW     (0x03<<10)
#define SBC_IDE_PIO1_TPM      (0x00<<6)
#define SBC_IDE_PIO1_TA       (0x0B<<0)
/* Timing parameters PIO mode 2 */
#define SBC_IDE_PIO2_TCSOE    (0x05<<29)
#define SBC_IDE_PIO2_TOECS    (0x01<<26)
#define SBC_IDE_PIO2_TWCS     (0x01<<28)
#define SBC_IDE_PIO2_TCSH     (0x07<<24)
#define SBC_IDE_PIO2_TCSOFF   (0x07<<20)
#define SBC_IDE_PIO2_TWP      (0x1F<<14)
#define SBC_IDE_PIO2_TCSW     (0x05<<10)
#define SBC_IDE_PIO2_TPM      (0x00<<6)
#define SBC_IDE_PIO2_TA       (0x22<<0)
/* Timing parameters PIO mode 3 */
#define SBC_IDE_PIO3_TCSOE    (0x05<<29)
#define SBC_IDE_PIO3_TOECS    (0x01<<26)
#define SBC_IDE_PIO3_TWCS     (0x01<<28)
#define SBC_IDE_PIO3_TCSH     (0x0D<<24)
#define SBC_IDE_PIO3_TCSOFF   (0x0D<<20)
#define SBC_IDE_PIO3_TWP      (0x15<<14)
#define SBC_IDE_PIO3_TCSW     (0x05<<10)
#define SBC_IDE_PIO3_TPM      (0x00<<6)
#define SBC_IDE_PIO3_TA       (0x1A<<0)
/* Timing parameters PIO mode 4 */
#define SBC_IDE_PIO4_TCSOE    (0x04<<29)
#define SBC_IDE_PIO4_TOECS    (0x01<<26)
#define SBC_IDE_PIO4_TWCS     (0x01<<28)
#define SBC_IDE_PIO4_TCSH     (0x04<<24)
#define SBC_IDE_PIO4_TCSOFF   (0x04<<20)
#define SBC_IDE_PIO4_TWP      (0x0D<<14)
#define SBC_IDE_PIO4_TCSW     (0x03<<10)
#define SBC_IDE_PIO4_TPM      (0x00<<6)
#define SBC_IDE_PIO4_TA       (0x12<<0)
/* Timing parameters MDMA mode 0 */
#define SBC_IDE_MDMA0_TCSOE   (0x03<<29)
#define SBC_IDE_MDMA0_TOECS   (0x01<<26)
#define SBC_IDE_MDMA0_TWCS    (0x01<<28)
#define SBC_IDE_MDMA0_TCSH    (0x07<<24)
#define SBC_IDE_MDMA0_TCSOFF  (0x07<<20)
#define SBC_IDE_MDMA0_TWP     (0x0C<<14)
#define SBC_IDE_MDMA0_TCSW    (0x03<<10)
#define SBC_IDE_MDMA0_TPM     (0x00<<6)
#define SBC_IDE_MDMA0_TA      (0x0F<<0)
/* Timing parameters MDMA mode 1 */
#define SBC_IDE_MDMA1_TCSOE   (0x05<<29)
#define SBC_IDE_MDMA1_TOECS   (0x01<<26)
#define SBC_IDE_MDMA1_TWCS    (0x01<<28)
#define SBC_IDE_MDMA1_TCSH    (0x05<<24)
#define SBC_IDE_MDMA1_TCSOFF  (0x05<<20)
#define SBC_IDE_MDMA1_TWP     (0x0F<<14)
#define SBC_IDE_MDMA1_TCSW    (0x05<<10)
#define SBC_IDE_MDMA1_TPM     (0x00<<6)
#define SBC_IDE_MDMA1_TA      (0x15<<0)
/* Timing parameters MDMA mode 2 */
#define SBC_IDE_MDMA2_TCSOE   (0x04<<29)
#define SBC_IDE_MDMA2_TOECS   (0x01<<26)
#define SBC_IDE_MDMA2_TWCS    (0x01<<28)
#define SBC_IDE_MDMA2_TCSH    (0x04<<24)
#define SBC_IDE_MDMA2_TCSOFF  (0x04<<20)
#define SBC_IDE_MDMA2_TWP     (0x0D<<14)
#define SBC_IDE_MDMA2_TCSW    (0x04<<10)
#define SBC_IDE_MDMA2_TPM     (0x00<<6)
#define SBC_IDE_MDMA2_TA      (0x12<<0)

#define SBC_IDE_TIMING(mode) \
         SBC_IDE_##mode##_TWCS | \
         SBC_IDE_##mode##_TCSH | \
         SBC_IDE_##mode##_TCSOFF | \
         SBC_IDE_##mode##_TWP | \
         SBC_IDE_##mode##_TCSW | \
         SBC_IDE_##mode##_TPM | \
         SBC_IDE_##mode##_TA
Commit	Line	Data
26a940e2 PP	1	/*
	2	* include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005
	3	*
	4	* BRIEF MODULE DESCRIPTION
	5	* AMD Alchemy Au1xxx IDE interface routines over the Static Bus
	6	*
	7	* Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
	8	*
	9	* This program is free software; you can redistribute it and/or modify it under
	10	* the terms of the GNU General Public License as published by the Free Software
	11	* Foundation; either version 2 of the License, or (at your option) any later
	12	* version.
	13	*
	14	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
	15	* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
	16	* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
	17	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	18	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	19	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	20	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	21	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	22	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	23	* POSSIBILITY OF SUCH DAMAGE.
	24	*
	25	* You should have received a copy of the GNU General Public License along with
	26	* this program; if not, write to the Free Software Foundation, Inc.,
	27	* 675 Mass Ave, Cambridge, MA 02139, USA.
	28	*
	29	* Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
	30	* Interface and Linux Device Driver" Application Note.
	31	*/
26a940e2 PP	32
	33	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
	34	#define DMA_WAIT_TIMEOUT 100
	35	#define NUM_DESCRIPTORS PRD_ENTRIES
	36	#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
	37	#define NUM_DESCRIPTORS 2
	38	#endif
	39
	40	#ifndef AU1XXX_ATA_RQSIZE
	41	#define AU1XXX_ATA_RQSIZE 128
	42	#endif
	43
	44	/* Disable Burstable-Support for DBDMA */
	45	#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
	46	#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
	47	#endif
	48
	49	#ifdef CONFIG_PM
	50	/*
	51	* This will enable the device to be powered up when write() or read()
	52	* is called. If this is not defined, the driver will return -EBUSY.
	53	*/
	54	#define WAKE_ON_ACCESS 1
	55
	56	typedef struct
	57	{
	58	spinlock_t lock; /* Used to block on state transitions */
	59	au1xxx_power_dev_t dev; / Power Managers device structure */
	60	unsigned stopped; /* USed to signaling device is stopped */
	61	} pm_state;
	62	#endif
	63
	64
	65	typedef struct
	66	{
	67	u32 tx_dev_id, rx_dev_id, target_dev_id;
	68	u32 tx_chan, rx_chan;
	69	void tx_desc_head, rx_desc_head;
	70	ide_hwif_t *hwif;
	71	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
	72	ide_drive_t *drive;
	73	u8 white_list, black_list;
	74	struct dbdma_cmd *dma_table_cpu;
	75	dma_addr_t dma_table_dma;
26a940e2 PP	76	#endif
	77	struct device *dev;
	78	int irq;
	79	u32 regbase;
	80	#ifdef CONFIG_PM
	81	pm_state pm;
	82	#endif
	83	} _auide_hwif;
	84
	85	#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
26a940e2 PP	86	/* HD white list */
	87	static const struct drive_list_entry dma_white_list [] = {
	88	/*
	89	* Hitachi
	90	*/
	91	{ "HITACHI_DK14FA-20" , "ALL" },
	92	{ "HTS726060M9AT00" , "ALL" },
	93	/*
	94	* Maxtor
	95	*/
	96	{ "Maxtor 6E040L0" , "ALL" },
	97	{ "Maxtor 6Y080P0" , "ALL" },
	98	{ "Maxtor 6Y160P0" , "ALL" },
	99	/*
	100	* Seagate
	101	*/
	102	{ "ST3120026A" , "ALL" },
	103	{ "ST320014A" , "ALL" },
	104	{ "ST94011A" , "ALL" },
	105	{ "ST340016A" , "ALL" },
	106	/*
	107	* Western Digital
	108	*/
	109	{ "WDC WD400UE-00HCT0" , "ALL" },
	110	{ "WDC WD400JB-00JJC0" , "ALL" },
	111	{ NULL , NULL }
	112	};
	113
	114	/* HD black list */
	115	static const struct drive_list_entry dma_black_list [] = {
	116	/*
	117	* Western Digital
	118	*/
	119	{ "WDC WD100EB-00CGH0" , "ALL" },
	120	{ "WDC WD200BB-00AUA1" , "ALL" },
	121	{ "WDC AC24300L" , "ALL" },
	122	{ NULL , NULL }
	123	};
	124	#endif
	125
	126	/* function prototyping */
	127	u8 auide_inb(unsigned long port);
	128	u16 auide_inw(unsigned long port);
	129	u32 auide_inl(unsigned long port);
	130	void auide_insw(unsigned long port, void *addr, u32 count);
	131	void auide_insl(unsigned long port, void *addr, u32 count);
	132	void auide_outb(u8 addr, unsigned long port);
	133	void auide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port);
	134	void auide_outw(u16 addr, unsigned long port);
	135	void auide_outl(u32 addr, unsigned long port);
	136	void auide_outsw(unsigned long port, void *addr, u32 count);
	137	void auide_outsl(unsigned long port, void *addr, u32 count);
	138	static void auide_tune_drive(ide_drive_t *drive, byte pio);
	139	static int auide_tune_chipset (ide_drive_t *drive, u8 speed);
	140	static int auide_ddma_init( _auide_hwif *auide );
	141	static void auide_setup_ports(hw_regs_t hw, _auide_hwif ahwif);
	142	int __init auide_probe(void);
	143
26a940e2 PP	144	/*******************************************************************************
	145	* PIO Mode timing calculation : *
	146	* *
	147	* Static Bus Spec ATA Spec *
	148	* Tcsoe = t1 *
	149	* Toecs = t9 *
	150	* Twcs = t9 *
	151	* Tcsh = t2i \| t2 *
	152	* Tcsoff = t2i \| t2 *
	153	* Twp = t2 *
	154	* Tcsw = t1 *
	155	* Tpm = 0 *
	156	* Ta = t1+t2 *
	157	*******************************************************************************/
	158
	159	#define TCSOE_MASK (0x07<<29)
	160	#define TOECS_MASK (0x07<<26)
	161	#define TWCS_MASK (0x07<<28)
	162	#define TCSH_MASK (0x0F<<24)
	163	#define TCSOFF_MASK (0x07<<20)
	164	#define TWP_MASK (0x3F<<14)
	165	#define TCSW_MASK (0x0F<<10)
	166	#define TPM_MASK (0x0F<<6)
	167	#define TA_MASK (0x3F<<0)
	168	#define TS_MASK (1<<8)
	169
	170	/* Timing parameters PIO mode 0 */
	171	#define SBC_IDE_PIO0_TCSOE (0x04<<29)
	172	#define SBC_IDE_PIO0_TOECS (0x01<<26)
	173	#define SBC_IDE_PIO0_TWCS (0x02<<28)
	174	#define SBC_IDE_PIO0_TCSH (0x08<<24)
	175	#define SBC_IDE_PIO0_TCSOFF (0x07<<20)
	176	#define SBC_IDE_PIO0_TWP (0x10<<14)
	177	#define SBC_IDE_PIO0_TCSW (0x04<<10)
	178	#define SBC_IDE_PIO0_TPM (0x0<<6)
	179	#define SBC_IDE_PIO0_TA (0x15<<0)
	180	/* Timing parameters PIO mode 1 */
	181	#define SBC_IDE_PIO1_TCSOE (0x03<<29)
	182	#define SBC_IDE_PIO1_TOECS (0x01<<26)
	183	#define SBC_IDE_PIO1_TWCS (0x01<<28)
	184	#define SBC_IDE_PIO1_TCSH (0x06<<24)
	185	#define SBC_IDE_PIO1_TCSOFF (0x06<<20)
	186	#define SBC_IDE_PIO1_TWP (0x08<<14)
	187	#define SBC_IDE_PIO1_TCSW (0x03<<10)
	188	#define SBC_IDE_PIO1_TPM (0x00<<6)
	189	#define SBC_IDE_PIO1_TA (0x0B<<0)
	190	/* Timing parameters PIO mode 2 */
	191	#define SBC_IDE_PIO2_TCSOE (0x05<<29)
	192	#define SBC_IDE_PIO2_TOECS (0x01<<26)
	193	#define SBC_IDE_PIO2_TWCS (0x01<<28)
	194	#define SBC_IDE_PIO2_TCSH (0x07<<24)
	195	#define SBC_IDE_PIO2_TCSOFF (0x07<<20)
	196	#define SBC_IDE_PIO2_TWP (0x1F<<14)
	197	#define SBC_IDE_PIO2_TCSW (0x05<<10)
	198	#define SBC_IDE_PIO2_TPM (0x00<<6)
	199	#define SBC_IDE_PIO2_TA (0x22<<0)
	200	/* Timing parameters PIO mode 3 */
	201	#define SBC_IDE_PIO3_TCSOE (0x05<<29)
	202	#define SBC_IDE_PIO3_TOECS (0x01<<26)
	203	#define SBC_IDE_PIO3_TWCS (0x01<<28)
	204	#define SBC_IDE_PIO3_TCSH (0x0D<<24)
	205	#define SBC_IDE_PIO3_TCSOFF (0x0D<<20)
	206	#define SBC_IDE_PIO3_TWP (0x15<<14)
	207	#define SBC_IDE_PIO3_TCSW (0x05<<10)
208	#define SBC_IDE_PIO3_TPM (0x00<<6)
209	#define SBC_IDE_PIO3_TA (0x1A<<0)
210	/* Timing parameters PIO mode 4 */
211	#define SBC_IDE_PIO4_TCSOE (0x04<<29)
212	#define SBC_IDE_PIO4_TOECS (0x01<<26)
213	#define SBC_IDE_PIO4_TWCS (0x01<<28)
214	#define SBC_IDE_PIO4_TCSH (0x04<<24)
215	#define SBC_IDE_PIO4_TCSOFF (0x04<<20)
216	#define SBC_IDE_PIO4_TWP (0x0D<<14)
217	#define SBC_IDE_PIO4_TCSW (0x03<<10)
218	#define SBC_IDE_PIO4_TPM (0x00<<6)
219	#define SBC_IDE_PIO4_TA (0x12<<0)
220	/* Timing parameters MDMA mode 0 */
221	#define SBC_IDE_MDMA0_TCSOE (0x03<<29)
222	#define SBC_IDE_MDMA0_TOECS (0x01<<26)
223	#define SBC_IDE_MDMA0_TWCS (0x01<<28)
224	#define SBC_IDE_MDMA0_TCSH (0x07<<24)
225	#define SBC_IDE_MDMA0_TCSOFF (0x07<<20)
226	#define SBC_IDE_MDMA0_TWP (0x0C<<14)
227	#define SBC_IDE_MDMA0_TCSW (0x03<<10)
228	#define SBC_IDE_MDMA0_TPM (0x00<<6)
229	#define SBC_IDE_MDMA0_TA (0x0F<<0)
230	/* Timing parameters MDMA mode 1 */
231	#define SBC_IDE_MDMA1_TCSOE (0x05<<29)
232	#define SBC_IDE_MDMA1_TOECS (0x01<<26)
233	#define SBC_IDE_MDMA1_TWCS (0x01<<28)
234	#define SBC_IDE_MDMA1_TCSH (0x05<<24)
235	#define SBC_IDE_MDMA1_TCSOFF (0x05<<20)
236	#define SBC_IDE_MDMA1_TWP (0x0F<<14)
237	#define SBC_IDE_MDMA1_TCSW (0x05<<10)
238	#define SBC_IDE_MDMA1_TPM (0x00<<6)
239	#define SBC_IDE_MDMA1_TA (0x15<<0)
240	/* Timing parameters MDMA mode 2 */
241	#define SBC_IDE_MDMA2_TCSOE (0x04<<29)
242	#define SBC_IDE_MDMA2_TOECS (0x01<<26)
243	#define SBC_IDE_MDMA2_TWCS (0x01<<28)
244	#define SBC_IDE_MDMA2_TCSH (0x04<<24)
245	#define SBC_IDE_MDMA2_TCSOFF (0x04<<20)
246	#define SBC_IDE_MDMA2_TWP (0x0D<<14)
247	#define SBC_IDE_MDMA2_TCSW (0x04<<10)
248	#define SBC_IDE_MDMA2_TPM (0x00<<6)
249	#define SBC_IDE_MDMA2_TA (0x12<<0)
250
8f29e650 JC	251	#define SBC_IDE_TIMING(mode) \
	252	SBC_IDE_##mode##_TWCS \| \
	253	SBC_IDE_##mode##_TCSH \| \
	254	SBC_IDE_##mode##_TCSOFF \| \
	255	SBC_IDE_##mode##_TWP \| \
	256	SBC_IDE_##mode##_TCSW \| \
	257	SBC_IDE_##mode##_TPM \| \
	258	SBC_IDE_##mode##_TA