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Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6
[linux.git] / drivers / net / 8139cp.c
CommitLineData
1da177e4
LT		 1/* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2/*
3 Copyright 2001-2004 Jeff Garzik <[email protected]>
4
5 Copyright (C) 2001, 2002 David S. Miller ([email protected]) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller ([email protected]) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <[email protected]>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
f3b197ac 22
1da177e4
LT		 23 Wake-on-LAN support - Felipe Damasio <[email protected]>
24 PCI suspend/resume - Felipe Damasio <[email protected]>
25 LinkChg interrupt - Felipe Damasio <[email protected]>
f3b197ac 26
1da177e4
LT		 27 TODO:
28 * Test Tx checksumming thoroughly
1da177e4
LT		 29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49#define DRV_NAME "8139cp"
d5b20697 50#define DRV_VERSION "1.3"
1da177e4
LT		 51#define DRV_RELDATE "Mar 22, 2004"
52
53
1da177e4 54#include <linux/module.h>
e21ba282 55#include <linux/moduleparam.h>
1da177e4
LT		 56#include <linux/kernel.h>
57#include <linux/compiler.h>
58#include <linux/netdevice.h>
59#include <linux/etherdevice.h>
60#include <linux/init.h>
61#include <linux/pci.h>
8662d061 62#include <linux/dma-mapping.h>
1da177e4
LT		 63#include <linux/delay.h>
64#include <linux/ethtool.h>
65#include <linux/mii.h>
66#include <linux/if_vlan.h>
67#include <linux/crc32.h>
68#include <linux/in.h>
69#include <linux/ip.h>
70#include <linux/tcp.h>
71#include <linux/udp.h>
72#include <linux/cache.h>
73#include <asm/io.h>
74#include <asm/irq.h>
75#include <asm/uaccess.h>
76
77/* VLAN tagging feature enable/disable */
78#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
79#define CP_VLAN_TAG_USED 1
80#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
cf983019 81 do { (tx_desc)->opts2 = cpu_to_le32(vlan_tag_value); } while (0)
1da177e4
LT		 82#else
83#define CP_VLAN_TAG_USED 0
84#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
85 do { (tx_desc)->opts2 = 0; } while (0)
86#endif
87
88/* These identify the driver base version and may not be removed. */
89static char version[] =
9cc40855 90DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
1da177e4
LT		 91
92MODULE_AUTHOR("Jeff Garzik <[email protected]>");
93MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
a78d8927 94MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 95MODULE_LICENSE("GPL");
96
97static int debug = -1;
e21ba282 98module_param(debug, int, 0);
1da177e4
LT		 99MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
100
101/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
102 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
103static int multicast_filter_limit = 32;
e21ba282 104module_param(multicast_filter_limit, int, 0);
1da177e4
LT		 105MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
106
107#define PFX DRV_NAME ": "
108
1da177e4
LT		 109#define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK)
112#define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
113#define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
114#define CP_REGS_SIZE (0xff + 1)
115#define CP_REGS_VER 1 /* version 1 */
116#define CP_RX_RING_SIZE 64
117#define CP_TX_RING_SIZE 64
118#define CP_RING_BYTES \
119 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
120 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
121 CP_STATS_SIZE)
122#define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
123#define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
124#define TX_BUFFS_AVAIL(CP) \
125 (((CP)->tx_tail <= (CP)->tx_head) ? \
126 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
127 (CP)->tx_tail - (CP)->tx_head - 1)
128
129#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
1da177e4
LT		 130#define CP_INTERNAL_PHY 32
131
132/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
133#define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
134#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
135#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
136#define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
137
138/* Time in jiffies before concluding the transmitter is hung. */
139#define TX_TIMEOUT (6*HZ)
140
141/* hardware minimum and maximum for a single frame's data payload */
142#define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
143#define CP_MAX_MTU 4096
144
145enum {
146 /* NIC register offsets */
147 MAC0 = 0x00, /* Ethernet hardware address. */
148 MAR0 = 0x08, /* Multicast filter. */
149 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
150 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
151 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
152 Cmd = 0x37, /* Command register */
153 IntrMask = 0x3C, /* Interrupt mask */
154 IntrStatus = 0x3E, /* Interrupt status */
155 TxConfig = 0x40, /* Tx configuration */
156 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
157 RxConfig = 0x44, /* Rx configuration */
158 RxMissed = 0x4C, /* 24 bits valid, write clears */
159 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
160 Config1 = 0x52, /* Config1 */
161 Config3 = 0x59, /* Config3 */
162 Config4 = 0x5A, /* Config4 */
163 MultiIntr = 0x5C, /* Multiple interrupt select */
164 BasicModeCtrl = 0x62, /* MII BMCR */
165 BasicModeStatus = 0x64, /* MII BMSR */
166 NWayAdvert = 0x66, /* MII ADVERTISE */
167 NWayLPAR = 0x68, /* MII LPA */
168 NWayExpansion = 0x6A, /* MII Expansion */
169 Config5 = 0xD8, /* Config5 */
170 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
171 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
172 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
173 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
174 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
175 TxThresh = 0xEC, /* Early Tx threshold */
176 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
177 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
178
179 /* Tx and Rx status descriptors */
180 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
181 RingEnd = (1 << 30), /* End of descriptor ring */
182 FirstFrag = (1 << 29), /* First segment of a packet */
183 LastFrag = (1 << 28), /* Final segment of a packet */
fcec3456
JG		 184 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
185 MSSShift = 16, /* MSS value position */
186 MSSMask = 0xfff, /* MSS value: 11 bits */
1da177e4
LT		 187 TxError = (1 << 23), /* Tx error summary */
188 RxError = (1 << 20), /* Rx error summary */
189 IPCS = (1 << 18), /* Calculate IP checksum */
190 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
191 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
192 TxVlanTag = (1 << 17), /* Add VLAN tag */
193 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
194 IPFail = (1 << 15), /* IP checksum failed */
195 UDPFail = (1 << 14), /* UDP/IP checksum failed */
196 TCPFail = (1 << 13), /* TCP/IP checksum failed */
197 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
198 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
199 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
200 RxProtoTCP = 1,
201 RxProtoUDP = 2,
202 RxProtoIP = 3,
203 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
204 TxOWC = (1 << 22), /* Tx Out-of-window collision */
205 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
206 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
207 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
208 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
209 RxErrFrame = (1 << 27), /* Rx frame alignment error */
210 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
211 RxErrCRC = (1 << 18), /* Rx CRC error */
212 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
213 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
214 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
215
216 /* StatsAddr register */
217 DumpStats = (1 << 3), /* Begin stats dump */
218
219 /* RxConfig register */
220 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
221 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
222 AcceptErr = 0x20, /* Accept packets with CRC errors */
223 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
224 AcceptBroadcast = 0x08, /* Accept broadcast packets */
225 AcceptMulticast = 0x04, /* Accept multicast packets */
226 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
227 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
228
229 /* IntrMask / IntrStatus registers */
230 PciErr = (1 << 15), /* System error on the PCI bus */
231 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
232 LenChg = (1 << 13), /* Cable length change */
233 SWInt = (1 << 8), /* Software-requested interrupt */
234 TxEmpty = (1 << 7), /* No Tx descriptors available */
235 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
236 LinkChg = (1 << 5), /* Packet underrun, or link change */
237 RxEmpty = (1 << 4), /* No Rx descriptors available */
238 TxErr = (1 << 3), /* Tx error */
239 TxOK = (1 << 2), /* Tx packet sent */
240 RxErr = (1 << 1), /* Rx error */
241 RxOK = (1 << 0), /* Rx packet received */
242 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
243 but hardware likes to raise it */
244
245 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
246 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
247 RxErr | RxOK | IntrResvd,
248
249 /* C mode command register */
250 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
251 RxOn = (1 << 3), /* Rx mode enable */
252 TxOn = (1 << 2), /* Tx mode enable */
253
254 /* C+ mode command register */
255 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
256 RxChkSum = (1 << 5), /* Rx checksum offload enable */
257 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
258 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
259 CpRxOn = (1 << 1), /* Rx mode enable */
260 CpTxOn = (1 << 0), /* Tx mode enable */
261
262 /* Cfg9436 EEPROM control register */
263 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
264 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
265
266 /* TxConfig register */
267 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
268 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
269
270 /* Early Tx Threshold register */
271 TxThreshMask = 0x3f, /* Mask bits 5-0 */
272 TxThreshMax = 2048, /* Max early Tx threshold */
273
274 /* Config1 register */
275 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
276 LWACT = (1 << 4), /* LWAKE active mode */
277 PMEnable = (1 << 0), /* Enable various PM features of chip */
278
279 /* Config3 register */
280 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
281 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
282 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
283
284 /* Config4 register */
285 LWPTN = (1 << 1), /* LWAKE Pattern */
286 LWPME = (1 << 4), /* LANWAKE vs PMEB */
287
288 /* Config5 register */
289 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
290 MWF = (1 << 5), /* Accept Multicast wakeup frame */
291 UWF = (1 << 4), /* Accept Unicast wakeup frame */
292 LANWake = (1 << 1), /* Enable LANWake signal */
293 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
294
295 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
296 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
297 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
298};
299
300static const unsigned int cp_rx_config =
301 (RX_FIFO_THRESH << RxCfgFIFOShift) |
302 (RX_DMA_BURST << RxCfgDMAShift);
303
304struct cp_desc {
03233b90 305 __le32 opts1;
cf983019 306 __le32 opts2;
03233b90 307 __le64 addr;
1da177e4
LT		 308};
309
1da177e4 310struct cp_dma_stats {
03233b90
AV		 311 __le64 tx_ok;
312 __le64 rx_ok;
313 __le64 tx_err;
314 __le32 rx_err;
315 __le16 rx_fifo;
316 __le16 frame_align;
317 __le32 tx_ok_1col;
318 __le32 tx_ok_mcol;
319 __le64 rx_ok_phys;
320 __le64 rx_ok_bcast;
321 __le32 rx_ok_mcast;
322 __le16 tx_abort;
323 __le16 tx_underrun;
1da177e4
LT		 324} __attribute__((packed));
325
326struct cp_extra_stats {
327 unsigned long rx_frags;
328};
329
330struct cp_private {
331 void __iomem *regs;
332 struct net_device *dev;
333 spinlock_t lock;
334 u32 msg_enable;
335
bea3348e
SH		 336 struct napi_struct napi;
337
1da177e4
LT		 338 struct pci_dev *pdev;
339 u32 rx_config;
340 u16 cpcmd;
341
1da177e4 342 struct cp_extra_stats cp_stats;
1da177e4 343
d03d376d
FR		 344 unsigned rx_head ____cacheline_aligned;
345 unsigned rx_tail;
1da177e4 346 struct cp_desc *rx_ring;
0ba894d4 347 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
1da177e4
LT		 348
349 unsigned tx_head ____cacheline_aligned;
350 unsigned tx_tail;
1da177e4 351 struct cp_desc *tx_ring;
48907e39 352 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
d03d376d
FR		 353
354 unsigned rx_buf_sz;
355 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
1da177e4
LT		 356
357#if CP_VLAN_TAG_USED
358 struct vlan_group *vlgrp;
359#endif
d03d376d 360 dma_addr_t ring_dma;
1da177e4
LT		 361
362 struct mii_if_info mii_if;
363};
364
365#define cpr8(reg) readb(cp->regs + (reg))
366#define cpr16(reg) readw(cp->regs + (reg))
367#define cpr32(reg) readl(cp->regs + (reg))
368#define cpw8(reg,val) writeb((val), cp->regs + (reg))
369#define cpw16(reg,val) writew((val), cp->regs + (reg))
370#define cpw32(reg,val) writel((val), cp->regs + (reg))
371#define cpw8_f(reg,val) do { \
372 writeb((val), cp->regs + (reg)); \
373 readb(cp->regs + (reg)); \
374 } while (0)
375#define cpw16_f(reg,val) do { \
376 writew((val), cp->regs + (reg)); \
377 readw(cp->regs + (reg)); \
378 } while (0)
379#define cpw32_f(reg,val) do { \
380 writel((val), cp->regs + (reg)); \
381 readl(cp->regs + (reg)); \
382 } while (0)
383
384
385static void __cp_set_rx_mode (struct net_device *dev);
386static void cp_tx (struct cp_private *cp);
387static void cp_clean_rings (struct cp_private *cp);
7502cd10
SK		 388#ifdef CONFIG_NET_POLL_CONTROLLER
389static void cp_poll_controller(struct net_device *dev);
390#endif
722fdb33
PC		 391static int cp_get_eeprom_len(struct net_device *dev);
392static int cp_get_eeprom(struct net_device *dev,
393 struct ethtool_eeprom *eeprom, u8 *data);
394static int cp_set_eeprom(struct net_device *dev,
395 struct ethtool_eeprom *eeprom, u8 *data);
1da177e4
LT		 396
397static struct pci_device_id cp_pci_tbl[] = {
cccb20d3
FR		 398 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
399 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
1da177e4
LT		 400 { },
401};
402MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
403
404static struct {
405 const char str[ETH_GSTRING_LEN];
406} ethtool_stats_keys[] = {
407 { "tx_ok" },
408 { "rx_ok" },
409 { "tx_err" },
410 { "rx_err" },
411 { "rx_fifo" },
412 { "frame_align" },
413 { "tx_ok_1col" },
414 { "tx_ok_mcol" },
415 { "rx_ok_phys" },
416 { "rx_ok_bcast" },
417 { "rx_ok_mcast" },
418 { "tx_abort" },
419 { "tx_underrun" },
420 { "rx_frags" },
421};
422
423
424#if CP_VLAN_TAG_USED
425static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
426{
427 struct cp_private *cp = netdev_priv(dev);
428 unsigned long flags;
429
430 spin_lock_irqsave(&cp->lock, flags);
431 cp->vlgrp = grp;
7b332244
SH		 432 if (grp)
433 cp->cpcmd |= RxVlanOn;
434 else
435 cp->cpcmd &= ~RxVlanOn;
1da177e4 436
1da177e4 437 cpw16(CpCmd, cp->cpcmd);
1da177e4
LT		 438 spin_unlock_irqrestore(&cp->lock, flags);
439}
440#endif /* CP_VLAN_TAG_USED */
441
442static inline void cp_set_rxbufsize (struct cp_private *cp)
443{
444 unsigned int mtu = cp->dev->mtu;
f3b197ac 445
1da177e4
LT		 446 if (mtu > ETH_DATA_LEN)
447 /* MTU + ethernet header + FCS + optional VLAN tag */
448 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
449 else
450 cp->rx_buf_sz = PKT_BUF_SZ;
451}
452
453static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
454 struct cp_desc *desc)
455{
456 skb->protocol = eth_type_trans (skb, cp->dev);
457
237225f7
PZ		 458 cp->dev->stats.rx_packets++;
459 cp->dev->stats.rx_bytes += skb->len;
1da177e4
LT		 460
461#if CP_VLAN_TAG_USED
cf983019 462 if (cp->vlgrp && (desc->opts2 & cpu_to_le32(RxVlanTagged))) {
1da177e4 463 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
cf983019 464 swab16(le32_to_cpu(desc->opts2) & 0xffff));
1da177e4
LT		 465 } else
466#endif
467 netif_receive_skb(skb);
468}
469
470static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
471 u32 status, u32 len)
472{
473 if (netif_msg_rx_err (cp))
b93d5847 474 pr_debug("%s: rx err, slot %d status 0x%x len %d\n",
1da177e4 475 cp->dev->name, rx_tail, status, len);
237225f7 476 cp->dev->stats.rx_errors++;
1da177e4 477 if (status & RxErrFrame)
237225f7 478 cp->dev->stats.rx_frame_errors++;
1da177e4 479 if (status & RxErrCRC)
237225f7 480 cp->dev->stats.rx_crc_errors++;
1da177e4 481 if ((status & RxErrRunt) || (status & RxErrLong))
237225f7 482 cp->dev->stats.rx_length_errors++;
1da177e4 483 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
237225f7 484 cp->dev->stats.rx_length_errors++;
1da177e4 485 if (status & RxErrFIFO)
237225f7 486 cp->dev->stats.rx_fifo_errors++;
1da177e4
LT		 487}
488
489static inline unsigned int cp_rx_csum_ok (u32 status)
490{
491 unsigned int protocol = (status >> 16) & 0x3;
f3b197ac 492
1da177e4
LT		 493 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
494 return 1;
495 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
496 return 1;
497 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
498 return 1;
499 return 0;
500}
501
bea3348e 502static int cp_rx_poll(struct napi_struct *napi, int budget)
1da177e4 503{
bea3348e
SH		 504 struct cp_private *cp = container_of(napi, struct cp_private, napi);
505 struct net_device *dev = cp->dev;
506 unsigned int rx_tail = cp->rx_tail;
507 int rx;
1da177e4
LT		 508
509rx_status_loop:
510 rx = 0;
511 cpw16(IntrStatus, cp_rx_intr_mask);
512
513 while (1) {
514 u32 status, len;
515 dma_addr_t mapping;
516 struct sk_buff *skb, *new_skb;
517 struct cp_desc *desc;
839d1624 518 const unsigned buflen = cp->rx_buf_sz;
1da177e4 519
0ba894d4 520 skb = cp->rx_skb[rx_tail];
5d9428de 521 BUG_ON(!skb);
1da177e4
LT		 522
523 desc = &cp->rx_ring[rx_tail];
524 status = le32_to_cpu(desc->opts1);
525 if (status & DescOwn)
526 break;
527
528 len = (status & 0x1fff) - 4;
3598b57b 529 mapping = le64_to_cpu(desc->addr);
1da177e4
LT		 530
531 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
532 /* we don't support incoming fragmented frames.
533 * instead, we attempt to ensure that the
534 * pre-allocated RX skbs are properly sized such
535 * that RX fragments are never encountered
536 */
537 cp_rx_err_acct(cp, rx_tail, status, len);
237225f7 538 dev->stats.rx_dropped++;
1da177e4
LT		 539 cp->cp_stats.rx_frags++;
540 goto rx_next;
541 }
542
543 if (status & (RxError | RxErrFIFO)) {
544 cp_rx_err_acct(cp, rx_tail, status, len);
545 goto rx_next;
546 }
547
548 if (netif_msg_rx_status(cp))
b93d5847 549 pr_debug("%s: rx slot %d status 0x%x len %d\n",
c48e9399 550 dev->name, rx_tail, status, len);
1da177e4 551
89d71a66 552 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
1da177e4 553 if (!new_skb) {
237225f7 554 dev->stats.rx_dropped++;
1da177e4
LT		 555 goto rx_next;
556 }
557
6cc92cdd 558 dma_unmap_single(&cp->pdev->dev, mapping,
1da177e4
LT		 559 buflen, PCI_DMA_FROMDEVICE);
560
561 /* Handle checksum offloading for incoming packets. */
562 if (cp_rx_csum_ok(status))
563 skb->ip_summed = CHECKSUM_UNNECESSARY;
564 else
565 skb->ip_summed = CHECKSUM_NONE;
566
567 skb_put(skb, len);
568
6cc92cdd 569 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
3598b57b 570 PCI_DMA_FROMDEVICE);
0ba894d4 571 cp->rx_skb[rx_tail] = new_skb;
1da177e4
LT		 572
573 cp_rx_skb(cp, skb, desc);
574 rx++;
575
576rx_next:
577 cp->rx_ring[rx_tail].opts2 = 0;
578 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
579 if (rx_tail == (CP_RX_RING_SIZE - 1))
580 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
581 cp->rx_buf_sz);
582 else
583 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
584 rx_tail = NEXT_RX(rx_tail);
585
bea3348e 586 if (rx >= budget)
1da177e4
LT		 587 break;
588 }
589
590 cp->rx_tail = rx_tail;
591
1da177e4
LT		 592 /* if we did not reach work limit, then we're done with
593 * this round of polling
594 */
bea3348e 595 if (rx < budget) {
d15e9c4d
FR		 596 unsigned long flags;
597
1da177e4
LT		 598 if (cpr16(IntrStatus) & cp_rx_intr_mask)
599 goto rx_status_loop;
600
bea3348e 601 spin_lock_irqsave(&cp->lock, flags);
1da177e4 602 cpw16_f(IntrMask, cp_intr_mask);
288379f0 603 __napi_complete(napi);
bea3348e 604 spin_unlock_irqrestore(&cp->lock, flags);
1da177e4
LT		 605 }
606
bea3348e 607 return rx;
1da177e4
LT		 608}
609
7d12e780 610static irqreturn_t cp_interrupt (int irq, void *dev_instance)
1da177e4
LT		 611{
612 struct net_device *dev = dev_instance;
613 struct cp_private *cp;
614 u16 status;
615
616 if (unlikely(dev == NULL))
617 return IRQ_NONE;
618 cp = netdev_priv(dev);
619
620 status = cpr16(IntrStatus);
621 if (!status || (status == 0xFFFF))
622 return IRQ_NONE;
623
624 if (netif_msg_intr(cp))
b93d5847 625 pr_debug("%s: intr, status %04x cmd %02x cpcmd %04x\n",
1da177e4
LT		 626 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
627
628 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
629
630 spin_lock(&cp->lock);
631
632 /* close possible race's with dev_close */
633 if (unlikely(!netif_running(dev))) {
634 cpw16(IntrMask, 0);
635 spin_unlock(&cp->lock);
636 return IRQ_HANDLED;
637 }
638
639 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
288379f0 640 if (napi_schedule_prep(&cp->napi)) {
1da177e4 641 cpw16_f(IntrMask, cp_norx_intr_mask);
288379f0 642 __napi_schedule(&cp->napi);
1da177e4
LT		 643 }
644
645 if (status & (TxOK | TxErr | TxEmpty | SWInt))
646 cp_tx(cp);
647 if (status & LinkChg)
2501f843 648 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
1da177e4
LT		 649
650 spin_unlock(&cp->lock);
651
652 if (status & PciErr) {
653 u16 pci_status;
654
655 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
656 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
b93d5847 657 pr_err("%s: PCI bus error, status=%04x, PCI status=%04x\n",
1da177e4
LT		 658 dev->name, status, pci_status);
659
660 /* TODO: reset hardware */
661 }
662
663 return IRQ_HANDLED;
664}
665
7502cd10
SK		 666#ifdef CONFIG_NET_POLL_CONTROLLER
667/*
668 * Polling receive - used by netconsole and other diagnostic tools
669 * to allow network i/o with interrupts disabled.
670 */
671static void cp_poll_controller(struct net_device *dev)
672{
673 disable_irq(dev->irq);
7d12e780 674 cp_interrupt(dev->irq, dev);
7502cd10
SK		 675 enable_irq(dev->irq);
676}
677#endif
678
1da177e4
LT		 679static void cp_tx (struct cp_private *cp)
680{
681 unsigned tx_head = cp->tx_head;
682 unsigned tx_tail = cp->tx_tail;
683
684 while (tx_tail != tx_head) {
3598b57b 685 struct cp_desc *txd = cp->tx_ring + tx_tail;
1da177e4
LT		 686 struct sk_buff *skb;
687 u32 status;
688
689 rmb();
3598b57b 690 status = le32_to_cpu(txd->opts1);
1da177e4
LT		 691 if (status & DescOwn)
692 break;
693
48907e39 694 skb = cp->tx_skb[tx_tail];
5d9428de 695 BUG_ON(!skb);
1da177e4 696
6cc92cdd 697 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
48907e39
FR		 698 le32_to_cpu(txd->opts1) & 0xffff,
699 PCI_DMA_TODEVICE);
1da177e4
LT		 700
701 if (status & LastFrag) {
702 if (status & (TxError | TxFIFOUnder)) {
703 if (netif_msg_tx_err(cp))
b93d5847 704 pr_debug("%s: tx err, status 0x%x\n",
1da177e4 705 cp->dev->name, status);
237225f7 706 cp->dev->stats.tx_errors++;
1da177e4 707 if (status & TxOWC)
237225f7 708 cp->dev->stats.tx_window_errors++;
1da177e4 709 if (status & TxMaxCol)
237225f7 710 cp->dev->stats.tx_aborted_errors++;
1da177e4 711 if (status & TxLinkFail)
237225f7 712 cp->dev->stats.tx_carrier_errors++;
1da177e4 713 if (status & TxFIFOUnder)
237225f7 714 cp->dev->stats.tx_fifo_errors++;
1da177e4 715 } else {
237225f7 716 cp->dev->stats.collisions +=
1da177e4 717 ((status >> TxColCntShift) & TxColCntMask);
237225f7
PZ		 718 cp->dev->stats.tx_packets++;
719 cp->dev->stats.tx_bytes += skb->len;
1da177e4 720 if (netif_msg_tx_done(cp))
b93d5847 721 pr_debug("%s: tx done, slot %d\n", cp->dev->name, tx_tail);
1da177e4
LT		 722 }
723 dev_kfree_skb_irq(skb);
724 }
725
48907e39 726 cp->tx_skb[tx_tail] = NULL;
1da177e4
LT		 727
728 tx_tail = NEXT_TX(tx_tail);
729 }
730
731 cp->tx_tail = tx_tail;
732
733 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
734 netif_wake_queue(cp->dev);
735}
736
61357325
SH		 737static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
738 struct net_device *dev)
1da177e4
LT		 739{
740 struct cp_private *cp = netdev_priv(dev);
741 unsigned entry;
fcec3456 742 u32 eor, flags;
553af567 743 unsigned long intr_flags;
1da177e4
LT		 744#if CP_VLAN_TAG_USED
745 u32 vlan_tag = 0;
746#endif
fcec3456 747 int mss = 0;
1da177e4 748
553af567 749 spin_lock_irqsave(&cp->lock, intr_flags);
1da177e4
LT		 750
751 /* This is a hard error, log it. */
752 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
753 netif_stop_queue(dev);
553af567 754 spin_unlock_irqrestore(&cp->lock, intr_flags);
b93d5847 755 pr_err(PFX "%s: BUG! Tx Ring full when queue awake!\n",
1da177e4 756 dev->name);
5b548140 757 return NETDEV_TX_BUSY;
1da177e4
LT		 758 }
759
760#if CP_VLAN_TAG_USED
761 if (cp->vlgrp && vlan_tx_tag_present(skb))
cf983019 762 vlan_tag = TxVlanTag | swab16(vlan_tx_tag_get(skb));
1da177e4
LT		 763#endif
764
765 entry = cp->tx_head;
766 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
fcec3456 767 if (dev->features & NETIF_F_TSO)
7967168c 768 mss = skb_shinfo(skb)->gso_size;
fcec3456 769
1da177e4
LT		 770 if (skb_shinfo(skb)->nr_frags == 0) {
771 struct cp_desc *txd = &cp->tx_ring[entry];
772 u32 len;
773 dma_addr_t mapping;
774
775 len = skb->len;
6cc92cdd 776 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
1da177e4
LT		 777 CP_VLAN_TX_TAG(txd, vlan_tag);
778 txd->addr = cpu_to_le64(mapping);
779 wmb();
780
fcec3456
JG		 781 flags = eor | len | DescOwn | FirstFrag | LastFrag;
782
783 if (mss)
784 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
84fa7933 785 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 786 const struct iphdr *ip = ip_hdr(skb);
1da177e4 787 if (ip->protocol == IPPROTO_TCP)
fcec3456 788 flags |= IPCS | TCPCS;
1da177e4 789 else if (ip->protocol == IPPROTO_UDP)
fcec3456 790 flags |= IPCS | UDPCS;
1da177e4 791 else
5734418d 792 WARN_ON(1); /* we need a WARN() */
fcec3456
JG		 793 }
794
795 txd->opts1 = cpu_to_le32(flags);
1da177e4
LT		 796 wmb();
797
48907e39 798 cp->tx_skb[entry] = skb;
1da177e4
LT		 799 entry = NEXT_TX(entry);
800 } else {
801 struct cp_desc *txd;
802 u32 first_len, first_eor;
803 dma_addr_t first_mapping;
804 int frag, first_entry = entry;
eddc9ec5 805 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 806
807 /* We must give this initial chunk to the device last.
808 * Otherwise we could race with the device.
809 */
810 first_eor = eor;
811 first_len = skb_headlen(skb);
6cc92cdd 812 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
1da177e4 813 first_len, PCI_DMA_TODEVICE);
48907e39 814 cp->tx_skb[entry] = skb;
1da177e4
LT		 815 entry = NEXT_TX(entry);
816
817 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
818 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
819 u32 len;
820 u32 ctrl;
821 dma_addr_t mapping;
822
823 len = this_frag->size;
6cc92cdd 824 mapping = dma_map_single(&cp->pdev->dev,
1da177e4
LT		 825 ((void *) page_address(this_frag->page) +
826 this_frag->page_offset),
827 len, PCI_DMA_TODEVICE);
828 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
829
fcec3456
JG		 830 ctrl = eor | len | DescOwn;
831
832 if (mss)
833 ctrl |= LargeSend |
834 ((mss & MSSMask) << MSSShift);
84fa7933 835 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4 836 if (ip->protocol == IPPROTO_TCP)
fcec3456 837 ctrl |= IPCS | TCPCS;
1da177e4 838 else if (ip->protocol == IPPROTO_UDP)
fcec3456 839 ctrl |= IPCS | UDPCS;
1da177e4
LT		 840 else
841 BUG();
fcec3456 842 }
1da177e4
LT		 843
844 if (frag == skb_shinfo(skb)->nr_frags - 1)
845 ctrl |= LastFrag;
846
847 txd = &cp->tx_ring[entry];
848 CP_VLAN_TX_TAG(txd, vlan_tag);
849 txd->addr = cpu_to_le64(mapping);
850 wmb();
851
852 txd->opts1 = cpu_to_le32(ctrl);
853 wmb();
854
48907e39 855 cp->tx_skb[entry] = skb;
1da177e4
LT		 856 entry = NEXT_TX(entry);
857 }
858
859 txd = &cp->tx_ring[first_entry];
860 CP_VLAN_TX_TAG(txd, vlan_tag);
861 txd->addr = cpu_to_le64(first_mapping);
862 wmb();
863
84fa7933 864 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 865 if (ip->protocol == IPPROTO_TCP)
866 txd->opts1 = cpu_to_le32(first_eor | first_len |
867 FirstFrag | DescOwn |
868 IPCS | TCPCS);
869 else if (ip->protocol == IPPROTO_UDP)
870 txd->opts1 = cpu_to_le32(first_eor | first_len |
871 FirstFrag | DescOwn |
872 IPCS | UDPCS);
873 else
874 BUG();
875 } else
876 txd->opts1 = cpu_to_le32(first_eor | first_len |
877 FirstFrag | DescOwn);
878 wmb();
879 }
880 cp->tx_head = entry;
881 if (netif_msg_tx_queued(cp))
b93d5847 882 pr_debug("%s: tx queued, slot %d, skblen %d\n",
1da177e4
LT		 883 dev->name, entry, skb->len);
884 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
885 netif_stop_queue(dev);
886
553af567 887 spin_unlock_irqrestore(&cp->lock, intr_flags);
1da177e4
LT		 888
889 cpw8(TxPoll, NormalTxPoll);
890 dev->trans_start = jiffies;
891
6ed10654 892 return NETDEV_TX_OK;
1da177e4
LT		 893}
894
895/* Set or clear the multicast filter for this adaptor.
896 This routine is not state sensitive and need not be SMP locked. */
897
898static void __cp_set_rx_mode (struct net_device *dev)
899{
900 struct cp_private *cp = netdev_priv(dev);
901 u32 mc_filter[2]; /* Multicast hash filter */
902 int i, rx_mode;
903 u32 tmp;
904
905 /* Note: do not reorder, GCC is clever about common statements. */
906 if (dev->flags & IFF_PROMISC) {
907 /* Unconditionally log net taps. */
1da177e4
LT		 908 rx_mode =
909 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
910 AcceptAllPhys;
911 mc_filter[1] = mc_filter[0] = 0xffffffff;
8e95a202
JP		 912 } else if ((dev->mc_count > multicast_filter_limit) ||
913 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 914 /* Too many to filter perfectly -- accept all multicasts. */
915 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
916 mc_filter[1] = mc_filter[0] = 0xffffffff;
917 } else {
918 struct dev_mc_list *mclist;
919 rx_mode = AcceptBroadcast | AcceptMyPhys;
920 mc_filter[1] = mc_filter[0] = 0;
921 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
922 i++, mclist = mclist->next) {
923 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
924
925 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
926 rx_mode |= AcceptMulticast;
927 }
928 }
929
930 /* We can safely update without stopping the chip. */
931 tmp = cp_rx_config | rx_mode;
932 if (cp->rx_config != tmp) {
933 cpw32_f (RxConfig, tmp);
934 cp->rx_config = tmp;
935 }
936 cpw32_f (MAR0 + 0, mc_filter[0]);
937 cpw32_f (MAR0 + 4, mc_filter[1]);
938}
939
940static void cp_set_rx_mode (struct net_device *dev)
941{
942 unsigned long flags;
943 struct cp_private *cp = netdev_priv(dev);
944
945 spin_lock_irqsave (&cp->lock, flags);
946 __cp_set_rx_mode(dev);
947 spin_unlock_irqrestore (&cp->lock, flags);
948}
949
950static void __cp_get_stats(struct cp_private *cp)
951{
952 /* only lower 24 bits valid; write any value to clear */
237225f7 953 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
1da177e4
LT		 954 cpw32 (RxMissed, 0);
955}
956
957static struct net_device_stats *cp_get_stats(struct net_device *dev)
958{
959 struct cp_private *cp = netdev_priv(dev);
960 unsigned long flags;
961
962 /* The chip only need report frame silently dropped. */
963 spin_lock_irqsave(&cp->lock, flags);
964 if (netif_running(dev) && netif_device_present(dev))
965 __cp_get_stats(cp);
966 spin_unlock_irqrestore(&cp->lock, flags);
967
237225f7 968 return &dev->stats;
1da177e4
LT		 969}
970
971static void cp_stop_hw (struct cp_private *cp)
972{
973 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
974 cpw16_f(IntrMask, 0);
975 cpw8(Cmd, 0);
976 cpw16_f(CpCmd, 0);
977 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
978
979 cp->rx_tail = 0;
980 cp->tx_head = cp->tx_tail = 0;
981}
982
983static void cp_reset_hw (struct cp_private *cp)
984{
985 unsigned work = 1000;
986
987 cpw8(Cmd, CmdReset);
988
989 while (work--) {
990 if (!(cpr8(Cmd) & CmdReset))
991 return;
992
3173c890 993 schedule_timeout_uninterruptible(10);
1da177e4
LT		 994 }
995
b93d5847 996 pr_err("%s: hardware reset timeout\n", cp->dev->name);
1da177e4
LT		 997}
998
999static inline void cp_start_hw (struct cp_private *cp)
1000{
1001 cpw16(CpCmd, cp->cpcmd);
1002 cpw8(Cmd, RxOn | TxOn);
1003}
1004
1005static void cp_init_hw (struct cp_private *cp)
1006{
1007 struct net_device *dev = cp->dev;
1008 dma_addr_t ring_dma;
1009
1010 cp_reset_hw(cp);
1011
1012 cpw8_f (Cfg9346, Cfg9346_Unlock);
1013
1014 /* Restore our idea of the MAC address. */
03233b90
AV		 1015 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1016 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1da177e4
LT		 1017
1018 cp_start_hw(cp);
1019 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1020
1021 __cp_set_rx_mode(dev);
1022 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1023
1024 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1025 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1026 cpw8(Config3, PARMEnable);
1027 cp->wol_enabled = 0;
1028
f3b197ac 1029 cpw8(Config5, cpr8(Config5) & PMEStatus);
1da177e4
LT		 1030
1031 cpw32_f(HiTxRingAddr, 0);
1032 cpw32_f(HiTxRingAddr + 4, 0);
1033
1034 ring_dma = cp->ring_dma;
1035 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1036 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1037
1038 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1039 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1040 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1041
1042 cpw16(MultiIntr, 0);
1043
1044 cpw16_f(IntrMask, cp_intr_mask);
1045
1046 cpw8_f(Cfg9346, Cfg9346_Lock);
1047}
1048
a52be1cb 1049static int cp_refill_rx(struct cp_private *cp)
1da177e4 1050{
a52be1cb 1051 struct net_device *dev = cp->dev;
1da177e4
LT		 1052 unsigned i;
1053
1054 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1055 struct sk_buff *skb;
3598b57b 1056 dma_addr_t mapping;
1da177e4 1057
89d71a66 1058 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1da177e4
LT		 1059 if (!skb)
1060 goto err_out;
1061
6cc92cdd
JG		 1062 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1063 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1064 cp->rx_skb[i] = skb;
1da177e4
LT		 1065
1066 cp->rx_ring[i].opts2 = 0;
3598b57b 1067 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1da177e4
LT		 1068 if (i == (CP_RX_RING_SIZE - 1))
1069 cp->rx_ring[i].opts1 =
1070 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1071 else
1072 cp->rx_ring[i].opts1 =
1073 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1074 }
1075
1076 return 0;
1077
1078err_out:
1079 cp_clean_rings(cp);
1080 return -ENOMEM;
1081}
1082
576cfa93
FR		 1083static void cp_init_rings_index (struct cp_private *cp)
1084{
1085 cp->rx_tail = 0;
1086 cp->tx_head = cp->tx_tail = 0;
1087}
1088
1da177e4
LT		 1089static int cp_init_rings (struct cp_private *cp)
1090{
1091 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1092 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1093
576cfa93 1094 cp_init_rings_index(cp);
1da177e4
LT		 1095
1096 return cp_refill_rx (cp);
1097}
1098
1099static int cp_alloc_rings (struct cp_private *cp)
1100{
1101 void *mem;
1102
6cc92cdd
JG		 1103 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1104 &cp->ring_dma, GFP_KERNEL);
1da177e4
LT		 1105 if (!mem)
1106 return -ENOMEM;
1107
1108 cp->rx_ring = mem;
1109 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1110
1da177e4
LT		 1111 return cp_init_rings(cp);
1112}
1113
1114static void cp_clean_rings (struct cp_private *cp)
1115{
3598b57b 1116 struct cp_desc *desc;
1da177e4
LT		 1117 unsigned i;
1118
1da177e4 1119 for (i = 0; i < CP_RX_RING_SIZE; i++) {
0ba894d4 1120 if (cp->rx_skb[i]) {
3598b57b 1121 desc = cp->rx_ring + i;
6cc92cdd 1122 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1da177e4 1123 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1124 dev_kfree_skb(cp->rx_skb[i]);
1da177e4
LT		 1125 }
1126 }
1127
1128 for (i = 0; i < CP_TX_RING_SIZE; i++) {
48907e39
FR		 1129 if (cp->tx_skb[i]) {
1130 struct sk_buff *skb = cp->tx_skb[i];
5734418d 1131
3598b57b 1132 desc = cp->tx_ring + i;
6cc92cdd 1133 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
48907e39
FR		 1134 le32_to_cpu(desc->opts1) & 0xffff,
1135 PCI_DMA_TODEVICE);
3598b57b 1136 if (le32_to_cpu(desc->opts1) & LastFrag)
5734418d 1137 dev_kfree_skb(skb);
237225f7 1138 cp->dev->stats.tx_dropped++;
1da177e4
LT		 1139 }
1140 }
1141
5734418d
FR		 1142 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1143 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1144
0ba894d4 1145 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
48907e39 1146 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1da177e4
LT		 1147}
1148
1149static void cp_free_rings (struct cp_private *cp)
1150{
1151 cp_clean_rings(cp);
6cc92cdd
JG		 1152 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1153 cp->ring_dma);
1da177e4
LT		 1154 cp->rx_ring = NULL;
1155 cp->tx_ring = NULL;
1da177e4
LT		 1156}
1157
1158static int cp_open (struct net_device *dev)
1159{
1160 struct cp_private *cp = netdev_priv(dev);
1161 int rc;
1162
1163 if (netif_msg_ifup(cp))
b93d5847 1164 pr_debug("%s: enabling interface\n", dev->name);
1da177e4
LT		 1165
1166 rc = cp_alloc_rings(cp);
1167 if (rc)
1168 return rc;
1169
bea3348e
SH		 1170 napi_enable(&cp->napi);
1171
1da177e4
LT		 1172 cp_init_hw(cp);
1173
1fb9df5d 1174 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1175 if (rc)
1176 goto err_out_hw;
1177
1178 netif_carrier_off(dev);
2501f843 1179 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1da177e4
LT		 1180 netif_start_queue(dev);
1181
1182 return 0;
1183
1184err_out_hw:
bea3348e 1185 napi_disable(&cp->napi);
1da177e4
LT		 1186 cp_stop_hw(cp);
1187 cp_free_rings(cp);
1188 return rc;
1189}
1190
1191static int cp_close (struct net_device *dev)
1192{
1193 struct cp_private *cp = netdev_priv(dev);
1194 unsigned long flags;
1195
bea3348e
SH		 1196 napi_disable(&cp->napi);
1197
1da177e4 1198 if (netif_msg_ifdown(cp))
b93d5847 1199 pr_debug("%s: disabling interface\n", dev->name);
1da177e4
LT		 1200
1201 spin_lock_irqsave(&cp->lock, flags);
1202
1203 netif_stop_queue(dev);
1204 netif_carrier_off(dev);
1205
1206 cp_stop_hw(cp);
1207
1208 spin_unlock_irqrestore(&cp->lock, flags);
1209
1da177e4
LT		 1210 free_irq(dev->irq, dev);
1211
1212 cp_free_rings(cp);
1213 return 0;
1214}
1215
9030c0d2
FR		 1216static void cp_tx_timeout(struct net_device *dev)
1217{
1218 struct cp_private *cp = netdev_priv(dev);
1219 unsigned long flags;
1220 int rc;
1221
b93d5847 1222 pr_warning("%s: Transmit timeout, status %2x %4x %4x %4x\n",
9030c0d2
FR		 1223 dev->name, cpr8(Cmd), cpr16(CpCmd),
1224 cpr16(IntrStatus), cpr16(IntrMask));
1225
1226 spin_lock_irqsave(&cp->lock, flags);
1227
1228 cp_stop_hw(cp);
1229 cp_clean_rings(cp);
1230 rc = cp_init_rings(cp);
1231 cp_start_hw(cp);
1232
1233 netif_wake_queue(dev);
1234
1235 spin_unlock_irqrestore(&cp->lock, flags);
1236
1237 return;
1238}
1239
1da177e4
LT		 1240#ifdef BROKEN
1241static int cp_change_mtu(struct net_device *dev, int new_mtu)
1242{
1243 struct cp_private *cp = netdev_priv(dev);
1244 int rc;
1245 unsigned long flags;
1246
1247 /* check for invalid MTU, according to hardware limits */
1248 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1249 return -EINVAL;
1250
1251 /* if network interface not up, no need for complexity */
1252 if (!netif_running(dev)) {
1253 dev->mtu = new_mtu;
1254 cp_set_rxbufsize(cp); /* set new rx buf size */
1255 return 0;
1256 }
1257
1258 spin_lock_irqsave(&cp->lock, flags);
1259
1260 cp_stop_hw(cp); /* stop h/w and free rings */
1261 cp_clean_rings(cp);
1262
1263 dev->mtu = new_mtu;
1264 cp_set_rxbufsize(cp); /* set new rx buf size */
1265
1266 rc = cp_init_rings(cp); /* realloc and restart h/w */
1267 cp_start_hw(cp);
1268
1269 spin_unlock_irqrestore(&cp->lock, flags);
1270
1271 return rc;
1272}
1273#endif /* BROKEN */
1274
f71e1309 1275static const char mii_2_8139_map[8] = {
1da177e4
LT		 1276 BasicModeCtrl,
1277 BasicModeStatus,
1278 0,
1279 0,
1280 NWayAdvert,
1281 NWayLPAR,
1282 NWayExpansion,
1283 0
1284};
1285
1286static int mdio_read(struct net_device *dev, int phy_id, int location)
1287{
1288 struct cp_private *cp = netdev_priv(dev);
1289
1290 return location < 8 && mii_2_8139_map[location] ?
1291 readw(cp->regs + mii_2_8139_map[location]) : 0;
1292}
1293
1294
1295static void mdio_write(struct net_device *dev, int phy_id, int location,
1296 int value)
1297{
1298 struct cp_private *cp = netdev_priv(dev);
1299
1300 if (location == 0) {
1301 cpw8(Cfg9346, Cfg9346_Unlock);
1302 cpw16(BasicModeCtrl, value);
1303 cpw8(Cfg9346, Cfg9346_Lock);
1304 } else if (location < 8 && mii_2_8139_map[location])
1305 cpw16(mii_2_8139_map[location], value);
1306}
1307
1308/* Set the ethtool Wake-on-LAN settings */
1309static int netdev_set_wol (struct cp_private *cp,
1310 const struct ethtool_wolinfo *wol)
1311{
1312 u8 options;
1313
1314 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1315 /* If WOL is being disabled, no need for complexity */
1316 if (wol->wolopts) {
1317 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1318 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1319 }
1320
1321 cpw8 (Cfg9346, Cfg9346_Unlock);
1322 cpw8 (Config3, options);
1323 cpw8 (Cfg9346, Cfg9346_Lock);
1324
1325 options = 0; /* Paranoia setting */
1326 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1327 /* If WOL is being disabled, no need for complexity */
1328 if (wol->wolopts) {
1329 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1330 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1331 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1332 }
1333
1334 cpw8 (Config5, options);
1335
1336 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1337
1338 return 0;
1339}
1340
1341/* Get the ethtool Wake-on-LAN settings */
1342static void netdev_get_wol (struct cp_private *cp,
1343 struct ethtool_wolinfo *wol)
1344{
1345 u8 options;
1346
1347 wol->wolopts = 0; /* Start from scratch */
1348 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1349 WAKE_MCAST | WAKE_UCAST;
1350 /* We don't need to go on if WOL is disabled */
1351 if (!cp->wol_enabled) return;
f3b197ac 1352
1da177e4
LT		 1353 options = cpr8 (Config3);
1354 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1355 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1356
1357 options = 0; /* Paranoia setting */
1358 options = cpr8 (Config5);
1359 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1360 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1361 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1362}
1363
1364static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1365{
1366 struct cp_private *cp = netdev_priv(dev);
1367
1368 strcpy (info->driver, DRV_NAME);
1369 strcpy (info->version, DRV_VERSION);
1370 strcpy (info->bus_info, pci_name(cp->pdev));
1371}
1372
1373static int cp_get_regs_len(struct net_device *dev)
1374{
1375 return CP_REGS_SIZE;
1376}
1377
b9f2c044 1378static int cp_get_sset_count (struct net_device *dev, int sset)
1da177e4 1379{
b9f2c044
JG		 1380 switch (sset) {
1381 case ETH_SS_STATS:
1382 return CP_NUM_STATS;
1383 default:
1384 return -EOPNOTSUPP;
1385 }
1da177e4
LT		 1386}
1387
1388static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1389{
1390 struct cp_private *cp = netdev_priv(dev);
1391 int rc;
1392 unsigned long flags;
1393
1394 spin_lock_irqsave(&cp->lock, flags);
1395 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1396 spin_unlock_irqrestore(&cp->lock, flags);
1397
1398 return rc;
1399}
1400
1401static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1402{
1403 struct cp_private *cp = netdev_priv(dev);
1404 int rc;
1405 unsigned long flags;
1406
1407 spin_lock_irqsave(&cp->lock, flags);
1408 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1409 spin_unlock_irqrestore(&cp->lock, flags);
1410
1411 return rc;
1412}
1413
1414static int cp_nway_reset(struct net_device *dev)
1415{
1416 struct cp_private *cp = netdev_priv(dev);
1417 return mii_nway_restart(&cp->mii_if);
1418}
1419
1420static u32 cp_get_msglevel(struct net_device *dev)
1421{
1422 struct cp_private *cp = netdev_priv(dev);
1423 return cp->msg_enable;
1424}
1425
1426static void cp_set_msglevel(struct net_device *dev, u32 value)
1427{
1428 struct cp_private *cp = netdev_priv(dev);
1429 cp->msg_enable = value;
1430}
1431
1432static u32 cp_get_rx_csum(struct net_device *dev)
1433{
1434 struct cp_private *cp = netdev_priv(dev);
1435 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1436}
1437
1438static int cp_set_rx_csum(struct net_device *dev, u32 data)
1439{
1440 struct cp_private *cp = netdev_priv(dev);
1441 u16 cmd = cp->cpcmd, newcmd;
1442
1443 newcmd = cmd;
1444
1445 if (data)
1446 newcmd |= RxChkSum;
1447 else
1448 newcmd &= ~RxChkSum;
1449
1450 if (newcmd != cmd) {
1451 unsigned long flags;
1452
1453 spin_lock_irqsave(&cp->lock, flags);
1454 cp->cpcmd = newcmd;
1455 cpw16_f(CpCmd, newcmd);
1456 spin_unlock_irqrestore(&cp->lock, flags);
1457 }
1458
1459 return 0;
1460}
1461
1462static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1463 void *p)
1464{
1465 struct cp_private *cp = netdev_priv(dev);
1466 unsigned long flags;
1467
1468 if (regs->len < CP_REGS_SIZE)
1469 return /* -EINVAL */;
1470
1471 regs->version = CP_REGS_VER;
1472
1473 spin_lock_irqsave(&cp->lock, flags);
1474 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1475 spin_unlock_irqrestore(&cp->lock, flags);
1476}
1477
1478static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1479{
1480 struct cp_private *cp = netdev_priv(dev);
1481 unsigned long flags;
1482
1483 spin_lock_irqsave (&cp->lock, flags);
1484 netdev_get_wol (cp, wol);
1485 spin_unlock_irqrestore (&cp->lock, flags);
1486}
1487
1488static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1489{
1490 struct cp_private *cp = netdev_priv(dev);
1491 unsigned long flags;
1492 int rc;
1493
1494 spin_lock_irqsave (&cp->lock, flags);
1495 rc = netdev_set_wol (cp, wol);
1496 spin_unlock_irqrestore (&cp->lock, flags);
1497
1498 return rc;
1499}
1500
1501static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1502{
1503 switch (stringset) {
1504 case ETH_SS_STATS:
1505 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1506 break;
1507 default:
1508 BUG();
1509 break;
1510 }
1511}
1512
1513static void cp_get_ethtool_stats (struct net_device *dev,
1514 struct ethtool_stats *estats, u64 *tmp_stats)
1515{
1516 struct cp_private *cp = netdev_priv(dev);
8b512927
SH		 1517 struct cp_dma_stats *nic_stats;
1518 dma_addr_t dma;
1da177e4
LT		 1519 int i;
1520
6cc92cdd
JG		 1521 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1522 &dma, GFP_KERNEL);
8b512927
SH		 1523 if (!nic_stats)
1524 return;
97f568d8 1525
1da177e4 1526 /* begin NIC statistics dump */
8b512927 1527 cpw32(StatsAddr + 4, (u64)dma >> 32);
284901a9 1528 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1da177e4
LT		 1529 cpr32(StatsAddr);
1530
97f568d8 1531 for (i = 0; i < 1000; i++) {
1da177e4
LT		 1532 if ((cpr32(StatsAddr) & DumpStats) == 0)
1533 break;
97f568d8 1534 udelay(10);
1da177e4 1535 }
97f568d8
SH		 1536 cpw32(StatsAddr, 0);
1537 cpw32(StatsAddr + 4, 0);
8b512927 1538 cpr32(StatsAddr);
1da177e4
LT		 1539
1540 i = 0;
8b512927
SH		 1541 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1542 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1543 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1544 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1545 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1546 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1547 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1548 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1549 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1550 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1551 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1552 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1553 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1da177e4 1554 tmp_stats[i++] = cp->cp_stats.rx_frags;
5d9428de 1555 BUG_ON(i != CP_NUM_STATS);
8b512927 1556
6cc92cdd 1557 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1da177e4
LT		 1558}
1559
7282d491 1560static const struct ethtool_ops cp_ethtool_ops = {
1da177e4
LT		 1561 .get_drvinfo = cp_get_drvinfo,
1562 .get_regs_len = cp_get_regs_len,
b9f2c044 1563 .get_sset_count = cp_get_sset_count,
1da177e4
LT		 1564 .get_settings = cp_get_settings,
1565 .set_settings = cp_set_settings,
1566 .nway_reset = cp_nway_reset,
1567 .get_link = ethtool_op_get_link,
1568 .get_msglevel = cp_get_msglevel,
1569 .set_msglevel = cp_set_msglevel,
1570 .get_rx_csum = cp_get_rx_csum,
1571 .set_rx_csum = cp_set_rx_csum,
1da177e4 1572 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1da177e4 1573 .set_sg = ethtool_op_set_sg,
fcec3456 1574 .set_tso = ethtool_op_set_tso,
1da177e4
LT		 1575 .get_regs = cp_get_regs,
1576 .get_wol = cp_get_wol,
1577 .set_wol = cp_set_wol,
1578 .get_strings = cp_get_strings,
1579 .get_ethtool_stats = cp_get_ethtool_stats,
722fdb33
PC		 1580 .get_eeprom_len = cp_get_eeprom_len,
1581 .get_eeprom = cp_get_eeprom,
1582 .set_eeprom = cp_set_eeprom,
1da177e4
LT		 1583};
1584
1585static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1586{
1587 struct cp_private *cp = netdev_priv(dev);
1588 int rc;
1589 unsigned long flags;
1590
1591 if (!netif_running(dev))
1592 return -EINVAL;
1593
1594 spin_lock_irqsave(&cp->lock, flags);
1595 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1596 spin_unlock_irqrestore(&cp->lock, flags);
1597 return rc;
1598}
1599
c048aaf4
JP		 1600static int cp_set_mac_address(struct net_device *dev, void *p)
1601{
1602 struct cp_private *cp = netdev_priv(dev);
1603 struct sockaddr *addr = p;
1604
1605 if (!is_valid_ether_addr(addr->sa_data))
1606 return -EADDRNOTAVAIL;
1607
1608 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1609
1610 spin_lock_irq(&cp->lock);
1611
1612 cpw8_f(Cfg9346, Cfg9346_Unlock);
1613 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1614 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1615 cpw8_f(Cfg9346, Cfg9346_Lock);
1616
1617 spin_unlock_irq(&cp->lock);
1618
1619 return 0;
1620}
1621
1da177e4
LT		 1622/* Serial EEPROM section. */
1623
1624/* EEPROM_Ctrl bits. */
1625#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1626#define EE_CS 0x08 /* EEPROM chip select. */
1627#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1628#define EE_WRITE_0 0x00
1629#define EE_WRITE_1 0x02
1630#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1631#define EE_ENB (0x80 | EE_CS)
1632
1633/* Delay between EEPROM clock transitions.
1634 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1635 */
1636
1637#define eeprom_delay() readl(ee_addr)
1638
1639/* The EEPROM commands include the alway-set leading bit. */
722fdb33 1640#define EE_EXTEND_CMD (4)
1da177e4
LT		 1641#define EE_WRITE_CMD (5)
1642#define EE_READ_CMD (6)
1643#define EE_ERASE_CMD (7)
1644
722fdb33
PC		 1645#define EE_EWDS_ADDR (0)
1646#define EE_WRAL_ADDR (1)
1647#define EE_ERAL_ADDR (2)
1648#define EE_EWEN_ADDR (3)
1649
1650#define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1da177e4 1651
722fdb33
PC		 1652static void eeprom_cmd_start(void __iomem *ee_addr)
1653{
1da177e4
LT		 1654 writeb (EE_ENB & ~EE_CS, ee_addr);
1655 writeb (EE_ENB, ee_addr);
1656 eeprom_delay ();
722fdb33 1657}
1da177e4 1658
722fdb33
PC		 1659static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1660{
1661 int i;
1662
1663 /* Shift the command bits out. */
1664 for (i = cmd_len - 1; i >= 0; i--) {
1665 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1da177e4
LT		 1666 writeb (EE_ENB | dataval, ee_addr);
1667 eeprom_delay ();
1668 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1669 eeprom_delay ();
1670 }
1671 writeb (EE_ENB, ee_addr);
1672 eeprom_delay ();
722fdb33
PC		 1673}
1674
1675static void eeprom_cmd_end(void __iomem *ee_addr)
1676{
1677 writeb (~EE_CS, ee_addr);
1678 eeprom_delay ();
1679}
1680
1681static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1682 int addr_len)
1683{
1684 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1685
1686 eeprom_cmd_start(ee_addr);
1687 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1688 eeprom_cmd_end(ee_addr);
1689}
1690
1691static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1692{
1693 int i;
1694 u16 retval = 0;
1695 void __iomem *ee_addr = ioaddr + Cfg9346;
1696 int read_cmd = location | (EE_READ_CMD << addr_len);
1697
1698 eeprom_cmd_start(ee_addr);
1699 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1da177e4
LT		 1700
1701 for (i = 16; i > 0; i--) {
1702 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1703 eeprom_delay ();
1704 retval =
1705 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1706 0);
1707 writeb (EE_ENB, ee_addr);
1708 eeprom_delay ();
1709 }
1710
722fdb33 1711 eeprom_cmd_end(ee_addr);
1da177e4
LT		 1712
1713 return retval;
1714}
1715
722fdb33
PC		 1716static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1717 int addr_len)
1718{
1719 int i;
1720 void __iomem *ee_addr = ioaddr + Cfg9346;
1721 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1722
1723 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1724
1725 eeprom_cmd_start(ee_addr);
1726 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1727 eeprom_cmd(ee_addr, val, 16);
1728 eeprom_cmd_end(ee_addr);
1729
1730 eeprom_cmd_start(ee_addr);
1731 for (i = 0; i < 20000; i++)
1732 if (readb(ee_addr) & EE_DATA_READ)
1733 break;
1734 eeprom_cmd_end(ee_addr);
1735
1736 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1737}
1738
1739static int cp_get_eeprom_len(struct net_device *dev)
1740{
1741 struct cp_private *cp = netdev_priv(dev);
1742 int size;
1743
1744 spin_lock_irq(&cp->lock);
1745 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1746 spin_unlock_irq(&cp->lock);
1747
1748 return size;
1749}
1750
1751static int cp_get_eeprom(struct net_device *dev,
1752 struct ethtool_eeprom *eeprom, u8 *data)
1753{
1754 struct cp_private *cp = netdev_priv(dev);
1755 unsigned int addr_len;
1756 u16 val;
1757 u32 offset = eeprom->offset >> 1;
1758 u32 len = eeprom->len;
1759 u32 i = 0;
1760
1761 eeprom->magic = CP_EEPROM_MAGIC;
1762
1763 spin_lock_irq(&cp->lock);
1764
1765 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1766
1767 if (eeprom->offset & 1) {
1768 val = read_eeprom(cp->regs, offset, addr_len);
1769 data[i++] = (u8)(val >> 8);
1770 offset++;
1771 }
1772
1773 while (i < len - 1) {
1774 val = read_eeprom(cp->regs, offset, addr_len);
1775 data[i++] = (u8)val;
1776 data[i++] = (u8)(val >> 8);
1777 offset++;
1778 }
1779
1780 if (i < len) {
1781 val = read_eeprom(cp->regs, offset, addr_len);
1782 data[i] = (u8)val;
1783 }
1784
1785 spin_unlock_irq(&cp->lock);
1786 return 0;
1787}
1788
1789static int cp_set_eeprom(struct net_device *dev,
1790 struct ethtool_eeprom *eeprom, u8 *data)
1791{
1792 struct cp_private *cp = netdev_priv(dev);
1793 unsigned int addr_len;
1794 u16 val;
1795 u32 offset = eeprom->offset >> 1;
1796 u32 len = eeprom->len;
1797 u32 i = 0;
1798
1799 if (eeprom->magic != CP_EEPROM_MAGIC)
1800 return -EINVAL;
1801
1802 spin_lock_irq(&cp->lock);
1803
1804 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1805
1806 if (eeprom->offset & 1) {
1807 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1808 val |= (u16)data[i++] << 8;
1809 write_eeprom(cp->regs, offset, val, addr_len);
1810 offset++;
1811 }
1812
1813 while (i < len - 1) {
1814 val = (u16)data[i++];
1815 val |= (u16)data[i++] << 8;
1816 write_eeprom(cp->regs, offset, val, addr_len);
1817 offset++;
1818 }
1819
1820 if (i < len) {
1821 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1822 val |= (u16)data[i];
1823 write_eeprom(cp->regs, offset, val, addr_len);
1824 }
1825
1826 spin_unlock_irq(&cp->lock);
1827 return 0;
1828}
1829
1da177e4
LT		 1830/* Put the board into D3cold state and wait for WakeUp signal */
1831static void cp_set_d3_state (struct cp_private *cp)
1832{
1833 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1834 pci_set_power_state (cp->pdev, PCI_D3hot);
1835}
1836
48dfcde4
SH		 1837static const struct net_device_ops cp_netdev_ops = {
1838 .ndo_open = cp_open,
1839 .ndo_stop = cp_close,
1840 .ndo_validate_addr = eth_validate_addr,
c048aaf4 1841 .ndo_set_mac_address = cp_set_mac_address,
48dfcde4
SH		 1842 .ndo_set_multicast_list = cp_set_rx_mode,
1843 .ndo_get_stats = cp_get_stats,
1844 .ndo_do_ioctl = cp_ioctl,
00829823 1845 .ndo_start_xmit = cp_start_xmit,
48dfcde4
SH		 1846 .ndo_tx_timeout = cp_tx_timeout,
1847#if CP_VLAN_TAG_USED
1848 .ndo_vlan_rx_register = cp_vlan_rx_register,
1849#endif
1850#ifdef BROKEN
1851 .ndo_change_mtu = cp_change_mtu,
1852#endif
fe96aaa1 1853
48dfcde4
SH		 1854#ifdef CONFIG_NET_POLL_CONTROLLER
1855 .ndo_poll_controller = cp_poll_controller,
1856#endif
1857};
1858
1da177e4
LT		 1859static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1860{
1861 struct net_device *dev;
1862 struct cp_private *cp;
1863 int rc;
1864 void __iomem *regs;
2427ddd8 1865 resource_size_t pciaddr;
1da177e4 1866 unsigned int addr_len, i, pci_using_dac;
1da177e4
LT		 1867
1868#ifndef MODULE
1869 static int version_printed;
1870 if (version_printed++ == 0)
b93d5847 1871 pr_info("%s", version);
1da177e4
LT		 1872#endif
1873
1da177e4 1874 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
44c10138 1875 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
de4549ca
SH		 1876 dev_info(&pdev->dev,
1877 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
44c10138 1878 pdev->vendor, pdev->device, pdev->revision);
1da177e4
LT		 1879 return -ENODEV;
1880 }
1881
1882 dev = alloc_etherdev(sizeof(struct cp_private));
1883 if (!dev)
1884 return -ENOMEM;
1da177e4
LT		 1885 SET_NETDEV_DEV(dev, &pdev->dev);
1886
1887 cp = netdev_priv(dev);
1888 cp->pdev = pdev;
1889 cp->dev = dev;
1890 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1891 spin_lock_init (&cp->lock);
1892 cp->mii_if.dev = dev;
1893 cp->mii_if.mdio_read = mdio_read;
1894 cp->mii_if.mdio_write = mdio_write;
1895 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1896 cp->mii_if.phy_id_mask = 0x1f;
1897 cp->mii_if.reg_num_mask = 0x1f;
1898 cp_set_rxbufsize(cp);
1899
1900 rc = pci_enable_device(pdev);
1901 if (rc)
1902 goto err_out_free;
1903
1904 rc = pci_set_mwi(pdev);
1905 if (rc)
1906 goto err_out_disable;
1907
1908 rc = pci_request_regions(pdev, DRV_NAME);
1909 if (rc)
1910 goto err_out_mwi;
1911
1912 pciaddr = pci_resource_start(pdev, 1);
1913 if (!pciaddr) {
1914 rc = -EIO;
9b91cf9d 1915 dev_err(&pdev->dev, "no MMIO resource\n");
1da177e4
LT		 1916 goto err_out_res;
1917 }
1918 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1919 rc = -EIO;
9b91cf9d 1920 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
2e8a538d 1921 (unsigned long long)pci_resource_len(pdev, 1));
1da177e4
LT		 1922 goto err_out_res;
1923 }
1924
1925 /* Configure DMA attributes. */
1926 if ((sizeof(dma_addr_t) > 4) &&
6a35528a
YH		 1927 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1928 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4
LT		 1929 pci_using_dac = 1;
1930 } else {
1931 pci_using_dac = 0;
1932
284901a9 1933 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 1934 if (rc) {
9b91cf9d 1935 dev_err(&pdev->dev,
2e8a538d 1936 "No usable DMA configuration, aborting.\n");
1da177e4
LT		 1937 goto err_out_res;
1938 }
284901a9 1939 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 1940 if (rc) {
9b91cf9d 1941 dev_err(&pdev->dev,
2e8a538d
JG		 1942 "No usable consistent DMA configuration, "
1943 "aborting.\n");
1da177e4
LT		 1944 goto err_out_res;
1945 }
1946 }
1947
1948 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1949 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1950
1951 regs = ioremap(pciaddr, CP_REGS_SIZE);
1952 if (!regs) {
1953 rc = -EIO;
4626dd46 1954 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
2e8a538d
JG		 1955 (unsigned long long)pci_resource_len(pdev, 1),
1956 (unsigned long long)pciaddr);
1da177e4
LT		 1957 goto err_out_res;
1958 }
1959 dev->base_addr = (unsigned long) regs;
1960 cp->regs = regs;
1961
1962 cp_stop_hw(cp);
1963
1964 /* read MAC address from EEPROM */
1965 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1966 for (i = 0; i < 3; i++)
03233b90
AV		 1967 ((__le16 *) (dev->dev_addr))[i] =
1968 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
bb0ce608 1969 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 1970
48dfcde4 1971 dev->netdev_ops = &cp_netdev_ops;
bea3348e 1972 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1da177e4 1973 dev->ethtool_ops = &cp_ethtool_ops;
1da177e4 1974 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4
LT		 1975
1976#if CP_VLAN_TAG_USED
1977 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 1978#endif
1979
1980 if (pci_using_dac)
1981 dev->features |= NETIF_F_HIGHDMA;
1982
fcec3456
JG		 1983#if 0 /* disabled by default until verified */
1984 dev->features |= NETIF_F_TSO;
1985#endif
1986
1da177e4
LT		 1987 dev->irq = pdev->irq;
1988
1989 rc = register_netdev(dev);
1990 if (rc)
1991 goto err_out_iomap;
1992
b93d5847 1993 pr_info("%s: RTL-8139C+ at 0x%lx, %pM, IRQ %d\n",
1da177e4
LT		 1994 dev->name,
1995 dev->base_addr,
e174961c 1996 dev->dev_addr,
1da177e4
LT		 1997 dev->irq);
1998
1999 pci_set_drvdata(pdev, dev);
2000
2001 /* enable busmastering and memory-write-invalidate */
2002 pci_set_master(pdev);
2003
2e8a538d
JG		 2004 if (cp->wol_enabled)
2005 cp_set_d3_state (cp);
1da177e4
LT		 2006
2007 return 0;
2008
2009err_out_iomap:
2010 iounmap(regs);
2011err_out_res:
2012 pci_release_regions(pdev);
2013err_out_mwi:
2014 pci_clear_mwi(pdev);
2015err_out_disable:
2016 pci_disable_device(pdev);
2017err_out_free:
2018 free_netdev(dev);
2019 return rc;
2020}
2021
2022static void cp_remove_one (struct pci_dev *pdev)
2023{
2024 struct net_device *dev = pci_get_drvdata(pdev);
2025 struct cp_private *cp = netdev_priv(dev);
2026
1da177e4
LT		 2027 unregister_netdev(dev);
2028 iounmap(cp->regs);
2e8a538d
JG		 2029 if (cp->wol_enabled)
2030 pci_set_power_state (pdev, PCI_D0);
1da177e4
LT		 2031 pci_release_regions(pdev);
2032 pci_clear_mwi(pdev);
2033 pci_disable_device(pdev);
2034 pci_set_drvdata(pdev, NULL);
2035 free_netdev(dev);
2036}
2037
2038#ifdef CONFIG_PM
05adc3b7 2039static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4 2040{
7668a494
FR		 2041 struct net_device *dev = pci_get_drvdata(pdev);
2042 struct cp_private *cp = netdev_priv(dev);
1da177e4
LT		 2043 unsigned long flags;
2044
7668a494
FR		 2045 if (!netif_running(dev))
2046 return 0;
1da177e4
LT		 2047
2048 netif_device_detach (dev);
2049 netif_stop_queue (dev);
2050
2051 spin_lock_irqsave (&cp->lock, flags);
2052
2053 /* Disable Rx and Tx */
2054 cpw16 (IntrMask, 0);
2055 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2056
2057 spin_unlock_irqrestore (&cp->lock, flags);
2058
576cfa93
FR		 2059 pci_save_state(pdev);
2060 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2061 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 2062
2063 return 0;
2064}
2065
2066static int cp_resume (struct pci_dev *pdev)
2067{
576cfa93
FR		 2068 struct net_device *dev = pci_get_drvdata (pdev);
2069 struct cp_private *cp = netdev_priv(dev);
a4cf0761 2070 unsigned long flags;
1da177e4 2071
576cfa93
FR		 2072 if (!netif_running(dev))
2073 return 0;
1da177e4
LT		 2074
2075 netif_device_attach (dev);
576cfa93
FR		 2076
2077 pci_set_power_state(pdev, PCI_D0);
2078 pci_restore_state(pdev);
2079 pci_enable_wake(pdev, PCI_D0, 0);
2080
2081 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2082 cp_init_rings_index (cp);
1da177e4
LT		 2083 cp_init_hw (cp);
2084 netif_start_queue (dev);
a4cf0761
PO		 2085
2086 spin_lock_irqsave (&cp->lock, flags);
2087
2501f843 2088 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
a4cf0761
PO		 2089
2090 spin_unlock_irqrestore (&cp->lock, flags);
f3b197ac 2091
1da177e4
LT		 2092 return 0;
2093}
2094#endif /* CONFIG_PM */
2095
2096static struct pci_driver cp_driver = {
2097 .name = DRV_NAME,
2098 .id_table = cp_pci_tbl,
2099 .probe = cp_init_one,
2100 .remove = cp_remove_one,
2101#ifdef CONFIG_PM
2102 .resume = cp_resume,
2103 .suspend = cp_suspend,
2104#endif
2105};
2106
2107static int __init cp_init (void)
2108{
2109#ifdef MODULE
b93d5847 2110 pr_info("%s", version);
1da177e4 2111#endif
29917620 2112 return pci_register_driver(&cp_driver);
1da177e4
LT		 2113}
2114
2115static void __exit cp_exit (void)
2116{
2117 pci_unregister_driver (&cp_driver);
2118}
2119
2120module_init(cp_init);
2121module_exit(cp_exit);
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