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amd64_edac: misc small cleanups
[linux.git] / drivers / serial / crisv10.c
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77accbf5 1/*
1da177e4
LT		 2 * Serial port driver for the ETRAX 100LX chip
3 *
77accbf5 4 * Copyright (C) 1998-2007 Axis Communications AB
1da177e4
LT		 5 *
6 * Many, many authors. Based once upon a time on serial.c for 16x50.
7 *
1da177e4
LT		 8 */
9
10static char *serial_version = "$Revision: 1.25 $";
11
1da177e4
LT		 12#include <linux/types.h>
13#include <linux/errno.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/timer.h>
17#include <linux/interrupt.h>
18#include <linux/tty.h>
19#include <linux/tty_flip.h>
20#include <linux/major.h>
21#include <linux/string.h>
22#include <linux/fcntl.h>
23#include <linux/mm.h>
24#include <linux/slab.h>
25#include <linux/init.h>
1da177e4 26#include <linux/kernel.h>
f392ecfa 27#include <linux/mutex.h>
1977f032 28#include <linux/bitops.h>
9e040a3e
JN		 29#include <linux/seq_file.h>
30#include <linux/delay.h>
31#include <linux/module.h>
32#include <linux/uaccess.h>
33#include <linux/io.h>
1da177e4 34
1da177e4 35#include <asm/irq.h>
77accbf5 36#include <asm/dma.h>
1da177e4 37#include <asm/system.h>
1da177e4 38
556dcee7 39#include <arch/svinto.h>
1da177e4
LT		 40
41/* non-arch dependent serial structures are in linux/serial.h */
42#include <linux/serial.h>
43/* while we keep our own stuff (struct e100_serial) in a local .h file */
77accbf5 44#include "crisv10.h"
1da177e4 45#include <asm/fasttimer.h>
556dcee7 46#include <arch/io_interface_mux.h>
1da177e4
LT		 47
48#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
49#ifndef CONFIG_ETRAX_FAST_TIMER
50#error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
51#endif
52#endif
53
54#if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
55 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
56#error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
57#endif
58
59#if defined(CONFIG_ETRAX_RS485_ON_PA) && defined(CONFIG_ETRAX_RS485_ON_PORT_G)
60#error "Disable either CONFIG_ETRAX_RS485_ON_PA or CONFIG_ETRAX_RS485_ON_PORT_G"
61#endif
62
63/*
64 * All of the compatibilty code so we can compile serial.c against
65 * older kernels is hidden in serial_compat.h
66 */
67#if defined(LOCAL_HEADERS)
68#include "serial_compat.h"
69#endif
70
1da177e4
LT		 71struct tty_driver *serial_driver;
72
1da177e4
LT		 73/* number of characters left in xmit buffer before we ask for more */
74#define WAKEUP_CHARS 256
75
76//#define SERIAL_DEBUG_INTR
77//#define SERIAL_DEBUG_OPEN
78//#define SERIAL_DEBUG_FLOW
79//#define SERIAL_DEBUG_DATA
80//#define SERIAL_DEBUG_THROTTLE
81//#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
82//#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
83
84/* Enable this to use serial interrupts to handle when you
85 expect the first received event on the serial port to
86 be an error, break or similar. Used to be able to flash IRMA
87 from eLinux */
88#define SERIAL_HANDLE_EARLY_ERRORS
89
1da177e4
LT		 90/* Currently 16 descriptors x 128 bytes = 2048 bytes */
91#define SERIAL_DESCR_BUF_SIZE 256
92
93#define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
94#define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
95
96/* We don't want to load the system with massive fast timer interrupt
97 * on high baudrates so limit it to 250 us (4kHz) */
98#define MIN_FLUSH_TIME_USEC 250
99
100/* Add an x here to log a lot of timer stuff */
101#define TIMERD(x)
102/* Debug details of interrupt handling */
103#define DINTR1(x) /* irq on/off, errors */
104#define DINTR2(x) /* tx and rx */
105/* Debug flip buffer stuff */
106#define DFLIP(x)
107/* Debug flow control and overview of data flow */
108#define DFLOW(x)
109#define DBAUD(x)
110#define DLOG_INT_TRIG(x)
111
112//#define DEBUG_LOG_INCLUDED
113#ifndef DEBUG_LOG_INCLUDED
114#define DEBUG_LOG(line, string, value)
115#else
116struct debug_log_info
117{
118 unsigned long time;
119 unsigned long timer_data;
120// int line;
121 const char *string;
122 int value;
123};
124#define DEBUG_LOG_SIZE 4096
125
126struct debug_log_info debug_log[DEBUG_LOG_SIZE];
127int debug_log_pos = 0;
128
129#define DEBUG_LOG(_line, _string, _value) do { \
130 if ((_line) == SERIAL_DEBUG_LINE) {\
131 debug_log_func(_line, _string, _value); \
132 }\
133}while(0)
134
135void debug_log_func(int line, const char *string, int value)
136{
137 if (debug_log_pos < DEBUG_LOG_SIZE) {
138 debug_log[debug_log_pos].time = jiffies;
139 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
140// debug_log[debug_log_pos].line = line;
141 debug_log[debug_log_pos].string = string;
142 debug_log[debug_log_pos].value = value;
143 debug_log_pos++;
144 }
145 /*printk(string, value);*/
146}
147#endif
148
149#ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
150/* Default number of timer ticks before flushing rx fifo
151 * When using "little data, low latency applications: use 0
152 * When using "much data applications (PPP)" use ~5
153 */
154#define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
155#endif
156
157unsigned long timer_data_to_ns(unsigned long timer_data);
158
159static void change_speed(struct e100_serial *info);
160static void rs_throttle(struct tty_struct * tty);
161static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
77accbf5
JN		 162static int rs_write(struct tty_struct *tty,
163 const unsigned char *buf, int count);
1da177e4 164#ifdef CONFIG_ETRAX_RS485
77accbf5
JN		 165static int e100_write_rs485(struct tty_struct *tty,
166 const unsigned char *buf, int count);
1da177e4 167#endif
77accbf5 168static int get_lsr_info(struct e100_serial *info, unsigned int *value);
1da177e4
LT		 169
170
171#define DEF_BAUD 115200 /* 115.2 kbit/s */
172#define STD_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
173#define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
174/* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
175#define DEF_TX 0x80 /* or SERIAL_CTRL_B */
176
177/* offsets from R_SERIALx_CTRL */
178
179#define REG_DATA 0
180#define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
181#define REG_TR_DATA 0
182#define REG_STATUS 1
183#define REG_TR_CTRL 1
184#define REG_REC_CTRL 2
185#define REG_BAUD 3
186#define REG_XOFF 4 /* this is a 32 bit register */
187
188/* The bitfields are the same for all serial ports */
189#define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
190#define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
191#define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
192#define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
193#define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
194
195#define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
196
197/* Values for info->errorcode */
198#define ERRCODE_SET_BREAK (TTY_BREAK)
199#define ERRCODE_INSERT 0x100
200#define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
201
202#define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
203
204/*
205 * General note regarding the use of IO_* macros in this file:
206 *
207 * We will use the bits defined for DMA channel 6 when using various
208 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
209 * the same for all channels (which of course they are).
210 *
211 * We will also use the bits defined for serial port 0 when writing commands
212 * to the different ports, as these bits too are the same for all ports.
213 */
214
215
216/* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
217static const unsigned long e100_ser_int_mask = 0
218#ifdef CONFIG_ETRAX_SERIAL_PORT0
219| IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
220#endif
221#ifdef CONFIG_ETRAX_SERIAL_PORT1
222| IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
223#endif
224#ifdef CONFIG_ETRAX_SERIAL_PORT2
225| IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
226#endif
227#ifdef CONFIG_ETRAX_SERIAL_PORT3
228| IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
229#endif
230;
231unsigned long r_alt_ser_baudrate_shadow = 0;
232
233/* this is the data for the four serial ports in the etrax100 */
234/* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
235/* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
236
237static struct e100_serial rs_table[] = {
238 { .baud = DEF_BAUD,
d7283353 239 .ioport = (unsigned char *)R_SERIAL0_CTRL,
1da177e4
LT		 240 .irq = 1U << 12, /* uses DMA 6 and 7 */
241 .oclrintradr = R_DMA_CH6_CLR_INTR,
242 .ofirstadr = R_DMA_CH6_FIRST,
243 .ocmdadr = R_DMA_CH6_CMD,
244 .ostatusadr = R_DMA_CH6_STATUS,
245 .iclrintradr = R_DMA_CH7_CLR_INTR,
246 .ifirstadr = R_DMA_CH7_FIRST,
247 .icmdadr = R_DMA_CH7_CMD,
248 .idescradr = R_DMA_CH7_DESCR,
249 .flags = STD_FLAGS,
250 .rx_ctrl = DEF_RX,
251 .tx_ctrl = DEF_TX,
252 .iseteop = 2,
77accbf5
JN		 253 .dma_owner = dma_ser0,
254 .io_if = if_serial_0,
1da177e4
LT		 255#ifdef CONFIG_ETRAX_SERIAL_PORT0
256 .enabled = 1,
257#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
258 .dma_out_enabled = 1,
77accbf5
JN		 259 .dma_out_nbr = SER0_TX_DMA_NBR,
260 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
261 .dma_out_irq_flags = IRQF_DISABLED,
262 .dma_out_irq_description = "serial 0 dma tr",
1da177e4
LT		 263#else
264 .dma_out_enabled = 0,
77accbf5
JN		 265 .dma_out_nbr = UINT_MAX,
266 .dma_out_irq_nbr = 0,
267 .dma_out_irq_flags = 0,
268 .dma_out_irq_description = NULL,
1da177e4
LT		 269#endif
270#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
271 .dma_in_enabled = 1,
77accbf5
JN		 272 .dma_in_nbr = SER0_RX_DMA_NBR,
273 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
274 .dma_in_irq_flags = IRQF_DISABLED,
275 .dma_in_irq_description = "serial 0 dma rec",
1da177e4 276#else
77accbf5
JN		 277 .dma_in_enabled = 0,
278 .dma_in_nbr = UINT_MAX,
279 .dma_in_irq_nbr = 0,
280 .dma_in_irq_flags = 0,
281 .dma_in_irq_description = NULL,
1da177e4
LT		 282#endif
283#else
284 .enabled = 0,
77accbf5 285 .io_if_description = NULL,
1da177e4
LT		 286 .dma_out_enabled = 0,
287 .dma_in_enabled = 0
288#endif
289
290}, /* ttyS0 */
291#ifndef CONFIG_SVINTO_SIM
292 { .baud = DEF_BAUD,
d7283353 293 .ioport = (unsigned char *)R_SERIAL1_CTRL,
1da177e4
LT		 294 .irq = 1U << 16, /* uses DMA 8 and 9 */
295 .oclrintradr = R_DMA_CH8_CLR_INTR,
296 .ofirstadr = R_DMA_CH8_FIRST,
297 .ocmdadr = R_DMA_CH8_CMD,
298 .ostatusadr = R_DMA_CH8_STATUS,
299 .iclrintradr = R_DMA_CH9_CLR_INTR,
300 .ifirstadr = R_DMA_CH9_FIRST,
301 .icmdadr = R_DMA_CH9_CMD,
302 .idescradr = R_DMA_CH9_DESCR,
303 .flags = STD_FLAGS,
304 .rx_ctrl = DEF_RX,
305 .tx_ctrl = DEF_TX,
306 .iseteop = 3,
77accbf5
JN		 307 .dma_owner = dma_ser1,
308 .io_if = if_serial_1,
1da177e4
LT		 309#ifdef CONFIG_ETRAX_SERIAL_PORT1
310 .enabled = 1,
77accbf5 311 .io_if_description = "ser1",
1da177e4
LT		 312#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
313 .dma_out_enabled = 1,
77accbf5
JN		 314 .dma_out_nbr = SER1_TX_DMA_NBR,
315 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
316 .dma_out_irq_flags = IRQF_DISABLED,
317 .dma_out_irq_description = "serial 1 dma tr",
1da177e4
LT		 318#else
319 .dma_out_enabled = 0,
77accbf5
JN		 320 .dma_out_nbr = UINT_MAX,
321 .dma_out_irq_nbr = 0,
322 .dma_out_irq_flags = 0,
323 .dma_out_irq_description = NULL,
1da177e4
LT		 324#endif
325#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
326 .dma_in_enabled = 1,
77accbf5
JN		 327 .dma_in_nbr = SER1_RX_DMA_NBR,
328 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
329 .dma_in_irq_flags = IRQF_DISABLED,
330 .dma_in_irq_description = "serial 1 dma rec",
1da177e4 331#else
77accbf5
JN		 332 .dma_in_enabled = 0,
333 .dma_in_enabled = 0,
334 .dma_in_nbr = UINT_MAX,
335 .dma_in_irq_nbr = 0,
336 .dma_in_irq_flags = 0,
337 .dma_in_irq_description = NULL,
1da177e4
LT		 338#endif
339#else
340 .enabled = 0,
77accbf5
JN		 341 .io_if_description = NULL,
342 .dma_in_irq_nbr = 0,
1da177e4
LT		 343 .dma_out_enabled = 0,
344 .dma_in_enabled = 0
345#endif
346}, /* ttyS1 */
347
348 { .baud = DEF_BAUD,
d7283353 349 .ioport = (unsigned char *)R_SERIAL2_CTRL,
1da177e4
LT		 350 .irq = 1U << 4, /* uses DMA 2 and 3 */
351 .oclrintradr = R_DMA_CH2_CLR_INTR,
352 .ofirstadr = R_DMA_CH2_FIRST,
353 .ocmdadr = R_DMA_CH2_CMD,
354 .ostatusadr = R_DMA_CH2_STATUS,
355 .iclrintradr = R_DMA_CH3_CLR_INTR,
356 .ifirstadr = R_DMA_CH3_FIRST,
357 .icmdadr = R_DMA_CH3_CMD,
358 .idescradr = R_DMA_CH3_DESCR,
359 .flags = STD_FLAGS,
360 .rx_ctrl = DEF_RX,
361 .tx_ctrl = DEF_TX,
362 .iseteop = 0,
77accbf5
JN		 363 .dma_owner = dma_ser2,
364 .io_if = if_serial_2,
1da177e4
LT		 365#ifdef CONFIG_ETRAX_SERIAL_PORT2
366 .enabled = 1,
77accbf5 367 .io_if_description = "ser2",
1da177e4
LT		 368#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
369 .dma_out_enabled = 1,
77accbf5
JN		 370 .dma_out_nbr = SER2_TX_DMA_NBR,
371 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
372 .dma_out_irq_flags = IRQF_DISABLED,
373 .dma_out_irq_description = "serial 2 dma tr",
1da177e4
LT		 374#else
375 .dma_out_enabled = 0,
77accbf5
JN		 376 .dma_out_nbr = UINT_MAX,
377 .dma_out_irq_nbr = 0,
378 .dma_out_irq_flags = 0,
379 .dma_out_irq_description = NULL,
1da177e4
LT		 380#endif
381#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
382 .dma_in_enabled = 1,
77accbf5
JN		 383 .dma_in_nbr = SER2_RX_DMA_NBR,
384 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
385 .dma_in_irq_flags = IRQF_DISABLED,
386 .dma_in_irq_description = "serial 2 dma rec",
1da177e4 387#else
77accbf5
JN		 388 .dma_in_enabled = 0,
389 .dma_in_nbr = UINT_MAX,
390 .dma_in_irq_nbr = 0,
391 .dma_in_irq_flags = 0,
392 .dma_in_irq_description = NULL,
1da177e4
LT		 393#endif
394#else
395 .enabled = 0,
77accbf5 396 .io_if_description = NULL,
1da177e4
LT		 397 .dma_out_enabled = 0,
398 .dma_in_enabled = 0
399#endif
400 }, /* ttyS2 */
401
402 { .baud = DEF_BAUD,
d7283353 403 .ioport = (unsigned char *)R_SERIAL3_CTRL,
1da177e4
LT		 404 .irq = 1U << 8, /* uses DMA 4 and 5 */
405 .oclrintradr = R_DMA_CH4_CLR_INTR,
406 .ofirstadr = R_DMA_CH4_FIRST,
407 .ocmdadr = R_DMA_CH4_CMD,
408 .ostatusadr = R_DMA_CH4_STATUS,
409 .iclrintradr = R_DMA_CH5_CLR_INTR,
410 .ifirstadr = R_DMA_CH5_FIRST,
411 .icmdadr = R_DMA_CH5_CMD,
412 .idescradr = R_DMA_CH5_DESCR,
413 .flags = STD_FLAGS,
414 .rx_ctrl = DEF_RX,
415 .tx_ctrl = DEF_TX,
416 .iseteop = 1,
77accbf5
JN		 417 .dma_owner = dma_ser3,
418 .io_if = if_serial_3,
1da177e4
LT		 419#ifdef CONFIG_ETRAX_SERIAL_PORT3
420 .enabled = 1,
77accbf5 421 .io_if_description = "ser3",
1da177e4
LT		 422#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
423 .dma_out_enabled = 1,
77accbf5
JN		 424 .dma_out_nbr = SER3_TX_DMA_NBR,
425 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
426 .dma_out_irq_flags = IRQF_DISABLED,
427 .dma_out_irq_description = "serial 3 dma tr",
1da177e4
LT		 428#else
429 .dma_out_enabled = 0,
77accbf5
JN		 430 .dma_out_nbr = UINT_MAX,
431 .dma_out_irq_nbr = 0,
432 .dma_out_irq_flags = 0,
433 .dma_out_irq_description = NULL,
1da177e4
LT		 434#endif
435#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
436 .dma_in_enabled = 1,
77accbf5
JN		 437 .dma_in_nbr = SER3_RX_DMA_NBR,
438 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
439 .dma_in_irq_flags = IRQF_DISABLED,
440 .dma_in_irq_description = "serial 3 dma rec",
1da177e4 441#else
77accbf5
JN		 442 .dma_in_enabled = 0,
443 .dma_in_nbr = UINT_MAX,
444 .dma_in_irq_nbr = 0,
445 .dma_in_irq_flags = 0,
446 .dma_in_irq_description = NULL
1da177e4
LT		 447#endif
448#else
449 .enabled = 0,
77accbf5 450 .io_if_description = NULL,
1da177e4
LT		 451 .dma_out_enabled = 0,
452 .dma_in_enabled = 0
453#endif
454 } /* ttyS3 */
455#endif
456};
457
458
459#define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
460
1da177e4
LT		 461#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
462static struct fast_timer fast_timers[NR_PORTS];
463#endif
464
465#ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY
466#define PROCSTAT(x) x
467struct ser_statistics_type {
468 int overrun_cnt;
469 int early_errors_cnt;
470 int ser_ints_ok_cnt;
471 int errors_cnt;
472 unsigned long int processing_flip;
473 unsigned long processing_flip_still_room;
474 unsigned long int timeout_flush_cnt;
475 int rx_dma_ints;
476 int tx_dma_ints;
477 int rx_tot;
478 int tx_tot;
479};
480
481static struct ser_statistics_type ser_stat[NR_PORTS];
482
483#else
484
485#define PROCSTAT(x)
486
487#endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */
488
489/* RS-485 */
490#if defined(CONFIG_ETRAX_RS485)
491#ifdef CONFIG_ETRAX_FAST_TIMER
492static struct fast_timer fast_timers_rs485[NR_PORTS];
493#endif
494#if defined(CONFIG_ETRAX_RS485_ON_PA)
495static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
496#endif
497#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
498static int rs485_port_g_bit = CONFIG_ETRAX_RS485_ON_PORT_G_BIT;
499#endif
500#endif
501
502/* Info and macros needed for each ports extra control/status signals. */
503#define E100_STRUCT_PORT(line, pinname) \
504 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
505 (R_PORT_PA_DATA): ( \
506 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
507 (R_PORT_PB_DATA):&dummy_ser[line]))
508
509#define E100_STRUCT_SHADOW(line, pinname) \
510 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
511 (&port_pa_data_shadow): ( \
512 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
513 (&port_pb_data_shadow):&dummy_ser[line]))
514#define E100_STRUCT_MASK(line, pinname) \
515 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
516 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
517 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
518 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
519
520#define DUMMY_DTR_MASK 1
521#define DUMMY_RI_MASK 2
522#define DUMMY_DSR_MASK 4
523#define DUMMY_CD_MASK 8
524static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
525
526/* If not all status pins are used or disabled, use mixed mode */
527#ifdef CONFIG_ETRAX_SERIAL_PORT0
528
529#define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
530
531#if SER0_PA_BITSUM != -4
532# if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
533# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
534# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
535# endif
536# endif
537# if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
538# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
539# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
540# endif
541# endif
542# if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
543# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
544# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
545# endif
546# endif
547# if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
548# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
549# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
550# endif
551# endif
552#endif
553
554#define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
555
556#if SER0_PB_BITSUM != -4
557# if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
558# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
559# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
560# endif
561# endif
562# if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
563# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
564# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
565# endif
566# endif
567# if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
568# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
569# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
570# endif
571# endif
572# if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
573# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
574# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
575# endif
576# endif
577#endif
578
579#endif /* PORT0 */
580
581
582#ifdef CONFIG_ETRAX_SERIAL_PORT1
583
584#define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
585
586#if SER1_PA_BITSUM != -4
587# if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
588# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
589# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
590# endif
591# endif
592# if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
593# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
594# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
595# endif
596# endif
597# if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
598# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
599# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
600# endif
601# endif
602# if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
603# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
604# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
605# endif
606# endif
607#endif
608
609#define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
610
611#if SER1_PB_BITSUM != -4
612# if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
613# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
614# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
615# endif
616# endif
617# if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
618# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
619# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
620# endif
621# endif
622# if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
623# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
624# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
625# endif
626# endif
627# if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
628# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
629# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
630# endif
631# endif
632#endif
633
634#endif /* PORT1 */
635
636#ifdef CONFIG_ETRAX_SERIAL_PORT2
637
638#define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
639
640#if SER2_PA_BITSUM != -4
641# if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
642# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
643# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
644# endif
645# endif
646# if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
647# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
648# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
649# endif
650# endif
651# if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
652# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
653# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
654# endif
655# endif
656# if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
657# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
658# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
659# endif
660# endif
661#endif
662
663#define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
664
665#if SER2_PB_BITSUM != -4
666# if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
667# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
668# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
669# endif
670# endif
671# if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
672# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
673# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
674# endif
675# endif
676# if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
677# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
678# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
679# endif
680# endif
681# if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
682# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
683# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
684# endif
685# endif
686#endif
687
688#endif /* PORT2 */
689
690#ifdef CONFIG_ETRAX_SERIAL_PORT3
691
692#define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
693
694#if SER3_PA_BITSUM != -4
695# if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
696# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
697# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
698# endif
699# endif
700# if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
701# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
702# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
703# endif
704# endif
705# if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
706# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
707# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
708# endif
709# endif
710# if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
711# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
712# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
713# endif
714# endif
715#endif
716
717#define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
718
719#if SER3_PB_BITSUM != -4
720# if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
721# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
722# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
723# endif
724# endif
725# if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
726# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
727# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
728# endif
729# endif
730# if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
731# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
732# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
733# endif
734# endif
735# if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
736# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
737# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
738# endif
739# endif
740#endif
741
742#endif /* PORT3 */
743
744
745#if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
746 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
747 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
748 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
749#define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
750#endif
751
752#ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
753/* The pins can be mixed on PA and PB */
754#define CONTROL_PINS_PORT_NOT_USED(line) \
755 &dummy_ser[line], &dummy_ser[line], \
756 &dummy_ser[line], &dummy_ser[line], \
757 &dummy_ser[line], &dummy_ser[line], \
758 &dummy_ser[line], &dummy_ser[line], \
759 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
760
761
762struct control_pins
763{
764 volatile unsigned char *dtr_port;
765 unsigned char *dtr_shadow;
766 volatile unsigned char *ri_port;
767 unsigned char *ri_shadow;
768 volatile unsigned char *dsr_port;
769 unsigned char *dsr_shadow;
770 volatile unsigned char *cd_port;
771 unsigned char *cd_shadow;
772
773 unsigned char dtr_mask;
774 unsigned char ri_mask;
775 unsigned char dsr_mask;
776 unsigned char cd_mask;
777};
778
779static const struct control_pins e100_modem_pins[NR_PORTS] =
780{
781 /* Ser 0 */
782 {
783#ifdef CONFIG_ETRAX_SERIAL_PORT0
784 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
785 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
786 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
787 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
788 E100_STRUCT_MASK(0,DTR),
789 E100_STRUCT_MASK(0,RI),
790 E100_STRUCT_MASK(0,DSR),
791 E100_STRUCT_MASK(0,CD)
792#else
793 CONTROL_PINS_PORT_NOT_USED(0)
794#endif
795 },
796
797 /* Ser 1 */
798 {
799#ifdef CONFIG_ETRAX_SERIAL_PORT1
800 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
801 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
802 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
803 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
804 E100_STRUCT_MASK(1,DTR),
805 E100_STRUCT_MASK(1,RI),
806 E100_STRUCT_MASK(1,DSR),
807 E100_STRUCT_MASK(1,CD)
808#else
809 CONTROL_PINS_PORT_NOT_USED(1)
810#endif
811 },
812
813 /* Ser 2 */
814 {
815#ifdef CONFIG_ETRAX_SERIAL_PORT2
816 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
817 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
818 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
819 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
820 E100_STRUCT_MASK(2,DTR),
821 E100_STRUCT_MASK(2,RI),
822 E100_STRUCT_MASK(2,DSR),
823 E100_STRUCT_MASK(2,CD)
824#else
825 CONTROL_PINS_PORT_NOT_USED(2)
826#endif
827 },
828
829 /* Ser 3 */
830 {
831#ifdef CONFIG_ETRAX_SERIAL_PORT3
832 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
833 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
834 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
835 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
836 E100_STRUCT_MASK(3,DTR),
837 E100_STRUCT_MASK(3,RI),
838 E100_STRUCT_MASK(3,DSR),
839 E100_STRUCT_MASK(3,CD)
840#else
841 CONTROL_PINS_PORT_NOT_USED(3)
842#endif
843 }
844};
845#else /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
846
847/* All pins are on either PA or PB for each serial port */
848#define CONTROL_PINS_PORT_NOT_USED(line) \
849 &dummy_ser[line], &dummy_ser[line], \
850 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
851
852
853struct control_pins
854{
855 volatile unsigned char *port;
856 unsigned char *shadow;
857
858 unsigned char dtr_mask;
859 unsigned char ri_mask;
860 unsigned char dsr_mask;
861 unsigned char cd_mask;
862};
863
864#define dtr_port port
865#define dtr_shadow shadow
866#define ri_port port
867#define ri_shadow shadow
868#define dsr_port port
869#define dsr_shadow shadow
870#define cd_port port
871#define cd_shadow shadow
872
873static const struct control_pins e100_modem_pins[NR_PORTS] =
874{
875 /* Ser 0 */
876 {
877#ifdef CONFIG_ETRAX_SERIAL_PORT0
878 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
879 E100_STRUCT_MASK(0,DTR),
880 E100_STRUCT_MASK(0,RI),
881 E100_STRUCT_MASK(0,DSR),
882 E100_STRUCT_MASK(0,CD)
883#else
884 CONTROL_PINS_PORT_NOT_USED(0)
885#endif
886 },
887
888 /* Ser 1 */
889 {
890#ifdef CONFIG_ETRAX_SERIAL_PORT1
891 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
892 E100_STRUCT_MASK(1,DTR),
893 E100_STRUCT_MASK(1,RI),
894 E100_STRUCT_MASK(1,DSR),
895 E100_STRUCT_MASK(1,CD)
896#else
897 CONTROL_PINS_PORT_NOT_USED(1)
898#endif
899 },
900
901 /* Ser 2 */
902 {
903#ifdef CONFIG_ETRAX_SERIAL_PORT2
904 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
905 E100_STRUCT_MASK(2,DTR),
906 E100_STRUCT_MASK(2,RI),
907 E100_STRUCT_MASK(2,DSR),
908 E100_STRUCT_MASK(2,CD)
909#else
910 CONTROL_PINS_PORT_NOT_USED(2)
911#endif
912 },
913
914 /* Ser 3 */
915 {
916#ifdef CONFIG_ETRAX_SERIAL_PORT3
917 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
918 E100_STRUCT_MASK(3,DTR),
919 E100_STRUCT_MASK(3,RI),
920 E100_STRUCT_MASK(3,DSR),
921 E100_STRUCT_MASK(3,CD)
922#else
923 CONTROL_PINS_PORT_NOT_USED(3)
924#endif
925 }
926};
927#endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
928
929#define E100_RTS_MASK 0x20
930#define E100_CTS_MASK 0x40
931
932/* All serial port signals are active low:
933 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
934 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
935 *
936 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
937 */
938
939/* Output */
940#define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
941/* Input */
d7283353 942#define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK)
1da177e4
LT		 943
944/* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
945/* Is an output */
946#define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
947
948/* Normally inputs */
949#define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
950#define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
951
952/* Input */
953#define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
954
955
956/*
957 * tmp_buf is used as a temporary buffer by serial_write. We need to
958 * lock it in case the memcpy_fromfs blocks while swapping in a page,
959 * and some other program tries to do a serial write at the same time.
960 * Since the lock will only come under contention when the system is
961 * swapping and available memory is low, it makes sense to share one
962 * buffer across all the serial ports, since it significantly saves
963 * memory if large numbers of serial ports are open.
964 */
965static unsigned char *tmp_buf;
f392ecfa 966static DEFINE_MUTEX(tmp_buf_mutex);
1da177e4
LT		 967
968/* Calculate the chartime depending on baudrate, numbor of bits etc. */
969static void update_char_time(struct e100_serial * info)
970{
a88487c7 971 tcflag_t cflags = info->port.tty->termios->c_cflag;
1da177e4
LT		 972 int bits;
973
974 /* calc. number of bits / data byte */
975 /* databits + startbit and 1 stopbit */
976 if ((cflags & CSIZE) == CS7)
977 bits = 9;
978 else
979 bits = 10;
980
981 if (cflags & CSTOPB) /* 2 stopbits ? */
982 bits++;
983
984 if (cflags & PARENB) /* parity bit ? */
985 bits++;
986
987 /* calc timeout */
988 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
989 info->flush_time_usec = 4*info->char_time_usec;
990 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
991 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
992
993}
994
995/*
996 * This function maps from the Bxxxx defines in asm/termbits.h into real
997 * baud rates.
998 */
999
1000static int
1001cflag_to_baud(unsigned int cflag)
1002{
1003 static int baud_table[] = {
1004 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
1005 4800, 9600, 19200, 38400 };
1006
1007 static int ext_baud_table[] = {
1008 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
1009 0, 0, 0, 0, 0, 0, 0, 0 };
1010
1011 if (cflag & CBAUDEX)
1012 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1013 else
1014 return baud_table[cflag & CBAUD];
1015}
1016
1017/* and this maps to an etrax100 hardware baud constant */
1018
1019static unsigned char
1020cflag_to_etrax_baud(unsigned int cflag)
1021{
1022 char retval;
1023
1024 static char baud_table[] = {
1025 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
1026
1027 static char ext_baud_table[] = {
1028 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
1029
1030 if (cflag & CBAUDEX)
1031 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1032 else
1033 retval = baud_table[cflag & CBAUD];
1034
1035 if (retval < 0) {
1036 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
1037 retval = 5; /* choose default 9600 instead */
1038 }
1039
1040 return retval | (retval << 4); /* choose same for both TX and RX */
1041}
1042
1043
1044/* Various static support functions */
1045
1046/* Functions to set or clear DTR/RTS on the requested line */
1047/* It is complicated by the fact that RTS is a serial port register, while
1048 * DTR might not be implemented in the HW at all, and if it is, it can be on
1049 * any general port.
1050 */
1051
1052
1053static inline void
1054e100_dtr(struct e100_serial *info, int set)
1055{
1056#ifndef CONFIG_SVINTO_SIM
1057 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1058
1059#ifdef SERIAL_DEBUG_IO
1060 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1061 printk("ser%i shadow before 0x%02X get: %i\n",
1062 info->line, *e100_modem_pins[info->line].dtr_shadow,
1063 E100_DTR_GET(info));
1064#endif
1065 /* DTR is active low */
1066 {
1067 unsigned long flags;
1068
77accbf5 1069 local_irq_save(flags);
1da177e4
LT		 1070 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1071 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1072 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
77accbf5 1073 local_irq_restore(flags);
1da177e4
LT		 1074 }
1075
1076#ifdef SERIAL_DEBUG_IO
1077 printk("ser%i shadow after 0x%02X get: %i\n",
1078 info->line, *e100_modem_pins[info->line].dtr_shadow,
1079 E100_DTR_GET(info));
1080#endif
1081#endif
1082}
1083
1084/* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1085 * 0=0V , 1=3.3V
1086 */
1087static inline void
1088e100_rts(struct e100_serial *info, int set)
1089{
1090#ifndef CONFIG_SVINTO_SIM
1091 unsigned long flags;
77accbf5 1092 local_irq_save(flags);
1da177e4
LT		 1093 info->rx_ctrl &= ~E100_RTS_MASK;
1094 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
d7283353 1095 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
77accbf5 1096 local_irq_restore(flags);
1da177e4
LT		 1097#ifdef SERIAL_DEBUG_IO
1098 printk("ser%i rts %i\n", info->line, set);
1099#endif
1100#endif
1101}
1102
1103
1104/* If this behaves as a modem, RI and CD is an output */
1105static inline void
1106e100_ri_out(struct e100_serial *info, int set)
1107{
1108#ifndef CONFIG_SVINTO_SIM
1109 /* RI is active low */
1110 {
1111 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1112 unsigned long flags;
1113
77accbf5 1114 local_irq_save(flags);
1da177e4
LT		 1115 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1116 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1117 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
77accbf5 1118 local_irq_restore(flags);
1da177e4
LT		 1119 }
1120#endif
1121}
1122static inline void
1123e100_cd_out(struct e100_serial *info, int set)
1124{
1125#ifndef CONFIG_SVINTO_SIM
1126 /* CD is active low */
1127 {
1128 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1129 unsigned long flags;
1130
77accbf5 1131 local_irq_save(flags);
1da177e4
LT		 1132 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1133 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1134 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
77accbf5 1135 local_irq_restore(flags);
1da177e4
LT		 1136 }
1137#endif
1138}
1139
1140static inline void
1141e100_disable_rx(struct e100_serial *info)
1142{
1143#ifndef CONFIG_SVINTO_SIM
1144 /* disable the receiver */
d7283353 1145 info->ioport[REG_REC_CTRL] =
1da177e4
LT		 1146 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1147#endif
1148}
1149
1150static inline void
1151e100_enable_rx(struct e100_serial *info)
1152{
1153#ifndef CONFIG_SVINTO_SIM
1154 /* enable the receiver */
d7283353 1155 info->ioport[REG_REC_CTRL] =
1da177e4
LT		 1156 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1157#endif
1158}
1159
1160/* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1161
1162static inline void
1163e100_disable_rxdma_irq(struct e100_serial *info)
1164{
1165#ifdef SERIAL_DEBUG_INTR
1166 printk("rxdma_irq(%d): 0\n",info->line);
1167#endif
1168 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1169 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1170}
1171
1172static inline void
1173e100_enable_rxdma_irq(struct e100_serial *info)
1174{
1175#ifdef SERIAL_DEBUG_INTR
1176 printk("rxdma_irq(%d): 1\n",info->line);
1177#endif
1178 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1179 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1180}
1181
1182/* the tx DMA uses only dma_descr interrupt */
1183
41c28ff1 1184static void e100_disable_txdma_irq(struct e100_serial *info)
1da177e4
LT		 1185{
1186#ifdef SERIAL_DEBUG_INTR
1187 printk("txdma_irq(%d): 0\n",info->line);
1188#endif
1189 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1190 *R_IRQ_MASK2_CLR = info->irq;
1191}
1192
41c28ff1 1193static void e100_enable_txdma_irq(struct e100_serial *info)
1da177e4
LT		 1194{
1195#ifdef SERIAL_DEBUG_INTR
1196 printk("txdma_irq(%d): 1\n",info->line);
1197#endif
1198 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1199 *R_IRQ_MASK2_SET = info->irq;
1200}
1201
41c28ff1 1202static void e100_disable_txdma_channel(struct e100_serial *info)
1da177e4
LT		 1203{
1204 unsigned long flags;
1205
1206 /* Disable output DMA channel for the serial port in question
025dfdaf 1207 * ( set to something other than serialX)
1da177e4 1208 */
77accbf5 1209 local_irq_save(flags);
1da177e4
LT		 1210 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1211 if (info->line == 0) {
1212 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1213 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1214 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1215 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1216 }
1217 } else if (info->line == 1) {
1218 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1219 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1220 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1221 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1222 }
1223 } else if (info->line == 2) {
1224 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1225 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1226 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1227 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1228 }
1229 } else if (info->line == 3) {
1230 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1231 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1232 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1233 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1234 }
1235 }
1236 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1237 local_irq_restore(flags);
1da177e4
LT		 1238}
1239
1240
41c28ff1 1241static void e100_enable_txdma_channel(struct e100_serial *info)
1da177e4
LT		 1242{
1243 unsigned long flags;
1244
77accbf5 1245 local_irq_save(flags);
1da177e4
LT		 1246 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1247 /* Enable output DMA channel for the serial port in question */
1248 if (info->line == 0) {
1249 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1250 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1251 } else if (info->line == 1) {
1252 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1253 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1254 } else if (info->line == 2) {
1255 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1256 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1257 } else if (info->line == 3) {
1258 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1259 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1260 }
1261 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1262 local_irq_restore(flags);
1da177e4
LT		 1263}
1264
41c28ff1 1265static void e100_disable_rxdma_channel(struct e100_serial *info)
1da177e4
LT		 1266{
1267 unsigned long flags;
1268
1269 /* Disable input DMA channel for the serial port in question
025dfdaf 1270 * ( set to something other than serialX)
1da177e4 1271 */
77accbf5 1272 local_irq_save(flags);
1da177e4
LT		 1273 if (info->line == 0) {
1274 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1275 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1276 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1277 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1278 }
1279 } else if (info->line == 1) {
1280 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1281 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1282 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1283 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1284 }
1285 } else if (info->line == 2) {
1286 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1287 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1288 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1289 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1290 }
1291 } else if (info->line == 3) {
1292 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1293 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1294 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1295 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1296 }
1297 }
1298 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1299 local_irq_restore(flags);
1da177e4
LT		 1300}
1301
1302
41c28ff1 1303static void e100_enable_rxdma_channel(struct e100_serial *info)
1da177e4
LT		 1304{
1305 unsigned long flags;
1306
77accbf5 1307 local_irq_save(flags);
1da177e4
LT		 1308 /* Enable input DMA channel for the serial port in question */
1309 if (info->line == 0) {
1310 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1311 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1312 } else if (info->line == 1) {
1313 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1314 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1315 } else if (info->line == 2) {
1316 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1317 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1318 } else if (info->line == 3) {
1319 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1320 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1321 }
1322 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1323 local_irq_restore(flags);
1da177e4
LT		 1324}
1325
1326#ifdef SERIAL_HANDLE_EARLY_ERRORS
1327/* in order to detect and fix errors on the first byte
1328 we have to use the serial interrupts as well. */
1329
1330static inline void
1331e100_disable_serial_data_irq(struct e100_serial *info)
1332{
1333#ifdef SERIAL_DEBUG_INTR
1334 printk("ser_irq(%d): 0\n",info->line);
1335#endif
1336 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1337 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1338}
1339
1340static inline void
1341e100_enable_serial_data_irq(struct e100_serial *info)
1342{
1343#ifdef SERIAL_DEBUG_INTR
1344 printk("ser_irq(%d): 1\n",info->line);
1345 printk("**** %d = %d\n",
1346 (8+2*info->line),
1347 (1U << (8+2*info->line)));
1348#endif
1349 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1350 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1351}
1352#endif
1353
1354static inline void
1355e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1356{
1357#ifdef SERIAL_DEBUG_INTR
1358 printk("ser_tx_irq(%d): 0\n",info->line);
1359#endif
1360 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1361 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1362}
1363
1364static inline void
1365e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1366{
1367#ifdef SERIAL_DEBUG_INTR
1368 printk("ser_tx_irq(%d): 1\n",info->line);
1369 printk("**** %d = %d\n",
1370 (8+1+2*info->line),
1371 (1U << (8+1+2*info->line)));
1372#endif
1373 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1374 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1375}
1376
1377static inline void e100_enable_rx_irq(struct e100_serial *info)
1378{
1379 if (info->uses_dma_in)
1380 e100_enable_rxdma_irq(info);
1381 else
1382 e100_enable_serial_data_irq(info);
1383}
1384static inline void e100_disable_rx_irq(struct e100_serial *info)
1385{
1386 if (info->uses_dma_in)
1387 e100_disable_rxdma_irq(info);
1388 else
1389 e100_disable_serial_data_irq(info);
1390}
1391
1392#if defined(CONFIG_ETRAX_RS485)
1393/* Enable RS-485 mode on selected port. This is UGLY. */
1394static int
6fd1af4c 1395e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r)
1da177e4
LT		 1396{
1397 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1398
1399#if defined(CONFIG_ETRAX_RS485_ON_PA)
1400 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1401#endif
1402#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
1403 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1404 rs485_port_g_bit, 1);
1405#endif
1406#if defined(CONFIG_ETRAX_RS485_LTC1387)
1407 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1408 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 1);
1409 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1410 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1);
1411#endif
1412
6fd1af4c 1413 info->rs485.flags = r->flags;
1da177e4
LT		 1414 if (r->delay_rts_before_send >= 1000)
1415 info->rs485.delay_rts_before_send = 1000;
1416 else
1417 info->rs485.delay_rts_before_send = r->delay_rts_before_send;
1da177e4
LT		 1418/* printk("rts: on send = %i, after = %i, enabled = %i",
1419 info->rs485.rts_on_send,
1420 info->rs485.rts_after_sent,
1421 info->rs485.enabled
1422 );
1423*/
1424 return 0;
1425}
1426
1427static int
77accbf5 1428e100_write_rs485(struct tty_struct *tty,
1da177e4
LT		 1429 const unsigned char *buf, int count)
1430{
1431 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
6fd1af4c 1432 int old_value = (info->rs485.flags) & SER_RS485_ENABLED;
1da177e4
LT		 1433
1434 /* rs485 is always implicitly enabled if we're using the ioctl()
6fd1af4c 1435 * but it doesn't have to be set in the serial_rs485
1da177e4
LT		 1436 * (to be backward compatible with old apps)
1437 * So we store, set and restore it.
1438 */
6fd1af4c 1439 info->rs485.flags |= SER_RS485_ENABLED;
1da177e4 1440 /* rs_write now deals with RS485 if enabled */
77accbf5 1441 count = rs_write(tty, buf, count);
6fd1af4c
CS		 1442 if (!old_value)
1443 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4
LT		 1444 return count;
1445}
1446
1447#ifdef CONFIG_ETRAX_FAST_TIMER
1448/* Timer function to toggle RTS when using FAST_TIMER */
1449static void rs485_toggle_rts_timer_function(unsigned long data)
1450{
1451 struct e100_serial *info = (struct e100_serial *)data;
1452
1453 fast_timers_rs485[info->line].function = NULL;
6fd1af4c 1454 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1da177e4
LT		 1455#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1456 e100_enable_rx(info);
1457 e100_enable_rx_irq(info);
1458#endif
1459}
1460#endif
1461#endif /* CONFIG_ETRAX_RS485 */
1462
1463/*
1464 * ------------------------------------------------------------
1465 * rs_stop() and rs_start()
1466 *
1467 * This routines are called before setting or resetting tty->stopped.
1468 * They enable or disable transmitter using the XOFF registers, as necessary.
1469 * ------------------------------------------------------------
1470 */
1471
1472static void
1473rs_stop(struct tty_struct *tty)
1474{
1475 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1476 if (info) {
1477 unsigned long flags;
1478 unsigned long xoff;
1479
77accbf5 1480 local_irq_save(flags);
1da177e4
LT		 1481 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1482 CIRC_CNT(info->xmit.head,
1483 info->xmit.tail,SERIAL_XMIT_SIZE)));
1484
a88487c7
TI		 1485 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char,
1486 STOP_CHAR(info->port.tty));
1da177e4
LT		 1487 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
1488 if (tty->termios->c_iflag & IXON ) {
1489 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1490 }
1491
d7283353 1492 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
77accbf5 1493 local_irq_restore(flags);
1da177e4
LT		 1494 }
1495}
1496
1497static void
1498rs_start(struct tty_struct *tty)
1499{
1500 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1501 if (info) {
1502 unsigned long flags;
1503 unsigned long xoff;
1504
77accbf5 1505 local_irq_save(flags);
1da177e4
LT		 1506 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1507 CIRC_CNT(info->xmit.head,
1508 info->xmit.tail,SERIAL_XMIT_SIZE)));
1509 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1510 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
1511 if (tty->termios->c_iflag & IXON ) {
1512 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1513 }
1514
d7283353 1515 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1da177e4
LT		 1516 if (!info->uses_dma_out &&
1517 info->xmit.head != info->xmit.tail && info->xmit.buf)
1518 e100_enable_serial_tx_ready_irq(info);
1519
77accbf5 1520 local_irq_restore(flags);
1da177e4
LT		 1521 }
1522}
1523
1524/*
1525 * ----------------------------------------------------------------------
1526 *
1527 * Here starts the interrupt handling routines. All of the following
1528 * subroutines are declared as inline and are folded into
1529 * rs_interrupt(). They were separated out for readability's sake.
1530 *
1531 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1532 * runs with interrupts turned off. People who may want to modify
1533 * rs_interrupt() should try to keep the interrupt handler as fast as
1534 * possible. After you are done making modifications, it is not a bad
1535 * idea to do:
1536 *
1537 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1538 *
1539 * and look at the resulting assemble code in serial.s.
1540 *
1541 * - Ted Ts'o ([email protected]), 7-Mar-93
1542 * -----------------------------------------------------------------------
1543 */
1544
1545/*
1546 * This routine is used by the interrupt handler to schedule
1547 * processing in the software interrupt portion of the driver.
1548 */
41c28ff1 1549static void rs_sched_event(struct e100_serial *info, int event)
1da177e4
LT		 1550{
1551 if (info->event & (1 << event))
1552 return;
1553 info->event |= 1 << event;
1554 schedule_work(&info->work);
1555}
1556
1557/* The output DMA channel is free - use it to send as many chars as possible
1558 * NOTES:
1559 * We don't pay attention to info->x_char, which means if the TTY wants to
1560 * use XON/XOFF it will set info->x_char but we won't send any X char!
1561 *
1562 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1563 * buffer containing the X char, and skip updating xmit. We'd also have to
1564 * check if the last sent char was the X char when we enter this function
1565 * the next time, to avoid updating xmit with the sent X value.
1566 */
1567
1568static void
1569transmit_chars_dma(struct e100_serial *info)
1570{
1571 unsigned int c, sentl;
1572 struct etrax_dma_descr *descr;
1573
1574#ifdef CONFIG_SVINTO_SIM
1575 /* This will output too little if tail is not 0 always since
1576 * we don't reloop to send the other part. Anyway this SHOULD be a
1577 * no-op - transmit_chars_dma would never really be called during sim
1578 * since rs_write does not write into the xmit buffer then.
1579 */
1580 if (info->xmit.tail)
1581 printk("Error in serial.c:transmit_chars-dma(), tail!=0\n");
1582 if (info->xmit.head != info->xmit.tail) {
1583 SIMCOUT(info->xmit.buf + info->xmit.tail,
1584 CIRC_CNT(info->xmit.head,
1585 info->xmit.tail,
1586 SERIAL_XMIT_SIZE));
1587 info->xmit.head = info->xmit.tail; /* move back head */
1588 info->tr_running = 0;
1589 }
1590 return;
1591#endif
1592 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1593 *info->oclrintradr =
1594 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1595 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1596
1597#ifdef SERIAL_DEBUG_INTR
1598 if (info->line == SERIAL_DEBUG_LINE)
1599 printk("tc\n");
1600#endif
1601 if (!info->tr_running) {
1602 /* weirdo... we shouldn't get here! */
1603 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1604 return;
1605 }
1606
1607 descr = &info->tr_descr;
1608
1609 /* first get the amount of bytes sent during the last DMA transfer,
1610 and update xmit accordingly */
1611
1612 /* if the stop bit was not set, all data has been sent */
1613 if (!(descr->status & d_stop)) {
1614 sentl = descr->sw_len;
1615 } else
1616 /* otherwise we find the amount of data sent here */
1617 sentl = descr->hw_len;
1618
1619 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1620
1621 /* update stats */
1622 info->icount.tx += sentl;
1623
1624 /* update xmit buffer */
1625 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1626
1627 /* if there is only a few chars left in the buf, wake up the blocked
1628 write if any */
1629 if (CIRC_CNT(info->xmit.head,
1630 info->xmit.tail,
1631 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1632 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1633
1634 /* find out the largest amount of consecutive bytes we want to send now */
1635
1636 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1637
1638 /* Don't send all in one DMA transfer - divide it so we wake up
1639 * application before all is sent
1640 */
1641
1642 if (c >= 4*WAKEUP_CHARS)
1643 c = c/2;
1644
1645 if (c <= 0) {
1646 /* our job here is done, don't schedule any new DMA transfer */
1647 info->tr_running = 0;
1648
1649#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
6fd1af4c 1650 if (info->rs485.flags & SER_RS485_ENABLED) {
1da177e4
LT		 1651 /* Set a short timer to toggle RTS */
1652 start_one_shot_timer(&fast_timers_rs485[info->line],
1653 rs485_toggle_rts_timer_function,
1654 (unsigned long)info,
1655 info->char_time_usec*2,
1656 "RS-485");
1657 }
1658#endif /* RS485 */
1659 return;
1660 }
1661
1662 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1663 /* set up the descriptor correctly for output */
1664 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1665 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1666 descr->sw_len = c;
1667 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1668 descr->status = 0;
1669
1670 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1671 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1672
1673 /* DMA is now running (hopefully) */
1674} /* transmit_chars_dma */
1675
1676static void
1677start_transmit(struct e100_serial *info)
1678{
1679#if 0
1680 if (info->line == SERIAL_DEBUG_LINE)
1681 printk("x\n");
1682#endif
1683
1684 info->tr_descr.sw_len = 0;
1685 info->tr_descr.hw_len = 0;
1686 info->tr_descr.status = 0;
1687 info->tr_running = 1;
1688 if (info->uses_dma_out)
1689 transmit_chars_dma(info);
1690 else
1691 e100_enable_serial_tx_ready_irq(info);
1692} /* start_transmit */
1693
1694#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1695static int serial_fast_timer_started = 0;
1696static int serial_fast_timer_expired = 0;
1697static void flush_timeout_function(unsigned long data);
1698#define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1699 unsigned long timer_flags; \
77accbf5 1700 local_irq_save(timer_flags); \
1da177e4
LT		 1701 if (fast_timers[info->line].function == NULL) { \
1702 serial_fast_timer_started++; \
1703 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1704 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1705 start_one_shot_timer(&fast_timers[info->line], \
1706 flush_timeout_function, \
1707 (unsigned long)info, \
1708 (usec), \
1709 string); \
1710 } \
1711 else { \
1712 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1713 } \
77accbf5 1714 local_irq_restore(timer_flags); \
1da177e4
LT		 1715}
1716#define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1717
1718#else
1719#define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1720#define START_FLUSH_FAST_TIMER(info, string)
1721#endif
1722
1723static struct etrax_recv_buffer *
1724alloc_recv_buffer(unsigned int size)
1725{
1726 struct etrax_recv_buffer *buffer;
1727
1728 if (!(buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC)))
1729 return NULL;
1730
1731 buffer->next = NULL;
1732 buffer->length = 0;
1733 buffer->error = TTY_NORMAL;
1734
1735 return buffer;
1736}
1737
1738static void
1739append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1740{
1741 unsigned long flags;
1742
77accbf5 1743 local_irq_save(flags);
1da177e4
LT		 1744
1745 if (!info->first_recv_buffer)
1746 info->first_recv_buffer = buffer;
1747 else
1748 info->last_recv_buffer->next = buffer;
1749
1750 info->last_recv_buffer = buffer;
1751
1752 info->recv_cnt += buffer->length;
1753 if (info->recv_cnt > info->max_recv_cnt)
1754 info->max_recv_cnt = info->recv_cnt;
1755
77accbf5 1756 local_irq_restore(flags);
1da177e4
LT		 1757}
1758
1759static int
1760add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1761{
1762 struct etrax_recv_buffer *buffer;
1763 if (info->uses_dma_in) {
1764 if (!(buffer = alloc_recv_buffer(4)))
1765 return 0;
1766
1767 buffer->length = 1;
1768 buffer->error = flag;
1769 buffer->buffer[0] = data;
1770
1771 append_recv_buffer(info, buffer);
1772
1773 info->icount.rx++;
1774 } else {
a88487c7 1775 struct tty_struct *tty = info->port.tty;
77accbf5 1776 tty_insert_flip_char(tty, data, flag);
1da177e4
LT		 1777 info->icount.rx++;
1778 }
1779
1780 return 1;
1781}
1782
41c28ff1
AB		 1783static unsigned int handle_descr_data(struct e100_serial *info,
1784 struct etrax_dma_descr *descr,
1785 unsigned int recvl)
1da177e4
LT		 1786{
1787 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1788
1789 if (info->recv_cnt + recvl > 65536) {
1790 printk(KERN_CRIT
71cc2c21 1791 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl);
1da177e4
LT		 1792 return 0;
1793 }
1794
1795 buffer->length = recvl;
1796
1797 if (info->errorcode == ERRCODE_SET_BREAK)
1798 buffer->error = TTY_BREAK;
1799 info->errorcode = 0;
1800
1801 append_recv_buffer(info, buffer);
1802
1803 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
71cc2c21 1804 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1da177e4
LT		 1805
1806 descr->buf = virt_to_phys(buffer->buffer);
1807
1808 return recvl;
1809}
1810
41c28ff1 1811static unsigned int handle_all_descr_data(struct e100_serial *info)
1da177e4
LT		 1812{
1813 struct etrax_dma_descr *descr;
1814 unsigned int recvl;
1815 unsigned int ret = 0;
1816
1817 while (1)
1818 {
1819 descr = &info->rec_descr[info->cur_rec_descr];
1820
1821 if (descr == phys_to_virt(*info->idescradr))
1822 break;
1823
1824 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1825 info->cur_rec_descr = 0;
1826
1827 /* find out how many bytes were read */
1828
1829 /* if the eop bit was not set, all data has been received */
1830 if (!(descr->status & d_eop)) {
1831 recvl = descr->sw_len;
1832 } else {
1833 /* otherwise we find the amount of data received here */
1834 recvl = descr->hw_len;
1835 }
1836
1837 /* Reset the status information */
1838 descr->status = 0;
1839
1840 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
a88487c7 1841 if (info->port.tty->stopped) {
1da177e4
LT		 1842 unsigned char *buf = phys_to_virt(descr->buf);
1843 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1844 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1845 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1846 }
1847 );
1848
1849 /* update stats */
1850 info->icount.rx += recvl;
1851
1852 ret += handle_descr_data(info, descr, recvl);
1853 }
1854
1855 return ret;
1856}
1857
41c28ff1 1858static void receive_chars_dma(struct e100_serial *info)
1da177e4
LT		 1859{
1860 struct tty_struct *tty;
1861 unsigned char rstat;
1862
1863#ifdef CONFIG_SVINTO_SIM
1864 /* No receive in the simulator. Will probably be when the rest of
1865 * the serial interface works, and this piece will just be removed.
1866 */
1867 return;
1868#endif
1869
1870 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1871 *info->iclrintradr =
1872 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1873 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1874
a88487c7 1875 tty = info->port.tty;
1da177e4
LT		 1876 if (!tty) /* Something wrong... */
1877 return;
1878
1879#ifdef SERIAL_HANDLE_EARLY_ERRORS
1880 if (info->uses_dma_in)
1881 e100_enable_serial_data_irq(info);
1882#endif
1883
1884 if (info->errorcode == ERRCODE_INSERT_BREAK)
1885 add_char_and_flag(info, '\0', TTY_BREAK);
1886
1887 handle_all_descr_data(info);
1888
1889 /* Read the status register to detect errors */
d7283353 1890 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 1891 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1892 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1893 }
1894
1895 if (rstat & SER_ERROR_MASK) {
1896 /* If we got an error, we must reset it by reading the
1897 * data_in field
1898 */
d7283353 1899 unsigned char data = info->ioport[REG_DATA];
1da177e4
LT		 1900
1901 PROCSTAT(ser_stat[info->line].errors_cnt++);
1902 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1903 ((rstat & SER_ERROR_MASK) << 8) | data);
1904
1905 if (rstat & SER_PAR_ERR_MASK)
1906 add_char_and_flag(info, data, TTY_PARITY);
1907 else if (rstat & SER_OVERRUN_MASK)
1908 add_char_and_flag(info, data, TTY_OVERRUN);
1909 else if (rstat & SER_FRAMING_ERR_MASK)
1910 add_char_and_flag(info, data, TTY_FRAME);
1911 }
1912
1913 START_FLUSH_FAST_TIMER(info, "receive_chars");
1914
1915 /* Restart the receiving DMA */
1916 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1917}
1918
41c28ff1 1919static int start_recv_dma(struct e100_serial *info)
1da177e4
LT		 1920{
1921 struct etrax_dma_descr *descr = info->rec_descr;
1922 struct etrax_recv_buffer *buffer;
1923 int i;
1924
1925 /* Set up the receiving descriptors */
1926 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
1927 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
71cc2c21 1928 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1da177e4
LT		 1929
1930 descr[i].ctrl = d_int;
1931 descr[i].buf = virt_to_phys(buffer->buffer);
1932 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1933 descr[i].hw_len = 0;
1934 descr[i].status = 0;
1935 descr[i].next = virt_to_phys(&descr[i+1]);
1936 }
1937
1938 /* Link the last descriptor to the first */
1939 descr[i-1].next = virt_to_phys(&descr[0]);
1940
1941 /* Start with the first descriptor in the list */
1942 info->cur_rec_descr = 0;
1943
1944 /* Start the DMA */
1945 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1946 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1947
1948 /* Input DMA should be running now */
1949 return 1;
1950}
1951
1952static void
1953start_receive(struct e100_serial *info)
1954{
1955#ifdef CONFIG_SVINTO_SIM
1956 /* No receive in the simulator. Will probably be when the rest of
1957 * the serial interface works, and this piece will just be removed.
1958 */
1959 return;
1960#endif
1da177e4
LT		 1961 if (info->uses_dma_in) {
1962 /* reset the input dma channel to be sure it works */
1963
1964 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1965 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1966 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1967
1968 start_recv_dma(info);
1969 }
1970}
1971
1972
1da177e4
LT		 1973/* the bits in the MASK2 register are laid out like this:
1974 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1975 where I is the input channel and O is the output channel for the port.
1976 info->irq is the bit number for the DMAO_DESCR so to check the others we
1977 shift info->irq to the left.
1978*/
1979
1980/* dma output channel interrupt handler
1981 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1982 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1983*/
1984
1985static irqreturn_t
7d12e780 1986tr_interrupt(int irq, void *dev_id)
1da177e4
LT		 1987{
1988 struct e100_serial *info;
1989 unsigned long ireg;
1990 int i;
1991 int handled = 0;
1992
1993#ifdef CONFIG_SVINTO_SIM
1994 /* No receive in the simulator. Will probably be when the rest of
1995 * the serial interface works, and this piece will just be removed.
1996 */
1997 {
1998 const char *s = "What? tr_interrupt in simulator??\n";
1999 SIMCOUT(s,strlen(s));
2000 }
2001 return IRQ_HANDLED;
2002#endif
2003
2004 /* find out the line that caused this irq and get it from rs_table */
2005
2006 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2007
2008 for (i = 0; i < NR_PORTS; i++) {
2009 info = rs_table + i;
2010 if (!info->enabled || !info->uses_dma_out)
2011 continue;
2012 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
2013 if (ireg & info->irq) {
2014 handled = 1;
2015 /* we can send a new dma bunch. make it so. */
2016 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
2017 /* Read jiffies_usec first,
2018 * we want this time to be as late as possible
2019 */
2020 PROCSTAT(ser_stat[info->line].tx_dma_ints++);
2021 info->last_tx_active_usec = GET_JIFFIES_USEC();
2022 info->last_tx_active = jiffies;
2023 transmit_chars_dma(info);
2024 }
2025
2026 /* FIXME: here we should really check for a change in the
2027 status lines and if so call status_handle(info) */
2028 }
2029 return IRQ_RETVAL(handled);
2030} /* tr_interrupt */
2031
2032/* dma input channel interrupt handler */
2033
2034static irqreturn_t
7d12e780 2035rec_interrupt(int irq, void *dev_id)
1da177e4
LT		 2036{
2037 struct e100_serial *info;
2038 unsigned long ireg;
2039 int i;
2040 int handled = 0;
2041
2042#ifdef CONFIG_SVINTO_SIM
2043 /* No receive in the simulator. Will probably be when the rest of
2044 * the serial interface works, and this piece will just be removed.
2045 */
2046 {
2047 const char *s = "What? rec_interrupt in simulator??\n";
2048 SIMCOUT(s,strlen(s));
2049 }
2050 return IRQ_HANDLED;
2051#endif
2052
2053 /* find out the line that caused this irq and get it from rs_table */
2054
2055 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2056
2057 for (i = 0; i < NR_PORTS; i++) {
2058 info = rs_table + i;
2059 if (!info->enabled || !info->uses_dma_in)
2060 continue;
2061 /* check for both dma_eop and dma_descr for the input dma channel */
2062 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
2063 handled = 1;
2064 /* we have received something */
2065 receive_chars_dma(info);
2066 }
2067
2068 /* FIXME: here we should really check for a change in the
2069 status lines and if so call status_handle(info) */
2070 }
2071 return IRQ_RETVAL(handled);
2072} /* rec_interrupt */
2073
41c28ff1 2074static int force_eop_if_needed(struct e100_serial *info)
1da177e4
LT		 2075{
2076 /* We check data_avail bit to determine if data has
2077 * arrived since last time
2078 */
d7283353 2079 unsigned char rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2080
2081 /* error or datavail? */
2082 if (rstat & SER_ERROR_MASK) {
2083 /* Some error has occurred. If there has been valid data, an
2084 * EOP interrupt will be made automatically. If no data, the
2085 * normal ser_interrupt should be enabled and handle it.
2086 * So do nothing!
2087 */
2088 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
2089 rstat | (info->line << 8));
2090 return 0;
2091 }
2092
2093 if (rstat & SER_DATA_AVAIL_MASK) {
2094 /* Ok data, no error, count it */
2095 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
2096 rstat | (info->line << 8)));
2097 /* Read data to clear status flags */
d7283353 2098 (void)info->ioport[REG_DATA];
1da177e4
LT		 2099
2100 info->forced_eop = 0;
2101 START_FLUSH_FAST_TIMER(info, "magic");
2102 return 0;
2103 }
2104
2105 /* hit the timeout, force an EOP for the input
2106 * dma channel if we haven't already
2107 */
2108 if (!info->forced_eop) {
2109 info->forced_eop = 1;
2110 PROCSTAT(ser_stat[info->line].timeout_flush_cnt++);
2111 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
2112 FORCE_EOP(info);
2113 }
2114
2115 return 1;
2116}
2117
41c28ff1 2118static void flush_to_flip_buffer(struct e100_serial *info)
1da177e4
LT		 2119{
2120 struct tty_struct *tty;
2121 struct etrax_recv_buffer *buffer;
1da177e4 2122 unsigned long flags;
1da177e4 2123
77accbf5 2124 local_irq_save(flags);
a88487c7 2125 tty = info->port.tty;
1da177e4 2126
77accbf5
JN		 2127 if (!tty) {
2128 local_irq_restore(flags);
1da177e4
LT		 2129 return;
2130 }
2131
2090ab05 2132 while ((buffer = info->first_recv_buffer) != NULL) {
1da177e4
LT		 2133 unsigned int count = buffer->length;
2134
77accbf5 2135 tty_insert_flip_string(tty, buffer->buffer, count);
1da177e4 2136 info->recv_cnt -= count;
1da177e4
LT		 2137
2138 if (count == buffer->length) {
2139 info->first_recv_buffer = buffer->next;
2140 kfree(buffer);
2141 } else {
2142 buffer->length -= count;
2143 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2144 buffer->error = TTY_NORMAL;
2145 }
2146 }
2147
2148 if (!info->first_recv_buffer)
2149 info->last_recv_buffer = NULL;
2150
77accbf5 2151 local_irq_restore(flags);
1da177e4 2152
77accbf5 2153 /* This includes a check for low-latency */
1da177e4
LT		 2154 tty_flip_buffer_push(tty);
2155}
2156
41c28ff1 2157static void check_flush_timeout(struct e100_serial *info)
1da177e4
LT		 2158{
2159 /* Flip what we've got (if we can) */
2160 flush_to_flip_buffer(info);
2161
2162 /* We might need to flip later, but not to fast
2163 * since the system is busy processing input... */
2164 if (info->first_recv_buffer)
2165 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2166
2167 /* Force eop last, since data might have come while we're processing
2168 * and if we started the slow timer above, we won't start a fast
2169 * below.
2170 */
2171 force_eop_if_needed(info);
2172}
2173
2174#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2175static void flush_timeout_function(unsigned long data)
2176{
2177 struct e100_serial *info = (struct e100_serial *)data;
2178
2179 fast_timers[info->line].function = NULL;
2180 serial_fast_timer_expired++;
2181 TIMERD(DEBUG_LOG(info->line, "flush_timout %i ", info->line));
2182 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2183 check_flush_timeout(info);
2184}
2185
2186#else
2187
2188/* dma fifo/buffer timeout handler
2189 forces an end-of-packet for the dma input channel if no chars
2190 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2191*/
2192
2193static struct timer_list flush_timer;
2194
2195static void
2196timed_flush_handler(unsigned long ptr)
2197{
2198 struct e100_serial *info;
2199 int i;
2200
2201#ifdef CONFIG_SVINTO_SIM
2202 return;
2203#endif
2204
2205 for (i = 0; i < NR_PORTS; i++) {
2206 info = rs_table + i;
2207 if (info->uses_dma_in)
2208 check_flush_timeout(info);
2209 }
2210
2211 /* restart flush timer */
2212 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2213}
2214#endif
2215
2216#ifdef SERIAL_HANDLE_EARLY_ERRORS
2217
2218/* If there is an error (ie break) when the DMA is running and
2219 * there are no bytes in the fifo the DMA is stopped and we get no
2220 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2221 * transfer, and if it is without error we can turn the serial
2222 * interrupts off.
2223 */
2224
2225/*
2226BREAK handling on ETRAX 100:
2227ETRAX will generate interrupt although there is no stop bit between the
2228characters.
2229
2230Depending on how long the break sequence is, the end of the breaksequence
2231will look differently:
2232| indicates start/end of a character.
2233
2234B= Break character (0x00) with framing error.
2235E= Error byte with parity error received after B characters.
2236F= "Faked" valid byte received immediately after B characters.
2237V= Valid byte
2238
22391.
2240 B BL ___________________________ V
2241.._|__________|__________| |valid data |
2242
2243Multiple frame errors with data == 0x00 (B),
2244the timing matches up "perfectly" so no extra ending char is detected.
2245The RXD pin is 1 in the last interrupt, in that case
2246we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2247know if another byte will come and this really is case 2. below
2248(e.g F=0xFF or 0xFE)
2249If RXD pin is 0 we can expect another character (see 2. below).
2250
2251
22522.
2253
2254 B B E or F__________________..__ V
2255.._|__________|__________|______ | |valid data
2256 "valid" or
2257 parity error
2258
2259Multiple frame errors with data == 0x00 (B),
2260but the part of the break trigs is interpreted as a start bit (and possibly
2261some 0 bits followed by a number of 1 bits and a stop bit).
2262Depending on parity settings etc. this last character can be either
2263a fake "valid" char (F) or have a parity error (E).
2264
2265If the character is valid it will be put in the buffer,
2266we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2267will set the flags so the tty will handle it,
2268if it's an error byte it will not be put in the buffer
2269and we set info->errorcode = ERRCODE_INSERT_BREAK.
2270
2271To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2272of the last faulty char (B) and compares it with the current time:
2273If the time elapsed time is less then 2*char_time_usec we will assume
2274it's a faked F char and not a Valid char and set
2275info->errorcode = ERRCODE_SET_BREAK.
2276
2277Flaws in the above solution:
2278~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2279We use the timer to distinguish a F character from a V character,
2280if a V character is to close after the break we might make the wrong decision.
2281
2282TODO: The break will be delayed until an F or V character is received.
2283
2284*/
2285
41c28ff1 2286static
1da177e4
LT		 2287struct e100_serial * handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
2288{
2289 unsigned long data_read;
a88487c7 2290 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 2291
2292 if (!tty) {
2293 printk("!NO TTY!\n");
2294 return info;
2295 }
77accbf5 2296
1da177e4 2297 /* Read data and status at the same time */
d7283353 2298 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
1da177e4
LT		 2299more_data:
2300 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2301 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2302 }
2303 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2304
2305 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2306 IO_MASK(R_SERIAL0_READ, par_err) |
2307 IO_MASK(R_SERIAL0_READ, overrun) )) {
2308 /* An error */
2309 info->last_rx_active_usec = GET_JIFFIES_USEC();
2310 info->last_rx_active = jiffies;
2311 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2312 DLOG_INT_TRIG(
2313 if (!log_int_trig1_pos) {
2314 log_int_trig1_pos = log_int_pos;
2315 log_int(rdpc(), 0, 0);
2316 }
2317 );
2318
2319
2320 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2321 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2322 /* Most likely a break, but we get interrupts over and
2323 * over again.
2324 */
2325
2326 if (!info->break_detected_cnt) {
2327 DEBUG_LOG(info->line, "#BRK start\n", 0);
2328 }
2329 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2330 /* The RX pin is high now, so the break
2331 * must be over, but....
2332 * we can't really know if we will get another
2333 * last byte ending the break or not.
2334 * And we don't know if the byte (if any) will
2335 * have an error or look valid.
2336 */
2337 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2338 info->errorcode = ERRCODE_INSERT_BREAK;
2339 }
2340 info->break_detected_cnt++;
2341 } else {
2342 /* The error does not look like a break, but could be
2343 * the end of one
2344 */
2345 if (info->break_detected_cnt) {
2346 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2347 info->errorcode = ERRCODE_INSERT_BREAK;
2348 } else {
77accbf5
JN		 2349 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2350 data_in, data_read);
2351 char flag = TTY_NORMAL;
1da177e4 2352 if (info->errorcode == ERRCODE_INSERT_BREAK) {
a88487c7 2353 struct tty_struct *tty = info->port.tty;
77accbf5 2354 tty_insert_flip_char(tty, 0, flag);
1da177e4
LT		 2355 info->icount.rx++;
2356 }
1da177e4
LT		 2357
2358 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2359 info->icount.parity++;
77accbf5 2360 flag = TTY_PARITY;
1da177e4
LT		 2361 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2362 info->icount.overrun++;
77accbf5 2363 flag = TTY_OVERRUN;
1da177e4
LT		 2364 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2365 info->icount.frame++;
77accbf5 2366 flag = TTY_FRAME;
1da177e4 2367 }
77accbf5 2368 tty_insert_flip_char(tty, data, flag);
1da177e4
LT		 2369 info->errorcode = 0;
2370 }
2371 info->break_detected_cnt = 0;
2372 }
2373 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2374 /* No error */
2375 DLOG_INT_TRIG(
2376 if (!log_int_trig1_pos) {
2377 if (log_int_pos >= log_int_size) {
2378 log_int_pos = 0;
2379 }
2380 log_int_trig0_pos = log_int_pos;
2381 log_int(rdpc(), 0, 0);
2382 }
2383 );
77accbf5
JN		 2384 tty_insert_flip_char(tty,
2385 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2386 TTY_NORMAL);
1da177e4
LT		 2387 } else {
2388 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2389 }
2390
2391
1da177e4 2392 info->icount.rx++;
d7283353 2393 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
1da177e4
LT		 2394 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2395 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2396 goto more_data;
2397 }
2398
a88487c7 2399 tty_flip_buffer_push(info->port.tty);
1da177e4
LT		 2400 return info;
2401}
2402
41c28ff1 2403static struct e100_serial* handle_ser_rx_interrupt(struct e100_serial *info)
1da177e4
LT		 2404{
2405 unsigned char rstat;
2406
2407#ifdef SERIAL_DEBUG_INTR
2408 printk("Interrupt from serport %d\n", i);
2409#endif
2410/* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2411 if (!info->uses_dma_in) {
2412 return handle_ser_rx_interrupt_no_dma(info);
2413 }
2414 /* DMA is used */
d7283353 2415 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2416 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2417 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2418 }
2419
2420 if (rstat & SER_ERROR_MASK) {
2421 unsigned char data;
2422
2423 info->last_rx_active_usec = GET_JIFFIES_USEC();
2424 info->last_rx_active = jiffies;
2425 /* If we got an error, we must reset it by reading the
2426 * data_in field
2427 */
d7283353 2428 data = info->ioport[REG_DATA];
1da177e4
LT		 2429 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2430 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2431 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2432 /* Most likely a break, but we get interrupts over and
2433 * over again.
2434 */
2435
2436 if (!info->break_detected_cnt) {
2437 DEBUG_LOG(info->line, "#BRK start\n", 0);
2438 }
2439 if (rstat & SER_RXD_MASK) {
2440 /* The RX pin is high now, so the break
2441 * must be over, but....
2442 * we can't really know if we will get another
2443 * last byte ending the break or not.
2444 * And we don't know if the byte (if any) will
2445 * have an error or look valid.
2446 */
2447 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2448 info->errorcode = ERRCODE_INSERT_BREAK;
2449 }
2450 info->break_detected_cnt++;
2451 } else {
2452 /* The error does not look like a break, but could be
2453 * the end of one
2454 */
2455 if (info->break_detected_cnt) {
2456 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2457 info->errorcode = ERRCODE_INSERT_BREAK;
2458 } else {
2459 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2460 info->icount.brk++;
2461 add_char_and_flag(info, '\0', TTY_BREAK);
2462 }
2463
2464 if (rstat & SER_PAR_ERR_MASK) {
2465 info->icount.parity++;
2466 add_char_and_flag(info, data, TTY_PARITY);
2467 } else if (rstat & SER_OVERRUN_MASK) {
2468 info->icount.overrun++;
2469 add_char_and_flag(info, data, TTY_OVERRUN);
2470 } else if (rstat & SER_FRAMING_ERR_MASK) {
2471 info->icount.frame++;
2472 add_char_and_flag(info, data, TTY_FRAME);
2473 }
2474
2475 info->errorcode = 0;
2476 }
2477 info->break_detected_cnt = 0;
2478 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2479 ((rstat & SER_ERROR_MASK) << 8) | data);
2480 }
2481 PROCSTAT(ser_stat[info->line].early_errors_cnt++);
2482 } else { /* It was a valid byte, now let the DMA do the rest */
2483 unsigned long curr_time_u = GET_JIFFIES_USEC();
2484 unsigned long curr_time = jiffies;
2485
2486 if (info->break_detected_cnt) {
2487 /* Detect if this character is a new valid char or the
2488 * last char in a break sequence: If LSBits are 0 and
2489 * MSBits are high AND the time is close to the
2490 * previous interrupt we should discard it.
2491 */
2492 long elapsed_usec =
2493 (curr_time - info->last_rx_active) * (1000000/HZ) +
2494 curr_time_u - info->last_rx_active_usec;
2495 if (elapsed_usec < 2*info->char_time_usec) {
2496 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2497 /* Report as BREAK (error) and let
2498 * receive_chars_dma() handle it
2499 */
2500 info->errorcode = ERRCODE_SET_BREAK;
2501 } else {
2502 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2503 }
2504 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2505 }
2506
2507#ifdef SERIAL_DEBUG_INTR
2508 printk("** OK, disabling ser_interrupts\n");
2509#endif
2510 e100_disable_serial_data_irq(info);
2511 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2512 info->break_detected_cnt = 0;
2513
2514 PROCSTAT(ser_stat[info->line].ser_ints_ok_cnt++);
2515 }
2516 /* Restarting the DMA never hurts */
2517 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2518 START_FLUSH_FAST_TIMER(info, "ser_int");
2519 return info;
2520} /* handle_ser_rx_interrupt */
2521
41c28ff1 2522static void handle_ser_tx_interrupt(struct e100_serial *info)
1da177e4
LT		 2523{
2524 unsigned long flags;
2525
2526 if (info->x_char) {
2527 unsigned char rstat;
2528 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
77accbf5 2529 local_irq_save(flags);
d7283353 2530 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2531 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2532
d7283353 2533 info->ioport[REG_TR_DATA] = info->x_char;
1da177e4
LT		 2534 info->icount.tx++;
2535 info->x_char = 0;
2536 /* We must enable since it is disabled in ser_interrupt */
2537 e100_enable_serial_tx_ready_irq(info);
77accbf5 2538 local_irq_restore(flags);
1da177e4
LT		 2539 return;
2540 }
2541 if (info->uses_dma_out) {
2542 unsigned char rstat;
2543 int i;
2544 /* We only use normal tx interrupt when sending x_char */
2545 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
77accbf5 2546 local_irq_save(flags);
d7283353 2547 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2548 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2549 e100_disable_serial_tx_ready_irq(info);
a88487c7
TI		 2550 if (info->port.tty->stopped)
2551 rs_stop(info->port.tty);
1da177e4
LT		 2552 /* Enable the DMA channel and tell it to continue */
2553 e100_enable_txdma_channel(info);
2554 /* Wait 12 cycles before doing the DMA command */
2555 for(i = 6; i > 0; i--)
2556 nop();
2557
2558 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
77accbf5 2559 local_irq_restore(flags);
1da177e4
LT		 2560 return;
2561 }
2562 /* Normal char-by-char interrupt */
2563 if (info->xmit.head == info->xmit.tail
a88487c7
TI		 2564 || info->port.tty->stopped
2565 || info->port.tty->hw_stopped) {
2566 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n",
2567 info->port.tty->stopped));
1da177e4
LT		 2568 e100_disable_serial_tx_ready_irq(info);
2569 info->tr_running = 0;
2570 return;
2571 }
2572 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2573 /* Send a byte, rs485 timing is critical so turn of ints */
77accbf5 2574 local_irq_save(flags);
d7283353 2575 info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
1da177e4
LT		 2576 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2577 info->icount.tx++;
2578 if (info->xmit.head == info->xmit.tail) {
2579#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
6fd1af4c 2580 if (info->rs485.flags & SER_RS485_ENABLED) {
1da177e4
LT		 2581 /* Set a short timer to toggle RTS */
2582 start_one_shot_timer(&fast_timers_rs485[info->line],
2583 rs485_toggle_rts_timer_function,
2584 (unsigned long)info,
2585 info->char_time_usec*2,
2586 "RS-485");
2587 }
2588#endif /* RS485 */
2589 info->last_tx_active_usec = GET_JIFFIES_USEC();
2590 info->last_tx_active = jiffies;
2591 e100_disable_serial_tx_ready_irq(info);
2592 info->tr_running = 0;
2593 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2594 } else {
2595 /* We must enable since it is disabled in ser_interrupt */
2596 e100_enable_serial_tx_ready_irq(info);
2597 }
77accbf5 2598 local_irq_restore(flags);
1da177e4
LT		 2599
2600 if (CIRC_CNT(info->xmit.head,
2601 info->xmit.tail,
2602 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2603 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2604
2605} /* handle_ser_tx_interrupt */
2606
2607/* result of time measurements:
2608 * RX duration 54-60 us when doing something, otherwise 6-9 us
2609 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2610 */
2611static irqreturn_t
7d12e780 2612ser_interrupt(int irq, void *dev_id)
1da177e4
LT		 2613{
2614 static volatile int tx_started = 0;
2615 struct e100_serial *info;
2616 int i;
2617 unsigned long flags;
2618 unsigned long irq_mask1_rd;
2619 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2620 int handled = 0;
2621 static volatile unsigned long reentered_ready_mask = 0;
2622
77accbf5 2623 local_irq_save(flags);
1da177e4
LT		 2624 irq_mask1_rd = *R_IRQ_MASK1_RD;
2625 /* First handle all rx interrupts with ints disabled */
2626 info = rs_table;
2627 irq_mask1_rd &= e100_ser_int_mask;
2628 for (i = 0; i < NR_PORTS; i++) {
2629 /* Which line caused the data irq? */
2630 if (irq_mask1_rd & data_mask) {
2631 handled = 1;
2632 handle_ser_rx_interrupt(info);
2633 }
2634 info += 1;
2635 data_mask <<= 2;
2636 }
2637 /* Handle tx interrupts with interrupts enabled so we
2638 * can take care of new data interrupts while transmitting
2639 * We protect the tx part with the tx_started flag.
2640 * We disable the tr_ready interrupts we are about to handle and
2641 * unblock the serial interrupt so new serial interrupts may come.
2642 *
2643 * If we get a new interrupt:
2644 * - it migth be due to synchronous serial ports.
2645 * - serial irq will be blocked by general irq handler.
2646 * - async data will be handled above (sync will be ignored).
2647 * - tx_started flag will prevent us from trying to send again and
2648 * we will exit fast - no need to unblock serial irq.
2649 * - Next (sync) serial interrupt handler will be runned with
2650 * disabled interrupt due to restore_flags() at end of function,
2651 * so sync handler will not be preempted or reentered.
2652 */
2653 if (!tx_started) {
2654 unsigned long ready_mask;
2655 unsigned long
2656 tx_started = 1;
2657 /* Only the tr_ready interrupts left */
2658 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2659 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2660 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2661 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2662 while (irq_mask1_rd) {
2663 /* Disable those we are about to handle */
2664 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2665 /* Unblock the serial interrupt */
2666 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2667
77accbf5 2668 local_irq_enable();
1da177e4
LT		 2669 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2670 info = rs_table;
2671 for (i = 0; i < NR_PORTS; i++) {
2672 /* Which line caused the ready irq? */
2673 if (irq_mask1_rd & ready_mask) {
2674 handled = 1;
2675 handle_ser_tx_interrupt(info);
2676 }
2677 info += 1;
2678 ready_mask <<= 2;
2679 }
2680 /* handle_ser_tx_interrupt enables tr_ready interrupts */
77accbf5 2681 local_irq_disable();
1da177e4
LT		 2682 /* Handle reentered TX interrupt */
2683 irq_mask1_rd = reentered_ready_mask;
2684 }
77accbf5 2685 local_irq_disable();
1da177e4
LT		 2686 tx_started = 0;
2687 } else {
2688 unsigned long ready_mask;
2689 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2690 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2691 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2692 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2693 if (ready_mask) {
2694 reentered_ready_mask |= ready_mask;
2695 /* Disable those we are about to handle */
2696 *R_IRQ_MASK1_CLR = ready_mask;
2697 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2698 }
2699 }
2700
77accbf5 2701 local_irq_restore(flags);
1da177e4
LT		 2702 return IRQ_RETVAL(handled);
2703} /* ser_interrupt */
2704#endif
2705
2706/*
2707 * -------------------------------------------------------------------
2708 * Here ends the serial interrupt routines.
2709 * -------------------------------------------------------------------
2710 */
2711
2712/*
2713 * This routine is used to handle the "bottom half" processing for the
2714 * serial driver, known also the "software interrupt" processing.
2715 * This processing is done at the kernel interrupt level, after the
2716 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2717 * is where time-consuming activities which can not be done in the
2718 * interrupt driver proper are done; the interrupt driver schedules
2719 * them using rs_sched_event(), and they get done here.
2720 */
2721static void
77accbf5 2722do_softint(struct work_struct *work)
1da177e4 2723{
77accbf5 2724 struct e100_serial *info;
1da177e4
LT		 2725 struct tty_struct *tty;
2726
77accbf5
JN		 2727 info = container_of(work, struct e100_serial, work);
2728
a88487c7 2729 tty = info->port.tty;
1da177e4
LT		 2730 if (!tty)
2731 return;
2732
b963a844
JS		 2733 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2734 tty_wakeup(tty);
1da177e4
LT		 2735}
2736
2737static int
2738startup(struct e100_serial * info)
2739{
2740 unsigned long flags;
2741 unsigned long xmit_page;
2742 int i;
2743
2744 xmit_page = get_zeroed_page(GFP_KERNEL);
2745 if (!xmit_page)
2746 return -ENOMEM;
2747
77accbf5 2748 local_irq_save(flags);
1da177e4
LT		 2749
2750 /* if it was already initialized, skip this */
2751
2752 if (info->flags & ASYNC_INITIALIZED) {
77accbf5 2753 local_irq_restore(flags);
1da177e4
LT		 2754 free_page(xmit_page);
2755 return 0;
2756 }
2757
2758 if (info->xmit.buf)
2759 free_page(xmit_page);
2760 else
2761 info->xmit.buf = (unsigned char *) xmit_page;
2762
2763#ifdef SERIAL_DEBUG_OPEN
2764 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2765#endif
2766
2767#ifdef CONFIG_SVINTO_SIM
2768 /* Bits and pieces collected from below. Better to have them
2769 in one ifdef:ed clause than to mix in a lot of ifdefs,
2770 right? */
a88487c7
TI		 2771 if (info->port.tty)
2772 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4
LT		 2773
2774 info->xmit.head = info->xmit.tail = 0;
2775 info->first_recv_buffer = info->last_recv_buffer = NULL;
2776 info->recv_cnt = info->max_recv_cnt = 0;
2777
2778 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2779 info->rec_descr[i].buf = NULL;
2780
2781 /* No real action in the simulator, but may set info important
2782 to ioctl. */
2783 change_speed(info);
2784#else
2785
2786 /*
2787 * Clear the FIFO buffers and disable them
2788 * (they will be reenabled in change_speed())
2789 */
2790
2791 /*
2792 * Reset the DMA channels and make sure their interrupts are cleared
2793 */
2794
2795 if (info->dma_in_enabled) {
2796 info->uses_dma_in = 1;
2797 e100_enable_rxdma_channel(info);
2798
2799 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2800
2801 /* Wait until reset cycle is complete */
2802 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2803 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2804
2805 /* Make sure the irqs are cleared */
2806 *info->iclrintradr =
2807 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2808 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2809 } else {
2810 e100_disable_rxdma_channel(info);
2811 }
2812
2813 if (info->dma_out_enabled) {
2814 info->uses_dma_out = 1;
2815 e100_enable_txdma_channel(info);
2816 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2817
2818 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2819 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2820
2821 /* Make sure the irqs are cleared */
2822 *info->oclrintradr =
2823 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2824 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2825 } else {
2826 e100_disable_txdma_channel(info);
2827 }
2828
a88487c7
TI		 2829 if (info->port.tty)
2830 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4
LT		 2831
2832 info->xmit.head = info->xmit.tail = 0;
2833 info->first_recv_buffer = info->last_recv_buffer = NULL;
2834 info->recv_cnt = info->max_recv_cnt = 0;
2835
2836 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2837 info->rec_descr[i].buf = 0;
2838
2839 /*
2840 * and set the speed and other flags of the serial port
2841 * this will start the rx/tx as well
2842 */
2843#ifdef SERIAL_HANDLE_EARLY_ERRORS
2844 e100_enable_serial_data_irq(info);
2845#endif
2846 change_speed(info);
2847
2848 /* dummy read to reset any serial errors */
2849
d7283353 2850 (void)info->ioport[REG_DATA];
1da177e4
LT		 2851
2852 /* enable the interrupts */
2853 if (info->uses_dma_out)
2854 e100_enable_txdma_irq(info);
2855
2856 e100_enable_rx_irq(info);
2857
2858 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2859
2860 /* setup the dma input descriptor and start dma */
2861
2862 start_receive(info);
2863
2864 /* for safety, make sure the descriptors last result is 0 bytes written */
2865
2866 info->tr_descr.sw_len = 0;
2867 info->tr_descr.hw_len = 0;
2868 info->tr_descr.status = 0;
2869
2870 /* enable RTS/DTR last */
2871
2872 e100_rts(info, 1);
2873 e100_dtr(info, 1);
2874
2875#endif /* CONFIG_SVINTO_SIM */
2876
2877 info->flags |= ASYNC_INITIALIZED;
2878
77accbf5 2879 local_irq_restore(flags);
1da177e4
LT		 2880 return 0;
2881}
2882
2883/*
2884 * This routine will shutdown a serial port; interrupts are disabled, and
2885 * DTR is dropped if the hangup on close termio flag is on.
2886 */
2887static void
2888shutdown(struct e100_serial * info)
2889{
2890 unsigned long flags;
2891 struct etrax_dma_descr *descr = info->rec_descr;
2892 struct etrax_recv_buffer *buffer;
2893 int i;
2894
2895#ifndef CONFIG_SVINTO_SIM
2896 /* shut down the transmitter and receiver */
2897 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2898 e100_disable_rx(info);
d7283353 2899 info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
1da177e4
LT		 2900
2901 /* disable interrupts, reset dma channels */
2902 if (info->uses_dma_in) {
2903 e100_disable_rxdma_irq(info);
2904 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2905 info->uses_dma_in = 0;
2906 } else {
2907 e100_disable_serial_data_irq(info);
2908 }
2909
2910 if (info->uses_dma_out) {
2911 e100_disable_txdma_irq(info);
2912 info->tr_running = 0;
2913 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2914 info->uses_dma_out = 0;
2915 } else {
2916 e100_disable_serial_tx_ready_irq(info);
2917 info->tr_running = 0;
2918 }
2919
2920#endif /* CONFIG_SVINTO_SIM */
2921
2922 if (!(info->flags & ASYNC_INITIALIZED))
2923 return;
2924
2925#ifdef SERIAL_DEBUG_OPEN
2926 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2927 info->irq);
2928#endif
2929
77accbf5 2930 local_irq_save(flags);
1da177e4
LT		 2931
2932 if (info->xmit.buf) {
2933 free_page((unsigned long)info->xmit.buf);
2934 info->xmit.buf = NULL;
2935 }
2936
2937 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2938 if (descr[i].buf) {
2939 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2940 kfree(buffer);
2941 descr[i].buf = 0;
2942 }
2943
a88487c7 2944 if (!info->port.tty || (info->port.tty->termios->c_cflag & HUPCL)) {
1da177e4
LT		 2945 /* hang up DTR and RTS if HUPCL is enabled */
2946 e100_dtr(info, 0);
2947 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2948 }
2949
a88487c7
TI		 2950 if (info->port.tty)
2951 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4
LT		 2952
2953 info->flags &= ~ASYNC_INITIALIZED;
77accbf5 2954 local_irq_restore(flags);
1da177e4
LT		 2955}
2956
2957
2958/* change baud rate and other assorted parameters */
2959
2960static void
2961change_speed(struct e100_serial *info)
2962{
2963 unsigned int cflag;
2964 unsigned long xoff;
2965 unsigned long flags;
2966 /* first some safety checks */
2967
a88487c7 2968 if (!info->port.tty || !info->port.tty->termios)
1da177e4 2969 return;
d7283353 2970 if (!info->ioport)
1da177e4
LT		 2971 return;
2972
a88487c7 2973 cflag = info->port.tty->termios->c_cflag;
1da177e4
LT		 2974
2975 /* possibly, the tx/rx should be disabled first to do this safely */
2976
2977 /* change baud-rate and write it to the hardware */
2978 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
2979 /* Special baudrate */
2980 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2981 unsigned long alt_source =
2982 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2983 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2984 /* R_ALT_SER_BAUDRATE selects the source */
2985 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2986 (unsigned long)info->baud_base, info->custom_divisor));
2987 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2988 /* 0, 2-65535 (0=65536) */
2989 u16 divisor = info->custom_divisor;
2990 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2991 /* baudrate is 3.125MHz/custom_divisor */
2992 alt_source =
2993 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2994 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2995 alt_source = 0x11;
2996 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
2997 *R_SERIAL_PRESCALE = divisor;
2998 info->baud = SERIAL_PRESCALE_BASE/divisor;
2999 }
3000#ifdef CONFIG_ETRAX_EXTERN_PB6CLK_ENABLED
3001 else if ((info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8 &&
3002 info->custom_divisor == 1) ||
3003 (info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ &&
3004 info->custom_divisor == 8)) {
3005 /* ext_clk selected */
3006 alt_source =
3007 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, extern) |
3008 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, extern);
3009 DBAUD(printk("using external baudrate: %lu\n", CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8));
3010 info->baud = CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8;
3011 }
1da177e4
LT		 3012#endif
3013 else
3014 {
3015 /* Bad baudbase, we don't support using timer0
3016 * for baudrate.
3017 */
3018 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
3019 (unsigned long)info->baud_base, info->custom_divisor);
3020 }
3021 r_alt_ser_baudrate_shadow &= ~mask;
3022 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3023 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3024 } else {
3025 /* Normal baudrate */
3026 /* Make sure we use normal baudrate */
3027 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
3028 unsigned long alt_source =
3029 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
3030 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
3031 r_alt_ser_baudrate_shadow &= ~mask;
3032 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3033#ifndef CONFIG_SVINTO_SIM
3034 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3035#endif /* CONFIG_SVINTO_SIM */
3036
3037 info->baud = cflag_to_baud(cflag);
3038#ifndef CONFIG_SVINTO_SIM
d7283353 3039 info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag);
1da177e4
LT		 3040#endif /* CONFIG_SVINTO_SIM */
3041 }
3042
3043#ifndef CONFIG_SVINTO_SIM
3044 /* start with default settings and then fill in changes */
77accbf5 3045 local_irq_save(flags);
1da177e4
LT		 3046 /* 8 bit, no/even parity */
3047 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
3048 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
3049 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
3050
3051 /* 8 bit, no/even parity, 1 stop bit, no cts */
3052 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
3053 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
3054 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
3055 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
3056 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
3057
3058 if ((cflag & CSIZE) == CS7) {
3059 /* set 7 bit mode */
3060 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
3061 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
3062 }
3063
3064 if (cflag & CSTOPB) {
3065 /* set 2 stop bit mode */
3066 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
3067 }
3068
3069 if (cflag & PARENB) {
3070 /* enable parity */
3071 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
3072 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
3073 }
3074
3075 if (cflag & CMSPAR) {
3076 /* enable stick parity, PARODD mean Mark which matches ETRAX */
3077 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
3078 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
3079 }
3080 if (cflag & PARODD) {
3081 /* set odd parity (or Mark if CMSPAR) */
3082 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
3083 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
3084 }
3085
3086 if (cflag & CRTSCTS) {
3087 /* enable automatic CTS handling */
3088 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
3089 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
3090 }
3091
3092 /* make sure the tx and rx are enabled */
3093
3094 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
3095 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
3096
3097 /* actually write the control regs to the hardware */
3098
d7283353
AC		 3099 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3100 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
a88487c7 3101 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty));
1da177e4 3102 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
a88487c7
TI		 3103 if (info->port.tty->termios->c_iflag & IXON ) {
3104 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n",
3105 STOP_CHAR(info->port.tty)));
1da177e4
LT		 3106 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
3107 }
3108
d7283353 3109 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
77accbf5 3110 local_irq_restore(flags);
1da177e4
LT		 3111#endif /* !CONFIG_SVINTO_SIM */
3112
3113 update_char_time(info);
3114
3115} /* change_speed */
3116
3117/* start transmitting chars NOW */
3118
3119static void
3120rs_flush_chars(struct tty_struct *tty)
3121{
3122 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3123 unsigned long flags;
3124
3125 if (info->tr_running ||
3126 info->xmit.head == info->xmit.tail ||
3127 tty->stopped ||
3128 tty->hw_stopped ||
3129 !info->xmit.buf)
3130 return;
3131
3132#ifdef SERIAL_DEBUG_FLOW
3133 printk("rs_flush_chars\n");
3134#endif
3135
3136 /* this protection might not exactly be necessary here */
3137
77accbf5 3138 local_irq_save(flags);
1da177e4 3139 start_transmit(info);
77accbf5 3140 local_irq_restore(flags);
1da177e4
LT		 3141}
3142
77accbf5 3143static int rs_raw_write(struct tty_struct *tty,
41c28ff1 3144 const unsigned char *buf, int count)
1da177e4
LT		 3145{
3146 int c, ret = 0;
3147 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3148 unsigned long flags;
3149
3150 /* first some sanity checks */
3151
3152 if (!tty || !info->xmit.buf || !tmp_buf)
3153 return 0;
3154
3155#ifdef SERIAL_DEBUG_DATA
3156 if (info->line == SERIAL_DEBUG_LINE)
3157 printk("rs_raw_write (%d), status %d\n",
d7283353 3158 count, info->ioport[REG_STATUS]);
1da177e4
LT		 3159#endif
3160
3161#ifdef CONFIG_SVINTO_SIM
3162 /* Really simple. The output is here and now. */
3163 SIMCOUT(buf, count);
3164 return count;
3165#endif
77accbf5 3166 local_save_flags(flags);
1da177e4
LT		 3167 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
3168 DFLOW(DEBUG_LOG(info->line, "ldisc %i\n", tty->ldisc.chars_in_buffer(tty)));
3169
3170
77accbf5
JN		 3171 /* The local_irq_disable/restore_flags pairs below are needed
3172 * because the DMA interrupt handler moves the info->xmit values.
3173 * the memcpy needs to be in the critical region unfortunately,
3174 * because we need to read xmit values, memcpy, write xmit values
3175 * in one atomic operation... this could perhaps be avoided by
3176 * more clever design.
1da177e4 3177 */
77accbf5 3178 local_irq_disable();
1da177e4
LT		 3179 while (count) {
3180 c = CIRC_SPACE_TO_END(info->xmit.head,
3181 info->xmit.tail,
3182 SERIAL_XMIT_SIZE);
3183
3184 if (count < c)
3185 c = count;
3186 if (c <= 0)
3187 break;
3188
3189 memcpy(info->xmit.buf + info->xmit.head, buf, c);
3190 info->xmit.head = (info->xmit.head + c) &
3191 (SERIAL_XMIT_SIZE-1);
3192 buf += c;
3193 count -= c;
3194 ret += c;
3195 }
77accbf5 3196 local_irq_restore(flags);
1da177e4
LT		 3197
3198 /* enable transmitter if not running, unless the tty is stopped
3199 * this does not need IRQ protection since if tr_running == 0
3200 * the IRQ's are not running anyway for this port.
3201 */
3202 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3203
3204 if (info->xmit.head != info->xmit.tail &&
3205 !tty->stopped &&
3206 !tty->hw_stopped &&
3207 !info->tr_running) {
3208 start_transmit(info);
3209 }
3210
3211 return ret;
3212} /* raw_raw_write() */
3213
3214static int
77accbf5 3215rs_write(struct tty_struct *tty,
1da177e4
LT		 3216 const unsigned char *buf, int count)
3217{
3218#if defined(CONFIG_ETRAX_RS485)
3219 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3220
6fd1af4c 3221 if (info->rs485.flags & SER_RS485_ENABLED)
1da177e4
LT		 3222 {
3223 /* If we are in RS-485 mode, we need to toggle RTS and disable
3224 * the receiver before initiating a DMA transfer
3225 */
3226#ifdef CONFIG_ETRAX_FAST_TIMER
3227 /* Abort any started timer */
3228 fast_timers_rs485[info->line].function = NULL;
3229 del_fast_timer(&fast_timers_rs485[info->line]);
3230#endif
6fd1af4c 3231 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND));
1da177e4
LT		 3232#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3233 e100_disable_rx(info);
3234 e100_enable_rx_irq(info);
3235#endif
3236
3237 if (info->rs485.delay_rts_before_send > 0)
3238 msleep(info->rs485.delay_rts_before_send);
3239 }
3240#endif /* CONFIG_ETRAX_RS485 */
3241
77accbf5 3242 count = rs_raw_write(tty, buf, count);
1da177e4
LT		 3243
3244#if defined(CONFIG_ETRAX_RS485)
6fd1af4c 3245 if (info->rs485.flags & SER_RS485_ENABLED)
1da177e4
LT		 3246 {
3247 unsigned int val;
3248 /* If we are in RS-485 mode the following has to be done:
3249 * wait until DMA is ready
3250 * wait on transmit shift register
3251 * toggle RTS
3252 * enable the receiver
3253 */
3254
3255 /* Sleep until all sent */
3256 tty_wait_until_sent(tty, 0);
3257#ifdef CONFIG_ETRAX_FAST_TIMER
3258 /* Now sleep a little more so that shift register is empty */
3259 schedule_usleep(info->char_time_usec * 2);
3260#endif
3261 /* wait on transmit shift register */
3262 do{
3263 get_lsr_info(info, &val);
3264 }while (!(val & TIOCSER_TEMT));
3265
6fd1af4c 3266 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1da177e4
LT		 3267
3268#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3269 e100_enable_rx(info);
3270 e100_enable_rxdma_irq(info);
3271#endif
3272 }
3273#endif /* CONFIG_ETRAX_RS485 */
3274
3275 return count;
3276} /* rs_write */
3277
3278
3279/* how much space is available in the xmit buffer? */
3280
3281static int
3282rs_write_room(struct tty_struct *tty)
3283{
3284 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3285
3286 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3287}
3288
3289/* How many chars are in the xmit buffer?
3290 * This does not include any chars in the transmitter FIFO.
3291 * Use wait_until_sent for waiting for FIFO drain.
3292 */
3293
3294static int
3295rs_chars_in_buffer(struct tty_struct *tty)
3296{
3297 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3298
3299 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3300}
3301
3302/* discard everything in the xmit buffer */
3303
3304static void
3305rs_flush_buffer(struct tty_struct *tty)
3306{
3307 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3308 unsigned long flags;
3309
77accbf5 3310 local_irq_save(flags);
1da177e4 3311 info->xmit.head = info->xmit.tail = 0;
77accbf5 3312 local_irq_restore(flags);
1da177e4 3313
b963a844 3314 tty_wakeup(tty);
1da177e4
LT		 3315}
3316
3317/*
3318 * This function is used to send a high-priority XON/XOFF character to
3319 * the device
3320 *
3321 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3322 * but we do it in handle_ser_tx_interrupt().
3323 * We disable DMA channel and enable tx ready interrupt and write the
3324 * character when possible.
3325 */
3326static void rs_send_xchar(struct tty_struct *tty, char ch)
3327{
3328 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3329 unsigned long flags;
77accbf5 3330 local_irq_save(flags);
1da177e4
LT		 3331 if (info->uses_dma_out) {
3332 /* Put the DMA on hold and disable the channel */
3333 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3334 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3335 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3336 e100_disable_txdma_channel(info);
3337 }
3338
3339 /* Must make sure transmitter is not stopped before we can transmit */
3340 if (tty->stopped)
3341 rs_start(tty);
3342
3343 /* Enable manual transmit interrupt and send from there */
3344 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3345 info->x_char = ch;
3346 e100_enable_serial_tx_ready_irq(info);
77accbf5 3347 local_irq_restore(flags);
1da177e4
LT		 3348}
3349
3350/*
3351 * ------------------------------------------------------------
3352 * rs_throttle()
3353 *
3354 * This routine is called by the upper-layer tty layer to signal that
3355 * incoming characters should be throttled.
3356 * ------------------------------------------------------------
3357 */
3358static void
3359rs_throttle(struct tty_struct * tty)
3360{
3361 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3362#ifdef SERIAL_DEBUG_THROTTLE
3363 char buf[64];
3364
3365 printk("throttle %s: %lu....\n", tty_name(tty, buf),
3366 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3367#endif
3368 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty)));
3369
3370 /* Do RTS before XOFF since XOFF might take some time */
3371 if (tty->termios->c_cflag & CRTSCTS) {
3372 /* Turn off RTS line */
3373 e100_rts(info, 0);
3374 }
3375 if (I_IXOFF(tty))
3376 rs_send_xchar(tty, STOP_CHAR(tty));
3377
3378}
3379
3380static void
3381rs_unthrottle(struct tty_struct * tty)
3382{
3383 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3384#ifdef SERIAL_DEBUG_THROTTLE
3385 char buf[64];
3386
3387 printk("unthrottle %s: %lu....\n", tty_name(tty, buf),
3388 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3389#endif
3390 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty)));
3391 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3392 /* Do RTS before XOFF since XOFF might take some time */
3393 if (tty->termios->c_cflag & CRTSCTS) {
3394 /* Assert RTS line */
3395 e100_rts(info, 1);
3396 }
3397
3398 if (I_IXOFF(tty)) {
3399 if (info->x_char)
3400 info->x_char = 0;
3401 else
3402 rs_send_xchar(tty, START_CHAR(tty));
3403 }
3404
3405}
3406
3407/*
3408 * ------------------------------------------------------------
3409 * rs_ioctl() and friends
3410 * ------------------------------------------------------------
3411 */
3412
3413static int
3414get_serial_info(struct e100_serial * info,
3415 struct serial_struct * retinfo)
3416{
3417 struct serial_struct tmp;
3418
3419 /* this is all probably wrong, there are a lot of fields
3420 * here that we don't have in e100_serial and maybe we
3421 * should set them to something else than 0.
3422 */
3423
3424 if (!retinfo)
3425 return -EFAULT;
3426 memset(&tmp, 0, sizeof(tmp));
3427 tmp.type = info->type;
3428 tmp.line = info->line;
d7283353 3429 tmp.port = (int)info->ioport;
1da177e4
LT		 3430 tmp.irq = info->irq;
3431 tmp.flags = info->flags;
3432 tmp.baud_base = info->baud_base;
3433 tmp.close_delay = info->close_delay;
3434 tmp.closing_wait = info->closing_wait;
3435 tmp.custom_divisor = info->custom_divisor;
3436 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3437 return -EFAULT;
3438 return 0;
3439}
3440
3441static int
3442set_serial_info(struct e100_serial *info,
3443 struct serial_struct *new_info)
3444{
3445 struct serial_struct new_serial;
3446 struct e100_serial old_info;
3447 int retval = 0;
3448
3449 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3450 return -EFAULT;
3451
3452 old_info = *info;
3453
3454 if (!capable(CAP_SYS_ADMIN)) {
3455 if ((new_serial.type != info->type) ||
3456 (new_serial.close_delay != info->close_delay) ||
3457 ((new_serial.flags & ~ASYNC_USR_MASK) !=
3458 (info->flags & ~ASYNC_USR_MASK)))
3459 return -EPERM;
3460 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
3461 (new_serial.flags & ASYNC_USR_MASK));
3462 goto check_and_exit;
3463 }
3464
3465 if (info->count > 1)
3466 return -EBUSY;
3467
3468 /*
3469 * OK, past this point, all the error checking has been done.
3470 * At this point, we start making changes.....
3471 */
3472
3473 info->baud_base = new_serial.baud_base;
3474 info->flags = ((info->flags & ~ASYNC_FLAGS) |
3475 (new_serial.flags & ASYNC_FLAGS));
3476 info->custom_divisor = new_serial.custom_divisor;
3477 info->type = new_serial.type;
3478 info->close_delay = new_serial.close_delay;
3479 info->closing_wait = new_serial.closing_wait;
a88487c7 3480 info->port.tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 3481
3482 check_and_exit:
3483 if (info->flags & ASYNC_INITIALIZED) {
3484 change_speed(info);
3485 } else
3486 retval = startup(info);
3487 return retval;
3488}
3489
3490/*
3491 * get_lsr_info - get line status register info
3492 *
3493 * Purpose: Let user call ioctl() to get info when the UART physically
3494 * is emptied. On bus types like RS485, the transmitter must
3495 * release the bus after transmitting. This must be done when
3496 * the transmit shift register is empty, not be done when the
3497 * transmit holding register is empty. This functionality
3498 * allows an RS485 driver to be written in user space.
3499 */
3500static int
3501get_lsr_info(struct e100_serial * info, unsigned int *value)
3502{
3503 unsigned int result = TIOCSER_TEMT;
3504#ifndef CONFIG_SVINTO_SIM
3505 unsigned long curr_time = jiffies;
3506 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3507 unsigned long elapsed_usec =
3508 (curr_time - info->last_tx_active) * 1000000/HZ +
3509 curr_time_usec - info->last_tx_active_usec;
3510
3511 if (info->xmit.head != info->xmit.tail ||
3512 elapsed_usec < 2*info->char_time_usec) {
3513 result = 0;
3514 }
3515#endif
3516
3517 if (copy_to_user(value, &result, sizeof(int)))
3518 return -EFAULT;
3519 return 0;
3520}
3521
3522#ifdef SERIAL_DEBUG_IO
3523struct state_str
3524{
3525 int state;
3526 const char *str;
3527};
3528
3529const struct state_str control_state_str[] = {
3530 {TIOCM_DTR, "DTR" },
3531 {TIOCM_RTS, "RTS"},
3532 {TIOCM_ST, "ST?" },
3533 {TIOCM_SR, "SR?" },
3534 {TIOCM_CTS, "CTS" },
3535 {TIOCM_CD, "CD" },
3536 {TIOCM_RI, "RI" },
3537 {TIOCM_DSR, "DSR" },
3538 {0, NULL }
3539};
3540
3541char *get_control_state_str(int MLines, char *s)
3542{
3543 int i = 0;
3544
3545 s[0]='\0';
3546 while (control_state_str[i].str != NULL) {
3547 if (MLines & control_state_str[i].state) {
3548 if (s[0] != '\0') {
3549 strcat(s, ", ");
3550 }
3551 strcat(s, control_state_str[i].str);
3552 }
3553 i++;
3554 }
3555 return s;
3556}
3557#endif
3558
d7283353 3559static int
77accbf5
JN		 3560rs_break(struct tty_struct *tty, int break_state)
3561{
3562 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3563 unsigned long flags;
3564
d7283353
AC		 3565 if (!info->ioport)
3566 return -EIO;
77accbf5
JN		 3567
3568 local_irq_save(flags);
3569 if (break_state == -1) {
3570 /* Go to manual mode and set the txd pin to 0 */
3571 /* Clear bit 7 (txd) and 6 (tr_enable) */
3572 info->tx_ctrl &= 0x3F;
3573 } else {
3574 /* Set bit 7 (txd) and 6 (tr_enable) */
3575 info->tx_ctrl |= (0x80 | 0x40);
3576 }
d7283353 3577 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
77accbf5 3578 local_irq_restore(flags);
d7283353 3579 return 0;
77accbf5
JN		 3580}
3581
1da177e4 3582static int
77accbf5
JN		 3583rs_tiocmset(struct tty_struct *tty, struct file *file,
3584 unsigned int set, unsigned int clear)
1da177e4 3585{
77accbf5 3586 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
978e595f 3587 unsigned long flags;
1da177e4 3588
978e595f 3589 local_irq_save(flags);
032c17e8 3590
77accbf5
JN		 3591 if (clear & TIOCM_RTS)
3592 e100_rts(info, 0);
3593 if (clear & TIOCM_DTR)
3594 e100_dtr(info, 0);
3595 /* Handle FEMALE behaviour */
3596 if (clear & TIOCM_RI)
3597 e100_ri_out(info, 0);
3598 if (clear & TIOCM_CD)
3599 e100_cd_out(info, 0);
3600
3601 if (set & TIOCM_RTS)
3602 e100_rts(info, 1);
3603 if (set & TIOCM_DTR)
3604 e100_dtr(info, 1);
3605 /* Handle FEMALE behaviour */
3606 if (set & TIOCM_RI)
3607 e100_ri_out(info, 1);
3608 if (set & TIOCM_CD)
3609 e100_cd_out(info, 1);
032c17e8 3610
978e595f 3611 local_irq_restore(flags);
77accbf5
JN		 3612 return 0;
3613}
3614
3615static int
3616rs_tiocmget(struct tty_struct *tty, struct file *file)
3617{
3618 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3619 unsigned int result;
978e595f
AC		 3620 unsigned long flags;
3621
3622 local_irq_save(flags);
1da177e4
LT		 3623
3624 result =
3625 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3626 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3627 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3628 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3629 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3630 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3631
978e595f 3632 local_irq_restore(flags);
032c17e8 3633
1da177e4 3634#ifdef SERIAL_DEBUG_IO
77accbf5
JN		 3635 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3636 info->line, result, result);
1da177e4
LT		 3637 {
3638 char s[100];
3639
3640 get_control_state_str(result, s);
77accbf5 3641 printk(KERN_DEBUG "state: %s\n", s);
1da177e4
LT		 3642 }
3643#endif
77accbf5 3644 return result;
1da177e4 3645
1da177e4
LT		 3646}
3647
3648
1da177e4
LT		 3649static int
3650rs_ioctl(struct tty_struct *tty, struct file * file,
3651 unsigned int cmd, unsigned long arg)
3652{
3653 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3654
3655 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3656 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3657 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
3658 if (tty->flags & (1 << TTY_IO_ERROR))
3659 return -EIO;
3660 }
3661
3662 switch (cmd) {
77accbf5
JN		 3663 case TIOCGSERIAL:
3664 return get_serial_info(info,
3665 (struct serial_struct *) arg);
3666 case TIOCSSERIAL:
3667 return set_serial_info(info,
3668 (struct serial_struct *) arg);
3669 case TIOCSERGETLSR: /* Get line status register */
3670 return get_lsr_info(info, (unsigned int *) arg);
3671
3672 case TIOCSERGSTRUCT:
3673 if (copy_to_user((struct e100_serial *) arg,
3674 info, sizeof(struct e100_serial)))
3675 return -EFAULT;
3676 return 0;
1da177e4
LT		 3677
3678#if defined(CONFIG_ETRAX_RS485)
77accbf5
JN		 3679 case TIOCSERSETRS485:
3680 {
6fd1af4c
CS		 3681 /* In this ioctl we still use the old structure
3682 * rs485_control for backward compatibility
3683 * (if we use serial_rs485, then old user-level code
3684 * wouldn't work anymore...).
3685 * The use of this ioctl is deprecated: use TIOCSRS485
3686 * instead.*/
77accbf5 3687 struct rs485_control rs485ctrl;
6fd1af4c
CS		 3688 struct serial_rs485 rs485data;
3689 printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n");
77accbf5
JN		 3690 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3691 sizeof(rs485ctrl)))
3692 return -EFAULT;
1da177e4 3693
6fd1af4c
CS		 3694 rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send;
3695 rs485data.flags = 0;
3696 if (rs485ctrl.enabled)
3697 rs485data.flags |= SER_RS485_ENABLED;
3698 else
3699 rs485data.flags &= ~(SER_RS485_ENABLED);
3700
3701 if (rs485ctrl.rts_on_send)
3702 rs485data.flags |= SER_RS485_RTS_ON_SEND;
3703 else
3704 rs485data.flags &= ~(SER_RS485_RTS_ON_SEND);
3705
3706 if (rs485ctrl.rts_after_sent)
3707 rs485data.flags |= SER_RS485_RTS_AFTER_SEND;
3708 else
3709 rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND);
3710
3711 return e100_enable_rs485(tty, &rs485data);
77accbf5 3712 }
1da177e4 3713
6fd1af4c
CS		 3714 case TIOCSRS485:
3715 {
3716 /* This is the new version of TIOCSRS485, with new
3717 * data structure serial_rs485 */
3718 struct serial_rs485 rs485data;
3719 if (copy_from_user(&rs485data, (struct rs485_control *)arg,
3720 sizeof(rs485data)))
3721 return -EFAULT;
3722
3723 return e100_enable_rs485(tty, &rs485data);
3724 }
3725
3726
77accbf5
JN		 3727 case TIOCSERWRRS485:
3728 {
3729 struct rs485_write rs485wr;
3730 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3731 sizeof(rs485wr)))
3732 return -EFAULT;
1da177e4 3733
77accbf5
JN		 3734 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3735 }
1da177e4
LT		 3736#endif
3737
77accbf5
JN		 3738 default:
3739 return -ENOIOCTLCMD;
1da177e4
LT		 3740 }
3741 return 0;
3742}
3743
3744static void
606d099c 3745rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4
LT		 3746{
3747 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3748
1da177e4
LT		 3749 change_speed(info);
3750
3751 /* Handle turning off CRTSCTS */
3752 if ((old_termios->c_cflag & CRTSCTS) &&
3753 !(tty->termios->c_cflag & CRTSCTS)) {
3754 tty->hw_stopped = 0;
3755 rs_start(tty);
3756 }
3757
3758}
3759
1da177e4
LT		 3760/*
3761 * ------------------------------------------------------------
3762 * rs_close()
3763 *
3764 * This routine is called when the serial port gets closed. First, we
3765 * wait for the last remaining data to be sent. Then, we unlink its
3766 * S structure from the interrupt chain if necessary, and we free
3767 * that IRQ if nothing is left in the chain.
3768 * ------------------------------------------------------------
3769 */
3770static void
3771rs_close(struct tty_struct *tty, struct file * filp)
3772{
3773 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3774 unsigned long flags;
3775
3776 if (!info)
3777 return;
3778
3779 /* interrupts are disabled for this entire function */
3780
77accbf5 3781 local_irq_save(flags);
1da177e4
LT		 3782
3783 if (tty_hung_up_p(filp)) {
77accbf5 3784 local_irq_restore(flags);
1da177e4
LT		 3785 return;
3786 }
3787
3788#ifdef SERIAL_DEBUG_OPEN
3789 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3790 info->line, info->count);
3791#endif
3792 if ((tty->count == 1) && (info->count != 1)) {
3793 /*
3794 * Uh, oh. tty->count is 1, which means that the tty
3795 * structure will be freed. Info->count should always
3796 * be one in these conditions. If it's greater than
3797 * one, we've got real problems, since it means the
3798 * serial port won't be shutdown.
3799 */
3800 printk(KERN_CRIT
3801 "rs_close: bad serial port count; tty->count is 1, "
3802 "info->count is %d\n", info->count);
3803 info->count = 1;
3804 }
3805 if (--info->count < 0) {
3806 printk(KERN_CRIT "rs_close: bad serial port count for ttyS%d: %d\n",
3807 info->line, info->count);
3808 info->count = 0;
3809 }
3810 if (info->count) {
77accbf5 3811 local_irq_restore(flags);
1da177e4
LT		 3812 return;
3813 }
3814 info->flags |= ASYNC_CLOSING;
3815 /*
3816 * Save the termios structure, since this port may have
3817 * separate termios for callout and dialin.
3818 */
3819 if (info->flags & ASYNC_NORMAL_ACTIVE)
3820 info->normal_termios = *tty->termios;
3821 /*
3822 * Now we wait for the transmit buffer to clear; and we notify
3823 * the line discipline to only process XON/XOFF characters.
3824 */
3825 tty->closing = 1;
3826 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
3827 tty_wait_until_sent(tty, info->closing_wait);
3828 /*
3829 * At this point we stop accepting input. To do this, we
3830 * disable the serial receiver and the DMA receive interrupt.
3831 */
3832#ifdef SERIAL_HANDLE_EARLY_ERRORS
3833 e100_disable_serial_data_irq(info);
3834#endif
3835
3836#ifndef CONFIG_SVINTO_SIM
3837 e100_disable_rx(info);
3838 e100_disable_rx_irq(info);
3839
3840 if (info->flags & ASYNC_INITIALIZED) {
3841 /*
3842 * Before we drop DTR, make sure the UART transmitter
3843 * has completely drained; this is especially
3844 * important as we have a transmit FIFO!
3845 */
3846 rs_wait_until_sent(tty, HZ);
3847 }
3848#endif
3849
3850 shutdown(info);
978e595f 3851 rs_flush_buffer(tty);
454aa389 3852 tty_ldisc_flush(tty);
1da177e4
LT		 3853 tty->closing = 0;
3854 info->event = 0;
a88487c7 3855 info->port.tty = NULL;
1da177e4 3856 if (info->blocked_open) {
3c76bc5b
NA		 3857 if (info->close_delay)
3858 schedule_timeout_interruptible(info->close_delay);
1da177e4
LT		 3859 wake_up_interruptible(&info->open_wait);
3860 }
3861 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3862 wake_up_interruptible(&info->close_wait);
77accbf5 3863 local_irq_restore(flags);
1da177e4
LT		 3864
3865 /* port closed */
3866
3867#if defined(CONFIG_ETRAX_RS485)
6fd1af4c
CS		 3868 if (info->rs485.flags & SER_RS485_ENABLED) {
3869 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4
LT		 3870#if defined(CONFIG_ETRAX_RS485_ON_PA)
3871 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
3872#endif
3873#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
3874 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3875 rs485_port_g_bit, 0);
3876#endif
3877#if defined(CONFIG_ETRAX_RS485_LTC1387)
3878 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3879 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 0);
3880 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3881 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 0);
3882#endif
3883 }
3884#endif
77accbf5
JN		 3885
3886 /*
3887 * Release any allocated DMA irq's.
3888 */
3889 if (info->dma_in_enabled) {
3890 free_irq(info->dma_in_irq_nbr, info);
3891 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3892 info->uses_dma_in = 0;
3893#ifdef SERIAL_DEBUG_OPEN
3894 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3895 info->dma_in_irq_description);
3896#endif
3897 }
3898 if (info->dma_out_enabled) {
3899 free_irq(info->dma_out_irq_nbr, info);
3900 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3901 info->uses_dma_out = 0;
3902#ifdef SERIAL_DEBUG_OPEN
3903 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3904 info->dma_out_irq_description);
3905#endif
3906 }
1da177e4
LT		 3907}
3908
3909/*
3910 * rs_wait_until_sent() --- wait until the transmitter is empty
3911 */
3912static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3913{
3914 unsigned long orig_jiffies;
3915 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3916 unsigned long curr_time = jiffies;
3917 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3918 long elapsed_usec =
3919 (curr_time - info->last_tx_active) * (1000000/HZ) +
3920 curr_time_usec - info->last_tx_active_usec;
3921
3922 /*
3923 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3924 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3925 */
978e595f 3926 lock_kernel();
1da177e4
LT		 3927 orig_jiffies = jiffies;
3928 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3929 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3930 (elapsed_usec < 2*info->char_time_usec)) {
3c76bc5b 3931 schedule_timeout_interruptible(1);
1da177e4
LT		 3932 if (signal_pending(current))
3933 break;
3934 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3935 break;
3936 curr_time = jiffies;
3937 curr_time_usec = GET_JIFFIES_USEC();
3938 elapsed_usec =
3939 (curr_time - info->last_tx_active) * (1000000/HZ) +
3940 curr_time_usec - info->last_tx_active_usec;
3941 }
3942 set_current_state(TASK_RUNNING);
978e595f 3943 unlock_kernel();
1da177e4
LT		 3944}
3945
3946/*
3947 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3948 */
3949void
3950rs_hangup(struct tty_struct *tty)
3951{
3952 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3953
3954 rs_flush_buffer(tty);
3955 shutdown(info);
3956 info->event = 0;
3957 info->count = 0;
3958 info->flags &= ~ASYNC_NORMAL_ACTIVE;
a88487c7 3959 info->port.tty = NULL;
1da177e4
LT		 3960 wake_up_interruptible(&info->open_wait);
3961}
3962
3963/*
3964 * ------------------------------------------------------------
3965 * rs_open() and friends
3966 * ------------------------------------------------------------
3967 */
3968static int
3969block_til_ready(struct tty_struct *tty, struct file * filp,
3970 struct e100_serial *info)
3971{
3972 DECLARE_WAITQUEUE(wait, current);
3973 unsigned long flags;
3974 int retval;
3975 int do_clocal = 0, extra_count = 0;
3976
3977 /*
3978 * If the device is in the middle of being closed, then block
3979 * until it's done, and then try again.
3980 */
3981 if (tty_hung_up_p(filp) ||
3982 (info->flags & ASYNC_CLOSING)) {
77accbf5
JN		 3983 wait_event_interruptible(info->close_wait,
3984 !(info->flags & ASYNC_CLOSING));
1da177e4
LT		 3985#ifdef SERIAL_DO_RESTART
3986 if (info->flags & ASYNC_HUP_NOTIFY)
3987 return -EAGAIN;
3988 else
3989 return -ERESTARTSYS;
3990#else
3991 return -EAGAIN;
3992#endif
3993 }
3994
3995 /*
3996 * If non-blocking mode is set, or the port is not enabled,
3997 * then make the check up front and then exit.
3998 */
3999 if ((filp->f_flags & O_NONBLOCK) ||
4000 (tty->flags & (1 << TTY_IO_ERROR))) {
4001 info->flags |= ASYNC_NORMAL_ACTIVE;
4002 return 0;
4003 }
4004
4005 if (tty->termios->c_cflag & CLOCAL) {
4006 do_clocal = 1;
4007 }
4008
4009 /*
4010 * Block waiting for the carrier detect and the line to become
4011 * free (i.e., not in use by the callout). While we are in
4012 * this loop, info->count is dropped by one, so that
4013 * rs_close() knows when to free things. We restore it upon
4014 * exit, either normal or abnormal.
4015 */
4016 retval = 0;
4017 add_wait_queue(&info->open_wait, &wait);
4018#ifdef SERIAL_DEBUG_OPEN
4019 printk("block_til_ready before block: ttyS%d, count = %d\n",
4020 info->line, info->count);
4021#endif
77accbf5 4022 local_irq_save(flags);
1da177e4
LT		 4023 if (!tty_hung_up_p(filp)) {
4024 extra_count++;
4025 info->count--;
4026 }
77accbf5 4027 local_irq_restore(flags);
1da177e4
LT		 4028 info->blocked_open++;
4029 while (1) {
77accbf5 4030 local_irq_save(flags);
1da177e4
LT		 4031 /* assert RTS and DTR */
4032 e100_rts(info, 1);
4033 e100_dtr(info, 1);
77accbf5 4034 local_irq_restore(flags);
1da177e4
LT		 4035 set_current_state(TASK_INTERRUPTIBLE);
4036 if (tty_hung_up_p(filp) ||
4037 !(info->flags & ASYNC_INITIALIZED)) {
4038#ifdef SERIAL_DO_RESTART
4039 if (info->flags & ASYNC_HUP_NOTIFY)
4040 retval = -EAGAIN;
4041 else
4042 retval = -ERESTARTSYS;
4043#else
4044 retval = -EAGAIN;
4045#endif
4046 break;
4047 }
4048 if (!(info->flags & ASYNC_CLOSING) && do_clocal)
4049 /* && (do_clocal || DCD_IS_ASSERTED) */
4050 break;
4051 if (signal_pending(current)) {
4052 retval = -ERESTARTSYS;
4053 break;
4054 }
4055#ifdef SERIAL_DEBUG_OPEN
4056 printk("block_til_ready blocking: ttyS%d, count = %d\n",
4057 info->line, info->count);
4058#endif
4059 schedule();
4060 }
4061 set_current_state(TASK_RUNNING);
4062 remove_wait_queue(&info->open_wait, &wait);
4063 if (extra_count)
4064 info->count++;
4065 info->blocked_open--;
4066#ifdef SERIAL_DEBUG_OPEN
4067 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
4068 info->line, info->count);
4069#endif
4070 if (retval)
4071 return retval;
4072 info->flags |= ASYNC_NORMAL_ACTIVE;
4073 return 0;
4074}
4075
77accbf5
JN		 4076static void
4077deinit_port(struct e100_serial *info)
4078{
4079 if (info->dma_out_enabled) {
4080 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
4081 free_irq(info->dma_out_irq_nbr, info);
4082 }
4083 if (info->dma_in_enabled) {
4084 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
4085 free_irq(info->dma_in_irq_nbr, info);
4086 }
4087}
4088
1da177e4
LT		 4089/*
4090 * This routine is called whenever a serial port is opened.
4091 * It performs the serial-specific initialization for the tty structure.
4092 */
4093static int
4094rs_open(struct tty_struct *tty, struct file * filp)
4095{
4096 struct e100_serial *info;
4097 int retval, line;
4098 unsigned long page;
77accbf5 4099 int allocated_resources = 0;
1da177e4
LT		 4100
4101 /* find which port we want to open */
1da177e4
LT		 4102 line = tty->index;
4103
4104 if (line < 0 || line >= NR_PORTS)
4105 return -ENODEV;
4106
4107 /* find the corresponding e100_serial struct in the table */
4108 info = rs_table + line;
4109
4110 /* don't allow the opening of ports that are not enabled in the HW config */
4111 if (!info->enabled)
4112 return -ENODEV;
4113
4114#ifdef SERIAL_DEBUG_OPEN
4115 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
4116 info->count);
4117#endif
4118
4119 info->count++;
4120 tty->driver_data = info;
a88487c7 4121 info->port.tty = tty;
1da177e4 4122
a88487c7 4123 info->port.tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 4124
4125 if (!tmp_buf) {
4126 page = get_zeroed_page(GFP_KERNEL);
4127 if (!page) {
4128 return -ENOMEM;
4129 }
4130 if (tmp_buf)
4131 free_page(page);
4132 else
4133 tmp_buf = (unsigned char *) page;
4134 }
4135
4136 /*
4137 * If the port is in the middle of closing, bail out now
4138 */
4139 if (tty_hung_up_p(filp) ||
4140 (info->flags & ASYNC_CLOSING)) {
77accbf5
JN		 4141 wait_event_interruptible(info->close_wait,
4142 !(info->flags & ASYNC_CLOSING));
1da177e4
LT		 4143#ifdef SERIAL_DO_RESTART
4144 return ((info->flags & ASYNC_HUP_NOTIFY) ?
4145 -EAGAIN : -ERESTARTSYS);
4146#else
4147 return -EAGAIN;
4148#endif
4149 }
4150
77accbf5
JN		 4151 /*
4152 * If DMA is enabled try to allocate the irq's.
4153 */
4154 if (info->count == 1) {
4155 allocated_resources = 1;
4156 if (info->dma_in_enabled) {
4157 if (request_irq(info->dma_in_irq_nbr,
4158 rec_interrupt,
4159 info->dma_in_irq_flags,
4160 info->dma_in_irq_description,
4161 info)) {
4162 printk(KERN_WARNING "DMA irq '%s' busy; "
4163 "falling back to non-DMA mode\n",
4164 info->dma_in_irq_description);
4165 /* Make sure we never try to use DMA in */
4166 /* for the port again. */
4167 info->dma_in_enabled = 0;
4168 } else if (cris_request_dma(info->dma_in_nbr,
4169 info->dma_in_irq_description,
4170 DMA_VERBOSE_ON_ERROR,
4171 info->dma_owner)) {
4172 free_irq(info->dma_in_irq_nbr, info);
4173 printk(KERN_WARNING "DMA '%s' busy; "
4174 "falling back to non-DMA mode\n",
4175 info->dma_in_irq_description);
4176 /* Make sure we never try to use DMA in */
4177 /* for the port again. */
4178 info->dma_in_enabled = 0;
4179 }
4180#ifdef SERIAL_DEBUG_OPEN
4181 else
4182 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4183 info->dma_in_irq_description);
4184#endif
4185 }
4186 if (info->dma_out_enabled) {
4187 if (request_irq(info->dma_out_irq_nbr,
4188 tr_interrupt,
4189 info->dma_out_irq_flags,
4190 info->dma_out_irq_description,
4191 info)) {
4192 printk(KERN_WARNING "DMA irq '%s' busy; "
4193 "falling back to non-DMA mode\n",
4194 info->dma_out_irq_description);
4195 /* Make sure we never try to use DMA out */
4196 /* for the port again. */
4197 info->dma_out_enabled = 0;
4198 } else if (cris_request_dma(info->dma_out_nbr,
4199 info->dma_out_irq_description,
4200 DMA_VERBOSE_ON_ERROR,
4201 info->dma_owner)) {
4202 free_irq(info->dma_out_irq_nbr, info);
4203 printk(KERN_WARNING "DMA '%s' busy; "
4204 "falling back to non-DMA mode\n",
4205 info->dma_out_irq_description);
4206 /* Make sure we never try to use DMA out */
4207 /* for the port again. */
4208 info->dma_out_enabled = 0;
4209 }
4210#ifdef SERIAL_DEBUG_OPEN
4211 else
4212 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4213 info->dma_out_irq_description);
4214#endif
4215 }
4216 }
4217
1da177e4
LT		 4218 /*
4219 * Start up the serial port
4220 */
4221
4222 retval = startup(info);
77accbf5
JN		 4223 if (retval) {
4224 if (allocated_resources)
4225 deinit_port(info);
4226
4227 /* FIXME Decrease count info->count here too? */
1da177e4 4228 return retval;
77accbf5
JN		 4229 }
4230
1da177e4
LT		 4231
4232 retval = block_til_ready(tty, filp, info);
4233 if (retval) {
4234#ifdef SERIAL_DEBUG_OPEN
4235 printk("rs_open returning after block_til_ready with %d\n",
4236 retval);
4237#endif
77accbf5
JN		 4238 if (allocated_resources)
4239 deinit_port(info);
4240
1da177e4
LT		 4241 return retval;
4242 }
4243
4244 if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) {
4245 *tty->termios = info->normal_termios;
4246 change_speed(info);
4247 }
4248
4249#ifdef SERIAL_DEBUG_OPEN
4250 printk("rs_open ttyS%d successful...\n", info->line);
4251#endif
4252 DLOG_INT_TRIG( log_int_pos = 0);
4253
4254 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
4255 info->icount.rx = 0;
4256 } );
4257
4258 return 0;
4259}
4260
9e040a3e 4261#ifdef CONFIG_PROC_FS
1da177e4
LT		 4262/*
4263 * /proc fs routines....
4264 */
4265
9e040a3e 4266static void seq_line_info(struct seq_file *m, struct e100_serial *info)
1da177e4 4267{
1da177e4
LT		 4268 unsigned long tmp;
4269
9e040a3e
JN		 4270 seq_printf(m, "%d: uart:E100 port:%lX irq:%d",
4271 info->line, (unsigned long)info->ioport, info->irq);
1da177e4 4272
d7283353 4273 if (!info->ioport || (info->type == PORT_UNKNOWN)) {
9e040a3e
JN		 4274 seq_printf(m, "\n");
4275 return;
1da177e4
LT		 4276 }
4277
9e040a3e
JN		 4278 seq_printf(m, " baud:%d", info->baud);
4279 seq_printf(m, " tx:%lu rx:%lu",
1da177e4
LT		 4280 (unsigned long)info->icount.tx,
4281 (unsigned long)info->icount.rx);
4282 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
9e040a3e
JN		 4283 if (tmp)
4284 seq_printf(m, " tx_pend:%lu/%lu",
4285 (unsigned long)tmp,
4286 (unsigned long)SERIAL_XMIT_SIZE);
1da177e4 4287
9e040a3e
JN		 4288 seq_printf(m, " rx_pend:%lu/%lu",
4289 (unsigned long)info->recv_cnt,
4290 (unsigned long)info->max_recv_cnt);
1da177e4
LT		 4291
4292#if 1
a88487c7 4293 if (info->port.tty) {
a88487c7 4294 if (info->port.tty->stopped)
9e040a3e
JN		 4295 seq_printf(m, " stopped:%i",
4296 (int)info->port.tty->stopped);
a88487c7 4297 if (info->port.tty->hw_stopped)
9e040a3e
JN		 4298 seq_printf(m, " hw_stopped:%i",
4299 (int)info->port.tty->hw_stopped);
1da177e4
LT		 4300 }
4301
4302 {
d7283353 4303 unsigned char rstat = info->ioport[REG_STATUS];
9e040a3e
JN		 4304 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))
4305 seq_printf(m, " xoff_detect:1");
1da177e4
LT		 4306 }
4307
4308#endif
4309
1da177e4 4310 if (info->icount.frame)
9e040a3e 4311 seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame);
1da177e4
LT		 4312
4313 if (info->icount.parity)
9e040a3e 4314 seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity);
1da177e4
LT		 4315
4316 if (info->icount.brk)
9e040a3e 4317 seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk);
1da177e4
LT		 4318
4319 if (info->icount.overrun)
9e040a3e 4320 seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun);
1da177e4
LT		 4321
4322 /*
4323 * Last thing is the RS-232 status lines
4324 */
9e040a3e
JN		 4325 if (!E100_RTS_GET(info))
4326 seq_puts(m, "|RTS");
4327 if (!E100_CTS_GET(info))
4328 seq_puts(m, "|CTS");
4329 if (!E100_DTR_GET(info))
4330 seq_puts(m, "|DTR");
4331 if (!E100_DSR_GET(info))
4332 seq_puts(m, "|DSR");
4333 if (!E100_CD_GET(info))
4334 seq_puts(m, "|CD");
4335 if (!E100_RI_GET(info))
4336 seq_puts(m, "|RI");
4337 seq_puts(m, "\n");
1da177e4
LT		 4338}
4339
9e040a3e
JN		 4340
4341static int crisv10_proc_show(struct seq_file *m, void *v)
1da177e4 4342{
9e040a3e 4343 int i;
1da177e4 4344
9e040a3e
JN		 4345 seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version);
4346
4347 for (i = 0; i < NR_PORTS; i++) {
1da177e4
LT		 4348 if (!rs_table[i].enabled)
4349 continue;
9e040a3e 4350 seq_line_info(m, &rs_table[i]);
1da177e4
LT		 4351 }
4352#ifdef DEBUG_LOG_INCLUDED
4353 for (i = 0; i < debug_log_pos; i++) {
9e040a3e
JN		 4354 seq_printf(m, "%-4i %lu.%lu ",
4355 i, debug_log[i].time,
4356 timer_data_to_ns(debug_log[i].timer_data));
4357 seq_printf(m, debug_log[i].string, debug_log[i].value);
1da177e4 4358 }
9e040a3e 4359 seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE);
1da177e4
LT		 4360 debug_log_pos = 0;
4361#endif
9e040a3e
JN		 4362 return 0;
4363}
1da177e4 4364
9e040a3e
JN		 4365static int crisv10_proc_open(struct inode *inode, struct file *file)
4366{
4367 return single_open(file, crisv10_proc_show, NULL);
1da177e4
LT		 4368}
4369
9e040a3e
JN		 4370static const struct file_operations crisv10_proc_fops = {
4371 .owner = THIS_MODULE,
4372 .open = crisv10_proc_open,
4373 .read = seq_read,
4374 .llseek = seq_lseek,
4375 .release = single_release,
4376};
4377#endif
4378
4379
1da177e4
LT		 4380/* Finally, routines used to initialize the serial driver. */
4381
9e040a3e 4382static void show_serial_version(void)
1da177e4
LT		 4383{
4384 printk(KERN_INFO
9e040a3e
JN		 4385 "ETRAX 100LX serial-driver %s, "
4386 "(c) 2000-2004 Axis Communications AB\r\n",
1da177e4
LT		 4387 &serial_version[11]); /* "$Revision: x.yy" */
4388}
4389
4390/* rs_init inits the driver at boot (using the module_init chain) */
4391
b68e31d0 4392static const struct tty_operations rs_ops = {
1da177e4
LT		 4393 .open = rs_open,
4394 .close = rs_close,
4395 .write = rs_write,
4396 .flush_chars = rs_flush_chars,
4397 .write_room = rs_write_room,
4398 .chars_in_buffer = rs_chars_in_buffer,
4399 .flush_buffer = rs_flush_buffer,
4400 .ioctl = rs_ioctl,
4401 .throttle = rs_throttle,
4402 .unthrottle = rs_unthrottle,
4403 .set_termios = rs_set_termios,
4404 .stop = rs_stop,
4405 .start = rs_start,
4406 .hangup = rs_hangup,
4407 .break_ctl = rs_break,
4408 .send_xchar = rs_send_xchar,
4409 .wait_until_sent = rs_wait_until_sent,
77accbf5 4410 .tiocmget = rs_tiocmget,
9e040a3e
JN		 4411 .tiocmset = rs_tiocmset,
4412#ifdef CONFIG_PROC_FS
4413 .proc_fops = &crisv10_proc_fops,
4414#endif
1da177e4
LT		 4415};
4416
9e040a3e 4417static int __init rs_init(void)
1da177e4
LT		 4418{
4419 int i;
4420 struct e100_serial *info;
4421 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4422
4423 if (!driver)
4424 return -ENOMEM;
4425
4426 show_serial_version();
4427
4428 /* Setup the timed flush handler system */
4429
4430#if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
77accbf5
JN		 4431 setup_timer(&flush_timer, timed_flush_handler, 0);
4432 mod_timer(&flush_timer, jiffies + 5);
4433#endif
4434
4435#if defined(CONFIG_ETRAX_RS485)
4436#if defined(CONFIG_ETRAX_RS485_ON_PA)
4437 if (cris_io_interface_allocate_pins(if_ser0, 'a', rs485_pa_bit,
4438 rs485_pa_bit)) {
4439 printk(KERN_CRIT "ETRAX100LX serial: Could not allocate "
4440 "RS485 pin\n");
41ca7322 4441 put_tty_driver(driver);
77accbf5
JN		 4442 return -EBUSY;
4443 }
4444#endif
4445#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
4446 if (cris_io_interface_allocate_pins(if_ser0, 'g', rs485_pa_bit,
4447 rs485_port_g_bit)) {
4448 printk(KERN_CRIT "ETRAX100LX serial: Could not allocate "
4449 "RS485 pin\n");
41ca7322 4450 put_tty_driver(driver);
77accbf5
JN		 4451 return -EBUSY;
4452 }
4453#endif
1da177e4
LT		 4454#endif
4455
4456 /* Initialize the tty_driver structure */
4457
4458 driver->driver_name = "serial";
4459 driver->name = "ttyS";
4460 driver->major = TTY_MAJOR;
4461 driver->minor_start = 64;
4462 driver->type = TTY_DRIVER_TYPE_SERIAL;
4463 driver->subtype = SERIAL_TYPE_NORMAL;
4464 driver->init_termios = tty_std_termios;
4465 driver->init_termios.c_cflag =
4466 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
606d099c
AC		 4467 driver->init_termios.c_ispeed = 115200;
4468 driver->init_termios.c_ospeed = 115200;
331b8319 4469 driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 4470
4471 tty_set_operations(driver, &rs_ops);
4472 serial_driver = driver;
4473 if (tty_register_driver(driver))
4474 panic("Couldn't register serial driver\n");
4475 /* do some initializing for the separate ports */
4476
4477 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
77accbf5
JN		 4478 if (info->enabled) {
4479 if (cris_request_io_interface(info->io_if,
4480 info->io_if_description)) {
4481 printk(KERN_CRIT "ETRAX100LX async serial: "
4482 "Could not allocate IO pins for "
4483 "%s, port %d\n",
4484 info->io_if_description, i);
4485 info->enabled = 0;
4486 }
4487 }
1da177e4
LT		 4488 info->uses_dma_in = 0;
4489 info->uses_dma_out = 0;
4490 info->line = i;
a88487c7 4491 info->port.tty = NULL;
1da177e4
LT		 4492 info->type = PORT_ETRAX;
4493 info->tr_running = 0;
4494 info->forced_eop = 0;
4495 info->baud_base = DEF_BAUD_BASE;
4496 info->custom_divisor = 0;
4497 info->flags = 0;
4498 info->close_delay = 5*HZ/10;
4499 info->closing_wait = 30*HZ;
4500 info->x_char = 0;
4501 info->event = 0;
4502 info->count = 0;
4503 info->blocked_open = 0;
4504 info->normal_termios = driver->init_termios;
4505 init_waitqueue_head(&info->open_wait);
4506 init_waitqueue_head(&info->close_wait);
4507 info->xmit.buf = NULL;
4508 info->xmit.tail = info->xmit.head = 0;
4509 info->first_recv_buffer = info->last_recv_buffer = NULL;
4510 info->recv_cnt = info->max_recv_cnt = 0;
4511 info->last_tx_active_usec = 0;
4512 info->last_tx_active = 0;
4513
4514#if defined(CONFIG_ETRAX_RS485)
4515 /* Set sane defaults */
6fd1af4c
CS		 4516 info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND);
4517 info->rs485.flags |= SER_RS485_RTS_AFTER_SEND;
1da177e4 4518 info->rs485.delay_rts_before_send = 0;
6fd1af4c 4519 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4 4520#endif
77accbf5 4521 INIT_WORK(&info->work, do_softint);
1da177e4
LT		 4522
4523 if (info->enabled) {
4524 printk(KERN_INFO "%s%d at 0x%x is a builtin UART with DMA\n",
d7283353 4525 serial_driver->name, info->line, (unsigned int)info->ioport);
1da177e4
LT		 4526 }
4527 }
4528#ifdef CONFIG_ETRAX_FAST_TIMER
4529#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4530 memset(fast_timers, 0, sizeof(fast_timers));
4531#endif
4532#ifdef CONFIG_ETRAX_RS485
4533 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4534#endif
4535 fast_timer_init();
4536#endif
4537
4538#ifndef CONFIG_SVINTO_SIM
77accbf5 4539#ifndef CONFIG_ETRAX_KGDB
1da177e4
LT		 4540 /* Not needed in simulator. May only complicate stuff. */
4541 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4542
77accbf5
JN		 4543 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
4544 IRQF_SHARED | IRQF_DISABLED, "serial ", driver))
71cc2c21 4545 panic("%s: Failed to request irq8", __func__);
1da177e4 4546
1da177e4
LT		 4547#endif
4548#endif /* CONFIG_SVINTO_SIM */
77accbf5 4549
1da177e4
LT		 4550 return 0;
4551}
4552
4553/* this makes sure that rs_init is called during kernel boot */
4554
4555module_init(rs_init);
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