[linux.git] / drivers / serial / clps711x.c

/*
 *  linux/drivers/char/clps711x.c
 *
 *  Driver for CLPS711x serial ports
 *
 *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
 *
 *  Copyright 1999 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
#endif

#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/hardware/clps7111.h>

#define UART_NR		2

#define SERIAL_CLPS711X_MAJOR	204
#define SERIAL_CLPS711X_MINOR	40
#define SERIAL_CLPS711X_NR	UART_NR

/*
 * We use the relevant SYSCON register as a base address for these ports.
 */
#define UBRLCR(port)		((port)->iobase + UBRLCR1 - SYSCON1)
#define UARTDR(port)		((port)->iobase + UARTDR1 - SYSCON1)
#define SYSFLG(port)		((port)->iobase + SYSFLG1 - SYSCON1)
#define SYSCON(port)		((port)->iobase + SYSCON1 - SYSCON1)

#define TX_IRQ(port)		((port)->irq)
#define RX_IRQ(port)		((port)->irq + 1)

#define UART_ANY_ERR		(UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR)

#define tx_enabled(port)	((port)->unused[0])

static void clps711xuart_stop_tx(struct uart_port *port)
{
	if (tx_enabled(port)) {
		disable_irq(TX_IRQ(port));
		tx_enabled(port) = 0;
	}
}

static void clps711xuart_start_tx(struct uart_port *port)
{
	if (!tx_enabled(port)) {
		enable_irq(TX_IRQ(port));
		tx_enabled(port) = 1;
	}
}

static void clps711xuart_stop_rx(struct uart_port *port)
{
	disable_irq(RX_IRQ(port));
}

static void clps711xuart_enable_ms(struct uart_port *port)
{
}

static irqreturn_t clps711xuart_int_rx(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	struct tty_struct *tty = port->info->port.tty;
	unsigned int status, ch, flg;

	status = clps_readl(SYSFLG(port));
	while (!(status & SYSFLG_URXFE)) {
		ch = clps_readl(UARTDR(port));

		port->icount.rx++;

		flg = TTY_NORMAL;

		/*
		 * Note that the error handling code is
		 * out of the main execution path
		 */
		if (unlikely(ch & UART_ANY_ERR)) {
			if (ch & UARTDR_PARERR)
				port->icount.parity++;
			else if (ch & UARTDR_FRMERR)
				port->icount.frame++;
			if (ch & UARTDR_OVERR)
				port->icount.overrun++;

			ch &= port->read_status_mask;

			if (ch & UARTDR_PARERR)
				flg = TTY_PARITY;
			else if (ch & UARTDR_FRMERR)
				flg = TTY_FRAME;

#ifdef SUPPORT_SYSRQ
			port->sysrq = 0;
#endif
		}

		if (uart_handle_sysrq_char(port, ch))
			goto ignore_char;

		/*
		 * CHECK: does overrun affect the current character?
		 * ASSUMPTION: it does not.
		 */
		uart_insert_char(port, ch, UARTDR_OVERR, ch, flg);

	ignore_char:
		status = clps_readl(SYSFLG(port));
	}
	tty_flip_buffer_push(tty);
	return IRQ_HANDLED;
}

static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	struct circ_buf *xmit = &port->info->xmit;
	int count;

	if (port->x_char) {
		clps_writel(port->x_char, UARTDR(port));
		port->icount.tx++;
		port->x_char = 0;
		return IRQ_HANDLED;
	}
	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
		clps711xuart_stop_tx(port);
		return IRQ_HANDLED;
	}

	count = port->fifosize >> 1;
	do {
		clps_writel(xmit->buf[xmit->tail], UARTDR(port));
		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
		port->icount.tx++;
		if (uart_circ_empty(xmit))
			break;
	} while (--count > 0);

	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);

	if (uart_circ_empty(xmit))
		clps711xuart_stop_tx(port);

	return IRQ_HANDLED;
}

static unsigned int clps711xuart_tx_empty(struct uart_port *port)
{
	unsigned int status = clps_readl(SYSFLG(port));
	return status & SYSFLG_UBUSY ? 0 : TIOCSER_TEMT;
}

static unsigned int clps711xuart_get_mctrl(struct uart_port *port)
{
	unsigned int port_addr;
	unsigned int result = 0;
	unsigned int status;

	port_addr = SYSFLG(port);
	if (port_addr == SYSFLG1) {
		status = clps_readl(SYSFLG1);
		if (status & SYSFLG1_DCD)
			result |= TIOCM_CAR;
		if (status & SYSFLG1_DSR)
			result |= TIOCM_DSR;
		if (status & SYSFLG1_CTS)
			result |= TIOCM_CTS;
	}

	return result;
}

static void
clps711xuart_set_mctrl_null(struct uart_port *port, unsigned int mctrl)
{
}

static void clps711xuart_break_ctl(struct uart_port *port, int break_state)
{
	unsigned long flags;
	unsigned int ubrlcr;

	spin_lock_irqsave(&port->lock, flags);
	ubrlcr = clps_readl(UBRLCR(port));
	if (break_state == -1)
		ubrlcr |= UBRLCR_BREAK;
	else
		ubrlcr &= ~UBRLCR_BREAK;
	clps_writel(ubrlcr, UBRLCR(port));
	spin_unlock_irqrestore(&port->lock, flags);
}

static int clps711xuart_startup(struct uart_port *port)
{
	unsigned int syscon;
	int retval;

	tx_enabled(port) = 1;

	/*
	 * Allocate the IRQs
	 */
	retval = request_irq(TX_IRQ(port), clps711xuart_int_tx, 0,
			     "clps711xuart_tx", port);
	if (retval)
		return retval;

	retval = request_irq(RX_IRQ(port), clps711xuart_int_rx, 0,
			     "clps711xuart_rx", port);
	if (retval) {
		free_irq(TX_IRQ(port), port);
		return retval;
	}

	/*
	 * enable the port
	 */
	syscon = clps_readl(SYSCON(port));
	syscon |= SYSCON_UARTEN;
	clps_writel(syscon, SYSCON(port));

	return 0;
}

static void clps711xuart_shutdown(struct uart_port *port)
{
	unsigned int ubrlcr, syscon;

	/*
	 * Free the interrupt
	 */
	free_irq(TX_IRQ(port), port);	/* TX interrupt */
	free_irq(RX_IRQ(port), port);	/* RX interrupt */

	/*
	 * disable the port
	 */
	syscon = clps_readl(SYSCON(port));
	syscon &= ~SYSCON_UARTEN;
	clps_writel(syscon, SYSCON(port));

	/*
	 * disable break condition and fifos
	 */
	ubrlcr = clps_readl(UBRLCR(port));
	ubrlcr &= ~(UBRLCR_FIFOEN | UBRLCR_BREAK);
	clps_writel(ubrlcr, UBRLCR(port));
}

static void
clps711xuart_set_termios(struct uart_port *port, struct ktermios *termios,
			 struct ktermios *old)
{
	unsigned int ubrlcr, baud, quot;
	unsigned long flags;

	/*
	 * We don't implement CREAD.
	 */
	termios->c_cflag |= CREAD;

	/*
	 * Ask the core to calculate the divisor for us.
	 */
	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 
	quot = uart_get_divisor(port, baud);

	switch (termios->c_cflag & CSIZE) {
	case CS5:
		ubrlcr = UBRLCR_WRDLEN5;
		break;
	case CS6:
		ubrlcr = UBRLCR_WRDLEN6;
		break;
	case CS7:
		ubrlcr = UBRLCR_WRDLEN7;
		break;
	default: // CS8
		ubrlcr = UBRLCR_WRDLEN8;
		break;
	}
	if (termios->c_cflag & CSTOPB)
		ubrlcr |= UBRLCR_XSTOP;
	if (termios->c_cflag & PARENB) {
		ubrlcr |= UBRLCR_PRTEN;
		if (!(termios->c_cflag & PARODD))
			ubrlcr |= UBRLCR_EVENPRT;
	}
	if (port->fifosize > 1)
		ubrlcr |= UBRLCR_FIFOEN;

	spin_lock_irqsave(&port->lock, flags);

	/*
	 * Update the per-port timeout.
	 */
	uart_update_timeout(port, termios->c_cflag, baud);

	port->read_status_mask = UARTDR_OVERR;
	if (termios->c_iflag & INPCK)
		port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR;

	/*
	 * Characters to ignore
	 */
	port->ignore_status_mask = 0;
	if (termios->c_iflag & IGNPAR)
		port->ignore_status_mask |= UARTDR_FRMERR | UARTDR_PARERR;
	if (termios->c_iflag & IGNBRK) {
		/*
		 * If we're ignoring parity and break indicators,
		 * ignore overruns to (for real raw support).
		 */
		if (termios->c_iflag & IGNPAR)
			port->ignore_status_mask |= UARTDR_OVERR;
	}

	quot -= 1;

	clps_writel(ubrlcr | quot, UBRLCR(port));

	spin_unlock_irqrestore(&port->lock, flags);
}

static const char *clps711xuart_type(struct uart_port *port)
{
	return port->type == PORT_CLPS711X ? "CLPS711x" : NULL;
}

/*
 * Configure/autoconfigure the port.
 */
static void clps711xuart_config_port(struct uart_port *port, int flags)
{
	if (flags & UART_CONFIG_TYPE)
		port->type = PORT_CLPS711X;
}

static void clps711xuart_release_port(struct uart_port *port)
{
}

static int clps711xuart_request_port(struct uart_port *port)
{
	return 0;
}

static struct uart_ops clps711x_pops = {
	.tx_empty	= clps711xuart_tx_empty,
	.set_mctrl	= clps711xuart_set_mctrl_null,
	.get_mctrl	= clps711xuart_get_mctrl,
	.stop_tx	= clps711xuart_stop_tx,
	.start_tx	= clps711xuart_start_tx,
	.stop_rx	= clps711xuart_stop_rx,
	.enable_ms	= clps711xuart_enable_ms,
	.break_ctl	= clps711xuart_break_ctl,
	.startup	= clps711xuart_startup,
	.shutdown	= clps711xuart_shutdown,
	.set_termios	= clps711xuart_set_termios,
	.type		= clps711xuart_type,
	.config_port	= clps711xuart_config_port,
	.release_port	= clps711xuart_release_port,
	.request_port	= clps711xuart_request_port,
};

static struct uart_port clps711x_ports[UART_NR] = {
	{
		.iobase		= SYSCON1,
		.irq		= IRQ_UTXINT1, /* IRQ_URXINT1, IRQ_UMSINT */
		.uartclk	= 3686400,
		.fifosize	= 16,
		.ops		= &clps711x_pops,
		.line		= 0,
		.flags		= UPF_BOOT_AUTOCONF,
	},
	{
		.iobase		= SYSCON2,
		.irq		= IRQ_UTXINT2, /* IRQ_URXINT2 */
		.uartclk	= 3686400,
		.fifosize	= 16,
		.ops		= &clps711x_pops,
		.line		= 1,
		.flags		= UPF_BOOT_AUTOCONF,
	}
};

#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
static void clps711xuart_console_putchar(struct uart_port *port, int ch)
{
	while (clps_readl(SYSFLG(port)) & SYSFLG_UTXFF)
		barrier();
	clps_writel(ch, UARTDR(port));
}

/*
 *	Print a string to the serial port trying not to disturb
 *	any possible real use of the port...
 *
 *	The console_lock must be held when we get here.
 *
 *	Note that this is called with interrupts already disabled
 */
static void
clps711xuart_console_write(struct console *co, const char *s,
			   unsigned int count)
{
	struct uart_port *port = clps711x_ports + co->index;
	unsigned int status, syscon;

	/*
	 *	Ensure that the port is enabled.
	 */
	syscon = clps_readl(SYSCON(port));
	clps_writel(syscon | SYSCON_UARTEN, SYSCON(port));

	uart_console_write(port, s, count, clps711xuart_console_putchar);

	/*
	 *	Finally, wait for transmitter to become empty
	 *	and restore the uart state.
	 */
	do {
		status = clps_readl(SYSFLG(port));
	} while (status & SYSFLG_UBUSY);

	clps_writel(syscon, SYSCON(port));
}

static void __init
clps711xuart_console_get_options(struct uart_port *port, int *baud,
				 int *parity, int *bits)
{
	if (clps_readl(SYSCON(port)) & SYSCON_UARTEN) {
		unsigned int ubrlcr, quot;

		ubrlcr = clps_readl(UBRLCR(port));

		*parity = 'n';
		if (ubrlcr & UBRLCR_PRTEN) {
			if (ubrlcr & UBRLCR_EVENPRT)
				*parity = 'e';
			else
				*parity = 'o';
		}

		if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
			*bits = 7;
		else
			*bits = 8;

		quot = ubrlcr & UBRLCR_BAUD_MASK;
		*baud = port->uartclk / (16 * (quot + 1));
	}
}

static int __init clps711xuart_console_setup(struct console *co, char *options)
{
	struct uart_port *port;
	int baud = 38400;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';

	/*
	 * Check whether an invalid uart number has been specified, and
	 * if so, search for the first available port that does have
	 * console support.
	 */
	port = uart_get_console(clps711x_ports, UART_NR, co);

	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);
	else
		clps711xuart_console_get_options(port, &baud, &parity, &bits);

	return uart_set_options(port, co, baud, parity, bits, flow);
}

static struct uart_driver clps711x_reg;
static struct console clps711x_console = {
	.name		= "ttyCL",
	.write		= clps711xuart_console_write,
	.device		= uart_console_device,
	.setup		= clps711xuart_console_setup,
	.flags		= CON_PRINTBUFFER,
	.index		= -1,
	.data		= &clps711x_reg,
};

static int __init clps711xuart_console_init(void)
{
	register_console(&clps711x_console);
	return 0;
}
console_initcall(clps711xuart_console_init);

#define CLPS711X_CONSOLE	&clps711x_console
#else
#define CLPS711X_CONSOLE	NULL
#endif

static struct uart_driver clps711x_reg = {
	.driver_name		= "ttyCL",
	.dev_name		= "ttyCL",
	.major			= SERIAL_CLPS711X_MAJOR,
	.minor			= SERIAL_CLPS711X_MINOR,
	.nr			= UART_NR,

	.cons			= CLPS711X_CONSOLE,
};

static int __init clps711xuart_init(void)
{
	int ret, i;

	printk(KERN_INFO "Serial: CLPS711x driver\n");

	ret = uart_register_driver(&clps711x_reg);
	if (ret)
		return ret;

	for (i = 0; i < UART_NR; i++)
		uart_add_one_port(&clps711x_reg, &clps711x_ports[i]);

	return 0;
}

static void __exit clps711xuart_exit(void)
{
	int i;

	for (i = 0; i < UART_NR; i++)
		uart_remove_one_port(&clps711x_reg, &clps711x_ports[i]);

	uart_unregister_driver(&clps711x_reg);
}

module_init(clps711xuart_init);
module_exit(clps711xuart_exit);

MODULE_AUTHOR("Deep Blue Solutions Ltd");
MODULE_DESCRIPTION("CLPS-711x generic serial driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS_CHARDEV(SERIAL_CLPS711X_MAJOR, SERIAL_CLPS711X_MINOR);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/char/clps711x.c
	3	*
	4	* Driver for CLPS711x serial ports
	5	*
	6	* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
	7	*
	8	* Copyright 1999 ARM Limited
	9	* Copyright (C) 2000 Deep Blue Solutions Ltd.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1da177e4	24	*/
1da177e4 LT	25
	26	#if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
	27	#define SUPPORT_SYSRQ
	28	#endif
	29
	30	#include <linux/module.h>
	31	#include <linux/ioport.h>
	32	#include <linux/init.h>
	33	#include <linux/console.h>
	34	#include <linux/sysrq.h>
	35	#include <linux/spinlock.h>
	36	#include <linux/device.h>
	37	#include <linux/tty.h>
	38	#include <linux/tty_flip.h>
	39	#include <linux/serial_core.h>
	40	#include <linux/serial.h>
99730225	41	#include <linux/io.h>
1da177e4	42
a09e64fb	43	#include <mach/hardware.h>
1da177e4 LT	44	#include <asm/irq.h>
	45	#include <asm/hardware/clps7111.h>
	46
	47	#define UART_NR 2
	48
	49	#define SERIAL_CLPS711X_MAJOR 204
	50	#define SERIAL_CLPS711X_MINOR 40
	51	#define SERIAL_CLPS711X_NR UART_NR
	52
	53	/*
	54	* We use the relevant SYSCON register as a base address for these ports.
	55	*/
	56	#define UBRLCR(port) ((port)->iobase + UBRLCR1 - SYSCON1)
	57	#define UARTDR(port) ((port)->iobase + UARTDR1 - SYSCON1)
	58	#define SYSFLG(port) ((port)->iobase + SYSFLG1 - SYSCON1)
	59	#define SYSCON(port) ((port)->iobase + SYSCON1 - SYSCON1)
	60
	61	#define TX_IRQ(port) ((port)->irq)
	62	#define RX_IRQ(port) ((port)->irq + 1)
	63
	64	#define UART_ANY_ERR (UARTDR_FRMERR \| UARTDR_PARERR \| UARTDR_OVERR)
	65
	66	#define tx_enabled(port) ((port)->unused[0])
	67
b129a8cc	68	static void clps711xuart_stop_tx(struct uart_port *port)
1da177e4 LT	69	{
	70	if (tx_enabled(port)) {
	71	disable_irq(TX_IRQ(port));
	72	tx_enabled(port) = 0;
	73	}
	74	}
	75
b129a8cc	76	static void clps711xuart_start_tx(struct uart_port *port)
1da177e4 LT	77	{
	78	if (!tx_enabled(port)) {
	79	enable_irq(TX_IRQ(port));
	80	tx_enabled(port) = 1;
	81	}
	82	}
	83
	84	static void clps711xuart_stop_rx(struct uart_port *port)
	85	{
	86	disable_irq(RX_IRQ(port));
	87	}
	88
	89	static void clps711xuart_enable_ms(struct uart_port *port)
	90	{
	91	}
	92
7d12e780	93	static irqreturn_t clps711xuart_int_rx(int irq, void *dev_id)
1da177e4 LT	94	{
1da177e4 LT	95	struct uart_port *port = dev_id;
a88487c7	96	struct tty_struct *tty = port->info->port.tty;
f9937242	97	unsigned int status, ch, flg;
1da177e4 LT	98
	99	status = clps_readl(SYSFLG(port));
	100	while (!(status & SYSFLG_URXFE)) {
	101	ch = clps_readl(UARTDR(port));
	102
1da177e4 LT	103	port->icount.rx++;
	104
	105	flg = TTY_NORMAL;
	106
	107	/*
	108	* Note that the error handling code is
	109	* out of the main execution path
	110	*/
2a9604b8 RK	111	if (unlikely(ch & UART_ANY_ERR)) {
	112	if (ch & UARTDR_PARERR)
	113	port->icount.parity++;
	114	else if (ch & UARTDR_FRMERR)
	115	port->icount.frame++;
	116	if (ch & UARTDR_OVERR)
	117	port->icount.overrun++;
1da177e4	118
2a9604b8	119	ch &= port->read_status_mask;
1da177e4	120
2a9604b8 RK	121	if (ch & UARTDR_PARERR)
	122	flg = TTY_PARITY;
	123	else if (ch & UARTDR_FRMERR)
	124	flg = TTY_FRAME;
1da177e4	125
2a9604b8 RK	126	#ifdef SUPPORT_SYSRQ
	127	port->sysrq = 0;
	128	#endif
	129	}
1da177e4	130
7d12e780	131	if (uart_handle_sysrq_char(port, ch))
2a9604b8	132	goto ignore_char;
1da177e4	133
1da177e4 LT	134	/*
	135	* CHECK: does overrun affect the current character?
	136	* ASSUMPTION: it does not.
	137	*/
05ab3014	138	uart_insert_char(port, ch, UARTDR_OVERR, ch, flg);
2a9604b8 RK	139
	140	ignore_char:
	141	status = clps_readl(SYSFLG(port));
1da177e4	142	}
2a9604b8 RK	143	tty_flip_buffer_push(tty);
2a9604b8 RK	144	return IRQ_HANDLED;
1da177e4 LT	145	}
1da177e4 LT	146
7d12e780	147	static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id)
1da177e4 LT	148	{
	149	struct uart_port *port = dev_id;
	150	struct circ_buf *xmit = &port->info->xmit;
	151	int count;
	152
	153	if (port->x_char) {
	154	clps_writel(port->x_char, UARTDR(port));
	155	port->icount.tx++;
	156	port->x_char = 0;
	157	return IRQ_HANDLED;
	158	}
	159	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port)) {
b129a8cc	160	clps711xuart_stop_tx(port);
1da177e4 LT	161	return IRQ_HANDLED;
	162	}
	163
	164	count = port->fifosize >> 1;
	165	do {
	166	clps_writel(xmit->buf[xmit->tail], UARTDR(port));
	167	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
	168	port->icount.tx++;
	169	if (uart_circ_empty(xmit))
	170	break;
	171	} while (--count > 0);
	172
	173	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
	174	uart_write_wakeup(port);
	175
	176	if (uart_circ_empty(xmit))
b129a8cc	177	clps711xuart_stop_tx(port);
1da177e4 LT	178
	179	return IRQ_HANDLED;
	180	}
	181
	182	static unsigned int clps711xuart_tx_empty(struct uart_port *port)
	183	{
	184	unsigned int status = clps_readl(SYSFLG(port));
	185	return status & SYSFLG_UBUSY ? 0 : TIOCSER_TEMT;
	186	}
	187
	188	static unsigned int clps711xuart_get_mctrl(struct uart_port *port)
	189	{
	190	unsigned int port_addr;
	191	unsigned int result = 0;
	192	unsigned int status;
	193
	194	port_addr = SYSFLG(port);
	195	if (port_addr == SYSFLG1) {
	196	status = clps_readl(SYSFLG1);
	197	if (status & SYSFLG1_DCD)
	198	result \|= TIOCM_CAR;
	199	if (status & SYSFLG1_DSR)
	200	result \|= TIOCM_DSR;
	201	if (status & SYSFLG1_CTS)
	202	result \|= TIOCM_CTS;
	203	}
	204
	205	return result;
	206	}
	207
	208	static void
	209	clps711xuart_set_mctrl_null(struct uart_port *port, unsigned int mctrl)
	210	{
	211	}
	212
	213	static void clps711xuart_break_ctl(struct uart_port *port, int break_state)
	214	{
	215	unsigned long flags;
	216	unsigned int ubrlcr;
	217
	218	spin_lock_irqsave(&port->lock, flags);
	219	ubrlcr = clps_readl(UBRLCR(port));
	220	if (break_state == -1)
	221	ubrlcr \|= UBRLCR_BREAK;
	222	else
	223	ubrlcr &= ~UBRLCR_BREAK;
	224	clps_writel(ubrlcr, UBRLCR(port));
	225	spin_unlock_irqrestore(&port->lock, flags);
	226	}
	227
	228	static int clps711xuart_startup(struct uart_port *port)
	229	{
	230	unsigned int syscon;
	231	int retval;
	232
	233	tx_enabled(port) = 1;
	234
	235	/*
	236	* Allocate the IRQs
	237	*/
	238	retval = request_irq(TX_IRQ(port), clps711xuart_int_tx, 0,
	239	"clps711xuart_tx", port);
	240	if (retval)
	241	return retval;
242
243	retval = request_irq(RX_IRQ(port), clps711xuart_int_rx, 0,
244	"clps711xuart_rx", port);
245	if (retval) {
246	free_irq(TX_IRQ(port), port);
247	return retval;
248	}
249
250	/*
251	* enable the port
252	*/
253	syscon = clps_readl(SYSCON(port));
254	syscon \|= SYSCON_UARTEN;
255	clps_writel(syscon, SYSCON(port));
256
257	return 0;
258	}
259
260	static void clps711xuart_shutdown(struct uart_port *port)
261	{
262	unsigned int ubrlcr, syscon;
263
264	/*
265	* Free the interrupt
266	*/
267	free_irq(TX_IRQ(port), port); /* TX interrupt */
268	free_irq(RX_IRQ(port), port); /* RX interrupt */
269
270	/*
271	* disable the port
272	*/
273	syscon = clps_readl(SYSCON(port));
274	syscon &= ~SYSCON_UARTEN;
275	clps_writel(syscon, SYSCON(port));
276
277	/*
278	* disable break condition and fifos
279	*/
280	ubrlcr = clps_readl(UBRLCR(port));
281	ubrlcr &= ~(UBRLCR_FIFOEN \| UBRLCR_BREAK);
282	clps_writel(ubrlcr, UBRLCR(port));
283	}
284
285	static void
606d099c AC	286	clps711xuart_set_termios(struct uart_port port, struct ktermios termios,
606d099c AC	287	struct ktermios *old)
1da177e4 LT	288	{
	289	unsigned int ubrlcr, baud, quot;
	290	unsigned long flags;
	291
	292	/*
	293	* We don't implement CREAD.
	294	*/
	295	termios->c_cflag \|= CREAD;
	296
	297	/*
	298	* Ask the core to calculate the divisor for us.
	299	*/
	300	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
	301	quot = uart_get_divisor(port, baud);
	302
	303	switch (termios->c_cflag & CSIZE) {
	304	case CS5:
	305	ubrlcr = UBRLCR_WRDLEN5;
	306	break;
	307	case CS6:
	308	ubrlcr = UBRLCR_WRDLEN6;
	309	break;
	310	case CS7:
	311	ubrlcr = UBRLCR_WRDLEN7;
	312	break;
	313	default: // CS8
	314	ubrlcr = UBRLCR_WRDLEN8;
	315	break;
	316	}
	317	if (termios->c_cflag & CSTOPB)
	318	ubrlcr \|= UBRLCR_XSTOP;
	319	if (termios->c_cflag & PARENB) {
	320	ubrlcr \|= UBRLCR_PRTEN;
	321	if (!(termios->c_cflag & PARODD))
	322	ubrlcr \|= UBRLCR_EVENPRT;
	323	}
	324	if (port->fifosize > 1)
	325	ubrlcr \|= UBRLCR_FIFOEN;
	326
	327	spin_lock_irqsave(&port->lock, flags);
	328
	329	/*
	330	* Update the per-port timeout.
	331	*/
	332	uart_update_timeout(port, termios->c_cflag, baud);
	333
	334	port->read_status_mask = UARTDR_OVERR;
	335	if (termios->c_iflag & INPCK)
	336	port->read_status_mask \|= UARTDR_PARERR \| UARTDR_FRMERR;
	337
	338	/*
	339	* Characters to ignore
	340	*/
	341	port->ignore_status_mask = 0;
	342	if (termios->c_iflag & IGNPAR)
	343	port->ignore_status_mask \|= UARTDR_FRMERR \| UARTDR_PARERR;
	344	if (termios->c_iflag & IGNBRK) {
	345	/*
	346	* If we're ignoring parity and break indicators,
	347	* ignore overruns to (for real raw support).
	348	*/
	349	if (termios->c_iflag & IGNPAR)
	350	port->ignore_status_mask \|= UARTDR_OVERR;
	351	}
352
353	quot -= 1;
354
355	clps_writel(ubrlcr \| quot, UBRLCR(port));
356
357	spin_unlock_irqrestore(&port->lock, flags);
358	}
359
360	static const char clps711xuart_type(struct uart_port port)
361	{
362	return port->type == PORT_CLPS711X ? "CLPS711x" : NULL;
363	}
364
365	/*
366	* Configure/autoconfigure the port.
367	*/
368	static void clps711xuart_config_port(struct uart_port *port, int flags)
369	{
370	if (flags & UART_CONFIG_TYPE)
371	port->type = PORT_CLPS711X;
372	}
373
374	static void clps711xuart_release_port(struct uart_port *port)
375	{
376	}
377
378	static int clps711xuart_request_port(struct uart_port *port)
379	{
380	return 0;
381	}
382
383	static struct uart_ops clps711x_pops = {
384	.tx_empty = clps711xuart_tx_empty,
385	.set_mctrl = clps711xuart_set_mctrl_null,
386	.get_mctrl = clps711xuart_get_mctrl,
387	.stop_tx = clps711xuart_stop_tx,
388	.start_tx = clps711xuart_start_tx,
389	.stop_rx = clps711xuart_stop_rx,
390	.enable_ms = clps711xuart_enable_ms,
391	.break_ctl = clps711xuart_break_ctl,
392	.startup = clps711xuart_startup,
393	.shutdown = clps711xuart_shutdown,
394	.set_termios = clps711xuart_set_termios,
395	.type = clps711xuart_type,
396	.config_port = clps711xuart_config_port,
397	.release_port = clps711xuart_release_port,
398	.request_port = clps711xuart_request_port,
399	};
400
401	static struct uart_port clps711x_ports[UART_NR] = {
402	{
403	.iobase = SYSCON1,
404	.irq = IRQ_UTXINT1, /* IRQ_URXINT1, IRQ_UMSINT */
405	.uartclk = 3686400,
406	.fifosize = 16,
407	.ops = &clps711x_pops,
408	.line = 0,
ce8337cb	409	.flags = UPF_BOOT_AUTOCONF,
1da177e4 LT	410	},
	411	{
	412	.iobase = SYSCON2,
	413	.irq = IRQ_UTXINT2, /* IRQ_URXINT2 */
	414	.uartclk = 3686400,
	415	.fifosize = 16,
	416	.ops = &clps711x_pops,
	417	.line = 1,
ce8337cb	418	.flags = UPF_BOOT_AUTOCONF,
1da177e4 LT	419	}
	420	};
	421
	422	#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
d358788f RK	423	static void clps711xuart_console_putchar(struct uart_port *port, int ch)
	424	{
	425	while (clps_readl(SYSFLG(port)) & SYSFLG_UTXFF)
	426	barrier();
	427	clps_writel(ch, UARTDR(port));
	428	}
	429
1da177e4 LT	430	/*
	431	* Print a string to the serial port trying not to disturb
	432	* any possible real use of the port...
	433	*
	434	* The console_lock must be held when we get here.
	435	*
	436	* Note that this is called with interrupts already disabled
	437	*/
	438	static void
	439	clps711xuart_console_write(struct console co, const char s,
	440	unsigned int count)
	441	{
	442	struct uart_port *port = clps711x_ports + co->index;
	443	unsigned int status, syscon;
1da177e4 LT	444
	445	/*
	446	* Ensure that the port is enabled.
	447	*/
	448	syscon = clps_readl(SYSCON(port));
	449	clps_writel(syscon \| SYSCON_UARTEN, SYSCON(port));
	450
d358788f	451	uart_console_write(port, s, count, clps711xuart_console_putchar);
1da177e4 LT	452
	453	/*
	454	* Finally, wait for transmitter to become empty
	455	* and restore the uart state.
	456	*/
	457	do {
	458	status = clps_readl(SYSFLG(port));
	459	} while (status & SYSFLG_UBUSY);
	460
	461	clps_writel(syscon, SYSCON(port));
	462	}
	463
	464	static void __init
	465	clps711xuart_console_get_options(struct uart_port port, int baud,
	466	int parity, int bits)
	467	{
	468	if (clps_readl(SYSCON(port)) & SYSCON_UARTEN) {
	469	unsigned int ubrlcr, quot;
	470
	471	ubrlcr = clps_readl(UBRLCR(port));
	472
	473	*parity = 'n';
	474	if (ubrlcr & UBRLCR_PRTEN) {
	475	if (ubrlcr & UBRLCR_EVENPRT)
	476	*parity = 'e';
	477	else
	478	*parity = 'o';
	479	}
	480
	481	if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
	482	*bits = 7;
	483	else
	484	*bits = 8;
	485
	486	quot = ubrlcr & UBRLCR_BAUD_MASK;
	487	baud = port->uartclk / (16 (quot + 1));
	488	}
	489	}
	490
	491	static int __init clps711xuart_console_setup(struct console co, char options)
	492	{
	493	struct uart_port *port;
	494	int baud = 38400;
	495	int bits = 8;
	496	int parity = 'n';
	497	int flow = 'n';
	498
	499	/*
	500	* Check whether an invalid uart number has been specified, and
	501	* if so, search for the first available port that does have
	502	* console support.
	503	*/
	504	port = uart_get_console(clps711x_ports, UART_NR, co);
	505
	506	if (options)
	507	uart_parse_options(options, &baud, &parity, &bits, &flow);
	508	else
	509	clps711xuart_console_get_options(port, &baud, &parity, &bits);
	510
	511	return uart_set_options(port, co, baud, parity, bits, flow);
	512	}
	513
2d93486c	514	static struct uart_driver clps711x_reg;
1da177e4 LT	515	static struct console clps711x_console = {
	516	.name = "ttyCL",
	517	.write = clps711xuart_console_write,
	518	.device = uart_console_device,
	519	.setup = clps711xuart_console_setup,
	520	.flags = CON_PRINTBUFFER,
	521	.index = -1,
	522	.data = &clps711x_reg,
	523	};
	524
	525	static int __init clps711xuart_console_init(void)
	526	{
	527	register_console(&clps711x_console);
	528	return 0;
	529	}
	530	console_initcall(clps711xuart_console_init);
	531
	532	#define CLPS711X_CONSOLE &clps711x_console
	533	#else
	534	#define CLPS711X_CONSOLE NULL
	535	#endif
	536
	537	static struct uart_driver clps711x_reg = {
	538	.driver_name = "ttyCL",
	539	.dev_name = "ttyCL",
	540	.major = SERIAL_CLPS711X_MAJOR,
	541	.minor = SERIAL_CLPS711X_MINOR,
	542	.nr = UART_NR,
	543
	544	.cons = CLPS711X_CONSOLE,
	545	};
	546
	547	static int __init clps711xuart_init(void)
	548	{
	549	int ret, i;
	550
d87a6d95	551	printk(KERN_INFO "Serial: CLPS711x driver\n");
1da177e4 LT	552
	553	ret = uart_register_driver(&clps711x_reg);
	554	if (ret)
	555	return ret;
	556
	557	for (i = 0; i < UART_NR; i++)
	558	uart_add_one_port(&clps711x_reg, &clps711x_ports[i]);
	559
	560	return 0;
	561	}
	562
	563	static void __exit clps711xuart_exit(void)
	564	{
	565	int i;
	566
	567	for (i = 0; i < UART_NR; i++)
	568	uart_remove_one_port(&clps711x_reg, &clps711x_ports[i]);
	569
	570	uart_unregister_driver(&clps711x_reg);
	571	}
	572
	573	module_init(clps711xuart_init);
	574	module_exit(clps711xuart_exit);
	575
	576	MODULE_AUTHOR("Deep Blue Solutions Ltd");
d87a6d95	577	MODULE_DESCRIPTION("CLPS-711x generic serial driver");
1da177e4 LT	578	MODULE_LICENSE("GPL");
1da177e4 LT	579	MODULE_ALIAS_CHARDEV(SERIAL_CLPS711X_MAJOR, SERIAL_CLPS711X_MINOR);