[linux.git] / drivers / pinctrl / pinctrl-lantiq.h

/*
 *  linux/drivers/pinctrl/pinctrl-lantiq.h
 *  based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  publishhed by the Free Software Foundation.
 *
 *  Copyright (C) 2012 John Crispin <[email protected]>
 */

#ifndef __PINCTRL_LANTIQ_H
#define __PINCTRL_LANTIQ_H

#include <linux/clkdev.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>

#include "core.h"

#define ARRAY_AND_SIZE(x)	(x), ARRAY_SIZE(x)

#define LTQ_MAX_MUX		4
#define MFPR_FUNC_MASK		0x3

#define LTQ_PINCONF_PACK(param, arg)		((param) << 16 | (arg))
#define LTQ_PINCONF_UNPACK_PARAM(conf)		((conf) >> 16)
#define LTQ_PINCONF_UNPACK_ARG(conf)		((conf) & 0xffff)

enum ltq_pinconf_param {
	LTQ_PINCONF_PARAM_PULL,
	LTQ_PINCONF_PARAM_OPEN_DRAIN,
	LTQ_PINCONF_PARAM_DRIVE_CURRENT,
	LTQ_PINCONF_PARAM_SLEW_RATE,
	LTQ_PINCONF_PARAM_OUTPUT,
};

struct ltq_cfg_param {
	const char *property;
	enum ltq_pinconf_param param;
};

struct ltq_mfp_pin {
	const char *name;
	const unsigned int pin;
	const unsigned short func[LTQ_MAX_MUX];
};

struct ltq_pin_group {
	const char *name;
	const unsigned mux;
	const unsigned *pins;
	const unsigned npins;
};

struct ltq_pmx_func {
	const char *name;
	const char * const *groups;
	const unsigned num_groups;
};

struct ltq_pinmux_info {
	struct device *dev;
	struct pinctrl_dev *pctrl;

	/* we need to manage up to 5 pad controllers */
	void __iomem *membase[5];

	/* the descriptor for the subsystem */
	struct pinctrl_desc *desc;

	/* we expose our pads to the subsystem */
	struct pinctrl_pin_desc *pads;

	/* the number of pads. this varies between socs */
	unsigned int num_pads;

	/* these are our multifunction pins */
	const struct ltq_mfp_pin *mfp;
	unsigned int num_mfp;

	/* a number of multifunction pins can be grouped together */
	const struct ltq_pin_group *grps;
	unsigned int num_grps;

	/* a mapping between function string and id */
	const struct ltq_pmx_func *funcs;
	unsigned int num_funcs;

	/* the pinconf options that we are able to read from the DT */
	const struct ltq_cfg_param *params;
	unsigned int num_params;

	/* the pad controller can have a irq mapping  */
	const unsigned *exin;
	unsigned int num_exin;

	/* we need 5 clocks max */
	struct clk *clk[5];

	/* soc specific callback used to apply muxing */
	int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux);
};

enum ltq_pin {
	GPIO0 = 0,
	GPIO1,
	GPIO2,
	GPIO3,
	GPIO4,
	GPIO5,
	GPIO6,
	GPIO7,
	GPIO8,
	GPIO9,
	GPIO10, /* 10 */
	GPIO11,
	GPIO12,
	GPIO13,
	GPIO14,
	GPIO15,
	GPIO16,
	GPIO17,
	GPIO18,
	GPIO19,
	GPIO20, /* 20 */
	GPIO21,
	GPIO22,
	GPIO23,
	GPIO24,
	GPIO25,
	GPIO26,
	GPIO27,
	GPIO28,
	GPIO29,
	GPIO30, /* 30 */
	GPIO31,
	GPIO32,
	GPIO33,
	GPIO34,
	GPIO35,
	GPIO36,
	GPIO37,
	GPIO38,
	GPIO39,
	GPIO40, /* 40 */
	GPIO41,
	GPIO42,
	GPIO43,
	GPIO44,
	GPIO45,
	GPIO46,
	GPIO47,
	GPIO48,
	GPIO49,
	GPIO50, /* 50 */
	GPIO51,
	GPIO52,
	GPIO53,
	GPIO54,
	GPIO55,
	GPIO56,
	GPIO57,
	GPIO58,
	GPIO59,
	GPIO60, /* 60 */
	GPIO61,
	GPIO62,
	GPIO63,

	GPIO64,
	GPIO65,
	GPIO66,
	GPIO67,
	GPIO68,
	GPIO69,
	GPIO70,
	GPIO71,
	GPIO72,
	GPIO73,
	GPIO74,
	GPIO75,
	GPIO76,
	GPIO77,
	GPIO78,
	GPIO79,
	GPIO80,
	GPIO81,
	GPIO82,
	GPIO83,
	GPIO84,
	GPIO85,
	GPIO86,
	GPIO87,
	GPIO88,
};

extern int ltq_pinctrl_register(struct platform_device *pdev,
				   struct ltq_pinmux_info *info);
extern int ltq_pinctrl_unregister(struct platform_device *pdev);
#endif	/* __PINCTRL_LANTIQ_H */
Commit	Line	Data
3f8c50c9 JC	1	/*
	2	* linux/drivers/pinctrl/pinctrl-lantiq.h
	3	* based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* publishhed by the Free Software Foundation.
	8	*
55e40950	9	* Copyright (C) 2012 John Crispin <[email protected]>
3f8c50c9 JC	10	*/
	11
	12	#ifndef __PINCTRL_LANTIQ_H
edb052c3	13	#define __PINCTRL_LANTIQ_H
3f8c50c9 JC	14
	15	#include <linux/clkdev.h>
	16	#include <linux/pinctrl/pinctrl.h>
	17	#include <linux/pinctrl/pinconf.h>
	18	#include <linux/pinctrl/pinmux.h>
	19	#include <linux/pinctrl/consumer.h>
	20	#include <linux/pinctrl/machine.h>
	21
	22	#include "core.h"
	23
	24	#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
	25
	26	#define LTQ_MAX_MUX 4
	27	#define MFPR_FUNC_MASK 0x3
	28
	29	#define LTQ_PINCONF_PACK(param, arg) ((param) << 16 \| (arg))
	30	#define LTQ_PINCONF_UNPACK_PARAM(conf) ((conf) >> 16)
	31	#define LTQ_PINCONF_UNPACK_ARG(conf) ((conf) & 0xffff)
	32
	33	enum ltq_pinconf_param {
	34	LTQ_PINCONF_PARAM_PULL,
	35	LTQ_PINCONF_PARAM_OPEN_DRAIN,
	36	LTQ_PINCONF_PARAM_DRIVE_CURRENT,
	37	LTQ_PINCONF_PARAM_SLEW_RATE,
6360350c	38	LTQ_PINCONF_PARAM_OUTPUT,
3f8c50c9 JC	39	};
	40
	41	struct ltq_cfg_param {
	42	const char *property;
	43	enum ltq_pinconf_param param;
	44	};
	45
	46	struct ltq_mfp_pin {
	47	const char *name;
	48	const unsigned int pin;
	49	const unsigned short func[LTQ_MAX_MUX];
	50	};
	51
	52	struct ltq_pin_group {
	53	const char *name;
	54	const unsigned mux;
	55	const unsigned *pins;
	56	const unsigned npins;
	57	};
	58
	59	struct ltq_pmx_func {
	60	const char *name;
	61	const char * const *groups;
	62	const unsigned num_groups;
	63	};
	64
	65	struct ltq_pinmux_info {
	66	struct device *dev;
	67	struct pinctrl_dev *pctrl;
	68
	69	/* we need to manage up to 5 pad controllers */
	70	void __iomem *membase[5];
	71
	72	/* the descriptor for the subsystem */
	73	struct pinctrl_desc *desc;
	74
	75	/* we expose our pads to the subsystem */
	76	struct pinctrl_pin_desc *pads;
	77
	78	/* the number of pads. this varies between socs */
	79	unsigned int num_pads;
	80
	81	/* these are our multifunction pins */
	82	const struct ltq_mfp_pin *mfp;
	83	unsigned int num_mfp;
	84
	85	/* a number of multifunction pins can be grouped together */
	86	const struct ltq_pin_group *grps;
	87	unsigned int num_grps;
	88
	89	/* a mapping between function string and id */
	90	const struct ltq_pmx_func *funcs;
	91	unsigned int num_funcs;
	92
	93	/* the pinconf options that we are able to read from the DT */
	94	const struct ltq_cfg_param *params;
	95	unsigned int num_params;
	96
	97	/* the pad controller can have a irq mapping */
	98	const unsigned *exin;
	99	unsigned int num_exin;
	100
	101	/* we need 5 clocks max */
	102	struct clk *clk[5];
103
104	/* soc specific callback used to apply muxing */
105	int (apply_mux)(struct pinctrl_dev pctrldev, int pin, int mux);
106	};
107
108	enum ltq_pin {
109	GPIO0 = 0,
110	GPIO1,
111	GPIO2,
112	GPIO3,
113	GPIO4,
114	GPIO5,
115	GPIO6,
116	GPIO7,
117	GPIO8,
118	GPIO9,
119	GPIO10, /* 10 */
120	GPIO11,
121	GPIO12,
122	GPIO13,
123	GPIO14,
124	GPIO15,
125	GPIO16,
126	GPIO17,
127	GPIO18,
128	GPIO19,
129	GPIO20, /* 20 */
130	GPIO21,
131	GPIO22,
132	GPIO23,
133	GPIO24,
134	GPIO25,
135	GPIO26,
136	GPIO27,
137	GPIO28,
138	GPIO29,
139	GPIO30, /* 30 */
140	GPIO31,
141	GPIO32,
142	GPIO33,
143	GPIO34,
144	GPIO35,
145	GPIO36,
146	GPIO37,
147	GPIO38,
148	GPIO39,
149	GPIO40, /* 40 */
150	GPIO41,
151	GPIO42,
152	GPIO43,
153	GPIO44,
154	GPIO45,
155	GPIO46,
156	GPIO47,
157	GPIO48,
158	GPIO49,
159	GPIO50, /* 50 */
160	GPIO51,
161	GPIO52,
162	GPIO53,
163	GPIO54,
164	GPIO55,
be14811c MS	165	GPIO56,
	166	GPIO57,
	167	GPIO58,
	168	GPIO59,
	169	GPIO60, /* 60 */
	170	GPIO61,
	171	GPIO62,
	172	GPIO63,
3f8c50c9 JC	173
	174	GPIO64,
	175	GPIO65,
	176	GPIO66,
	177	GPIO67,
	178	GPIO68,
	179	GPIO69,
	180	GPIO70,
	181	GPIO71,
	182	GPIO72,
	183	GPIO73,
	184	GPIO74,
	185	GPIO75,
	186	GPIO76,
	187	GPIO77,
	188	GPIO78,
	189	GPIO79,
	190	GPIO80,
	191	GPIO81,
	192	GPIO82,
	193	GPIO83,
	194	GPIO84,
	195	GPIO85,
	196	GPIO86,
	197	GPIO87,
	198	GPIO88,
	199	};
	200
	201	extern int ltq_pinctrl_register(struct platform_device *pdev,
	202	struct ltq_pinmux_info *info);
	203	extern int ltq_pinctrl_unregister(struct platform_device *pdev);
b5eec4d0	204	#endif /* __PINCTRL_LANTIQ_H */