[linux.git] / drivers / ata / pata_hpt3x3.c

/*
 *	pata_hpt3x3		-	HPT3x3 driver
 *	(c) Copyright 2005-2006 Red Hat
 *
 *	Was pata_hpt34x but the naming was confusing as it supported the
 *	343 and 363 so it has been renamed.
 *
 *	Based on:
 *	linux/drivers/ide/pci/hpt34x.c		Version 0.40	Sept 10, 2002
 *	Copyright (C) 1998-2000	Andre Hedrick <[email protected]>
 *
 *	May be copied or modified under the terms of the GNU General Public
 *	License
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pata_hpt3x3"
#define DRV_VERSION	"0.6.1"

/**
 *	hpt3x3_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Set our PIO requirements. This is fairly simple on the HPT3x3 as
 *	all we have to do is clear the MWDMA and UDMA bits then load the
 *	mode number.
 */

static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 r1, r2;
	int dn = 2 * ap->port_no + adev->devno;

	pci_read_config_dword(pdev, 0x44, &r1);
	pci_read_config_dword(pdev, 0x48, &r2);
	/* Load the PIO timing number */
	r1 &= ~(7 << (3 * dn));
	r1 |= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
	r2 &= ~(0x11 << dn);	/* Clear MWDMA and UDMA bits */

	pci_write_config_dword(pdev, 0x44, r1);
	pci_write_config_dword(pdev, 0x48, r2);
}

#if defined(CONFIG_PATA_HPT3X3_DMA)
/**
 *	hpt3x3_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 *	Set up the channel for MWDMA or UDMA modes. Much the same as with
 *	PIO, load the mode number and then set MWDMA or UDMA flag.
 *
 *	0x44 : bit 0-2 master mode, 3-5 slave mode, etc
 *	0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
 */

static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 r1, r2;
	int dn = 2 * ap->port_no + adev->devno;
	int mode_num = adev->dma_mode & 0x0F;

	pci_read_config_dword(pdev, 0x44, &r1);
	pci_read_config_dword(pdev, 0x48, &r2);
	/* Load the timing number */
	r1 &= ~(7 << (3 * dn));
	r1 |= (mode_num << (3 * dn));
	r2 &= ~(0x11 << dn);	/* Clear MWDMA and UDMA bits */

	if (adev->dma_mode >= XFER_UDMA_0)
		r2 |= (0x01 << dn);	/* Ultra mode */
	else
		r2 |= (0x10 << dn);	/* MWDMA */

	pci_write_config_dword(pdev, 0x44, r1);
	pci_write_config_dword(pdev, 0x48, r2);
}

/**
 *	hpt3x3_freeze		-	DMA workaround
 *	@ap: port to freeze
 *
 *	When freezing an HPT3x3 we must stop any pending DMA before
 *	writing to the control register or the chip will hang
 */

static void hpt3x3_freeze(struct ata_port *ap)
{
	void __iomem *mmio = ap->ioaddr.bmdma_addr;

	iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ ATA_DMA_START,
			mmio + ATA_DMA_CMD);
	ata_sff_dma_pause(ap);
	ata_sff_freeze(ap);
}

/**
 *	hpt3x3_bmdma_setup	-	DMA workaround
 *	@qc: Queued command
 *
 *	When issuing BMDMA we must clean up the error/active bits in
 *	software on this device
 */

static void hpt3x3_bmdma_setup(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	u8 r = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
	r |= ATA_DMA_INTR | ATA_DMA_ERR;
	iowrite8(r, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
	return ata_bmdma_setup(qc);
}

/**
 *	hpt3x3_atapi_dma	-	ATAPI DMA check
 *	@qc: Queued command
 *
 *	Just say no - we don't do ATAPI DMA
 */

static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
{
	return 1;
}

#endif /* CONFIG_PATA_HPT3X3_DMA */

static struct scsi_host_template hpt3x3_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations hpt3x3_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= ata_cable_40wire,
	.set_piomode	= hpt3x3_set_piomode,
#if defined(CONFIG_PATA_HPT3X3_DMA)
	.set_dmamode	= hpt3x3_set_dmamode,
	.bmdma_setup	= hpt3x3_bmdma_setup,
	.check_atapi_dma= hpt3x3_atapi_dma,
	.freeze		= hpt3x3_freeze,
#endif
	
};

/**
 *	hpt3x3_init_chipset	-	chip setup
 *	@dev: PCI device
 *
 *	Perform the setup required at boot and on resume.
 */

static void hpt3x3_init_chipset(struct pci_dev *dev)
{
	u16 cmd;
	/* Initialize the board */
	pci_write_config_word(dev, 0x80, 0x00);
	/* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	if (cmd & PCI_COMMAND_MEMORY)
		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
	else
		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
}

/**
 *	hpt3x3_init_one		-	Initialise an HPT343/363
 *	@pdev: PCI device
 *	@id: Entry in match table
 *
 *	Perform basic initialisation. We set the device up so we access all
 *	ports via BAR4. This is necessary to work around errata.
 */

static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static int printed_version;
	static const struct ata_port_info info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
#if defined(CONFIG_PATA_HPT3X3_DMA)
		/* Further debug needed */
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA2,
#endif
		.port_ops = &hpt3x3_port_ops
	};
	/* Register offsets of taskfiles in BAR4 area */
	static const u8 offset_cmd[2] = { 0x20, 0x28 };
	static const u8 offset_ctl[2] = { 0x36, 0x3E };
	const struct ata_port_info *ppi[] = { &info, NULL };
	struct ata_host *host;
	int i, rc;
	void __iomem *base;

	hpt3x3_init_chipset(pdev);

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	if (!host)
		return -ENOMEM;
	/* acquire resources and fill host */
	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* Everything is relative to BAR4 if we set up this way */
	rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
	if (rc == -EBUSY)
		pcim_pin_device(pdev);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);
	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;

	base = host->iomap[4];	/* Bus mastering base */

	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
		struct ata_ioports *ioaddr = &ap->ioaddr;

		ioaddr->cmd_addr = base + offset_cmd[i];
		ioaddr->altstatus_addr =
		ioaddr->ctl_addr = base + offset_ctl[i];
		ioaddr->scr_addr = NULL;
		ata_sff_std_ports(ioaddr);
		ioaddr->bmdma_addr = base + 8 * i;

		ata_port_pbar_desc(ap, 4, -1, "ioport");
		ata_port_pbar_desc(ap, 4, offset_cmd[i], "cmd");
	}
	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
				 IRQF_SHARED, &hpt3x3_sht);
}

#ifdef CONFIG_PM
static int hpt3x3_reinit_one(struct pci_dev *dev)
{
	struct ata_host *host = dev_get_drvdata(&dev->dev);
	int rc;

	rc = ata_pci_device_do_resume(dev);
	if (rc)
		return rc;

	hpt3x3_init_chipset(dev);

	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id hpt3x3[] = {
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },

	{ },
};

static struct pci_driver hpt3x3_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= hpt3x3,
	.probe 		= hpt3x3_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= hpt3x3_reinit_one,
#endif
};

static int __init hpt3x3_init(void)
{
	return pci_register_driver(&hpt3x3_pci_driver);
}


static void __exit hpt3x3_exit(void)
{
	pci_unregister_driver(&hpt3x3_pci_driver);
}


MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, hpt3x3);
MODULE_VERSION(DRV_VERSION);

module_init(hpt3x3_init);
module_exit(hpt3x3_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_hpt3x3 - HPT3x3 driver
	3	* (c) Copyright 2005-2006 Red Hat
	4	*
	5	* Was pata_hpt34x but the naming was confusing as it supported the
	6	* 343 and 363 so it has been renamed.
	7	*
	8	* Based on:
	9	* linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
	10	* Copyright (C) 1998-2000 Andre Hedrick <[email protected]>
	11	*
	12	* May be copied or modified under the terms of the GNU General Public
	13	* License
	14	*/
85cd7251	15
669a5db4 JG	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/pci.h>
	19	#include <linux/init.h>
	20	#include <linux/blkdev.h>
	21	#include <linux/delay.h>
	22	#include <scsi/scsi_host.h>
	23	#include <linux/libata.h>
	24
	25	#define DRV_NAME "pata_hpt3x3"
978ff6db	26	#define DRV_VERSION "0.6.1"
669a5db4	27
669a5db4 JG	28	/**
	29	* hpt3x3_set_piomode - PIO setup
	30	* @ap: ATA interface
	31	* @adev: device on the interface
	32	*
	33	* Set our PIO requirements. This is fairly simple on the HPT3x3 as
	34	* all we have to do is clear the MWDMA and UDMA bits then load the
	35	* mode number.
	36	*/
	37
	38	static void hpt3x3_set_piomode(struct ata_port ap, struct ata_device adev)
	39	{
	40	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	41	u32 r1, r2;
	42	int dn = 2 * ap->port_no + adev->devno;
	43
	44	pci_read_config_dword(pdev, 0x44, &r1);
	45	pci_read_config_dword(pdev, 0x48, &r2);
	46	/* Load the PIO timing number */
	47	r1 &= ~(7 << (3 * dn));
	48	r1 \|= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
	49	r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
	50
	51	pci_write_config_dword(pdev, 0x44, r1);
	52	pci_write_config_dword(pdev, 0x48, r2);
	53	}
	54
790956e7	55	#if defined(CONFIG_PATA_HPT3X3_DMA)
669a5db4 JG	56	/**
	57	* hpt3x3_set_dmamode - DMA timing setup
	58	* @ap: ATA interface
	59	* @adev: Device being configured
	60	*
	61	* Set up the channel for MWDMA or UDMA modes. Much the same as with
	62	* PIO, load the mode number and then set MWDMA or UDMA flag.
66e7da4e AC	63	*
	64	* 0x44 : bit 0-2 master mode, 3-5 slave mode, etc
	65	* 0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
669a5db4 JG	66	*/
	67
	68	static void hpt3x3_set_dmamode(struct ata_port ap, struct ata_device adev)
	69	{
	70	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	71	u32 r1, r2;
	72	int dn = 2 * ap->port_no + adev->devno;
	73	int mode_num = adev->dma_mode & 0x0F;
	74
	75	pci_read_config_dword(pdev, 0x44, &r1);
	76	pci_read_config_dword(pdev, 0x48, &r2);
	77	/* Load the timing number */
	78	r1 &= ~(7 << (3 * dn));
	79	r1 \|= (mode_num << (3 * dn));
	80	r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
	81
	82	if (adev->dma_mode >= XFER_UDMA_0)
978ff6db	83	r2 \|= (0x01 << dn); /* Ultra mode */
669a5db4	84	else
978ff6db	85	r2 \|= (0x10 << dn); /* MWDMA */
669a5db4 JG	86
	87	pci_write_config_dword(pdev, 0x44, r1);
	88	pci_write_config_dword(pdev, 0x48, r2);
	89	}
978ff6db AC	90
	91	/**
	92	* hpt3x3_freeze - DMA workaround
	93	* @ap: port to freeze
	94	*
	95	* When freezing an HPT3x3 we must stop any pending DMA before
	96	* writing to the control register or the chip will hang
	97	*/
	98
b63d3953	99	static void hpt3x3_freeze(struct ata_port *ap)
978ff6db AC	100	{
	101	void __iomem *mmio = ap->ioaddr.bmdma_addr;
	102
	103	iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ ATA_DMA_START,
	104	mmio + ATA_DMA_CMD);
	105	ata_sff_dma_pause(ap);
	106	ata_sff_freeze(ap);
	107	}
	108
	109	/**
	110	* hpt3x3_bmdma_setup - DMA workaround
	111	* @qc: Queued command
	112	*
	113	* When issuing BMDMA we must clean up the error/active bits in
	114	* software on this device
	115	*/
	116
	117	static void hpt3x3_bmdma_setup(struct ata_queued_cmd *qc)
	118	{
	119	struct ata_port *ap = qc->ap;
	120	u8 r = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
	121	r \|= ATA_DMA_INTR \| ATA_DMA_ERR;
	122	iowrite8(r, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
	123	return ata_bmdma_setup(qc);
	124	}
669a5db4	125
66e7da4e AC	126	/**
	127	* hpt3x3_atapi_dma - ATAPI DMA check
	128	* @qc: Queued command
	129	*
	130	* Just say no - we don't do ATAPI DMA
	131	*/
	132
	133	static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
	134	{
	135	return 1;
	136	}
	137
978ff6db AC	138	#endif /* CONFIG_PATA_HPT3X3_DMA */
978ff6db AC	139
669a5db4	140	static struct scsi_host_template hpt3x3_sht = {
68d1d07b	141	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	142	};
	143
	144	static struct ata_port_operations hpt3x3_port_ops = {
029cfd6b	145	.inherits = &ata_bmdma_port_ops,
029cfd6b	146	.cable_detect = ata_cable_40wire,
669a5db4	147	.set_piomode = hpt3x3_set_piomode,
790956e7 JG	148	#if defined(CONFIG_PATA_HPT3X3_DMA)
790956e7 JG	149	.set_dmamode = hpt3x3_set_dmamode,
978ff6db AC	150	.bmdma_setup = hpt3x3_bmdma_setup,
	151	.check_atapi_dma= hpt3x3_atapi_dma,
	152	.freeze = hpt3x3_freeze,
790956e7	153	#endif
978ff6db	154
669a5db4 JG	155	};
669a5db4 JG	156
aff0df05 AC	157	/**
	158	* hpt3x3_init_chipset - chip setup
	159	* @dev: PCI device
	160	*
	161	* Perform the setup required at boot and on resume.
	162	*/
f20b16ff	163
aff0df05 AC	164	static void hpt3x3_init_chipset(struct pci_dev *dev)
	165	{
	166	u16 cmd;
	167	/* Initialize the board */
	168	pci_write_config_word(dev, 0x80, 0x00);
	169	/* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
	170	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	171	if (cmd & PCI_COMMAND_MEMORY)
	172	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
	173	else
	174	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
	175	}
	176
669a5db4 JG	177	/**
669a5db4 JG	178	* hpt3x3_init_one - Initialise an HPT343/363
66e7da4e	179	* @pdev: PCI device
669a5db4 JG	180	* @id: Entry in match table
669a5db4 JG	181	*
66e7da4e	182	* Perform basic initialisation. We set the device up so we access all
3ad2f3fb	183	* ports via BAR4. This is necessary to work around errata.
669a5db4 JG	184	*/
669a5db4 JG	185
66e7da4e	186	static int hpt3x3_init_one(struct pci_dev pdev, const struct pci_device_id id)
669a5db4	187	{
66e7da4e	188	static int printed_version;
1626aeb8	189	static const struct ata_port_info info = {
1d2808fd	190	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98	191	.pio_mask = ATA_PIO4,
66e7da4e AC	192	#if defined(CONFIG_PATA_HPT3X3_DMA)
66e7da4e AC	193	/* Further debug needed */
14bdef98 EIB	194	.mwdma_mask = ATA_MWDMA2,
14bdef98 EIB	195	.udma_mask = ATA_UDMA2,
66e7da4e	196	#endif
669a5db4 JG	197	.port_ops = &hpt3x3_port_ops
669a5db4 JG	198	};
66e7da4e AC	199	/* Register offsets of taskfiles in BAR4 area */
	200	static const u8 offset_cmd[2] = { 0x20, 0x28 };
	201	static const u8 offset_ctl[2] = { 0x36, 0x3E };
1626aeb8	202	const struct ata_port_info *ppi[] = { &info, NULL };
66e7da4e AC	203	struct ata_host *host;
	204	int i, rc;
	205	void __iomem *base;
	206
	207	hpt3x3_init_chipset(pdev);
	208
	209	if (!printed_version++)
	210	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
	211
	212	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	213	if (!host)
	214	return -ENOMEM;
	215	/* acquire resources and fill host */
	216	rc = pcim_enable_device(pdev);
	217	if (rc)
	218	return rc;
	219
	220	/* Everything is relative to BAR4 if we set up this way */
	221	rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
	222	if (rc == -EBUSY)
	223	pcim_pin_device(pdev);
	224	if (rc)
	225	return rc;
	226	host->iomap = pcim_iomap_table(pdev);
	227	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	228	if (rc)
	229	return rc;
	230	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	231	if (rc)
	232	return rc;
	233
	234	base = host->iomap[4]; /* Bus mastering base */
	235
	236	for (i = 0; i < host->n_ports; i++) {
cbcdd875 TH	237	struct ata_port *ap = host->ports[i];
cbcdd875 TH	238	struct ata_ioports *ioaddr = &ap->ioaddr;
66e7da4e AC	239
	240	ioaddr->cmd_addr = base + offset_cmd[i];
	241	ioaddr->altstatus_addr =
	242	ioaddr->ctl_addr = base + offset_ctl[i];
	243	ioaddr->scr_addr = NULL;
9363c382	244	ata_sff_std_ports(ioaddr);
66e7da4e	245	ioaddr->bmdma_addr = base + 8 * i;
cbcdd875 TH	246
	247	ata_port_pbar_desc(ap, 4, -1, "ioport");
	248	ata_port_pbar_desc(ap, 4, offset_cmd[i], "cmd");
66e7da4e AC	249	}
66e7da4e AC	250	pci_set_master(pdev);
9363c382 TH	251	return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
9363c382 TH	252	IRQF_SHARED, &hpt3x3_sht);
669a5db4 JG	253	}
669a5db4 JG	254
438ac6d5	255	#ifdef CONFIG_PM
aff0df05 AC	256	static int hpt3x3_reinit_one(struct pci_dev *dev)
aff0df05 AC	257	{
39150444 BZ	258	struct ata_host *host = dev_get_drvdata(&dev->dev);
	259	int rc;
	260
	261	rc = ata_pci_device_do_resume(dev);
	262	if (rc)
	263	return rc;
	264
aff0df05	265	hpt3x3_init_chipset(dev);
39150444 BZ	266
	267	ata_host_resume(host);
	268	return 0;
aff0df05	269	}
438ac6d5	270	#endif
aff0df05	271
2d2744fc JG	272	static const struct pci_device_id hpt3x3[] = {
	273	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },
	274
	275	{ },
669a5db4 JG	276	};
	277
	278	static struct pci_driver hpt3x3_pci_driver = {
2d2744fc	279	.name = DRV_NAME,
669a5db4 JG	280	.id_table = hpt3x3,
669a5db4 JG	281	.probe = hpt3x3_init_one,
aff0df05	282	.remove = ata_pci_remove_one,
438ac6d5	283	#ifdef CONFIG_PM
aff0df05 AC	284	.suspend = ata_pci_device_suspend,
aff0df05 AC	285	.resume = hpt3x3_reinit_one,
438ac6d5	286	#endif
669a5db4 JG	287	};
	288
	289	static int __init hpt3x3_init(void)
	290	{
	291	return pci_register_driver(&hpt3x3_pci_driver);
	292	}
	293
	294
	295	static void __exit hpt3x3_exit(void)
	296	{
	297	pci_unregister_driver(&hpt3x3_pci_driver);
	298	}
	299
	300
	301	MODULE_AUTHOR("Alan Cox");
	302	MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
	303	MODULE_LICENSE("GPL");
	304	MODULE_DEVICE_TABLE(pci, hpt3x3);
	305	MODULE_VERSION(DRV_VERSION);
	306
	307	module_init(hpt3x3_init);
b63d3953	308	module_exit(hpt3x3_exit);