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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/signal
[linux.git] / drivers / pinctrl / sh-pfc / pfc-r8a73a4.c
CommitLineData
c98f6c21
MD		 1/*
2 * Copyright (C) 2012-2013 Renesas Solutions Corp.
3 * Copyright (C) 2013 Magnus Damm
4 * Copyright (C) 2012 Kuninori Morimoto <[email protected]>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of the
9 * License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
57ef73b4 20#include <linux/io.h>
c98f6c21 21#include <linux/kernel.h>
57ef73b4 22#include <linux/pinctrl/pinconf-generic.h>
c98f6c21
MD		 23#include <mach/irqs.h>
24#include <mach/r8a73a4.h>
25
57ef73b4 26#include "core.h"
c98f6c21
MD		 27#include "sh_pfc.h"
28
29#define CPU_ALL_PORT(fn, pfx, sfx) \
30 /* Port0 - Port30 */ \
31 PORT_10(fn, pfx, sfx), \
32 PORT_10(fn, pfx##1, sfx), \
33 PORT_10(fn, pfx##2, sfx), \
34 PORT_1(fn, pfx##30, sfx), \
35 /* Port32 - Port40 */ \
36 PORT_1(fn, pfx##32, sfx), PORT_1(fn, pfx##33, sfx), \
37 PORT_1(fn, pfx##34, sfx), PORT_1(fn, pfx##35, sfx), \
38 PORT_1(fn, pfx##36, sfx), PORT_1(fn, pfx##37, sfx), \
39 PORT_1(fn, pfx##38, sfx), PORT_1(fn, pfx##39, sfx), \
40 PORT_1(fn, pfx##40, sfx), \
41 /* Port64 - Port85 */ \
42 PORT_1(fn, pfx##64, sfx), PORT_1(fn, pfx##65, sfx), \
43 PORT_1(fn, pfx##66, sfx), PORT_1(fn, pfx##67, sfx), \
44 PORT_1(fn, pfx##68, sfx), PORT_1(fn, pfx##69, sfx), \
45 PORT_10(fn, pfx##7, sfx), \
46 PORT_1(fn, pfx##80, sfx), PORT_1(fn, pfx##81, sfx), \
47 PORT_1(fn, pfx##82, sfx), PORT_1(fn, pfx##83, sfx), \
48 PORT_1(fn, pfx##84, sfx), PORT_1(fn, pfx##85, sfx), \
49 /* Port96 - Port126 */ \
50 PORT_1(fn, pfx##96, sfx), PORT_1(fn, pfx##97, sfx), \
51 PORT_1(fn, pfx##98, sfx), PORT_1(fn, pfx##99, sfx), \
52 PORT_10(fn, pfx##10, sfx), \
53 PORT_10(fn, pfx##11, sfx), \
54 PORT_1(fn, pfx##120, sfx), PORT_1(fn, pfx##121, sfx), \
55 PORT_1(fn, pfx##122, sfx), PORT_1(fn, pfx##123, sfx), \
56 PORT_1(fn, pfx##124, sfx), PORT_1(fn, pfx##125, sfx), \
57 PORT_1(fn, pfx##126, sfx), \
58 /* Port128 - Port134 */ \
59 PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
60 PORT_1(fn, pfx##130, sfx), PORT_1(fn, pfx##131, sfx), \
61 PORT_1(fn, pfx##132, sfx), PORT_1(fn, pfx##133, sfx), \
62 PORT_1(fn, pfx##134, sfx), \
63 /* Port160 - Port178 */ \
64 PORT_10(fn, pfx##16, sfx), \
65 PORT_1(fn, pfx##170, sfx), PORT_1(fn, pfx##171, sfx), \
66 PORT_1(fn, pfx##172, sfx), PORT_1(fn, pfx##173, sfx), \
67 PORT_1(fn, pfx##174, sfx), PORT_1(fn, pfx##175, sfx), \
68 PORT_1(fn, pfx##176, sfx), PORT_1(fn, pfx##177, sfx), \
69 PORT_1(fn, pfx##178, sfx), \
70 /* Port192 - Port222 */ \
71 PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
72 PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
73 PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
74 PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
75 PORT_10(fn, pfx##20, sfx), \
76 PORT_10(fn, pfx##21, sfx), \
77 PORT_1(fn, pfx##220, sfx), PORT_1(fn, pfx##221, sfx), \
78 PORT_1(fn, pfx##222, sfx), \
79 /* Port224 - Port250 */ \
80 PORT_1(fn, pfx##224, sfx), PORT_1(fn, pfx##225, sfx), \
81 PORT_1(fn, pfx##226, sfx), PORT_1(fn, pfx##227, sfx), \
82 PORT_1(fn, pfx##228, sfx), PORT_1(fn, pfx##229, sfx), \
83 PORT_10(fn, pfx##23, sfx), \
84 PORT_10(fn, pfx##24, sfx), \
85 PORT_1(fn, pfx##250, sfx), \
86 /* Port256 - Port283 */ \
87 PORT_1(fn, pfx##256, sfx), PORT_1(fn, pfx##257, sfx), \
88 PORT_1(fn, pfx##258, sfx), PORT_1(fn, pfx##259, sfx), \
89 PORT_10(fn, pfx##26, sfx), \
90 PORT_10(fn, pfx##27, sfx), \
91 PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
92 PORT_1(fn, pfx##282, sfx), PORT_1(fn, pfx##283, sfx), \
93 /* Port288 - Port308 */ \
94 PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
95 PORT_10(fn, pfx##29, sfx), \
96 PORT_1(fn, pfx##300, sfx), PORT_1(fn, pfx##301, sfx), \
97 PORT_1(fn, pfx##302, sfx), PORT_1(fn, pfx##303, sfx), \
98 PORT_1(fn, pfx##304, sfx), PORT_1(fn, pfx##305, sfx), \
99 PORT_1(fn, pfx##306, sfx), PORT_1(fn, pfx##307, sfx), \
100 PORT_1(fn, pfx##308, sfx), \
101 /* Port320 - Port329 */ \
102 PORT_10(fn, pfx##32, sfx)
103
104
105enum {
106 PINMUX_RESERVED = 0,
107
108 /* PORT0_DATA -> PORT329_DATA */
109 PINMUX_DATA_BEGIN,
110 PORT_ALL(DATA),
111 PINMUX_DATA_END,
112
113 /* PORT0_IN -> PORT329_IN */
114 PINMUX_INPUT_BEGIN,
115 PORT_ALL(IN),
116 PINMUX_INPUT_END,
117
c98f6c21
MD		 118 /* PORT0_OUT -> PORT329_OUT */
119 PINMUX_OUTPUT_BEGIN,
120 PORT_ALL(OUT),
121 PINMUX_OUTPUT_END,
122
123 PINMUX_FUNCTION_BEGIN,
124 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
125 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
126 PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
127 PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
128 PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
129 PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
130 PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
131 PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
132 PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
133 PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
134
135 MSEL1CR_31_0, MSEL1CR_31_1,
136 MSEL1CR_27_0, MSEL1CR_27_1,
137 MSEL1CR_25_0, MSEL1CR_25_1,
138 MSEL1CR_24_0, MSEL1CR_24_1,
139 MSEL1CR_22_0, MSEL1CR_22_1,
140 MSEL1CR_21_0, MSEL1CR_21_1,
141 MSEL1CR_20_0, MSEL1CR_20_1,
142 MSEL1CR_19_0, MSEL1CR_19_1,
143 MSEL1CR_18_0, MSEL1CR_18_1,
144 MSEL1CR_17_0, MSEL1CR_17_1,
145 MSEL1CR_16_0, MSEL1CR_16_1,
146 MSEL1CR_15_0, MSEL1CR_15_1,
147 MSEL1CR_14_0, MSEL1CR_14_1,
148 MSEL1CR_13_0, MSEL1CR_13_1,
149 MSEL1CR_12_0, MSEL1CR_12_1,
150 MSEL1CR_11_0, MSEL1CR_11_1,
151 MSEL1CR_10_0, MSEL1CR_10_1,
152 MSEL1CR_09_0, MSEL1CR_09_1,
153 MSEL1CR_08_0, MSEL1CR_08_1,
154 MSEL1CR_07_0, MSEL1CR_07_1,
155 MSEL1CR_06_0, MSEL1CR_06_1,
156 MSEL1CR_05_0, MSEL1CR_05_1,
157 MSEL1CR_04_0, MSEL1CR_04_1,
158 MSEL1CR_03_0, MSEL1CR_03_1,
159 MSEL1CR_02_0, MSEL1CR_02_1,
160 MSEL1CR_01_0, MSEL1CR_01_1,
161 MSEL1CR_00_0, MSEL1CR_00_1,
162
163 MSEL3CR_31_0, MSEL3CR_31_1,
164 MSEL3CR_28_0, MSEL3CR_28_1,
165 MSEL3CR_27_0, MSEL3CR_27_1,
166 MSEL3CR_26_0, MSEL3CR_26_1,
167 MSEL3CR_23_0, MSEL3CR_23_1,
168 MSEL3CR_22_0, MSEL3CR_22_1,
169 MSEL3CR_21_0, MSEL3CR_21_1,
170 MSEL3CR_20_0, MSEL3CR_20_1,
171 MSEL3CR_19_0, MSEL3CR_19_1,
172 MSEL3CR_18_0, MSEL3CR_18_1,
173 MSEL3CR_17_0, MSEL3CR_17_1,
174 MSEL3CR_16_0, MSEL3CR_16_1,
175 MSEL3CR_15_0, MSEL3CR_15_1,
176 MSEL3CR_12_0, MSEL3CR_12_1,
177 MSEL3CR_11_0, MSEL3CR_11_1,
178 MSEL3CR_10_0, MSEL3CR_10_1,
179 MSEL3CR_09_0, MSEL3CR_09_1,
180 MSEL3CR_06_0, MSEL3CR_06_1,
181 MSEL3CR_03_0, MSEL3CR_03_1,
182 MSEL3CR_01_0, MSEL3CR_01_1,
183 MSEL3CR_00_0, MSEL3CR_00_1,
184
185 MSEL4CR_30_0, MSEL4CR_30_1,
186 MSEL4CR_29_0, MSEL4CR_29_1,
187 MSEL4CR_28_0, MSEL4CR_28_1,
188 MSEL4CR_27_0, MSEL4CR_27_1,
189 MSEL4CR_26_0, MSEL4CR_26_1,
190 MSEL4CR_25_0, MSEL4CR_25_1,
191 MSEL4CR_24_0, MSEL4CR_24_1,
192 MSEL4CR_23_0, MSEL4CR_23_1,
193 MSEL4CR_22_0, MSEL4CR_22_1,
194 MSEL4CR_21_0, MSEL4CR_21_1,
195 MSEL4CR_20_0, MSEL4CR_20_1,
196 MSEL4CR_19_0, MSEL4CR_19_1,
197 MSEL4CR_18_0, MSEL4CR_18_1,
198 MSEL4CR_17_0, MSEL4CR_17_1,
199 MSEL4CR_16_0, MSEL4CR_16_1,
200 MSEL4CR_15_0, MSEL4CR_15_1,
201 MSEL4CR_14_0, MSEL4CR_14_1,
202 MSEL4CR_13_0, MSEL4CR_13_1,
203 MSEL4CR_12_0, MSEL4CR_12_1,
204 MSEL4CR_11_0, MSEL4CR_11_1,
205 MSEL4CR_10_0, MSEL4CR_10_1,
206 MSEL4CR_09_0, MSEL4CR_09_1,
207 MSEL4CR_07_0, MSEL4CR_07_1,
208 MSEL4CR_04_0, MSEL4CR_04_1,
209 MSEL4CR_01_0, MSEL4CR_01_1,
210
211 MSEL5CR_31_0, MSEL5CR_31_1,
212 MSEL5CR_30_0, MSEL5CR_30_1,
213 MSEL5CR_29_0, MSEL5CR_29_1,
214 MSEL5CR_28_0, MSEL5CR_28_1,
215 MSEL5CR_27_0, MSEL5CR_27_1,
216 MSEL5CR_26_0, MSEL5CR_26_1,
217 MSEL5CR_25_0, MSEL5CR_25_1,
218 MSEL5CR_24_0, MSEL5CR_24_1,
219 MSEL5CR_23_0, MSEL5CR_23_1,
220 MSEL5CR_22_0, MSEL5CR_22_1,
221 MSEL5CR_21_0, MSEL5CR_21_1,
222 MSEL5CR_20_0, MSEL5CR_20_1,
223 MSEL5CR_19_0, MSEL5CR_19_1,
224 MSEL5CR_18_0, MSEL5CR_18_1,
225 MSEL5CR_17_0, MSEL5CR_17_1,
226 MSEL5CR_16_0, MSEL5CR_16_1,
227 MSEL5CR_15_0, MSEL5CR_15_1,
228 MSEL5CR_14_0, MSEL5CR_14_1,
229 MSEL5CR_13_0, MSEL5CR_13_1,
230 MSEL5CR_12_0, MSEL5CR_12_1,
231 MSEL5CR_11_0, MSEL5CR_11_1,
232 MSEL5CR_10_0, MSEL5CR_10_1,
233 MSEL5CR_09_0, MSEL5CR_09_1,
234 MSEL5CR_08_0, MSEL5CR_08_1,
235 MSEL5CR_07_0, MSEL5CR_07_1,
236 MSEL5CR_06_0, MSEL5CR_06_1,
237
238 MSEL8CR_16_0, MSEL8CR_16_1,
239 MSEL8CR_01_0, MSEL8CR_01_1,
240 MSEL8CR_00_0, MSEL8CR_00_1,
241
242 PINMUX_FUNCTION_END,
243
244 PINMUX_MARK_BEGIN,
245
246
247#define F1(a) a##_MARK
248#define F2(a) a##_MARK
249#define F3(a) a##_MARK
250#define F4(a) a##_MARK
251#define F5(a) a##_MARK
252#define F6(a) a##_MARK
253#define F7(a) a##_MARK
254#define IRQ(a) IRQ##a##_MARK
255
256 F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
257 F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
258 F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
259 F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
260 F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
261 F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
262 F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
263 F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
264 F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
265 F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
266 F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
267 F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
268 F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
269 F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
270 F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
271 F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
272 F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
273 F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
274 F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
275 F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
276 F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
277 F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
278 F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
279 F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
280 F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
281 F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
282 F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
283 F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
284 F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
285 F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
286 F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
287 F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
288
289 F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
290 F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
291 F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
292 F1(SCIFA1_RTS), F7(CSCIF1_RTS),
293 F1(SCIFA1_CTS), F7(CSCIF1_CTS),
294 F1(SCIFA1_SCK), F7(CSCIF1_SCK),
295 F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
296 F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
297 F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
298 F7(CHSCIF0_HSCK), /* Port40 */
299
300 F1(PDM0_DATA), /* Port64 */
301 F1(PDM1_DATA),
302 F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
303 IRQ(40),
304 F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
305 F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
306 F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
307 F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
308 F7(CHSCIF1_HRTS), /* Port70 */
309 F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
310 F7(CHSCIF1_HCTS),
311 F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
312 F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
313 F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
314 F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
315 F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
316
317 F1(KEYIN0), /* Port96 */
318 F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
319 F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
320 F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
321 F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
322 F2(KEYOUT7), F5(RFANAEN), IRQ(45),
323 F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
324 F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
325 F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
326 F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
327 F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
328 F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
329 F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
330 F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
331 F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
332 F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
333 F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
334 F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
335 F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
336 F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
337 F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
338 F5(SIM0_VOLTSEL1), /* Port130 */
339 F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
340 F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
341 F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
342 IRQ(20), /* Port160 */
343 IRQ(21), IRQ(22), IRQ(23),
344 F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
345 F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
346 F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
347 IRQ(24), IRQ(25), IRQ(26), IRQ(27),
348 F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
349 F1(A9), F2(MMCD1_6), IRQ(32),
350 F1(A8), F2(MMCD1_5), IRQ(33),
351 F1(A7), F2(MMCD1_4), IRQ(34),
352 F1(A6), F2(MMCD1_3), IRQ(35),
353 F1(A5), F2(MMCD1_2), IRQ(36),
354 F1(A4), F2(MMCD1_1), IRQ(37),
355 F1(A3), F2(MMCD1_0), IRQ(38),
356 F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
357 F1(A1),
358 F1(A0), F2(BS),
359 F1(CKO), F2(MMCCLK1),
360 F1(CS0_N), F5(SIM0_GPO1),
361 F1(CS2_N), F5(SIM0_GPO2),
362 F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
363 F1(D15), F5(GIO_OUT15),
364 F1(D14), F5(GIO_OUT14),
365 F1(D13), F5(GIO_OUT13),
366 F1(D12), F5(GIO_OUT12), /* Port210 */
367 F1(D11), F5(WGM_TXP2),
368 F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
369 F1(D9), F2(VIO_D9), F5(GIO_OUT9),
370 F1(D8), F2(VIO_D8), F5(GIO_OUT8),
371 F1(D7), F2(VIO_D7), F5(GIO_OUT7),
372 F1(D6), F2(VIO_D6), F5(GIO_OUT6),
373 F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
374 F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
375 F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
376 F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
377 F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
378 F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
379 F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
380 F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
381 F1(WE0_N), F2(RDWR_227),
382 F1(WE1_N), F5(SIM0_GPO0),
383 F1(PWMO), F2(VIO_CKO1_229),
384 F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
385 F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
386 F2(VIO_CKO3_233), F4(SF_PORT_1_233),
387 F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
388 F1(FSIAISLD), F2(PDM3_DATA_235),
389 F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
390 F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
391 F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
392 F1(FSIBISLD), /* Port240 */
393 F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
394 F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
395 F1(FSIBCK), F3(ISP_SHUTTER0_245),
396 F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
397 F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
398 F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
399 F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
400 F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
401 F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
402 F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
403 F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
404 F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
405 F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
406 F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
407 F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
408 F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
409 F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
410 F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
411 F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
412 F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
413 F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
414 F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
415 F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
416 F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
417 F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
418 F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
419 F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
420 F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
421 F4(MSIOF6_SS1), /* Port300 */
422 F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
423 F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
424 F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
425 F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
426 IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
427 IRQ(55), IRQ(56), IRQ(57),
428 PINMUX_MARK_END,
429};
430
202ac6a2
MD		 431#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
432#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
433
c98f6c21
MD		 434static const pinmux_enum_t pinmux_data[] = {
435 /* specify valid pin states for each pin in GPIO mode */
202ac6a2 436 PINMUX_DATA_ALL(),
c98f6c21
MD		 437
438 /* Port0 */
439 PINMUX_DATA(LCDD0_MARK, PORT0_FN1),
440 PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3),
441 PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7),
442 PINMUX_DATA(IRQ0_MARK, PORT0_FN0),
443
444 /* Port1 */
445 PINMUX_DATA(LCDD1_MARK, PORT1_FN1),
446 PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0),
447 PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7),
448 PINMUX_DATA(IRQ1_MARK, PORT1_FN0),
449
450 /* Port2 */
451 PINMUX_DATA(LCDD2_MARK, PORT2_FN1),
452 PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3),
453 PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7),
454 PINMUX_DATA(IRQ2_MARK, PORT2_FN0),
455
456 /* Port3 */
457 PINMUX_DATA(LCDD3_MARK, PORT3_FN1),
458 PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0),
459 PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7),
460 PINMUX_DATA(IRQ3_MARK, PORT3_FN0),
461
462 /* Port4 */
463 PINMUX_DATA(LCDD4_MARK, PORT4_FN1),
464 PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3),
465 PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7),
466 PINMUX_DATA(IRQ4_MARK, PORT4_FN0),
467
468 /* Port5 */
469 PINMUX_DATA(LCDD5_MARK, PORT5_FN1),
470 PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0),
471 PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7),
472 PINMUX_DATA(IRQ5_MARK, PORT5_FN0),
473
474 /* Port6 */
475 PINMUX_DATA(LCDD6_MARK, PORT6_FN1),
476 PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3),
477 PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7),
478 PINMUX_DATA(IRQ6_MARK, PORT6_FN0),
479
480 /* Port7 */
481 PINMUX_DATA(LCDD7_MARK, PORT7_FN1),
482 PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3),
483 PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7),
484 PINMUX_DATA(IRQ7_MARK, PORT7_FN0),
485
486 /* Port8 */
487 PINMUX_DATA(LCDD8_MARK, PORT8_FN1),
488 PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3),
489 PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7),
490 PINMUX_DATA(IRQ8_MARK, PORT8_FN0),
491
492 /* Port9 */
493 PINMUX_DATA(LCDD9_MARK, PORT9_FN1),
494 PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
495 PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7),
496 PINMUX_DATA(IRQ9_MARK, PORT9_FN0),
497
498 /* Port10 */
499 PINMUX_DATA(LCDD10_MARK, PORT10_FN1),
500 PINMUX_DATA(FSICCK_MARK, PORT10_FN3),
501 PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7),
502 PINMUX_DATA(IRQ10_MARK, PORT10_FN0),
503
504 /* Port11 */
505 PINMUX_DATA(LCDD11_MARK, PORT11_FN1),
506 PINMUX_DATA(FSICISLD_MARK, PORT11_FN3),
507 PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7),
508 PINMUX_DATA(IRQ11_MARK, PORT11_FN0),
509
510 /* Port12 */
511 PINMUX_DATA(LCDD12_MARK, PORT12_FN1),
512 PINMUX_DATA(FSICOMC_MARK, PORT12_FN3),
513 PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7),
514 PINMUX_DATA(IRQ12_MARK, PORT12_FN0),
515
516 /* Port13 */
517 PINMUX_DATA(LCDD13_MARK, PORT13_FN1),
518 PINMUX_DATA(FSICOLR_MARK, PORT13_FN3),
519 PINMUX_DATA(FSICILR_MARK, PORT13_FN4),
520 PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7),
521 PINMUX_DATA(IRQ13_MARK, PORT13_FN0),
522
523 /* Port14 */
524 PINMUX_DATA(LCDD14_MARK, PORT14_FN1),
525 PINMUX_DATA(FSICOBT_MARK, PORT14_FN3),
526 PINMUX_DATA(FSICIBT_MARK, PORT14_FN4),
527 PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7),
528 PINMUX_DATA(IRQ14_MARK, PORT14_FN0),
529
530 /* Port15 */
531 PINMUX_DATA(LCDD15_MARK, PORT15_FN1),
532 PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3),
533 PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7),
534 PINMUX_DATA(IRQ15_MARK, PORT15_FN0),
535
536 /* Port16 */
537 PINMUX_DATA(LCDD16_MARK, PORT16_FN1),
538 PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4),
539 PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7),
540
541 /* Port17 */
542 PINMUX_DATA(LCDD17_MARK, PORT17_FN1),
543 PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4),
544 PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7),
545
546 /* Port18 */
547 PINMUX_DATA(LCDD18_MARK, PORT18_FN1),
548 PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4),
549 PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7),
550
551 /* Port19 */
552 PINMUX_DATA(LCDD19_MARK, PORT19_FN1),
553 PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3),
554 PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7),
555
556 /* Port20 */
557 PINMUX_DATA(LCDD20_MARK, PORT20_FN1),
558 PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0),
559 PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7),
560
561 /* Port21 */
562 PINMUX_DATA(LCDD21_MARK, PORT21_FN1),
563 PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0),
564 PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7),
565
566 /* Port22 */
567 PINMUX_DATA(LCDD22_MARK, PORT22_FN1),
568 PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0),
569 PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7),
570
571 /* Port23 */
572 PINMUX_DATA(LCDD23_MARK, PORT23_FN1),
573 PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3),
574 PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7),
575
576 /* Port24 */
577 PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1),
578 PINMUX_DATA(LCDCS_MARK, PORT24_FN2),
579 PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3),
580 PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7),
581
582 /* Port25 */
583 PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1),
584 PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
585 PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7),
586
587 /* Port26 */
588 PINMUX_DATA(LCDDCK_MARK, PORT26_FN1),
589 PINMUX_DATA(LCDWR_MARK, PORT26_FN2),
590 PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0),
591 PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7),
592
593 /* Port27 */
594 PINMUX_DATA(LCDDISP_MARK, PORT27_FN1),
595 PINMUX_DATA(LCDRS_MARK, PORT27_FN2),
596 PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0),
597 PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7),
598
599 /* Port28 */
600 PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1),
601 PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3),
602 PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7),
603
604 /* Port29 */
605 PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1),
606 PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4),
607 PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7),
608
609 /* Port30 */
610 PINMUX_DATA(LCDDON_MARK, PORT30_FN1),
611 PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4),
612 PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7),
613
614 /* Port32 */
615 PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1),
616 PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5),
617 PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7),
618
619 /* Port33 */
620 PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1),
621 PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5),
622 PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7),
623
624 /* Port34 */
625 PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1),
626 PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5),
627 PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7),
628
629 /* Port35 */
630 PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1),
631 PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7),
632
633 /* Port36 */
634 PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1),
635 PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7),
636
637 /* Port37 */
638 PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1),
639 PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7),
640
641 /* Port38 */
642 PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1),
643 PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3),
644 PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4),
645 PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7),
646
647 /* Port39 */
648 PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1),
649 PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3),
650 PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1),
651 PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7),
652
653 /* Port40 */
654 PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1),
655 PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3),
656 PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4),
657 PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7),
658
659 /* Port64 */
660 PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1),
661
662 /* Port65 */
663 PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1),
664
665 /* Port66 */
666 PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1),
667 PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0),
668 PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3),
669 PINMUX_DATA(GenIO4_MARK, PORT66_FN5),
670 PINMUX_DATA(IRQ40_MARK, PORT66_FN0),
671
672 /* Port67 */
673 PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1),
674 PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1),
675 PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5),
676 PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7),
677
678 /* Port68 */
679 PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1),
680 PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0),
681 PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3),
682 PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5),
683
684 /* Port69 */
685 PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1),
686 PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0),
687 PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3),
688 PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5),
689
690 /* Port70 */
691 PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1),
692 PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2),
693 PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5),
694 PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6),
695 PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7),
696
697 /* Port71 */
698 PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1),
699 PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1),
700 PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5),
701 PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6),
702 PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7),
703
704 /* Port72 */
705 PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1),
706 PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1),
707 PINMUX_DATA(GenIO8_MARK, PORT72_FN5),
708 PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7),
709
710 /* Port73 */
711 PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1),
712 PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2),
713 PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3),
714 PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5),
715
716 /* Port74 - Port85 */
717 PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1),
718 PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1),
719 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1),
720 PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1),
721 PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1),
722 PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1),
723 PINMUX_DATA(TXP_MARK, PORT80_FN1),
724 PINMUX_DATA(TXP2_MARK, PORT81_FN1),
725 PINMUX_DATA(COEX_0_MARK, PORT82_FN1),
726 PINMUX_DATA(COEX_1_MARK, PORT83_FN1),
727 PINMUX_DATA(IRQ19_MARK, PORT84_FN0),
728 PINMUX_DATA(IRQ18_MARK, PORT85_FN0),
729
730 /* Port96 - Port101 */
731 PINMUX_DATA(KEYIN0_MARK, PORT96_FN1),
732 PINMUX_DATA(KEYIN1_MARK, PORT97_FN1),
733 PINMUX_DATA(KEYIN2_MARK, PORT98_FN1),
734 PINMUX_DATA(KEYIN3_MARK, PORT99_FN1),
735 PINMUX_DATA(KEYIN4_MARK, PORT100_FN1),
736 PINMUX_DATA(KEYIN5_MARK, PORT101_FN1),
737
738 /* Port102 */
739 PINMUX_DATA(KEYIN6_MARK, PORT102_FN1),
740 PINMUX_DATA(IRQ41_MARK, PORT102_FN0),
741
742 /* Port103 */
743 PINMUX_DATA(KEYIN7_MARK, PORT103_FN1),
744 PINMUX_DATA(IRQ42_MARK, PORT103_FN0),
745
746 /* Port104 - Port108 */
747 PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2),
748 PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2),
749 PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2),
750 PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2),
751 PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2),
752
753 /* Port109 */
754 PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2),
755 PINMUX_DATA(IRQ43_MARK, PORT109_FN0),
756
757 /* Port110 */
758 PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2),
759 PINMUX_DATA(IRQ44_MARK, PORT110_FN0),
760
761 /* Port111 */
762 PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2),
763 PINMUX_DATA(RFANAEN_MARK, PORT111_FN5),
764 PINMUX_DATA(IRQ45_MARK, PORT111_FN0),
765
766 /* Port112 */
767 PINMUX_DATA(KEYIN8_MARK, PORT112_FN1),
768 PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2),
769 PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4),
770 PINMUX_DATA(IRQ46_MARK, PORT112_FN0),
771
772 /* Port113 */
773 PINMUX_DATA(KEYIN9_MARK, PORT113_FN1),
774 PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2),
775 PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4),
776 PINMUX_DATA(IRQ47_MARK, PORT113_FN0),
777
778 /* Port114 */
779 PINMUX_DATA(KEYIN10_MARK, PORT114_FN1),
780 PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2),
781 PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4),
782 PINMUX_DATA(IRQ48_MARK, PORT114_FN0),
783
784 /* Port115 */
785 PINMUX_DATA(KEYIN11_MARK, PORT115_FN1),
786 PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2),
787 PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4),
788 PINMUX_DATA(IRQ49_MARK, PORT115_FN0),
789
790 /* Port116 */
791 PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1),
792 PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7),
793
794 /* Port117 */
795 PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1),
796 PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7),
797
798 /* Port118 */
799 PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1),
800 PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7),
801
802 /* Port119 */
803 PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1),
804 PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7),
805
806 /* Port120 */
807 PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3),
808 PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1),
809 PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7),
810
811 /* Port121 */
812 PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3),
813 PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1),
814
815 /* Port122 */
816 PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1),
817 PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7),
818
819 /* Port123 */
820 PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1),
821 PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7),
822
823 /* Port124 */
824 PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3),
825
826 /* Port125 */
827 PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1),
828 PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2),
829 PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3),
830 PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5),
831
832 /* Port126 */
833 PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1),
834 PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2),
835 PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3),
836
837 /* Port128 */
838 PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1),
839 PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2),
840 PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3),
841 PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5),
842
843 /* Port129 */
844 PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1),
845 PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2),
846 PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3),
847
848 /* Port130 */
849 PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1),
850 PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1),
851 PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3),
852 PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5),
853
854 /* Port131 */
855 PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1),
856 PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5),
857
858 /* Port132 */
859 PINMUX_DATA(TS_SCK_MARK, PORT132_FN1),
860 PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2),
861 PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3),
862
863 /* Port133 */
864 PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1),
865 PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2),
866 PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3),
867 PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5),
868
869 /* Port134 */
870 PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1),
871 PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2),
872 PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3),
873
874 /* Port160 - Port178 */
875 PINMUX_DATA(IRQ20_MARK, PORT160_FN0),
876 PINMUX_DATA(IRQ21_MARK, PORT161_FN0),
877 PINMUX_DATA(IRQ22_MARK, PORT162_FN0),
878 PINMUX_DATA(IRQ23_MARK, PORT163_FN0),
879 PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1),
880 PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1),
881 PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1),
882 PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1),
883 PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1),
884 PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1),
885 PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1),
886 PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1),
887 PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1),
888 PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1),
889 PINMUX_DATA(MMCRST_MARK, PORT174_FN1),
890 PINMUX_DATA(IRQ24_MARK, PORT175_FN0),
891 PINMUX_DATA(IRQ25_MARK, PORT176_FN0),
892 PINMUX_DATA(IRQ26_MARK, PORT177_FN0),
893 PINMUX_DATA(IRQ27_MARK, PORT178_FN0),
894
895 /* Port192 - Port200 FN1 */
896 PINMUX_DATA(A10_MARK, PORT192_FN1),
897 PINMUX_DATA(A9_MARK, PORT193_FN1),
898 PINMUX_DATA(A8_MARK, PORT194_FN1),
899 PINMUX_DATA(A7_MARK, PORT195_FN1),
900 PINMUX_DATA(A6_MARK, PORT196_FN1),
901 PINMUX_DATA(A5_MARK, PORT197_FN1),
902 PINMUX_DATA(A4_MARK, PORT198_FN1),
903 PINMUX_DATA(A3_MARK, PORT199_FN1),
904 PINMUX_DATA(A2_MARK, PORT200_FN1),
905
906 /* Port192 - Port200 FN2 */
907 PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2),
908 PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2),
909 PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2),
910 PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2),
911 PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2),
912 PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2),
913 PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2),
914 PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2),
915 PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2),
916
917 /* Port192 - Port200 IRQ */
918 PINMUX_DATA(IRQ31_MARK, PORT192_FN0),
919 PINMUX_DATA(IRQ32_MARK, PORT193_FN0),
920 PINMUX_DATA(IRQ33_MARK, PORT194_FN0),
921 PINMUX_DATA(IRQ34_MARK, PORT195_FN0),
922 PINMUX_DATA(IRQ35_MARK, PORT196_FN0),
923 PINMUX_DATA(IRQ36_MARK, PORT197_FN0),
924 PINMUX_DATA(IRQ37_MARK, PORT198_FN0),
925 PINMUX_DATA(IRQ38_MARK, PORT199_FN0),
926 PINMUX_DATA(IRQ39_MARK, PORT200_FN0),
927
928 /* Port201 */
929 PINMUX_DATA(A1_MARK, PORT201_FN1),
930
931 /* Port202 */
932 PINMUX_DATA(A0_MARK, PORT202_FN1),
933 PINMUX_DATA(BS_MARK, PORT202_FN2),
934
935 /* Port203 */
936 PINMUX_DATA(CKO_MARK, PORT203_FN1),
937 PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2),
938
939 /* Port204 */
940 PINMUX_DATA(CS0_N_MARK, PORT204_FN1),
941 PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5),
942
943 /* Port205 */
944 PINMUX_DATA(CS2_N_MARK, PORT205_FN1),
945 PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5),
946
947 /* Port206 */
948 PINMUX_DATA(CS4_N_MARK, PORT206_FN1),
949 PINMUX_DATA(VIO_VD_MARK, PORT206_FN2),
950 PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5),
951
952 /* Port207 - Port212 FN1 */
953 PINMUX_DATA(D15_MARK, PORT207_FN1),
954 PINMUX_DATA(D14_MARK, PORT208_FN1),
955 PINMUX_DATA(D13_MARK, PORT209_FN1),
956 PINMUX_DATA(D12_MARK, PORT210_FN1),
957 PINMUX_DATA(D11_MARK, PORT211_FN1),
958 PINMUX_DATA(D10_MARK, PORT212_FN1),
959
960 /* Port207 - Port212 FN5 */
961 PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5),
962 PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5),
963 PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5),
964 PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5),
965 PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5),
966 PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5),
967
968 /* Port213 - Port222 FN1 */
969 PINMUX_DATA(D9_MARK, PORT213_FN1),
970 PINMUX_DATA(D8_MARK, PORT214_FN1),
971 PINMUX_DATA(D7_MARK, PORT215_FN1),
972 PINMUX_DATA(D6_MARK, PORT216_FN1),
973 PINMUX_DATA(D5_MARK, PORT217_FN1),
974 PINMUX_DATA(D4_MARK, PORT218_FN1),
975 PINMUX_DATA(D3_MARK, PORT219_FN1),
976 PINMUX_DATA(D2_MARK, PORT220_FN1),
977 PINMUX_DATA(D1_MARK, PORT221_FN1),
978 PINMUX_DATA(D0_MARK, PORT222_FN1),
979
980 /* Port213 - Port222 FN2 */
981 PINMUX_DATA(VIO_D9_MARK, PORT213_FN2),
982 PINMUX_DATA(VIO_D8_MARK, PORT214_FN2),
983 PINMUX_DATA(VIO_D7_MARK, PORT215_FN2),
984 PINMUX_DATA(VIO_D6_MARK, PORT216_FN2),
985 PINMUX_DATA(VIO_D5_MARK, PORT217_FN2),
986 PINMUX_DATA(VIO_D4_MARK, PORT218_FN2),
987 PINMUX_DATA(VIO_D3_MARK, PORT219_FN2),
988 PINMUX_DATA(VIO_D2_MARK, PORT220_FN2),
989 PINMUX_DATA(VIO_D1_MARK, PORT221_FN2),
990 PINMUX_DATA(VIO_D0_MARK, PORT222_FN2),
991
992 /* Port213 - Port222 FN5 */
993 PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5),
994 PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5),
995 PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5),
996 PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5),
997 PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5),
998 PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5),
999 PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5),
1000 PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5),
1001 PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5),
1002 PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5),
1003
1004 /* Port224 */
1005 PINMUX_DATA(RDWR_224_MARK, PORT224_FN1),
1006 PINMUX_DATA(VIO_HD_MARK, PORT224_FN2),
1007 PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5),
1008
1009 /* Port225 */
1010 PINMUX_DATA(RD_N_MARK, PORT225_FN1),
1011
1012 /* Port226 */
1013 PINMUX_DATA(WAIT_N_MARK, PORT226_FN1),
1014 PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2),
1015 PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5),
1016
1017 /* Port227 */
1018 PINMUX_DATA(WE0_N_MARK, PORT227_FN1),
1019 PINMUX_DATA(RDWR_227_MARK, PORT227_FN2),
1020
1021 /* Port228 */
1022 PINMUX_DATA(WE1_N_MARK, PORT228_FN1),
1023 PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5),
1024
1025 /* Port229 */
1026 PINMUX_DATA(PWMO_MARK, PORT229_FN1),
1027 PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2),
1028
1029 /* Port230 */
1030 PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1),
1031 PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2),
1032
1033 /* Port231 */
1034 PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1),
1035 PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2),
1036
1037 /* Port232 */
1038 PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2),
1039 PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4),
1040
1041 /* Port233 */
1042 PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2),
1043 PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4),
1044
1045 /* Port234 */
1046 PINMUX_DATA(FSIACK_MARK, PORT234_FN1),
1047 PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2),
1048 PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3),
1049
1050 /* Port235 */
1051 PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1),
1052 PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1),
1053
1054 /* Port236 */
1055 PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1),
1056 PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2),
1057 PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3),
1058
1059 /* Port237 */
1060 PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1),
1061 PINMUX_DATA(FSIAILR_MARK, PORT237_FN2),
1062
1063 /* Port238 */
1064 PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1),
1065 PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2),
1066
1067 /* Port239 */
1068 PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1),
1069 PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2),
1070
1071 /* Port240 */
1072 PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1),
1073
1074 /* Port241 */
1075 PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1),
1076 PINMUX_DATA(FSIBILR_MARK, PORT241_FN2),
1077
1078 /* Port242 */
1079 PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1),
1080 PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3),
1081
1082 /* Port243 */
1083 PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1),
1084 PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2),
1085
1086 /* Port244 */
1087 PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1),
1088 PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2),
1089
1090 /* Port245 */
1091 PINMUX_DATA(FSIBCK_MARK, PORT245_FN1),
1092 PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3),
1093
1094 /* Port246 - Port250 FN1 */
1095 PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1),
1096 PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1),
1097 PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1),
1098 PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1),
1099 PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1),
1100
1101 /* Port256 - Port258 */
1102 PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1),
1103 PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1),
1104 PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1),
1105
1106 /* Port259 */
1107 PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1),
1108 PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3),
1109
1110 /* Port260 */
1111 PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1),
1112
1113 /* Port261 */
1114 PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2),
1115 PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7),
1116
1117 /* Port262 */
1118 PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2),
1119
1120 /* Port263 - Port266 FN1 */
1121 PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1),
1122 PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1),
1123 PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1),
1124 PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1),
1125
1126 /* Port263 - Port266 FN4 */
1127 PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4),
1128 PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4),
1129 PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4),
1130 PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4),
1131
1132 /* Port267 */
1133 PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1),
1134
1135 /* Port268 */
1136 PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1),
1137 PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4),
1138
1139 /* Port269 */
1140 PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1),
1141 PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4),
1142
1143 /* Port270 - Port273 FN1 */
1144 PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1),
1145 PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1),
1146 PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1),
1147 PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1),
1148
1149 /* Port270 - Port273 FN3 */
1150 PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3),
1151 PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3),
1152 PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3),
1153 PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3),
1154
1155 /* Port274 */
1156 PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1),
1157 PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4),
1158
1159 /* Port275 - Port280 */
1160 PINMUX_DATA(IC_DP_MARK, PORT275_FN1),
1161 PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1),
1162 PINMUX_DATA(IC_DM_MARK, PORT277_FN1),
1163 PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1),
1164 PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1),
1165 PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1),
1166
1167 /* Port281 */
1168 PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1),
1169 PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1),
1170
1171 /* Port282 */
1172 PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1),
1173 PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2),
1174
1175 /* Port283 */
1176 PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1),
1177
1178 /* Port289 */
1179 PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1),
1180 PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3),
1181
1182 /* Port290 */
1183 PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1),
1184 PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3),
1185 PINMUX_DATA(IRQ51_MARK, PORT290_FN0),
1186
1187 /* Port291 - Port294 FN1 */
1188 PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1),
1189 PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1),
1190 PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1),
1191 PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1),
1192
1193 /* Port291 - Port294 FN3 */
1194 PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3),
1195 PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3),
1196 PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3),
1197 PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3),
1198
1199 /* Port295 */
1200 PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1),
1201 PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2),
1202 PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1),
1203 PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4),
1204
1205 /* Port296 */
1206 PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1),
1207 PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4),
1208 PINMUX_DATA(IRQ52_MARK, PORT296_FN0),
1209
1210 /* Port297 - Port300 FN1 */
1211 PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1),
1212 PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1),
1213 PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1),
1214 PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1),
1215
1216 /* Port297 - Port300 FN2 */
1217 PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2),
1218 PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2),
1219 PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2),
1220 PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2),
1221
1222 /* Port297 - Port300 FN3 */
1223 PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1),
1224 PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1),
1225 PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3),
1226 PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3),
1227
1228 /* Port297 - Port300 FN4 */
1229 PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4),
1230 PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4),
1231 PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4),
1232 PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4),
1233
1234 /* Port301 */
1235 PINMUX_DATA(SDHICD0_MARK, PORT301_FN1),
1236 PINMUX_DATA(IRQ50_MARK, PORT301_FN0),
1237
1238 /* Port302 - Port306 FN1 */
1239 PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1),
1240 PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1),
1241 PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1),
1242 PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1),
1243 PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1),
1244
1245 /* Port302 - Port306 FN3 */
1246 PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3),
1247 PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3),
1248 PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3),
1249 PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3),
1250 PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3),
1251
1252 /* Port307 */
1253 PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1),
1254
1255 /* Port308 */
1256 PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1),
1257 PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3),
1258
1259 /* Port320 - Port329 */
1260 PINMUX_DATA(IRQ16_MARK, PORT320_FN0),
1261 PINMUX_DATA(IRQ17_MARK, PORT321_FN0),
1262 PINMUX_DATA(IRQ28_MARK, PORT322_FN0),
1263 PINMUX_DATA(IRQ29_MARK, PORT323_FN0),
1264 PINMUX_DATA(IRQ30_MARK, PORT324_FN0),
1265 PINMUX_DATA(IRQ53_MARK, PORT325_FN0),
1266 PINMUX_DATA(IRQ54_MARK, PORT326_FN0),
1267 PINMUX_DATA(IRQ55_MARK, PORT327_FN0),
1268 PINMUX_DATA(IRQ56_MARK, PORT328_FN0),
1269 PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
1270};
1271
57ef73b4
MD		 1272#define R8A73A4_PIN(pin, cfgs) \
1273 { \
1274 .name = __stringify(PORT##pin), \
1275 .enum_id = PORT##pin##_DATA, \
1276 .configs = cfgs, \
1277 }
1278
1279#define __O (SH_PFC_PIN_CFG_OUTPUT)
1280#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1281#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1282
1283#define R8A73A4_PIN_IO_PU_PD(pin) R8A73A4_PIN(pin, __IO | __PUD)
1284#define R8A73A4_PIN_O(pin) R8A73A4_PIN(pin, __O)
1285
c98f6c21 1286static struct sh_pfc_pin pinmux_pins[] = {
57ef73b4
MD		 1287 R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1288 R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1289 R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
1290 R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
1291 R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
1292 R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
1293 R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
1294 R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
1295 R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
1296 R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
1297 R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
1298 R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
1299 R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
1300 R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
1301 R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
1302 R8A73A4_PIN_IO_PU_PD(30),
1303 R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
1304 R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
1305 R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
1306 R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
1307 R8A73A4_PIN_IO_PU_PD(40),
1308 R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
1309 R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
1310 R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
1311 R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
1312 R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
1313 R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
1314 R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
1315 R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
1316 R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
1317 R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
1318 R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
1319 R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
1320 R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
1321 R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
1322 R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
1323 R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
1324 R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
1325 R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
1326 R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
1327 R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
1328 R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
1329 R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
1330 R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
1331 R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
1332 R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
1333 R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
1334 R8A73A4_PIN_IO_PU_PD(126),
1335 R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
1336 R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
1337 R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
1338 R8A73A4_PIN_IO_PU_PD(134),
1339 R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
1340 R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
1341 R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
1342 R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
1343 R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
1344 R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
1345 R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
1346 R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
1347 R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
1348 R8A73A4_PIN_IO_PU_PD(178),
1349 R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
1350 R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
1351 R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
1352 R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
1353 R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
1354 R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
1355 R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
1356 R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
1357 R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
1358 R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
1359 R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
1360 R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
1361 R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
1362 R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
1363 R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
1364 R8A73A4_PIN_IO_PU_PD(222),
1365 R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
1366 R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
1367 R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
1368 R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
1369 R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
1370 R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
1371 R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
1372 R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
1373 R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
1374 R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
1375 R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
1376 R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
1377 R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
1378 R8A73A4_PIN_IO_PU_PD(250),
1379 R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
1380 R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
1381 R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
1382 R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
1383 R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
1384 R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
1385 R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
1386 R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
1387 R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
1388 R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
1389 R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
1390 R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
1391 R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
1392 R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
1393 R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
1394 R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
1395 R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
1396 R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
1397 R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
1398 R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
1399 R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
1400 R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
1401 R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
1402 R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
1403 R8A73A4_PIN_IO_PU_PD(308),
1404 R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
1405 R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
1406 R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
1407 R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
1408 R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
c98f6c21
MD		 1409};
1410
f365bfcc
MD		 1411static const struct pinmux_range pinmux_ranges[] = {
1412 {.begin = 0, .end = 30,},
1413 {.begin = 32, .end = 40,},
1414 {.begin = 64, .end = 85,},
1415 {.begin = 96, .end = 126,},
1416 {.begin = 128, .end = 134,},
1417 {.begin = 160, .end = 178,},
1418 {.begin = 192, .end = 222,},
1419 {.begin = 224, .end = 250,},
1420 {.begin = 256, .end = 283,},
1421 {.begin = 288, .end = 308,},
1422 {.begin = 320, .end = 329,},
1423};
1424
515a828f
MD		 1425/* - IRQC ------------------------------------------------------------------- */
1426#define IRQC_PINS_MUX(pin, irq_mark) \
1427static const unsigned int irqc_irq##irq_mark##_pins[] = { \
1428 pin, \
1429}; \
1430static const unsigned int irqc_irq##irq_mark##_mux[] = { \
1431 IRQ##irq_mark##_MARK, \
1432}
1433IRQC_PINS_MUX(0, 0);
1434IRQC_PINS_MUX(1, 1);
1435IRQC_PINS_MUX(2, 2);
1436IRQC_PINS_MUX(3, 3);
1437IRQC_PINS_MUX(4, 4);
1438IRQC_PINS_MUX(5, 5);
1439IRQC_PINS_MUX(6, 6);
1440IRQC_PINS_MUX(7, 7);
1441IRQC_PINS_MUX(8, 8);
1442IRQC_PINS_MUX(9, 9);
1443IRQC_PINS_MUX(10, 10);
1444IRQC_PINS_MUX(11, 11);
1445IRQC_PINS_MUX(12, 12);
1446IRQC_PINS_MUX(13, 13);
1447IRQC_PINS_MUX(14, 14);
1448IRQC_PINS_MUX(15, 15);
1449IRQC_PINS_MUX(66, 40);
1450IRQC_PINS_MUX(84, 19);
1451IRQC_PINS_MUX(85, 18);
1452IRQC_PINS_MUX(102, 41);
1453IRQC_PINS_MUX(103, 42);
1454IRQC_PINS_MUX(109, 43);
1455IRQC_PINS_MUX(110, 44);
1456IRQC_PINS_MUX(111, 45);
1457IRQC_PINS_MUX(112, 46);
1458IRQC_PINS_MUX(113, 47);
1459IRQC_PINS_MUX(114, 48);
1460IRQC_PINS_MUX(115, 49);
1461IRQC_PINS_MUX(160, 20);
1462IRQC_PINS_MUX(161, 21);
1463IRQC_PINS_MUX(162, 22);
1464IRQC_PINS_MUX(163, 23);
1465IRQC_PINS_MUX(175, 24);
1466IRQC_PINS_MUX(176, 25);
1467IRQC_PINS_MUX(177, 26);
1468IRQC_PINS_MUX(178, 27);
1469IRQC_PINS_MUX(192, 31);
1470IRQC_PINS_MUX(193, 32);
1471IRQC_PINS_MUX(194, 33);
1472IRQC_PINS_MUX(195, 34);
1473IRQC_PINS_MUX(196, 35);
1474IRQC_PINS_MUX(197, 36);
1475IRQC_PINS_MUX(198, 37);
1476IRQC_PINS_MUX(199, 38);
1477IRQC_PINS_MUX(200, 39);
1478IRQC_PINS_MUX(290, 51);
1479IRQC_PINS_MUX(296, 52);
1480IRQC_PINS_MUX(301, 50);
1481IRQC_PINS_MUX(320, 16);
1482IRQC_PINS_MUX(321, 17);
1483IRQC_PINS_MUX(322, 28);
1484IRQC_PINS_MUX(323, 29);
1485IRQC_PINS_MUX(324, 30);
1486IRQC_PINS_MUX(325, 53);
1487IRQC_PINS_MUX(326, 54);
1488IRQC_PINS_MUX(327, 55);
1489IRQC_PINS_MUX(328, 56);
1490IRQC_PINS_MUX(329, 57);
172fd616
MD		 1491/* - SCIFA0 ----------------------------------------------------------------- */
1492static const unsigned int scifa0_data_pins[] = {
1493 /* SCIFA0_RXD, SCIFA0_TXD */
1494 117, 116,
1495};
1496static const unsigned int scifa0_data_mux[] = {
1497 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1498};
1499static const unsigned int scifa0_clk_pins[] = {
1500 /* SCIFA0_SCK */
1501 34,
1502};
1503static const unsigned int scifa0_clk_mux[] = {
1504 SCIFA0_SCK_MARK,
1505};
1506static const unsigned int scifa0_ctrl_pins[] = {
1507 /* SCIFA0_RTS, SCIFA0_CTS */
1508 32, 33,
1509};
1510static const unsigned int scifa0_ctrl_mux[] = {
1511 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1512};
1513/* - SCIFA1 ----------------------------------------------------------------- */
1514static const unsigned int scifa1_data_pins[] = {
1515 /* SCIFA1_RXD, SCIFA1_TXD */
1516 119, 118,
1517};
1518static const unsigned int scifa1_data_mux[] = {
1519 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1520};
1521static const unsigned int scifa1_clk_pins[] = {
1522 /* SCIFA1_SCK */
1523 37,
1524};
1525static const unsigned int scifa1_clk_mux[] = {
1526 SCIFA1_SCK_MARK,
1527};
1528static const unsigned int scifa1_ctrl_pins[] = {
1529 /* SCIFA1_RTS, SCIFA1_CTS */
1530 35, 36,
1531};
1532static const unsigned int scifa1_ctrl_mux[] = {
1533 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1534};
1535/* - SCIFB0 ----------------------------------------------------------------- */
1536static const unsigned int scifb0_data_pins[] = {
1537 /* SCIFB0_RXD, SCIFB0_TXD */
1538 123, 122,
1539};
1540static const unsigned int scifb0_data_mux[] = {
1541 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
1542};
1543static const unsigned int scifb0_clk_pins[] = {
1544 /* SCIFB0_SCK */
1545 40,
1546};
1547static const unsigned int scifb0_clk_mux[] = {
1548 SCIFB0_SCK_MARK,
1549};
1550static const unsigned int scifb0_ctrl_pins[] = {
1551 /* SCIFB0_RTS, SCIFB0_CTS */
1552 38, 39,
1553};
1554static const unsigned int scifb0_ctrl_mux[] = {
1555 SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
1556};
1557/* - SCIFB1 ----------------------------------------------------------------- */
1558static const unsigned int scifb1_data_pins[] = {
1559 /* SCIFB1_RXD, SCIFB1_TXD */
1560 27, 26,
1561};
1562static const unsigned int scifb1_data_mux[] = {
1563 SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
1564};
1565static const unsigned int scifb1_clk_pins[] = {
1566 /* SCIFB1_SCK */
1567 28,
1568};
1569static const unsigned int scifb1_clk_mux[] = {
1570 SCIFB1_SCK_28_MARK,
1571};
1572static const unsigned int scifb1_ctrl_pins[] = {
1573 /* SCIFB1_RTS, SCIFB1_CTS */
1574 24, 25,
1575};
1576static const unsigned int scifb1_ctrl_mux[] = {
1577 SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
1578};
1579static const unsigned int scifb1_data_b_pins[] = {
1580 /* SCIFB1_RXD, SCIFB1_TXD */
1581 72, 67,
1582};
1583static const unsigned int scifb1_data_b_mux[] = {
1584 SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
1585};
1586static const unsigned int scifb1_clk_b_pins[] = {
1587 /* SCIFB1_SCK */
1588 261,
1589};
1590static const unsigned int scifb1_clk_b_mux[] = {
1591 SCIFB1_SCK_261_MARK,
1592};
1593static const unsigned int scifb1_ctrl_b_pins[] = {
1594 /* SCIFB1_RTS, SCIFB1_CTS */
1595 70, 71,
1596};
1597static const unsigned int scifb1_ctrl_b_mux[] = {
1598 SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
1599};
1600/* - SCIFB2 ----------------------------------------------------------------- */
1601static const unsigned int scifb2_data_pins[] = {
1602 /* SCIFB2_RXD, SCIFB2_TXD */
1603 69, 68,
1604};
1605static const unsigned int scifb2_data_mux[] = {
1606 SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
1607};
1608static const unsigned int scifb2_clk_pins[] = {
1609 /* SCIFB2_SCK */
1610 262,
1611};
1612static const unsigned int scifb2_clk_mux[] = {
1613 SCIFB2_SCK_262_MARK,
1614};
1615static const unsigned int scifb2_ctrl_pins[] = {
1616 /* SCIFB2_RTS, SCIFB2_CTS */
1617 73, 66,
1618};
1619static const unsigned int scifb2_ctrl_mux[] = {
1620 SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
1621};
1622static const unsigned int scifb2_data_b_pins[] = {
1623 /* SCIFB2_RXD, SCIFB2_TXD */
1624 297, 295,
1625};
1626static const unsigned int scifb2_data_b_mux[] = {
1627 SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
1628};
1629static const unsigned int scifb2_clk_b_pins[] = {
1630 /* SCIFB2_SCK */
1631 299,
1632};
1633static const unsigned int scifb2_clk_b_mux[] = {
1634 SCIFB2_SCK_299_MARK,
1635};
1636static const unsigned int scifb2_ctrl_b_pins[] = {
1637 /* SCIFB2_RTS, SCIFB2_CTS */
1638 300, 298,
1639};
1640static const unsigned int scifb2_ctrl_b_mux[] = {
1641 SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
1642};
1643/* - SCIFB3 ----------------------------------------------------------------- */
1644static const unsigned int scifb3_data_pins[] = {
1645 /* SCIFB3_RXD, SCIFB3_TXD */
1646 22, 21,
1647};
1648static const unsigned int scifb3_data_mux[] = {
1649 SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
1650};
1651static const unsigned int scifb3_clk_pins[] = {
1652 /* SCIFB3_SCK */
1653 23,
1654};
1655static const unsigned int scifb3_clk_mux[] = {
1656 SCIFB3_SCK_23_MARK,
1657};
1658static const unsigned int scifb3_ctrl_pins[] = {
1659 /* SCIFB3_RTS, SCIFB3_CTS */
1660 19, 20,
1661};
1662static const unsigned int scifb3_ctrl_mux[] = {
1663 SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
1664};
1665static const unsigned int scifb3_data_b_pins[] = {
1666 /* SCIFB3_RXD, SCIFB3_TXD */
1667 120, 121,
1668};
1669static const unsigned int scifb3_data_b_mux[] = {
1670 SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
1671};
1672static const unsigned int scifb3_clk_b_pins[] = {
1673 /* SCIFB3_SCK */
1674 40,
1675};
1676static const unsigned int scifb3_clk_b_mux[] = {
1677 SCIFB3_SCK_40_MARK,
1678};
1679static const unsigned int scifb3_ctrl_b_pins[] = {
1680 /* SCIFB3_RTS, SCIFB3_CTS */
1681 38, 39,
1682};
1683static const unsigned int scifb3_ctrl_b_mux[] = {
1684 SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1685};
1686
1687static const struct sh_pfc_pin_group pinmux_groups[] = {
515a828f
MD		 1688 SH_PFC_PIN_GROUP(irqc_irq0),
1689 SH_PFC_PIN_GROUP(irqc_irq1),
1690 SH_PFC_PIN_GROUP(irqc_irq2),
1691 SH_PFC_PIN_GROUP(irqc_irq3),
1692 SH_PFC_PIN_GROUP(irqc_irq4),
1693 SH_PFC_PIN_GROUP(irqc_irq5),
1694 SH_PFC_PIN_GROUP(irqc_irq6),
1695 SH_PFC_PIN_GROUP(irqc_irq7),
1696 SH_PFC_PIN_GROUP(irqc_irq8),
1697 SH_PFC_PIN_GROUP(irqc_irq9),
1698 SH_PFC_PIN_GROUP(irqc_irq10),
1699 SH_PFC_PIN_GROUP(irqc_irq11),
1700 SH_PFC_PIN_GROUP(irqc_irq12),
1701 SH_PFC_PIN_GROUP(irqc_irq13),
1702 SH_PFC_PIN_GROUP(irqc_irq14),
1703 SH_PFC_PIN_GROUP(irqc_irq15),
1704 SH_PFC_PIN_GROUP(irqc_irq16),
1705 SH_PFC_PIN_GROUP(irqc_irq17),
1706 SH_PFC_PIN_GROUP(irqc_irq18),
1707 SH_PFC_PIN_GROUP(irqc_irq19),
1708 SH_PFC_PIN_GROUP(irqc_irq20),
1709 SH_PFC_PIN_GROUP(irqc_irq21),
1710 SH_PFC_PIN_GROUP(irqc_irq22),
1711 SH_PFC_PIN_GROUP(irqc_irq23),
1712 SH_PFC_PIN_GROUP(irqc_irq24),
1713 SH_PFC_PIN_GROUP(irqc_irq25),
1714 SH_PFC_PIN_GROUP(irqc_irq26),
1715 SH_PFC_PIN_GROUP(irqc_irq27),
1716 SH_PFC_PIN_GROUP(irqc_irq28),
1717 SH_PFC_PIN_GROUP(irqc_irq29),
1718 SH_PFC_PIN_GROUP(irqc_irq30),
1719 SH_PFC_PIN_GROUP(irqc_irq31),
1720 SH_PFC_PIN_GROUP(irqc_irq32),
1721 SH_PFC_PIN_GROUP(irqc_irq33),
1722 SH_PFC_PIN_GROUP(irqc_irq34),
1723 SH_PFC_PIN_GROUP(irqc_irq35),
1724 SH_PFC_PIN_GROUP(irqc_irq36),
1725 SH_PFC_PIN_GROUP(irqc_irq37),
1726 SH_PFC_PIN_GROUP(irqc_irq38),
1727 SH_PFC_PIN_GROUP(irqc_irq39),
1728 SH_PFC_PIN_GROUP(irqc_irq40),
1729 SH_PFC_PIN_GROUP(irqc_irq41),
1730 SH_PFC_PIN_GROUP(irqc_irq42),
1731 SH_PFC_PIN_GROUP(irqc_irq43),
1732 SH_PFC_PIN_GROUP(irqc_irq44),
1733 SH_PFC_PIN_GROUP(irqc_irq45),
1734 SH_PFC_PIN_GROUP(irqc_irq46),
1735 SH_PFC_PIN_GROUP(irqc_irq47),
1736 SH_PFC_PIN_GROUP(irqc_irq48),
1737 SH_PFC_PIN_GROUP(irqc_irq49),
1738 SH_PFC_PIN_GROUP(irqc_irq50),
1739 SH_PFC_PIN_GROUP(irqc_irq51),
1740 SH_PFC_PIN_GROUP(irqc_irq52),
1741 SH_PFC_PIN_GROUP(irqc_irq53),
1742 SH_PFC_PIN_GROUP(irqc_irq54),
1743 SH_PFC_PIN_GROUP(irqc_irq55),
1744 SH_PFC_PIN_GROUP(irqc_irq56),
1745 SH_PFC_PIN_GROUP(irqc_irq57),
172fd616
MD		 1746 SH_PFC_PIN_GROUP(scifa0_data),
1747 SH_PFC_PIN_GROUP(scifa0_clk),
1748 SH_PFC_PIN_GROUP(scifa0_ctrl),
1749 SH_PFC_PIN_GROUP(scifa1_data),
1750 SH_PFC_PIN_GROUP(scifa1_clk),
1751 SH_PFC_PIN_GROUP(scifa1_ctrl),
1752 SH_PFC_PIN_GROUP(scifb0_data),
1753 SH_PFC_PIN_GROUP(scifb0_clk),
1754 SH_PFC_PIN_GROUP(scifb0_ctrl),
1755 SH_PFC_PIN_GROUP(scifb1_data),
1756 SH_PFC_PIN_GROUP(scifb1_clk),
1757 SH_PFC_PIN_GROUP(scifb1_ctrl),
1758 SH_PFC_PIN_GROUP(scifb1_data_b),
1759 SH_PFC_PIN_GROUP(scifb1_clk_b),
1760 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
1761 SH_PFC_PIN_GROUP(scifb2_data),
1762 SH_PFC_PIN_GROUP(scifb2_clk),
1763 SH_PFC_PIN_GROUP(scifb2_ctrl),
1764 SH_PFC_PIN_GROUP(scifb2_data_b),
1765 SH_PFC_PIN_GROUP(scifb2_clk_b),
1766 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
1767 SH_PFC_PIN_GROUP(scifb3_data),
1768 SH_PFC_PIN_GROUP(scifb3_clk),
1769 SH_PFC_PIN_GROUP(scifb3_ctrl),
1770 SH_PFC_PIN_GROUP(scifb3_data_b),
1771 SH_PFC_PIN_GROUP(scifb3_clk_b),
1772 SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1773};
1774
515a828f
MD		 1775static const char * const irqc_groups[] = {
1776 "irqc_irq0",
1777 "irqc_irq1",
1778 "irqc_irq2",
1779 "irqc_irq3",
1780 "irqc_irq4",
1781 "irqc_irq5",
1782 "irqc_irq6",
1783 "irqc_irq7",
1784 "irqc_irq8",
1785 "irqc_irq9",
1786 "irqc_irq10",
1787 "irqc_irq11",
1788 "irqc_irq12",
1789 "irqc_irq13",
1790 "irqc_irq14",
1791 "irqc_irq15",
1792 "irqc_irq16",
1793 "irqc_irq17",
1794 "irqc_irq18",
1795 "irqc_irq19",
1796 "irqc_irq20",
1797 "irqc_irq21",
1798 "irqc_irq22",
1799 "irqc_irq23",
1800 "irqc_irq24",
1801 "irqc_irq25",
1802 "irqc_irq26",
1803 "irqc_irq27",
1804 "irqc_irq28",
1805 "irqc_irq29",
1806 "irqc_irq30",
1807 "irqc_irq31",
1808 "irqc_irq32",
1809 "irqc_irq33",
1810 "irqc_irq34",
1811 "irqc_irq35",
1812 "irqc_irq36",
1813 "irqc_irq37",
1814 "irqc_irq38",
1815 "irqc_irq39",
1816 "irqc_irq40",
1817 "irqc_irq41",
1818 "irqc_irq42",
1819 "irqc_irq43",
1820 "irqc_irq44",
1821 "irqc_irq45",
1822 "irqc_irq46",
1823 "irqc_irq47",
1824 "irqc_irq48",
1825 "irqc_irq49",
1826 "irqc_irq50",
1827 "irqc_irq51",
1828 "irqc_irq52",
1829 "irqc_irq53",
1830 "irqc_irq54",
1831 "irqc_irq55",
1832 "irqc_irq56",
1833 "irqc_irq57",
1834};
1835
172fd616
MD		 1836static const char * const scifa0_groups[] = {
1837 "scifa0_data",
1838 "scifa0_clk",
1839 "scifa0_ctrl",
1840};
1841
1842static const char * const scifa1_groups[] = {
1843 "scifa1_data",
1844 "scifa1_clk",
1845 "scifa1_ctrl",
1846};
1847
1848static const char * const scifb0_groups[] = {
1849 "scifb0_data",
1850 "scifb0_clk",
1851 "scifb0_ctrl",
1852};
1853
1854static const char * const scifb1_groups[] = {
1855 "scifb1_data",
1856 "scifb1_clk",
1857 "scifb1_ctrl",
1858 "scifb1_data_b",
1859 "scifb1_clk_b",
1860 "scifb1_ctrl_b",
1861};
1862
1863static const char * const scifb2_groups[] = {
1864 "scifb2_data",
1865 "scifb2_clk",
1866 "scifb2_ctrl",
1867 "scifb2_data_b",
1868 "scifb2_clk_b",
1869 "scifb2_ctrl_b",
1870};
1871
1872static const char * const scifb3_groups[] = {
1873 "scifb3_data",
1874 "scifb3_clk",
1875 "scifb3_ctrl",
1876 "scifb3_data_b",
1877 "scifb3_clk_b",
1878 "scifb3_ctrl_b",
1879};
1880
1881static const struct sh_pfc_function pinmux_functions[] = {
515a828f 1882 SH_PFC_FUNCTION(irqc),
172fd616
MD		 1883 SH_PFC_FUNCTION(scifa0),
1884 SH_PFC_FUNCTION(scifa1),
1885 SH_PFC_FUNCTION(scifb0),
1886 SH_PFC_FUNCTION(scifb1),
1887 SH_PFC_FUNCTION(scifb2),
1888 SH_PFC_FUNCTION(scifb3),
1889};
1890
202ac6a2
MD		 1891#undef PORTCR
1892#define PORTCR(nr, reg) \
1893 { \
1894 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
1895 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
1896 PORT##nr##_FN0, PORT##nr##_FN1, \
1897 PORT##nr##_FN2, PORT##nr##_FN3, \
1898 PORT##nr##_FN4, PORT##nr##_FN5, \
1899 PORT##nr##_FN6, PORT##nr##_FN7 } \
1900 }
c98f6c21 1901
202ac6a2 1902static const struct pinmux_cfg_reg pinmux_config_regs[] = {
c98f6c21
MD		 1903 PORTCR(0, 0xe6050000),
1904 PORTCR(1, 0xe6050001),
1905 PORTCR(2, 0xe6050002),
1906 PORTCR(3, 0xe6050003),
1907 PORTCR(4, 0xe6050004),
1908 PORTCR(5, 0xe6050005),
1909 PORTCR(6, 0xe6050006),
1910 PORTCR(7, 0xe6050007),
1911 PORTCR(8, 0xe6050008),
1912 PORTCR(9, 0xe6050009),
1913 PORTCR(10, 0xe605000A),
1914 PORTCR(11, 0xe605000B),
1915 PORTCR(12, 0xe605000C),
1916 PORTCR(13, 0xe605000D),
1917 PORTCR(14, 0xe605000E),
1918 PORTCR(15, 0xe605000F),
1919 PORTCR(16, 0xe6050010),
1920 PORTCR(17, 0xe6050011),
1921 PORTCR(18, 0xe6050012),
1922 PORTCR(19, 0xe6050013),
1923 PORTCR(20, 0xe6050014),
1924 PORTCR(21, 0xe6050015),
1925 PORTCR(22, 0xe6050016),
1926 PORTCR(23, 0xe6050017),
1927 PORTCR(24, 0xe6050018),
1928 PORTCR(25, 0xe6050019),
1929 PORTCR(26, 0xe605001A),
1930 PORTCR(27, 0xe605001B),
1931 PORTCR(28, 0xe605001C),
1932 PORTCR(29, 0xe605001D),
1933 PORTCR(30, 0xe605001E),
1934 PORTCR(32, 0xe6051020),
1935 PORTCR(33, 0xe6051021),
1936 PORTCR(34, 0xe6051022),
1937 PORTCR(35, 0xe6051023),
1938 PORTCR(36, 0xe6051024),
1939 PORTCR(37, 0xe6051025),
1940 PORTCR(38, 0xe6051026),
1941 PORTCR(39, 0xe6051027),
1942 PORTCR(40, 0xe6051028),
1943 PORTCR(64, 0xe6050040),
1944 PORTCR(65, 0xe6050041),
1945 PORTCR(66, 0xe6050042),
1946 PORTCR(67, 0xe6050043),
1947 PORTCR(68, 0xe6050044),
1948 PORTCR(69, 0xe6050045),
1949 PORTCR(70, 0xe6050046),
1950 PORTCR(71, 0xe6050047),
1951 PORTCR(72, 0xe6050048),
1952 PORTCR(73, 0xe6050049),
1953 PORTCR(74, 0xe605004A),
1954 PORTCR(75, 0xe605004B),
1955 PORTCR(76, 0xe605004C),
1956 PORTCR(77, 0xe605004D),
1957 PORTCR(78, 0xe605004E),
1958 PORTCR(79, 0xe605004F),
1959 PORTCR(80, 0xe6050050),
1960 PORTCR(81, 0xe6050051),
1961 PORTCR(82, 0xe6050052),
1962 PORTCR(83, 0xe6050053),
1963 PORTCR(84, 0xe6050054),
1964 PORTCR(85, 0xe6050055),
1965 PORTCR(96, 0xe6051060),
1966 PORTCR(97, 0xe6051061),
1967 PORTCR(98, 0xe6051062),
1968 PORTCR(99, 0xe6051063),
1969 PORTCR(100, 0xe6051064),
1970 PORTCR(101, 0xe6051065),
1971 PORTCR(102, 0xe6051066),
1972 PORTCR(103, 0xe6051067),
1973 PORTCR(104, 0xe6051068),
1974 PORTCR(105, 0xe6051069),
1975 PORTCR(106, 0xe605106A),
1976 PORTCR(107, 0xe605106B),
1977 PORTCR(108, 0xe605106C),
1978 PORTCR(109, 0xe605106D),
1979 PORTCR(110, 0xe605106E),
1980 PORTCR(111, 0xe605106F),
1981 PORTCR(112, 0xe6051070),
1982 PORTCR(113, 0xe6051071),
1983 PORTCR(114, 0xe6051072),
1984 PORTCR(115, 0xe6051073),
1985 PORTCR(116, 0xe6051074),
1986 PORTCR(117, 0xe6051075),
1987 PORTCR(118, 0xe6051076),
1988 PORTCR(119, 0xe6051077),
1989 PORTCR(120, 0xe6051078),
1990 PORTCR(121, 0xe6051079),
1991 PORTCR(122, 0xe605107A),
1992 PORTCR(123, 0xe605107B),
1993 PORTCR(124, 0xe605107C),
1994 PORTCR(125, 0xe605107D),
1995 PORTCR(126, 0xe605107E),
1996 PORTCR(128, 0xe6051080),
1997 PORTCR(129, 0xe6051081),
1998 PORTCR(130, 0xe6051082),
1999 PORTCR(131, 0xe6051083),
2000 PORTCR(132, 0xe6051084),
2001 PORTCR(133, 0xe6051085),
2002 PORTCR(134, 0xe6051086),
2003 PORTCR(160, 0xe60520A0),
2004 PORTCR(161, 0xe60520A1),
2005 PORTCR(162, 0xe60520A2),
2006 PORTCR(163, 0xe60520A3),
2007 PORTCR(164, 0xe60520A4),
2008 PORTCR(165, 0xe60520A5),
2009 PORTCR(166, 0xe60520A6),
2010 PORTCR(167, 0xe60520A7),
2011 PORTCR(168, 0xe60520A8),
2012 PORTCR(169, 0xe60520A9),
2013 PORTCR(170, 0xe60520AA),
2014 PORTCR(171, 0xe60520AB),
2015 PORTCR(172, 0xe60520AC),
2016 PORTCR(173, 0xe60520AD),
2017 PORTCR(174, 0xe60520AE),
2018 PORTCR(175, 0xe60520AF),
2019 PORTCR(176, 0xe60520B0),
2020 PORTCR(177, 0xe60520B1),
2021 PORTCR(178, 0xe60520B2),
2022 PORTCR(192, 0xe60520C0),
2023 PORTCR(193, 0xe60520C1),
2024 PORTCR(194, 0xe60520C2),
2025 PORTCR(195, 0xe60520C3),
2026 PORTCR(196, 0xe60520C4),
2027 PORTCR(197, 0xe60520C5),
2028 PORTCR(198, 0xe60520C6),
2029 PORTCR(199, 0xe60520C7),
2030 PORTCR(200, 0xe60520C8),
2031 PORTCR(201, 0xe60520C9),
2032 PORTCR(202, 0xe60520CA),
2033 PORTCR(203, 0xe60520CB),
2034 PORTCR(204, 0xe60520CC),
2035 PORTCR(205, 0xe60520CD),
2036 PORTCR(206, 0xe60520CE),
2037 PORTCR(207, 0xe60520CF),
2038 PORTCR(208, 0xe60520D0),
2039 PORTCR(209, 0xe60520D1),
2040 PORTCR(210, 0xe60520D2),
2041 PORTCR(211, 0xe60520D3),
2042 PORTCR(212, 0xe60520D4),
2043 PORTCR(213, 0xe60520D5),
2044 PORTCR(214, 0xe60520D6),
2045 PORTCR(215, 0xe60520D7),
2046 PORTCR(216, 0xe60520D8),
2047 PORTCR(217, 0xe60520D9),
2048 PORTCR(218, 0xe60520DA),
2049 PORTCR(219, 0xe60520DB),
2050 PORTCR(220, 0xe60520DC),
2051 PORTCR(221, 0xe60520DD),
2052 PORTCR(222, 0xe60520DE),
2053 PORTCR(224, 0xe60520E0),
2054 PORTCR(225, 0xe60520E1),
2055 PORTCR(226, 0xe60520E2),
2056 PORTCR(227, 0xe60520E3),
2057 PORTCR(228, 0xe60520E4),
2058 PORTCR(229, 0xe60520E5),
2059 PORTCR(230, 0xe60520e6),
2060 PORTCR(231, 0xe60520E7),
2061 PORTCR(232, 0xe60520E8),
2062 PORTCR(233, 0xe60520E9),
2063 PORTCR(234, 0xe60520EA),
2064 PORTCR(235, 0xe60520EB),
2065 PORTCR(236, 0xe60520EC),
2066 PORTCR(237, 0xe60520ED),
2067 PORTCR(238, 0xe60520EE),
2068 PORTCR(239, 0xe60520EF),
2069 PORTCR(240, 0xe60520F0),
2070 PORTCR(241, 0xe60520F1),
2071 PORTCR(242, 0xe60520F2),
2072 PORTCR(243, 0xe60520F3),
2073 PORTCR(244, 0xe60520F4),
2074 PORTCR(245, 0xe60520F5),
2075 PORTCR(246, 0xe60520F6),
2076 PORTCR(247, 0xe60520F7),
2077 PORTCR(248, 0xe60520F8),
2078 PORTCR(249, 0xe60520F9),
2079 PORTCR(250, 0xe60520FA),
2080 PORTCR(256, 0xe6052100),
2081 PORTCR(257, 0xe6052101),
2082 PORTCR(258, 0xe6052102),
2083 PORTCR(259, 0xe6052103),
2084 PORTCR(260, 0xe6052104),
2085 PORTCR(261, 0xe6052105),
2086 PORTCR(262, 0xe6052106),
2087 PORTCR(263, 0xe6052107),
2088 PORTCR(264, 0xe6052108),
2089 PORTCR(265, 0xe6052109),
2090 PORTCR(266, 0xe605210A),
2091 PORTCR(267, 0xe605210B),
2092 PORTCR(268, 0xe605210C),
2093 PORTCR(269, 0xe605210D),
2094 PORTCR(270, 0xe605210E),
2095 PORTCR(271, 0xe605210F),
2096 PORTCR(272, 0xe6052110),
2097 PORTCR(273, 0xe6052111),
2098 PORTCR(274, 0xe6052112),
2099 PORTCR(275, 0xe6052113),
2100 PORTCR(276, 0xe6052114),
2101 PORTCR(277, 0xe6052115),
2102 PORTCR(278, 0xe6052116),
2103 PORTCR(279, 0xe6052117),
2104 PORTCR(280, 0xe6052118),
2105 PORTCR(281, 0xe6052119),
2106 PORTCR(282, 0xe605211A),
2107 PORTCR(283, 0xe605211B),
2108 PORTCR(288, 0xe6053120),
2109 PORTCR(289, 0xe6053121),
2110 PORTCR(290, 0xe6053122),
2111 PORTCR(291, 0xe6053123),
2112 PORTCR(292, 0xe6053124),
2113 PORTCR(293, 0xe6053125),
2114 PORTCR(294, 0xe6053126),
2115 PORTCR(295, 0xe6053127),
2116 PORTCR(296, 0xe6053128),
2117 PORTCR(297, 0xe6053129),
2118 PORTCR(298, 0xe605312A),
2119 PORTCR(299, 0xe605312B),
2120 PORTCR(300, 0xe605312C),
2121 PORTCR(301, 0xe605312D),
2122 PORTCR(302, 0xe605312E),
2123 PORTCR(303, 0xe605312F),
2124 PORTCR(304, 0xe6053130),
2125 PORTCR(305, 0xe6053131),
2126 PORTCR(306, 0xe6053132),
2127 PORTCR(307, 0xe6053133),
2128 PORTCR(308, 0xe6053134),
2129 PORTCR(320, 0xe6053140),
2130 PORTCR(321, 0xe6053141),
2131 PORTCR(322, 0xe6053142),
2132 PORTCR(323, 0xe6053143),
2133 PORTCR(324, 0xe6053144),
2134 PORTCR(325, 0xe6053145),
2135 PORTCR(326, 0xe6053146),
2136 PORTCR(327, 0xe6053147),
2137 PORTCR(328, 0xe6053148),
2138 PORTCR(329, 0xe6053149),
2139
2140 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2141 MSEL1CR_31_0, MSEL1CR_31_1,
2142 0, 0,
2143 0, 0,
2144 0, 0,
2145 MSEL1CR_27_0, MSEL1CR_27_1,
2146 0, 0,
2147 MSEL1CR_25_0, MSEL1CR_25_1,
2148 MSEL1CR_24_0, MSEL1CR_24_1,
2149 0, 0,
2150 MSEL1CR_22_0, MSEL1CR_22_1,
2151 MSEL1CR_21_0, MSEL1CR_21_1,
2152 MSEL1CR_20_0, MSEL1CR_20_1,
2153 MSEL1CR_19_0, MSEL1CR_19_1,
2154 MSEL1CR_18_0, MSEL1CR_18_1,
2155 MSEL1CR_17_0, MSEL1CR_17_1,
2156 MSEL1CR_16_0, MSEL1CR_16_1,
2157 MSEL1CR_15_0, MSEL1CR_15_1,
2158 MSEL1CR_14_0, MSEL1CR_14_1,
2159 MSEL1CR_13_0, MSEL1CR_13_1,
2160 MSEL1CR_12_0, MSEL1CR_12_1,
2161 MSEL1CR_11_0, MSEL1CR_11_1,
2162 MSEL1CR_10_0, MSEL1CR_10_1,
2163 MSEL1CR_09_0, MSEL1CR_09_1,
2164 MSEL1CR_08_0, MSEL1CR_08_1,
2165 MSEL1CR_07_0, MSEL1CR_07_1,
2166 MSEL1CR_06_0, MSEL1CR_06_1,
2167 MSEL1CR_05_0, MSEL1CR_05_1,
2168 MSEL1CR_04_0, MSEL1CR_04_1,
2169 MSEL1CR_03_0, MSEL1CR_03_1,
2170 MSEL1CR_02_0, MSEL1CR_02_1,
2171 MSEL1CR_01_0, MSEL1CR_01_1,
2172 MSEL1CR_00_0, MSEL1CR_00_1,
2173 }
2174 },
2175 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
2176 MSEL3CR_31_0, MSEL3CR_31_1,
2177 0, 0,
2178 0, 0,
2179 MSEL3CR_28_0, MSEL3CR_28_1,
2180 MSEL3CR_27_0, MSEL3CR_27_1,
2181 MSEL3CR_26_0, MSEL3CR_26_1,
2182 0, 0,
2183 0, 0,
2184 MSEL3CR_23_0, MSEL3CR_23_1,
2185 MSEL3CR_22_0, MSEL3CR_22_1,
2186 MSEL3CR_21_0, MSEL3CR_21_1,
2187 MSEL3CR_20_0, MSEL3CR_20_1,
2188 MSEL3CR_19_0, MSEL3CR_19_1,
2189 MSEL3CR_18_0, MSEL3CR_18_1,
2190 MSEL3CR_17_0, MSEL3CR_17_1,
2191 MSEL3CR_16_0, MSEL3CR_16_1,
2192 MSEL3CR_15_0, MSEL3CR_15_1,
2193 0, 0,
2194 0, 0,
2195 MSEL3CR_12_0, MSEL3CR_12_1,
2196 MSEL3CR_11_0, MSEL3CR_11_1,
2197 MSEL3CR_10_0, MSEL3CR_10_1,
2198 MSEL3CR_09_0, MSEL3CR_09_1,
2199 0, 0,
2200 0, 0,
2201 MSEL3CR_06_0, MSEL3CR_06_1,
2202 0, 0,
2203 0, 0,
2204 MSEL3CR_03_0, MSEL3CR_03_1,
2205 0, 0,
2206 MSEL3CR_01_0, MSEL3CR_01_1,
2207 MSEL3CR_00_0, MSEL3CR_00_1,
2208 }
2209 },
2210 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
2211 0, 0,
2212 MSEL4CR_30_0, MSEL4CR_30_1,
2213 MSEL4CR_29_0, MSEL4CR_29_1,
2214 MSEL4CR_28_0, MSEL4CR_28_1,
2215 MSEL4CR_27_0, MSEL4CR_27_1,
2216 MSEL4CR_26_0, MSEL4CR_26_1,
2217 MSEL4CR_25_0, MSEL4CR_25_1,
2218 MSEL4CR_24_0, MSEL4CR_24_1,
2219 MSEL4CR_23_0, MSEL4CR_23_1,
2220 MSEL4CR_22_0, MSEL4CR_22_1,
2221 MSEL4CR_21_0, MSEL4CR_21_1,
2222 MSEL4CR_20_0, MSEL4CR_20_1,
2223 MSEL4CR_19_0, MSEL4CR_19_1,
2224 MSEL4CR_18_0, MSEL4CR_18_1,
2225 MSEL4CR_17_0, MSEL4CR_17_1,
2226 MSEL4CR_16_0, MSEL4CR_16_1,
2227 MSEL4CR_15_0, MSEL4CR_15_1,
2228 MSEL4CR_14_0, MSEL4CR_14_1,
2229 MSEL4CR_13_0, MSEL4CR_13_1,
2230 MSEL4CR_12_0, MSEL4CR_12_1,
2231 MSEL4CR_11_0, MSEL4CR_11_1,
2232 MSEL4CR_10_0, MSEL4CR_10_1,
2233 MSEL4CR_09_0, MSEL4CR_09_1,
2234 0, 0,
2235 MSEL4CR_07_0, MSEL4CR_07_1,
2236 0, 0,
2237 0, 0,
2238 MSEL4CR_04_0, MSEL4CR_04_1,
2239 0, 0,
2240 0, 0,
2241 MSEL4CR_01_0, MSEL4CR_01_1,
2242 0, 0,
2243 }
2244 },
2245 { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
2246 MSEL5CR_31_0, MSEL5CR_31_1,
2247 MSEL5CR_30_0, MSEL5CR_30_1,
2248 MSEL5CR_29_0, MSEL5CR_29_1,
2249 MSEL5CR_28_0, MSEL5CR_28_1,
2250 MSEL5CR_27_0, MSEL5CR_27_1,
2251 MSEL5CR_26_0, MSEL5CR_26_1,
2252 MSEL5CR_25_0, MSEL5CR_25_1,
2253 MSEL5CR_24_0, MSEL5CR_24_1,
2254 MSEL5CR_23_0, MSEL5CR_23_1,
2255 MSEL5CR_22_0, MSEL5CR_22_1,
2256 MSEL5CR_21_0, MSEL5CR_21_1,
2257 MSEL5CR_20_0, MSEL5CR_20_1,
2258 MSEL5CR_19_0, MSEL5CR_19_1,
2259 MSEL5CR_18_0, MSEL5CR_18_1,
2260 MSEL5CR_17_0, MSEL5CR_17_1,
2261 MSEL5CR_16_0, MSEL5CR_16_1,
2262 MSEL5CR_15_0, MSEL5CR_15_1,
2263 MSEL5CR_14_0, MSEL5CR_14_1,
2264 MSEL5CR_13_0, MSEL5CR_13_1,
2265 MSEL5CR_12_0, MSEL5CR_12_1,
2266 MSEL5CR_11_0, MSEL5CR_11_1,
2267 MSEL5CR_10_0, MSEL5CR_10_1,
2268 MSEL5CR_09_0, MSEL5CR_09_1,
2269 MSEL5CR_08_0, MSEL5CR_08_1,
2270 MSEL5CR_07_0, MSEL5CR_07_1,
2271 MSEL5CR_06_0, MSEL5CR_06_1,
2272 0, 0,
2273 0, 0,
2274 0, 0,
2275 0, 0,
2276 0, 0,
2277 0, 0,
2278 }
2279 },
2280 { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
2281 0, 0,
2282 0, 0,
2283 0, 0,
2284 0, 0,
2285 0, 0,
2286 0, 0,
2287 0, 0,
2288 0, 0,
2289 0, 0,
2290 0, 0,
2291 0, 0,
2292 0, 0,
2293 0, 0,
2294 0, 0,
2295 0, 0,
2296 MSEL8CR_16_0, MSEL8CR_16_1,
2297 0, 0,
2298 0, 0,
2299 0, 0,
2300 0, 0,
2301 0, 0,
2302 0, 0,
2303 0, 0,
2304 0, 0,
2305 0, 0,
2306 0, 0,
2307 0, 0,
2308 0, 0,
2309 0, 0,
2310 0, 0,
2311 MSEL8CR_01_0, MSEL8CR_01_1,
2312 MSEL8CR_00_0, MSEL8CR_00_1,
2313 }
2314 },
2315 { },
2316};
2317
2318static const struct pinmux_data_reg pinmux_data_regs[] = {
2319
2320 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
2321 0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2322 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2323 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2324 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2325 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2326 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2327 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2328 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2329 }
2330 },
2331 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
2332 0, 0, 0, 0,
2333 0, 0, 0, 0,
2334 0, 0, 0, 0,
2335 0, 0, 0, 0,
2336 0, 0, 0, 0,
2337 0, 0, 0, PORT40_DATA,
2338 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2339 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2340 }
2341 },
2342 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
2343 0, 0, 0, 0,
2344 0, 0, 0, 0,
2345 0, 0, PORT85_DATA, PORT84_DATA,
2346 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2347 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2348 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2349 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2350 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2351 }
2352 },
2353 { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
2354 0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2355 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2356 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2357 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2358 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2359 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2360 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2361 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2362 }
2363 },
2364 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
2365 0, 0, 0, 0,
2366 0, 0, 0, 0,
2367 0, 0, 0, 0,
2368 0, 0, 0, 0,
2369 0, 0, 0, 0,
2370 0, 0, 0, 0,
2371 0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2372 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2373 }
2374 },
2375 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
2376 0, 0, 0, 0,
2377 0, 0, 0, 0,
2378 0, 0, 0, 0,
2379 0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2380 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2381 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2382 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2383 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2384 }
2385 },
2386 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
2387 0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
2388 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
2389 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
2390 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
2391 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2392 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2393 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2394 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
2395 }
2396 },
2397 { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
2398 0, 0, 0, 0,
2399 0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
2400 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
2401 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
2402 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
2403 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
2404 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
2405 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
2406 }
2407 },
2408 { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
2409 0, 0, 0, 0,
2410 PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
2411 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
2412 PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
2413 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
2414 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
2415 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
2416 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
2417 }
2418 },
2419 { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
2420 0, 0, 0, 0,
2421 0, 0, 0, 0,
2422 0, 0, 0, PORT308_DATA,
2423 PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
2424 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
2425 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
2426 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
2427 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
2428 }
2429 },
2430 { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
2431 0, 0, 0, 0,
2432 0, 0, 0, 0,
2433 0, 0, 0, 0,
2434 0, 0, 0, 0,
2435 0, 0, 0, 0,
2436 0, 0, PORT329_DATA, PORT328_DATA,
2437 PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
2438 PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
2439 }
2440 },
2441 { },
2442};
2443
c96931ca
MD		 2444static const struct pinmux_irq pinmux_irqs[] = {
2445 PINMUX_IRQ(irq_pin(0), 0),
2446 PINMUX_IRQ(irq_pin(1), 1),
2447 PINMUX_IRQ(irq_pin(2), 2),
2448 PINMUX_IRQ(irq_pin(3), 3),
2449 PINMUX_IRQ(irq_pin(4), 4),
2450 PINMUX_IRQ(irq_pin(5), 5),
2451 PINMUX_IRQ(irq_pin(6), 6),
2452 PINMUX_IRQ(irq_pin(7), 7),
2453 PINMUX_IRQ(irq_pin(8), 8),
2454 PINMUX_IRQ(irq_pin(9), 9),
2455 PINMUX_IRQ(irq_pin(10), 10),
2456 PINMUX_IRQ(irq_pin(11), 11),
2457 PINMUX_IRQ(irq_pin(12), 12),
2458 PINMUX_IRQ(irq_pin(13), 13),
2459 PINMUX_IRQ(irq_pin(14), 14),
2460 PINMUX_IRQ(irq_pin(15), 15),
2461 PINMUX_IRQ(irq_pin(16), 320),
2462 PINMUX_IRQ(irq_pin(17), 321),
2463 PINMUX_IRQ(irq_pin(18), 85),
2464 PINMUX_IRQ(irq_pin(19), 84),
2465 PINMUX_IRQ(irq_pin(20), 160),
2466 PINMUX_IRQ(irq_pin(21), 161),
2467 PINMUX_IRQ(irq_pin(22), 162),
2468 PINMUX_IRQ(irq_pin(23), 163),
2469 PINMUX_IRQ(irq_pin(24), 175),
2470 PINMUX_IRQ(irq_pin(25), 176),
2471 PINMUX_IRQ(irq_pin(26), 177),
2472 PINMUX_IRQ(irq_pin(27), 178),
2473 PINMUX_IRQ(irq_pin(28), 322),
2474 PINMUX_IRQ(irq_pin(29), 323),
2475 PINMUX_IRQ(irq_pin(30), 324),
2476 PINMUX_IRQ(irq_pin(31), 192),
2477 PINMUX_IRQ(irq_pin(32), 193),
2478 PINMUX_IRQ(irq_pin(33), 194),
2479 PINMUX_IRQ(irq_pin(34), 195),
2480 PINMUX_IRQ(irq_pin(35), 196),
2481 PINMUX_IRQ(irq_pin(36), 197),
2482 PINMUX_IRQ(irq_pin(37), 198),
2483 PINMUX_IRQ(irq_pin(38), 199),
2484 PINMUX_IRQ(irq_pin(39), 200),
2485 PINMUX_IRQ(irq_pin(40), 66),
2486 PINMUX_IRQ(irq_pin(41), 102),
2487 PINMUX_IRQ(irq_pin(42), 103),
2488 PINMUX_IRQ(irq_pin(43), 109),
2489 PINMUX_IRQ(irq_pin(44), 110),
2490 PINMUX_IRQ(irq_pin(45), 111),
2491 PINMUX_IRQ(irq_pin(46), 112),
2492 PINMUX_IRQ(irq_pin(47), 113),
2493 PINMUX_IRQ(irq_pin(48), 114),
2494 PINMUX_IRQ(irq_pin(49), 115),
2495 PINMUX_IRQ(irq_pin(50), 301),
2496 PINMUX_IRQ(irq_pin(51), 290),
2497 PINMUX_IRQ(irq_pin(52), 296),
2498 PINMUX_IRQ(irq_pin(53), 325),
2499 PINMUX_IRQ(irq_pin(54), 326),
2500 PINMUX_IRQ(irq_pin(55), 327),
2501 PINMUX_IRQ(irq_pin(56), 328),
2502 PINMUX_IRQ(irq_pin(57), 329),
2503};
57ef73b4
MD		 2504
2505#define PORTCR_PULMD_OFF (0 << 6)
2506#define PORTCR_PULMD_DOWN (2 << 6)
2507#define PORTCR_PULMD_UP (3 << 6)
2508#define PORTCR_PULMD_MASK (3 << 6)
2509
2510static const unsigned int r8a73a4_portcr_offsets[] = {
2511 0x00000000, 0x00001000, 0x00000000, 0x00001000,
2512 0x00001000, 0x00002000, 0x00002000, 0x00002000,
2513 0x00002000, 0x00003000, 0x00003000,
2514};
2515
2516static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
2517 unsigned int pin)
2518{
2519 void __iomem *addr;
2520
2521 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2522
2523 switch (ioread8(addr) & PORTCR_PULMD_MASK) {
2524 case PORTCR_PULMD_UP:
2525 return PIN_CONFIG_BIAS_PULL_UP;
2526 case PORTCR_PULMD_DOWN:
2527 return PIN_CONFIG_BIAS_PULL_DOWN;
2528 case PORTCR_PULMD_OFF:
2529 default:
2530 return PIN_CONFIG_BIAS_DISABLE;
2531 }
2532}
2533
2534static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2535 unsigned int bias)
2536{
2537 void __iomem *addr;
2538 u32 value;
2539
2540 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2541 value = ioread8(addr) & ~PORTCR_PULMD_MASK;
2542
2543 switch (bias) {
2544 case PIN_CONFIG_BIAS_PULL_UP:
2545 value |= PORTCR_PULMD_UP;
2546 break;
2547 case PIN_CONFIG_BIAS_PULL_DOWN:
2548 value |= PORTCR_PULMD_DOWN;
2549 break;
2550 }
2551
2552 iowrite8(value, addr);
2553}
2554
2555static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
2556 .get_bias = r8a73a4_pinmux_get_bias,
2557 .set_bias = r8a73a4_pinmux_set_bias,
2558};
2559
c98f6c21
MD		 2560const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2561 .name = "r8a73a4_pfc",
57ef73b4 2562 .ops = &r8a73a4_pinmux_ops,
c98f6c21
MD		 2563
2564 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
c98f6c21
MD		 2565 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2566 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2567
2568 .pins = pinmux_pins,
2569 .nr_pins = ARRAY_SIZE(pinmux_pins),
172fd616 2570
f365bfcc
MD		 2571 .ranges = pinmux_ranges,
2572 .nr_ranges = ARRAY_SIZE(pinmux_ranges),
172fd616
MD		 2573
2574 .groups = pinmux_groups,
2575 .nr_groups = ARRAY_SIZE(pinmux_groups),
2576 .functions = pinmux_functions,
2577 .nr_functions = ARRAY_SIZE(pinmux_functions),
2578
c98f6c21
MD		 2579 .cfg_regs = pinmux_config_regs,
2580 .data_regs = pinmux_data_regs,
2581
2582 .gpio_data = pinmux_data,
2583 .gpio_data_size = ARRAY_SIZE(pinmux_data),
c96931ca
MD		 2584
2585 .gpio_irq = pinmux_irqs,
2586 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
c98f6c21 2587};
Empty description
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