[linux.git] / drivers / ata / pdc_adma.c

/*
 *  pdc_adma.c - Pacific Digital Corporation ADMA
 *
 *  Maintained by:  Mark Lord <[email protected]>
 *
 *  Copyright 2005 Mark Lord
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *
 *  Supports ATA disks in single-packet ADMA mode.
 *  Uses PIO for everything else.
 *
 *  TODO:  Use ADMA transfers for ATAPI devices, when possible.
 *  This requires careful attention to a number of quirks of the chip.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/gfp.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pdc_adma"
#define DRV_VERSION	"1.0"

/* macro to calculate base address for ATA regs */
#define ADMA_ATA_REGS(base, port_no)	((base) + ((port_no) * 0x40))

/* macro to calculate base address for ADMA regs */
#define ADMA_REGS(base, port_no)	((base) + 0x80 + ((port_no) * 0x20))

/* macro to obtain addresses from ata_port */
#define ADMA_PORT_REGS(ap) \
	ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)

enum {
	ADMA_MMIO_BAR		= 4,

	ADMA_PORTS		= 2,
	ADMA_CPB_BYTES		= 40,
	ADMA_PRD_BYTES		= LIBATA_MAX_PRD * 16,
	ADMA_PKT_BYTES		= ADMA_CPB_BYTES + ADMA_PRD_BYTES,

	ADMA_DMA_BOUNDARY	= 0xffffffff,

	/* global register offsets */
	ADMA_MODE_LOCK		= 0x00c7,

	/* per-channel register offsets */
	ADMA_CONTROL		= 0x0000, /* ADMA control */
	ADMA_STATUS		= 0x0002, /* ADMA status */
	ADMA_CPB_COUNT		= 0x0004, /* CPB count */
	ADMA_CPB_CURRENT	= 0x000c, /* current CPB address */
	ADMA_CPB_NEXT		= 0x000c, /* next CPB address */
	ADMA_CPB_LOOKUP		= 0x0010, /* CPB lookup table */
	ADMA_FIFO_IN		= 0x0014, /* input FIFO threshold */
	ADMA_FIFO_OUT		= 0x0016, /* output FIFO threshold */

	/* ADMA_CONTROL register bits */
	aNIEN			= (1 << 8), /* irq mask: 1==masked */
	aGO			= (1 << 7), /* packet trigger ("Go!") */
	aRSTADM			= (1 << 5), /* ADMA logic reset */
	aPIOMD4			= 0x0003,   /* PIO mode 4 */

	/* ADMA_STATUS register bits */
	aPSD			= (1 << 6),
	aUIRQ			= (1 << 4),
	aPERR			= (1 << 0),

	/* CPB bits */
	cDONE			= (1 << 0),
	cATERR			= (1 << 3),

	cVLD			= (1 << 0),
	cDAT			= (1 << 2),
	cIEN			= (1 << 3),

	/* PRD bits */
	pORD			= (1 << 4),
	pDIRO			= (1 << 5),
	pEND			= (1 << 7),

	/* ATA register flags */
	rIGN			= (1 << 5),
	rEND			= (1 << 7),

	/* ATA register addresses */
	ADMA_REGS_CONTROL	= 0x0e,
	ADMA_REGS_SECTOR_COUNT	= 0x12,
	ADMA_REGS_LBA_LOW	= 0x13,
	ADMA_REGS_LBA_MID	= 0x14,
	ADMA_REGS_LBA_HIGH	= 0x15,
	ADMA_REGS_DEVICE	= 0x16,
	ADMA_REGS_COMMAND	= 0x17,

	/* PCI device IDs */
	board_1841_idx		= 0,	/* ADMA 2-port controller */
};

typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;

struct adma_port_priv {
	u8			*pkt;
	dma_addr_t		pkt_dma;
	adma_state_t		state;
};

static int adma_ata_init_one(struct pci_dev *pdev,
				const struct pci_device_id *ent);
static int adma_port_start(struct ata_port *ap);
static void adma_port_stop(struct ata_port *ap);
static void adma_qc_prep(struct ata_queued_cmd *qc);
static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
static void adma_freeze(struct ata_port *ap);
static void adma_thaw(struct ata_port *ap);
static int adma_prereset(struct ata_link *link, unsigned long deadline);

static struct scsi_host_template adma_ata_sht = {
	ATA_BASE_SHT(DRV_NAME),
	.sg_tablesize		= LIBATA_MAX_PRD,
	.dma_boundary		= ADMA_DMA_BOUNDARY,
};

static struct ata_port_operations adma_ata_ops = {
	.inherits		= &ata_sff_port_ops,

	.lost_interrupt		= ATA_OP_NULL,

	.check_atapi_dma	= adma_check_atapi_dma,
	.qc_prep		= adma_qc_prep,
	.qc_issue		= adma_qc_issue,

	.freeze			= adma_freeze,
	.thaw			= adma_thaw,
	.prereset		= adma_prereset,

	.port_start		= adma_port_start,
	.port_stop		= adma_port_stop,
};

static struct ata_port_info adma_port_info[] = {
	/* board_1841_idx */
	{
		.flags		= ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_POLLING,
		.pio_mask	= ATA_PIO4_ONLY,
		.udma_mask	= ATA_UDMA4,
		.port_ops	= &adma_ata_ops,
	},
};

static const struct pci_device_id adma_ata_pci_tbl[] = {
	{ PCI_VDEVICE(PDC, 0x1841), board_1841_idx },

	{ }	/* terminate list */
};

static struct pci_driver adma_ata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= adma_ata_pci_tbl,
	.probe			= adma_ata_init_one,
	.remove			= ata_pci_remove_one,
};

static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
{
	return 1;	/* ATAPI DMA not yet supported */
}

static void adma_reset_engine(struct ata_port *ap)
{
	void __iomem *chan = ADMA_PORT_REGS(ap);

	/* reset ADMA to idle state */
	writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
	udelay(2);
	writew(aPIOMD4, chan + ADMA_CONTROL);
	udelay(2);
}

static void adma_reinit_engine(struct ata_port *ap)
{
	struct adma_port_priv *pp = ap->private_data;
	void __iomem *chan = ADMA_PORT_REGS(ap);

	/* mask/clear ATA interrupts */
	writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
	ata_sff_check_status(ap);

	/* reset the ADMA engine */
	adma_reset_engine(ap);

	/* set in-FIFO threshold to 0x100 */
	writew(0x100, chan + ADMA_FIFO_IN);

	/* set CPB pointer */
	writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);

	/* set out-FIFO threshold to 0x100 */
	writew(0x100, chan + ADMA_FIFO_OUT);

	/* set CPB count */
	writew(1, chan + ADMA_CPB_COUNT);

	/* read/discard ADMA status */
	readb(chan + ADMA_STATUS);
}

static inline void adma_enter_reg_mode(struct ata_port *ap)
{
	void __iomem *chan = ADMA_PORT_REGS(ap);

	writew(aPIOMD4, chan + ADMA_CONTROL);
	readb(chan + ADMA_STATUS);	/* flush */
}

static void adma_freeze(struct ata_port *ap)
{
	void __iomem *chan = ADMA_PORT_REGS(ap);

	/* mask/clear ATA interrupts */
	writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
	ata_sff_check_status(ap);

	/* reset ADMA to idle state */
	writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
	udelay(2);
	writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
	udelay(2);
}

static void adma_thaw(struct ata_port *ap)
{
	adma_reinit_engine(ap);
}

static int adma_prereset(struct ata_link *link, unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct adma_port_priv *pp = ap->private_data;

	if (pp->state != adma_state_idle) /* healthy paranoia */
		pp->state = adma_state_mmio;
	adma_reinit_engine(ap);

	return ata_sff_prereset(link, deadline);
}

static int adma_fill_sg(struct ata_queued_cmd *qc)
{
	struct scatterlist *sg;
	struct ata_port *ap = qc->ap;
	struct adma_port_priv *pp = ap->private_data;
	u8  *buf = pp->pkt, *last_buf = NULL;
	int i = (2 + buf[3]) * 8;
	u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
	unsigned int si;

	for_each_sg(qc->sg, sg, qc->n_elem, si) {
		u32 addr;
		u32 len;

		addr = (u32)sg_dma_address(sg);
		*(__le32 *)(buf + i) = cpu_to_le32(addr);
		i += 4;

		len = sg_dma_len(sg) >> 3;
		*(__le32 *)(buf + i) = cpu_to_le32(len);
		i += 4;

		last_buf = &buf[i];
		buf[i++] = pFLAGS;
		buf[i++] = qc->dev->dma_mode & 0xf;
		buf[i++] = 0;	/* pPKLW */
		buf[i++] = 0;	/* reserved */

		*(__le32 *)(buf + i) =
			(pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
		i += 4;

		VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
					(unsigned long)addr, len);
	}

	if (likely(last_buf))
		*last_buf |= pEND;

	return i;
}

static void adma_qc_prep(struct ata_queued_cmd *qc)
{
	struct adma_port_priv *pp = qc->ap->private_data;
	u8  *buf = pp->pkt;
	u32 pkt_dma = (u32)pp->pkt_dma;
	int i = 0;

	VPRINTK("ENTER\n");

	adma_enter_reg_mode(qc->ap);
	if (qc->tf.protocol != ATA_PROT_DMA)
		return;

	buf[i++] = 0;	/* Response flags */
	buf[i++] = 0;	/* reserved */
	buf[i++] = cVLD | cDAT | cIEN;
	i++;		/* cLEN, gets filled in below */

	*(__le32 *)(buf+i) = cpu_to_le32(pkt_dma);	/* cNCPB */
	i += 4;		/* cNCPB */
	i += 4;		/* cPRD, gets filled in below */

	buf[i++] = 0;	/* reserved */
	buf[i++] = 0;	/* reserved */
	buf[i++] = 0;	/* reserved */
	buf[i++] = 0;	/* reserved */

	/* ATA registers; must be a multiple of 4 */
	buf[i++] = qc->tf.device;
	buf[i++] = ADMA_REGS_DEVICE;
	if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
		buf[i++] = qc->tf.hob_nsect;
		buf[i++] = ADMA_REGS_SECTOR_COUNT;
		buf[i++] = qc->tf.hob_lbal;
		buf[i++] = ADMA_REGS_LBA_LOW;
		buf[i++] = qc->tf.hob_lbam;
		buf[i++] = ADMA_REGS_LBA_MID;
		buf[i++] = qc->tf.hob_lbah;
		buf[i++] = ADMA_REGS_LBA_HIGH;
	}
	buf[i++] = qc->tf.nsect;
	buf[i++] = ADMA_REGS_SECTOR_COUNT;
	buf[i++] = qc->tf.lbal;
	buf[i++] = ADMA_REGS_LBA_LOW;
	buf[i++] = qc->tf.lbam;
	buf[i++] = ADMA_REGS_LBA_MID;
	buf[i++] = qc->tf.lbah;
	buf[i++] = ADMA_REGS_LBA_HIGH;
	buf[i++] = 0;
	buf[i++] = ADMA_REGS_CONTROL;
	buf[i++] = rIGN;
	buf[i++] = 0;
	buf[i++] = qc->tf.command;
	buf[i++] = ADMA_REGS_COMMAND | rEND;

	buf[3] = (i >> 3) - 2;				/* cLEN */
	*(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i);	/* cPRD */

	i = adma_fill_sg(qc);
	wmb();	/* flush PRDs and pkt to memory */
#if 0
	/* dump out CPB + PRDs for debug */
	{
		int j, len = 0;
		static char obuf[2048];
		for (j = 0; j < i; ++j) {
			len += sprintf(obuf+len, "%02x ", buf[j]);
			if ((j & 7) == 7) {
				printk("%s\n", obuf);
				len = 0;
			}
		}
		if (len)
			printk("%s\n", obuf);
	}
#endif
}

static inline void adma_packet_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	void __iomem *chan = ADMA_PORT_REGS(ap);

	VPRINTK("ENTER, ap %p\n", ap);

	/* fire up the ADMA engine */
	writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
}

static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
{
	struct adma_port_priv *pp = qc->ap->private_data;

	switch (qc->tf.protocol) {
	case ATA_PROT_DMA:
		pp->state = adma_state_pkt;
		adma_packet_start(qc);
		return 0;

	case ATAPI_PROT_DMA:
		BUG();
		break;

	default:
		break;
	}

	pp->state = adma_state_mmio;
	return ata_sff_qc_issue(qc);
}

static inline unsigned int adma_intr_pkt(struct ata_host *host)
{
	unsigned int handled = 0, port_no;

	for (port_no = 0; port_no < host->n_ports; ++port_no) {
		struct ata_port *ap = host->ports[port_no];
		struct adma_port_priv *pp;
		struct ata_queued_cmd *qc;
		void __iomem *chan = ADMA_PORT_REGS(ap);
		u8 status = readb(chan + ADMA_STATUS);

		if (status == 0)
			continue;
		handled = 1;
		adma_enter_reg_mode(ap);
		pp = ap->private_data;
		if (!pp || pp->state != adma_state_pkt)
			continue;
		qc = ata_qc_from_tag(ap, ap->link.active_tag);
		if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
			if (status & aPERR)
				qc->err_mask |= AC_ERR_HOST_BUS;
			else if ((status & (aPSD | aUIRQ)))
				qc->err_mask |= AC_ERR_OTHER;

			if (pp->pkt[0] & cATERR)
				qc->err_mask |= AC_ERR_DEV;
			else if (pp->pkt[0] != cDONE)
				qc->err_mask |= AC_ERR_OTHER;

			if (!qc->err_mask)
				ata_qc_complete(qc);
			else {
				struct ata_eh_info *ehi = &ap->link.eh_info;
				ata_ehi_clear_desc(ehi);
				ata_ehi_push_desc(ehi,
					"ADMA-status 0x%02X", status);
				ata_ehi_push_desc(ehi,
					"pkt[0] 0x%02X", pp->pkt[0]);

				if (qc->err_mask == AC_ERR_DEV)
					ata_port_abort(ap);
				else
					ata_port_freeze(ap);
			}
		}
	}
	return handled;
}

static inline unsigned int adma_intr_mmio(struct ata_host *host)
{
	unsigned int handled = 0, port_no;

	for (port_no = 0; port_no < host->n_ports; ++port_no) {
		struct ata_port *ap = host->ports[port_no];
		struct adma_port_priv *pp = ap->private_data;
		struct ata_queued_cmd *qc;

		if (!pp || pp->state != adma_state_mmio)
			continue;
		qc = ata_qc_from_tag(ap, ap->link.active_tag);
		if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {

			/* check main status, clearing INTRQ */
			u8 status = ata_sff_check_status(ap);
			if ((status & ATA_BUSY))
				continue;
			DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
				ap->print_id, qc->tf.protocol, status);

			/* complete taskfile transaction */
			pp->state = adma_state_idle;
			qc->err_mask |= ac_err_mask(status);
			if (!qc->err_mask)
				ata_qc_complete(qc);
			else {
				struct ata_eh_info *ehi = &ap->link.eh_info;
				ata_ehi_clear_desc(ehi);
				ata_ehi_push_desc(ehi, "status 0x%02X", status);

				if (qc->err_mask == AC_ERR_DEV)
					ata_port_abort(ap);
				else
					ata_port_freeze(ap);
			}
			handled = 1;
		}
	}
	return handled;
}

static irqreturn_t adma_intr(int irq, void *dev_instance)
{
	struct ata_host *host = dev_instance;
	unsigned int handled = 0;

	VPRINTK("ENTER\n");

	spin_lock(&host->lock);
	handled  = adma_intr_pkt(host) | adma_intr_mmio(host);
	spin_unlock(&host->lock);

	VPRINTK("EXIT\n");

	return IRQ_RETVAL(handled);
}

static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
{
	port->cmd_addr		=
	port->data_addr		= base + 0x000;
	port->error_addr	=
	port->feature_addr	= base + 0x004;
	port->nsect_addr	= base + 0x008;
	port->lbal_addr		= base + 0x00c;
	port->lbam_addr		= base + 0x010;
	port->lbah_addr		= base + 0x014;
	port->device_addr	= base + 0x018;
	port->status_addr	=
	port->command_addr	= base + 0x01c;
	port->altstatus_addr	=
	port->ctl_addr		= base + 0x038;
}

static int adma_port_start(struct ata_port *ap)
{
	struct device *dev = ap->host->dev;
	struct adma_port_priv *pp;

	adma_enter_reg_mode(ap);
	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
	if (!pp)
		return -ENOMEM;
	pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
				      GFP_KERNEL);
	if (!pp->pkt)
		return -ENOMEM;
	/* paranoia? */
	if ((pp->pkt_dma & 7) != 0) {
		printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
						(u32)pp->pkt_dma);
		return -ENOMEM;
	}
	memset(pp->pkt, 0, ADMA_PKT_BYTES);
	ap->private_data = pp;
	adma_reinit_engine(ap);
	return 0;
}

static void adma_port_stop(struct ata_port *ap)
{
	adma_reset_engine(ap);
}

static void adma_host_init(struct ata_host *host, unsigned int chip_id)
{
	unsigned int port_no;

	/* enable/lock aGO operation */
	writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);

	/* reset the ADMA logic */
	for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
		adma_reset_engine(host->ports[port_no]);
}

static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
{
	int rc;

	rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	if (rc) {
		dev_err(&pdev->dev, "32-bit DMA enable failed\n");
		return rc;
	}
	rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
	if (rc) {
		dev_err(&pdev->dev, "32-bit consistent DMA enable failed\n");
		return rc;
	}
	return 0;
}

static int adma_ata_init_one(struct pci_dev *pdev,
			     const struct pci_device_id *ent)
{
	unsigned int board_idx = (unsigned int) ent->driver_data;
	const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
	struct ata_host *host;
	void __iomem *mmio_base;
	int rc, port_no;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	/* alloc host */
	host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
	if (!host)
		return -ENOMEM;

	/* acquire resources and fill host */
	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
		return -ENODEV;

	rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);
	mmio_base = host->iomap[ADMA_MMIO_BAR];

	rc = adma_set_dma_masks(pdev, mmio_base);
	if (rc)
		return rc;

	for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
		struct ata_port *ap = host->ports[port_no];
		void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
		unsigned int offset = port_base - mmio_base;

		adma_ata_setup_port(&ap->ioaddr, port_base);

		ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
		ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
	}

	/* initialize adapter */
	adma_host_init(host, board_idx);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
				 &adma_ata_sht);
}

static int __init adma_ata_init(void)
{
	return pci_register_driver(&adma_ata_pci_driver);
}

static void __exit adma_ata_exit(void)
{
	pci_unregister_driver(&adma_ata_pci_driver);
}

MODULE_AUTHOR("Mark Lord");
MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
MODULE_VERSION(DRV_VERSION);

module_init(adma_ata_init);
module_exit(adma_ata_exit);
Commit	Line	Data
edea3ab5 ML	1	/*
	2	* pdc_adma.c - Pacific Digital Corporation ADMA
	3	*
	4	* Maintained by: Mark Lord <[email protected]>
	5	*
	6	* Copyright 2005 Mark Lord
	7	*
68399bb5 JG	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2, or (at your option)
	11	* any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; see the file COPYING. If not, write to
	20	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*
	22	*
	23	* libata documentation is available via 'make {ps\|pdf}docs',
	24	* as Documentation/DocBook/libata.*
edea3ab5	25	*
edea3ab5 ML	26	*
	27	* Supports ATA disks in single-packet ADMA mode.
	28	* Uses PIO for everything else.
	29	*
	30	* TODO: Use ADMA transfers for ATAPI devices, when possible.
	31	* This requires careful attention to a number of quirks of the chip.
	32	*
	33	*/
	34
	35	#include <linux/kernel.h>
	36	#include <linux/module.h>
5a0e3ad6	37	#include <linux/gfp.h>
edea3ab5 ML	38	#include <linux/pci.h>
	39	#include <linux/init.h>
	40	#include <linux/blkdev.h>
	41	#include <linux/delay.h>
	42	#include <linux/interrupt.h>
a9524a76	43	#include <linux/device.h>
edea3ab5	44	#include <scsi/scsi_host.h>
edea3ab5 ML	45	#include <linux/libata.h>
	46
	47	#define DRV_NAME "pdc_adma"
2a3103ce	48	#define DRV_VERSION "1.0"
edea3ab5 ML	49
edea3ab5 ML	50	/* macro to calculate base address for ATA regs */
5796d1c4	51	#define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
edea3ab5 ML	52
edea3ab5 ML	53	/* macro to calculate base address for ADMA regs */
5796d1c4	54	#define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
0d5ff566	55
5d728824 TH	56	/* macro to obtain addresses from ata_port */
	57	#define ADMA_PORT_REGS(ap) \
	58	ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
edea3ab5 ML	59
edea3ab5 ML	60	enum {
0d5ff566 TH	61	ADMA_MMIO_BAR = 4,
0d5ff566 TH	62
edea3ab5 ML	63	ADMA_PORTS = 2,
	64	ADMA_CPB_BYTES = 40,
	65	ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
	66	ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
	67
	68	ADMA_DMA_BOUNDARY = 0xffffffff,
	69
	70	/* global register offsets */
	71	ADMA_MODE_LOCK = 0x00c7,
	72
	73	/* per-channel register offsets */
	74	ADMA_CONTROL = 0x0000, /* ADMA control */
	75	ADMA_STATUS = 0x0002, /* ADMA status */
	76	ADMA_CPB_COUNT = 0x0004, /* CPB count */
	77	ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
	78	ADMA_CPB_NEXT = 0x000c, /* next CPB address */
	79	ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
	80	ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
	81	ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
	82
	83	/* ADMA_CONTROL register bits */
	84	aNIEN = (1 << 8), /* irq mask: 1==masked */
	85	aGO = (1 << 7), /* packet trigger ("Go!") */
	86	aRSTADM = (1 << 5), /* ADMA logic reset */
edea3ab5 ML	87	aPIOMD4 = 0x0003, /* PIO mode 4 */
	88
	89	/* ADMA_STATUS register bits */
	90	aPSD = (1 << 6),
	91	aUIRQ = (1 << 4),
	92	aPERR = (1 << 0),
	93
	94	/* CPB bits */
	95	cDONE = (1 << 0),
640fdb50 JG	96	cATERR = (1 << 3),
640fdb50 JG	97
edea3ab5 ML	98	cVLD = (1 << 0),
	99	cDAT = (1 << 2),
	100	cIEN = (1 << 3),
	101
	102	/* PRD bits */
	103	pORD = (1 << 4),
	104	pDIRO = (1 << 5),
	105	pEND = (1 << 7),
	106
	107	/* ATA register flags */
	108	rIGN = (1 << 5),
	109	rEND = (1 << 7),
	110
	111	/* ATA register addresses */
	112	ADMA_REGS_CONTROL = 0x0e,
	113	ADMA_REGS_SECTOR_COUNT = 0x12,
	114	ADMA_REGS_LBA_LOW = 0x13,
	115	ADMA_REGS_LBA_MID = 0x14,
	116	ADMA_REGS_LBA_HIGH = 0x15,
	117	ADMA_REGS_DEVICE = 0x16,
	118	ADMA_REGS_COMMAND = 0x17,
	119
	120	/* PCI device IDs */
	121	board_1841_idx = 0, /* ADMA 2-port controller */
	122	};
	123
	124	typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
	125
	126	struct adma_port_priv {
	127	u8 *pkt;
	128	dma_addr_t pkt_dma;
	129	adma_state_t state;
	130	};
	131
5796d1c4	132	static int adma_ata_init_one(struct pci_dev *pdev,
edea3ab5	133	const struct pci_device_id *ent);
edea3ab5	134	static int adma_port_start(struct ata_port *ap);
edea3ab5	135	static void adma_port_stop(struct ata_port *ap);
edea3ab5	136	static void adma_qc_prep(struct ata_queued_cmd *qc);
9a3d9eb0	137	static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
edea3ab5	138	static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
640fdb50 JG	139	static void adma_freeze(struct ata_port *ap);
640fdb50 JG	140	static void adma_thaw(struct ata_port *ap);
a1efdaba	141	static int adma_prereset(struct ata_link *link, unsigned long deadline);
edea3ab5	142
193515d5	143	static struct scsi_host_template adma_ata_sht = {
68d1d07b	144	ATA_BASE_SHT(DRV_NAME),
edea3ab5	145	.sg_tablesize = LIBATA_MAX_PRD,
49de0ac8	146	.dma_boundary = ADMA_DMA_BOUNDARY,
edea3ab5 ML	147	};
edea3ab5 ML	148
029cfd6b	149	static struct ata_port_operations adma_ata_ops = {
b0316b15 TH	150	.inherits = &ata_sff_port_ops,
b0316b15 TH	151
c96f1732 AC	152	.lost_interrupt = ATA_OP_NULL,
c96f1732 AC	153
029cfd6b	154	.check_atapi_dma = adma_check_atapi_dma,
edea3ab5 ML	155	.qc_prep = adma_qc_prep,
edea3ab5 ML	156	.qc_issue = adma_qc_issue,
029cfd6b	157
640fdb50 JG	158	.freeze = adma_freeze,
640fdb50 JG	159	.thaw = adma_thaw,
a1efdaba	160	.prereset = adma_prereset,
029cfd6b	161
edea3ab5 ML	162	.port_start = adma_port_start,
edea3ab5 ML	163	.port_stop = adma_port_stop,
edea3ab5 ML	164	};
	165
	166	static struct ata_port_info adma_port_info[] = {
	167	/* board_1841_idx */
	168	{
9cbe056f	169	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_PIO_POLLING,
14bdef98	170	.pio_mask = ATA_PIO4_ONLY,
bf6263a8	171	.udma_mask = ATA_UDMA4,
edea3ab5 ML	172	.port_ops = &adma_ata_ops,
	173	},
	174	};
	175
3b7d697d	176	static const struct pci_device_id adma_ata_pci_tbl[] = {
54bb3a94	177	{ PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
edea3ab5 ML	178
	179	{ } /* terminate list */
	180	};
	181
	182	static struct pci_driver adma_ata_pci_driver = {
	183	.name = DRV_NAME,
	184	.id_table = adma_ata_pci_tbl,
	185	.probe = adma_ata_init_one,
	186	.remove = ata_pci_remove_one,
	187	};
	188
	189	static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
	190	{
	191	return 1; /* ATAPI DMA not yet supported */
	192	}
	193
5d728824	194	static void adma_reset_engine(struct ata_port *ap)
edea3ab5	195	{
5d728824 TH	196	void __iomem *chan = ADMA_PORT_REGS(ap);
5d728824 TH	197
edea3ab5 ML	198	/* reset ADMA to idle state */
	199	writew(aPIOMD4 \| aNIEN \| aRSTADM, chan + ADMA_CONTROL);
	200	udelay(2);
	201	writew(aPIOMD4, chan + ADMA_CONTROL);
	202	udelay(2);
	203	}
	204
	205	static void adma_reinit_engine(struct ata_port *ap)
	206	{
	207	struct adma_port_priv *pp = ap->private_data;
5d728824	208	void __iomem *chan = ADMA_PORT_REGS(ap);
edea3ab5 ML	209
edea3ab5 ML	210	/* mask/clear ATA interrupts */
0d5ff566	211	writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
9363c382	212	ata_sff_check_status(ap);
edea3ab5 ML	213
edea3ab5 ML	214	/* reset the ADMA engine */
5d728824	215	adma_reset_engine(ap);
edea3ab5 ML	216
	217	/* set in-FIFO threshold to 0x100 */
	218	writew(0x100, chan + ADMA_FIFO_IN);
	219
	220	/* set CPB pointer */
	221	writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
	222
	223	/* set out-FIFO threshold to 0x100 */
	224	writew(0x100, chan + ADMA_FIFO_OUT);
	225
	226	/* set CPB count */
	227	writew(1, chan + ADMA_CPB_COUNT);
	228
	229	/* read/discard ADMA status */
	230	readb(chan + ADMA_STATUS);
	231	}
	232
	233	static inline void adma_enter_reg_mode(struct ata_port *ap)
	234	{
5d728824	235	void __iomem *chan = ADMA_PORT_REGS(ap);
edea3ab5 ML	236
	237	writew(aPIOMD4, chan + ADMA_CONTROL);
	238	readb(chan + ADMA_STATUS); /* flush */
	239	}
	240
640fdb50	241	static void adma_freeze(struct ata_port *ap)
edea3ab5	242	{
640fdb50 JG	243	void __iomem *chan = ADMA_PORT_REGS(ap);
	244
	245	/* mask/clear ATA interrupts */
	246	writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
9363c382	247	ata_sff_check_status(ap);
640fdb50 JG	248
	249	/* reset ADMA to idle state */
	250	writew(aPIOMD4 \| aNIEN \| aRSTADM, chan + ADMA_CONTROL);
	251	udelay(2);
	252	writew(aPIOMD4 \| aNIEN, chan + ADMA_CONTROL);
	253	udelay(2);
	254	}
edea3ab5	255
640fdb50 JG	256	static void adma_thaw(struct ata_port *ap)
640fdb50 JG	257	{
edea3ab5	258	adma_reinit_engine(ap);
edea3ab5 ML	259	}
edea3ab5 ML	260
0260731f	261	static int adma_prereset(struct ata_link *link, unsigned long deadline)
edea3ab5	262	{
0260731f	263	struct ata_port *ap = link->ap;
edea3ab5 ML	264	struct adma_port_priv *pp = ap->private_data;
	265
	266	if (pp->state != adma_state_idle) /* healthy paranoia */
	267	pp->state = adma_state_mmio;
	268	adma_reinit_engine(ap);
640fdb50	269
9363c382	270	return ata_sff_prereset(link, deadline);
640fdb50 JG	271	}
640fdb50 JG	272
edea3ab5 ML	273	static int adma_fill_sg(struct ata_queued_cmd *qc)
edea3ab5 ML	274	{
972c26bd	275	struct scatterlist *sg;
edea3ab5 ML	276	struct ata_port *ap = qc->ap;
edea3ab5 ML	277	struct adma_port_priv *pp = ap->private_data;
3be6cbd7	278	u8 buf = pp->pkt, last_buf = NULL;
972c26bd	279	int i = (2 + buf[3]) * 8;
edea3ab5	280	u8 pFLAGS = pORD \| ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
ff2aeb1e	281	unsigned int si;
edea3ab5	282
ff2aeb1e	283	for_each_sg(qc->sg, sg, qc->n_elem, si) {
edea3ab5 ML	284	u32 addr;
	285	u32 len;
	286
	287	addr = (u32)sg_dma_address(sg);
	288	(__le32 )(buf + i) = cpu_to_le32(addr);
	289	i += 4;
	290
	291	len = sg_dma_len(sg) >> 3;
	292	(__le32 )(buf + i) = cpu_to_le32(len);
	293	i += 4;
	294
3be6cbd7	295	last_buf = &buf[i];
edea3ab5 ML	296	buf[i++] = pFLAGS;
	297	buf[i++] = qc->dev->dma_mode & 0xf;
	298	buf[i++] = 0; /* pPKLW */
	299	buf[i++] = 0; /* reserved */
	300
5796d1c4 JG	301	(__le32 )(buf + i) =
5796d1c4 JG	302	(pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
edea3ab5 ML	303	i += 4;
edea3ab5 ML	304
db7f44d9	305	VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
edea3ab5 ML	306	(unsigned long)addr, len);
edea3ab5 ML	307	}
3be6cbd7 JG	308
	309	if (likely(last_buf))
	310	*last_buf \|= pEND;
	311
edea3ab5 ML	312	return i;
	313	}
	314
	315	static void adma_qc_prep(struct ata_queued_cmd *qc)
	316	{
	317	struct adma_port_priv *pp = qc->ap->private_data;
	318	u8 *buf = pp->pkt;
	319	u32 pkt_dma = (u32)pp->pkt_dma;
	320	int i = 0;
	321
	322	VPRINTK("ENTER\n");
	323
	324	adma_enter_reg_mode(qc->ap);
f47451c4	325	if (qc->tf.protocol != ATA_PROT_DMA)
edea3ab5	326	return;
edea3ab5 ML	327
	328	buf[i++] = 0; /* Response flags */
	329	buf[i++] = 0; /* reserved */
	330	buf[i++] = cVLD \| cDAT \| cIEN;
	331	i++; /* cLEN, gets filled in below */
	332
	333	(__le32 )(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
	334	i += 4; /* cNCPB */
	335	i += 4; /* cPRD, gets filled in below */
	336
	337	buf[i++] = 0; /* reserved */
	338	buf[i++] = 0; /* reserved */
	339	buf[i++] = 0; /* reserved */
	340	buf[i++] = 0; /* reserved */
	341
	342	/* ATA registers; must be a multiple of 4 */
	343	buf[i++] = qc->tf.device;
	344	buf[i++] = ADMA_REGS_DEVICE;
	345	if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
	346	buf[i++] = qc->tf.hob_nsect;
	347	buf[i++] = ADMA_REGS_SECTOR_COUNT;
	348	buf[i++] = qc->tf.hob_lbal;
	349	buf[i++] = ADMA_REGS_LBA_LOW;
	350	buf[i++] = qc->tf.hob_lbam;
	351	buf[i++] = ADMA_REGS_LBA_MID;
	352	buf[i++] = qc->tf.hob_lbah;
	353	buf[i++] = ADMA_REGS_LBA_HIGH;
	354	}
	355	buf[i++] = qc->tf.nsect;
	356	buf[i++] = ADMA_REGS_SECTOR_COUNT;
	357	buf[i++] = qc->tf.lbal;
	358	buf[i++] = ADMA_REGS_LBA_LOW;
	359	buf[i++] = qc->tf.lbam;
	360	buf[i++] = ADMA_REGS_LBA_MID;
	361	buf[i++] = qc->tf.lbah;
	362	buf[i++] = ADMA_REGS_LBA_HIGH;
	363	buf[i++] = 0;
	364	buf[i++] = ADMA_REGS_CONTROL;
	365	buf[i++] = rIGN;
	366	buf[i++] = 0;
	367	buf[i++] = qc->tf.command;
	368	buf[i++] = ADMA_REGS_COMMAND \| rEND;
	369
	370	buf[3] = (i >> 3) - 2; /* cLEN */
	371	(__le32 )(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
	372
	373	i = adma_fill_sg(qc);
	374	wmb(); /* flush PRDs and pkt to memory */
	375	#if 0
	376	/* dump out CPB + PRDs for debug */
	377	{
	378	int j, len = 0;
	379	static char obuf[2048];
	380	for (j = 0; j < i; ++j) {
	381	len += sprintf(obuf+len, "%02x ", buf[j]);
	382	if ((j & 7) == 7) {
	383	printk("%s\n", obuf);
	384	len = 0;
	385	}
	386	}
	387	if (len)
	388	printk("%s\n", obuf);
	389	}
	390	#endif
391	}
392
393	static inline void adma_packet_start(struct ata_queued_cmd *qc)
394	{
395	struct ata_port *ap = qc->ap;
5d728824	396	void __iomem *chan = ADMA_PORT_REGS(ap);
edea3ab5 ML	397
	398	VPRINTK("ENTER, ap %p\n", ap);
	399
	400	/* fire up the ADMA engine */
68399bb5	401	writew(aPIOMD4 \| aGO, chan + ADMA_CONTROL);
edea3ab5 ML	402	}
edea3ab5 ML	403
9a3d9eb0	404	static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
edea3ab5 ML	405	{
	406	struct adma_port_priv *pp = qc->ap->private_data;
	407
	408	switch (qc->tf.protocol) {
	409	case ATA_PROT_DMA:
	410	pp->state = adma_state_pkt;
	411	adma_packet_start(qc);
	412	return 0;
	413
0dc36888	414	case ATAPI_PROT_DMA:
edea3ab5 ML	415	BUG();
	416	break;
	417
	418	default:
	419	break;
	420	}
	421
	422	pp->state = adma_state_mmio;
9363c382	423	return ata_sff_qc_issue(qc);
edea3ab5 ML	424	}
edea3ab5 ML	425
cca3974e	426	static inline unsigned int adma_intr_pkt(struct ata_host *host)
edea3ab5 ML	427	{
edea3ab5 ML	428	unsigned int handled = 0, port_no;
edea3ab5	429
cca3974e JG	430	for (port_no = 0; port_no < host->n_ports; ++port_no) {
cca3974e JG	431	struct ata_port *ap = host->ports[port_no];
edea3ab5 ML	432	struct adma_port_priv *pp;
edea3ab5 ML	433	struct ata_queued_cmd *qc;
5d728824	434	void __iomem *chan = ADMA_PORT_REGS(ap);
a7dac447	435	u8 status = readb(chan + ADMA_STATUS);
edea3ab5 ML	436
	437	if (status == 0)
	438	continue;
	439	handled = 1;
	440	adma_enter_reg_mode(ap);
edea3ab5 ML	441	pp = ap->private_data;
	442	if (!pp \|\| pp->state != adma_state_pkt)
	443	continue;
9af5c9c9	444	qc = ata_qc_from_tag(ap, ap->link.active_tag);
94ec1ef1	445	if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
640fdb50 JG	446	if (status & aPERR)
	447	qc->err_mask \|= AC_ERR_HOST_BUS;
	448	else if ((status & (aPSD \| aUIRQ)))
a22e2eb0	449	qc->err_mask \|= AC_ERR_OTHER;
640fdb50 JG	450
	451	if (pp->pkt[0] & cATERR)
	452	qc->err_mask \|= AC_ERR_DEV;
a21a84a3	453	else if (pp->pkt[0] != cDONE)
a22e2eb0	454	qc->err_mask \|= AC_ERR_OTHER;
a7dac447	455
640fdb50 JG	456	if (!qc->err_mask)
	457	ata_qc_complete(qc);
	458	else {
9af5c9c9	459	struct ata_eh_info *ehi = &ap->link.eh_info;
640fdb50 JG	460	ata_ehi_clear_desc(ehi);
	461	ata_ehi_push_desc(ehi,
	462	"ADMA-status 0x%02X", status);
	463	ata_ehi_push_desc(ehi,
	464	"pkt[0] 0x%02X", pp->pkt[0]);
	465
	466	if (qc->err_mask == AC_ERR_DEV)
	467	ata_port_abort(ap);
	468	else
	469	ata_port_freeze(ap);
	470	}
a21a84a3	471	}
edea3ab5 ML	472	}
	473	return handled;
	474	}
	475
cca3974e	476	static inline unsigned int adma_intr_mmio(struct ata_host *host)
edea3ab5 ML	477	{
	478	unsigned int handled = 0, port_no;
	479
cca3974e	480	for (port_no = 0; port_no < host->n_ports; ++port_no) {
3e4ec344 TH	481	struct ata_port *ap = host->ports[port_no];
	482	struct adma_port_priv *pp = ap->private_data;
	483	struct ata_queued_cmd *qc;
	484
	485	if (!pp \|\| pp->state != adma_state_mmio)
	486	continue;
	487	qc = ata_qc_from_tag(ap, ap->link.active_tag);
	488	if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
	489
	490	/* check main status, clearing INTRQ */
	491	u8 status = ata_sff_check_status(ap);
	492	if ((status & ATA_BUSY))
edea3ab5	493	continue;
3e4ec344 TH	494	DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
	495	ap->print_id, qc->tf.protocol, status);
	496
	497	/* complete taskfile transaction */
	498	pp->state = adma_state_idle;
	499	qc->err_mask \|= ac_err_mask(status);
	500	if (!qc->err_mask)
	501	ata_qc_complete(qc);
	502	else {
	503	struct ata_eh_info *ehi = &ap->link.eh_info;
	504	ata_ehi_clear_desc(ehi);
	505	ata_ehi_push_desc(ehi, "status 0x%02X", status);
	506
	507	if (qc->err_mask == AC_ERR_DEV)
	508	ata_port_abort(ap);
	509	else
	510	ata_port_freeze(ap);
edea3ab5	511	}
3e4ec344	512	handled = 1;
edea3ab5 ML	513	}
	514	}
	515	return handled;
	516	}
	517
7d12e780	518	static irqreturn_t adma_intr(int irq, void *dev_instance)
edea3ab5	519	{
cca3974e	520	struct ata_host *host = dev_instance;
edea3ab5 ML	521	unsigned int handled = 0;
	522
	523	VPRINTK("ENTER\n");
	524
cca3974e JG	525	spin_lock(&host->lock);
	526	handled = adma_intr_pkt(host) \| adma_intr_mmio(host);
	527	spin_unlock(&host->lock);
edea3ab5 ML	528
	529	VPRINTK("EXIT\n");
	530
	531	return IRQ_RETVAL(handled);
	532	}
	533
0d5ff566	534	static void adma_ata_setup_port(struct ata_ioports port, void __iomem base)
edea3ab5 ML	535	{
	536	port->cmd_addr =
	537	port->data_addr = base + 0x000;
	538	port->error_addr =
	539	port->feature_addr = base + 0x004;
	540	port->nsect_addr = base + 0x008;
	541	port->lbal_addr = base + 0x00c;
	542	port->lbam_addr = base + 0x010;
	543	port->lbah_addr = base + 0x014;
	544	port->device_addr = base + 0x018;
	545	port->status_addr =
	546	port->command_addr = base + 0x01c;
	547	port->altstatus_addr =
	548	port->ctl_addr = base + 0x038;
	549	}
	550
	551	static int adma_port_start(struct ata_port *ap)
	552	{
cca3974e	553	struct device *dev = ap->host->dev;
edea3ab5	554	struct adma_port_priv *pp;
edea3ab5	555
edea3ab5	556	adma_enter_reg_mode(ap);
24dc5f33	557	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
edea3ab5	558	if (!pp)
24dc5f33 TH	559	return -ENOMEM;
	560	pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
	561	GFP_KERNEL);
edea3ab5	562	if (!pp->pkt)
24dc5f33	563	return -ENOMEM;
edea3ab5 ML	564	/* paranoia? */
edea3ab5 ML	565	if ((pp->pkt_dma & 7) != 0) {
5796d1c4	566	printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
edea3ab5	567	(u32)pp->pkt_dma);
24dc5f33	568	return -ENOMEM;
edea3ab5 ML	569	}
	570	memset(pp->pkt, 0, ADMA_PKT_BYTES);
	571	ap->private_data = pp;
	572	adma_reinit_engine(ap);
	573	return 0;
edea3ab5 ML	574	}
	575
	576	static void adma_port_stop(struct ata_port *ap)
	577	{
5d728824	578	adma_reset_engine(ap);
edea3ab5 ML	579	}
edea3ab5 ML	580
5d728824	581	static void adma_host_init(struct ata_host *host, unsigned int chip_id)
edea3ab5 ML	582	{
edea3ab5 ML	583	unsigned int port_no;
edea3ab5 ML	584
edea3ab5 ML	585	/* enable/lock aGO operation */
5d728824	586	writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
edea3ab5 ML	587
	588	/* reset the ADMA logic */
	589	for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
5d728824	590	adma_reset_engine(host->ports[port_no]);
edea3ab5 ML	591	}
	592
	593	static int adma_set_dma_masks(struct pci_dev pdev, void __iomem mmio_base)
	594	{
	595	int rc;
	596
284901a9	597	rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
edea3ab5	598	if (rc) {
a44fec1f	599	dev_err(&pdev->dev, "32-bit DMA enable failed\n");
edea3ab5 ML	600	return rc;
edea3ab5 ML	601	}
284901a9	602	rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
edea3ab5	603	if (rc) {
a44fec1f	604	dev_err(&pdev->dev, "32-bit consistent DMA enable failed\n");
edea3ab5 ML	605	return rc;
	606	}
	607	return 0;
	608	}
	609
	610	static int adma_ata_init_one(struct pci_dev *pdev,
0d5ff566	611	const struct pci_device_id *ent)
edea3ab5	612	{
edea3ab5	613	unsigned int board_idx = (unsigned int) ent->driver_data;
5d728824 TH	614	const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
	615	struct ata_host *host;
	616	void __iomem *mmio_base;
edea3ab5 ML	617	int rc, port_no;
edea3ab5 ML	618
06296a1e	619	ata_print_version_once(&pdev->dev, DRV_VERSION);
edea3ab5	620
5d728824 TH	621	/* alloc host */
	622	host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
	623	if (!host)
	624	return -ENOMEM;
	625
	626	/* acquire resources and fill host */
24dc5f33	627	rc = pcim_enable_device(pdev);
edea3ab5 ML	628	if (rc)
	629	return rc;
	630
24dc5f33 TH	631	if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
24dc5f33 TH	632	return -ENODEV;
edea3ab5	633
0d5ff566 TH	634	rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
	635	if (rc)
	636	return rc;
5d728824 TH	637	host->iomap = pcim_iomap_table(pdev);
5d728824 TH	638	mmio_base = host->iomap[ADMA_MMIO_BAR];
edea3ab5 ML	639
	640	rc = adma_set_dma_masks(pdev, mmio_base);
	641	if (rc)
24dc5f33	642	return rc;
edea3ab5	643
cbcdd875 TH	644	for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
	645	struct ata_port *ap = host->ports[port_no];
	646	void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
	647	unsigned int offset = port_base - mmio_base;
	648
	649	adma_ata_setup_port(&ap->ioaddr, port_base);
	650
	651	ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
	652	ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
	653	}
edea3ab5 ML	654
edea3ab5 ML	655	/* initialize adapter */
5d728824	656	adma_host_init(host, board_idx);
edea3ab5	657
5d728824 TH	658	pci_set_master(pdev);
	659	return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
	660	&adma_ata_sht);
edea3ab5 ML	661	}
	662
	663	static int __init adma_ata_init(void)
	664	{
b7887196	665	return pci_register_driver(&adma_ata_pci_driver);
edea3ab5 ML	666	}
	667
	668	static void __exit adma_ata_exit(void)
	669	{
	670	pci_unregister_driver(&adma_ata_pci_driver);
	671	}
	672
	673	MODULE_AUTHOR("Mark Lord");
	674	MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
	675	MODULE_LICENSE("GPL");
	676	MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
	677	MODULE_VERSION(DRV_VERSION);
	678
	679	module_init(adma_ata_init);
	680	module_exit(adma_ata_exit);