projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /************************************************************************** |
| 2 | * Initio 9100 device driver for Linux. | |
| 3 | * | |
| 4 | * Copyright (c) 1994-1998 Initio Corporation | |
| 5 | * All rights reserved. | |
| 6 | * | |
| fa195afe | 7 | * Cleanups (c) Copyright 2007 Red Hat <[email protected]> |
| 72d39fea | 8 | * |
| 1da177e4 LT |
9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by | |
| 11 | * the Free Software Foundation; either version 2, or (at your option) | |
| 12 | * any later version. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; see the file COPYING. If not, write to | |
| 21 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
| 22 | * | |
| 1da177e4 LT |
23 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 24 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
| 26 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR | |
| 27 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
| 28 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
| 29 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
| 30 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
| 31 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
| 32 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
| 33 | * SUCH DAMAGE. | |
| 34 | * | |
| 35 | **************************************************************************/ | |
| 36 | ||
| 37 | ||
| 1da177e4 LT |
38 | #include <linux/types.h> |
| 39 | ||
| 1da177e4 LT |
40 | #define TOTAL_SG_ENTRY 32 |
| 41 | #define MAX_SUPPORTED_ADAPTERS 8 | |
| 42 | #define MAX_OFFSET 15 | |
| 43 | #define MAX_TARGETS 16 | |
| 44 | ||
| 45 | typedef struct { | |
| 46 | unsigned short base; | |
| 47 | unsigned short vec; | |
| 48 | } i91u_config; | |
| 49 | ||
| 50 | /***************************************/ | |
| 51 | /* Tulip Configuration Register Set */ | |
| 52 | /***************************************/ | |
| 53 | #define TUL_PVID 0x00 /* Vendor ID */ | |
| 54 | #define TUL_PDID 0x02 /* Device ID */ | |
| 55 | #define TUL_PCMD 0x04 /* Command */ | |
| 56 | #define TUL_PSTUS 0x06 /* Status */ | |
| 57 | #define TUL_PRID 0x08 /* Revision number */ | |
| 58 | #define TUL_PPI 0x09 /* Programming interface */ | |
| 59 | #define TUL_PSC 0x0A /* Sub Class */ | |
| 60 | #define TUL_PBC 0x0B /* Base Class */ | |
| 61 | #define TUL_PCLS 0x0C /* Cache line size */ | |
| 62 | #define TUL_PLTR 0x0D /* Latency timer */ | |
| 63 | #define TUL_PHDT 0x0E /* Header type */ | |
| 64 | #define TUL_PBIST 0x0F /* BIST */ | |
| 65 | #define TUL_PBAD 0x10 /* Base address */ | |
| 66 | #define TUL_PBAD1 0x14 /* Base address */ | |
| 67 | #define TUL_PBAD2 0x18 /* Base address */ | |
| 68 | #define TUL_PBAD3 0x1C /* Base address */ | |
| 69 | #define TUL_PBAD4 0x20 /* Base address */ | |
| 70 | #define TUL_PBAD5 0x24 /* Base address */ | |
| 71 | #define TUL_PRSVD 0x28 /* Reserved */ | |
| 72 | #define TUL_PRSVD1 0x2C /* Reserved */ | |
| 73 | #define TUL_PRAD 0x30 /* Expansion ROM base address */ | |
| 74 | #define TUL_PRSVD2 0x34 /* Reserved */ | |
| 75 | #define TUL_PRSVD3 0x38 /* Reserved */ | |
| 76 | #define TUL_PINTL 0x3C /* Interrupt line */ | |
| 77 | #define TUL_PINTP 0x3D /* Interrupt pin */ | |
| 78 | #define TUL_PIGNT 0x3E /* MIN_GNT */ | |
| 79 | #define TUL_PMGNT 0x3F /* MAX_GNT */ | |
| 80 | ||
| 81 | /************************/ | |
| 82 | /* Jasmin Register Set */ | |
| 83 | /************************/ | |
| 84 | #define TUL_HACFG0 0x40 /* H/A Configuration Register 0 */ | |
| 85 | #define TUL_HACFG1 0x41 /* H/A Configuration Register 1 */ | |
| 86 | #define TUL_HACFG2 0x42 /* H/A Configuration Register 2 */ | |
| 87 | ||
| 88 | #define TUL_SDCFG0 0x44 /* SCSI Device Configuration 0 */ | |
| 89 | #define TUL_SDCFG1 0x45 /* SCSI Device Configuration 1 */ | |
| 90 | #define TUL_SDCFG2 0x46 /* SCSI Device Configuration 2 */ | |
| 91 | #define TUL_SDCFG3 0x47 /* SCSI Device Configuration 3 */ | |
| 92 | ||
| 93 | #define TUL_GINTS 0x50 /* Global Interrupt Status Register */ | |
| 94 | #define TUL_GIMSK 0x52 /* Global Interrupt MASK Register */ | |
| 95 | #define TUL_GCTRL 0x54 /* Global Control Register */ | |
| 96 | #define TUL_GCTRL_EEPROM_BIT 0x04 | |
| 97 | #define TUL_GCTRL1 0x55 /* Global Control Register */ | |
| 98 | #define TUL_DMACFG 0x5B /* DMA configuration */ | |
| 99 | #define TUL_NVRAM 0x5D /* Non-volatile RAM port */ | |
| 100 | ||
| 101 | #define TUL_SCnt0 0x80 /* 00 R/W Transfer Counter Low */ | |
| 102 | #define TUL_SCnt1 0x81 /* 01 R/W Transfer Counter Mid */ | |
| 103 | #define TUL_SCnt2 0x82 /* 02 R/W Transfer Count High */ | |
| 104 | #define TUL_SFifoCnt 0x83 /* 03 R FIFO counter */ | |
| 105 | #define TUL_SIntEnable 0x84 /* 03 W Interrupt enble */ | |
| 106 | #define TUL_SInt 0x84 /* 04 R Interrupt Register */ | |
| 107 | #define TUL_SCtrl0 0x85 /* 05 W Control 0 */ | |
| 108 | #define TUL_SStatus0 0x85 /* 05 R Status 0 */ | |
| 109 | #define TUL_SCtrl1 0x86 /* 06 W Control 1 */ | |
| 110 | #define TUL_SStatus1 0x86 /* 06 R Status 1 */ | |
| 111 | #define TUL_SConfig 0x87 /* 07 W Configuration */ | |
| 112 | #define TUL_SStatus2 0x87 /* 07 R Status 2 */ | |
| 113 | #define TUL_SPeriod 0x88 /* 08 W Sync. Transfer Period & Offset */ | |
| 114 | #define TUL_SOffset 0x88 /* 08 R Offset */ | |
| 115 | #define TUL_SScsiId 0x89 /* 09 W SCSI ID */ | |
| 116 | #define TUL_SBusId 0x89 /* 09 R SCSI BUS ID */ | |
| 117 | #define TUL_STimeOut 0x8A /* 0A W Sel/Resel Time Out Register */ | |
| 118 | #define TUL_SIdent 0x8A /* 0A R Identify Message Register */ | |
| 25985edc | 119 | #define TUL_SAvail 0x8A /* 0A R Available Counter Register */ |
| 1da177e4 LT |
120 | #define TUL_SData 0x8B /* 0B R/W SCSI data in/out */ |
| 121 | #define TUL_SFifo 0x8C /* 0C R/W FIFO */ | |
| 122 | #define TUL_SSignal 0x90 /* 10 R/W SCSI signal in/out */ | |
| 123 | #define TUL_SCmd 0x91 /* 11 R/W Command */ | |
| 124 | #define TUL_STest0 0x92 /* 12 R/W Test0 */ | |
| 125 | #define TUL_STest1 0x93 /* 13 R/W Test1 */ | |
| 126 | #define TUL_SCFG1 0x94 /* 14 R/W Configuration */ | |
| 127 | ||
| 128 | #define TUL_XAddH 0xC0 /*DMA Transfer Physical Address */ | |
| 129 | #define TUL_XAddW 0xC8 /*DMA Current Transfer Physical Address */ | |
| 130 | #define TUL_XCntH 0xD0 /*DMA Transfer Counter */ | |
| 131 | #define TUL_XCntW 0xD4 /*DMA Current Transfer Counter */ | |
| 132 | #define TUL_XCmd 0xD8 /*DMA Command Register */ | |
| 133 | #define TUL_Int 0xDC /*Interrupt Register */ | |
| 134 | #define TUL_XStatus 0xDD /*DMA status Register */ | |
| 135 | #define TUL_Mask 0xE0 /*Interrupt Mask Register */ | |
| 136 | #define TUL_XCtrl 0xE4 /*DMA Control Register */ | |
| 137 | #define TUL_XCtrl1 0xE5 /*DMA Control Register 1 */ | |
| 138 | #define TUL_XFifo 0xE8 /*DMA FIFO */ | |
| 139 | ||
| 140 | #define TUL_WCtrl 0xF7 /*Bus master wait state control */ | |
| 141 | #define TUL_DCtrl 0xFB /*DMA delay control */ | |
| 142 | ||
| 143 | /*----------------------------------------------------------------------*/ | |
| 144 | /* bit definition for Command register of Configuration Space Header */ | |
| 145 | /*----------------------------------------------------------------------*/ | |
| 146 | #define BUSMS 0x04 /* BUS MASTER Enable */ | |
| 147 | #define IOSPA 0x01 /* IO Space Enable */ | |
| 148 | ||
| 149 | /*----------------------------------------------------------------------*/ | |
| 150 | /* Command Codes of Tulip SCSI Command register */ | |
| 151 | /*----------------------------------------------------------------------*/ | |
| 152 | #define TSC_EN_RESEL 0x80 /* Enable Reselection */ | |
| 153 | #define TSC_CMD_COMP 0x84 /* Command Complete Sequence */ | |
| 154 | #define TSC_SEL 0x01 /* Select Without ATN Sequence */ | |
| 155 | #define TSC_SEL_ATN 0x11 /* Select With ATN Sequence */ | |
| 156 | #define TSC_SEL_ATN_DMA 0x51 /* Select With ATN Sequence with DMA */ | |
| 157 | #define TSC_SEL_ATN3 0x31 /* Select With ATN3 Sequence */ | |
| 158 | #define TSC_SEL_ATNSTOP 0x12 /* Select With ATN and Stop Sequence */ | |
| 159 | #define TSC_SELATNSTOP 0x1E /* Select With ATN and Stop Sequence */ | |
| 160 | ||
| 161 | #define TSC_SEL_ATN_DIRECT_IN 0x95 /* Select With ATN Sequence */ | |
| 162 | #define TSC_SEL_ATN_DIRECT_OUT 0x15 /* Select With ATN Sequence */ | |
| 163 | #define TSC_SEL_ATN3_DIRECT_IN 0xB5 /* Select With ATN3 Sequence */ | |
| 164 | #define TSC_SEL_ATN3_DIRECT_OUT 0x35 /* Select With ATN3 Sequence */ | |
| 47bdd718 AB |
165 | #define TSC_XF_DMA_OUT_DIRECT 0x06 /* DMA Xfer Information out */ |
| 166 | #define TSC_XF_DMA_IN_DIRECT 0x86 /* DMA Xfer Information in */ | |
| 1da177e4 | 167 | |
| 47bdd718 AB |
168 | #define TSC_XF_DMA_OUT 0x43 /* DMA Xfer Information out */ |
| 169 | #define TSC_XF_DMA_IN 0xC3 /* DMA Xfer Information in */ | |
| 170 | #define TSC_XF_FIFO_OUT 0x03 /* FIFO Xfer Information out */ | |
| 171 | #define TSC_XF_FIFO_IN 0x83 /* FIFO Xfer Information in */ | |
| 1da177e4 LT |
172 | |
| 173 | #define TSC_MSG_ACCEPT 0x0F /* Message Accept */ | |
| 174 | ||
| 175 | /*----------------------------------------------------------------------*/ | |
| 176 | /* bit definition for Tulip SCSI Control 0 Register */ | |
| 177 | /*----------------------------------------------------------------------*/ | |
| 178 | #define TSC_RST_SEQ 0x20 /* Reset sequence counter */ | |
| 179 | #define TSC_FLUSH_FIFO 0x10 /* Flush FIFO */ | |
| 180 | #define TSC_ABT_CMD 0x04 /* Abort command (sequence) */ | |
| 181 | #define TSC_RST_CHIP 0x02 /* Reset SCSI Chip */ | |
| 182 | #define TSC_RST_BUS 0x01 /* Reset SCSI Bus */ | |
| 183 | ||
| 184 | /*----------------------------------------------------------------------*/ | |
| 185 | /* bit definition for Tulip SCSI Control 1 Register */ | |
| 186 | /*----------------------------------------------------------------------*/ | |
| 187 | #define TSC_EN_SCAM 0x80 /* Enable SCAM */ | |
| 188 | #define TSC_TIMER 0x40 /* Select timeout unit */ | |
| 189 | #define TSC_EN_SCSI2 0x20 /* SCSI-2 mode */ | |
| 190 | #define TSC_PWDN 0x10 /* Power down mode */ | |
| 191 | #define TSC_WIDE_CPU 0x08 /* Wide CPU */ | |
| 192 | #define TSC_HW_RESELECT 0x04 /* Enable HW reselect */ | |
| 193 | #define TSC_EN_BUS_OUT 0x02 /* Enable SCSI data bus out latch */ | |
| 194 | #define TSC_EN_BUS_IN 0x01 /* Enable SCSI data bus in latch */ | |
| 195 | ||
| 196 | /*----------------------------------------------------------------------*/ | |
| 197 | /* bit definition for Tulip SCSI Configuration Register */ | |
| 198 | /*----------------------------------------------------------------------*/ | |
| 199 | #define TSC_EN_LATCH 0x80 /* Enable phase latch */ | |
| 200 | #define TSC_INITIATOR 0x40 /* Initiator mode */ | |
| 201 | #define TSC_EN_SCSI_PAR 0x20 /* Enable SCSI parity */ | |
| 202 | #define TSC_DMA_8BIT 0x10 /* Alternate dma 8-bits mode */ | |
| 203 | #define TSC_DMA_16BIT 0x08 /* Alternate dma 16-bits mode */ | |
| 204 | #define TSC_EN_WDACK 0x04 /* Enable DACK while wide SCSI xfer */ | |
| 205 | #define TSC_ALT_PERIOD 0x02 /* Alternate sync period mode */ | |
| 206 | #define TSC_DIS_SCSIRST 0x01 /* Disable SCSI bus reset us */ | |
| 207 | ||
| 208 | #define TSC_INITDEFAULT (TSC_INITIATOR | TSC_EN_LATCH | TSC_ALT_PERIOD | TSC_DIS_SCSIRST) | |
| 209 | ||
| 210 | #define TSC_WIDE_SCSI 0x80 /* Enable Wide SCSI */ | |
| 211 | ||
| 212 | /*----------------------------------------------------------------------*/ | |
| 213 | /* bit definition for Tulip SCSI signal Register */ | |
| 214 | /*----------------------------------------------------------------------*/ | |
| 215 | #define TSC_RST_ACK 0x00 /* Release ACK signal */ | |
| 216 | #define TSC_RST_ATN 0x00 /* Release ATN signal */ | |
| 217 | #define TSC_RST_BSY 0x00 /* Release BSY signal */ | |
| 218 | ||
| 219 | #define TSC_SET_ACK 0x40 /* ACK signal */ | |
| 220 | #define TSC_SET_ATN 0x08 /* ATN signal */ | |
| 221 | ||
| 222 | #define TSC_REQI 0x80 /* REQ signal */ | |
| 223 | #define TSC_ACKI 0x40 /* ACK signal */ | |
| 224 | #define TSC_BSYI 0x20 /* BSY signal */ | |
| 225 | #define TSC_SELI 0x10 /* SEL signal */ | |
| 226 | #define TSC_ATNI 0x08 /* ATN signal */ | |
| 227 | #define TSC_MSGI 0x04 /* MSG signal */ | |
| 228 | #define TSC_CDI 0x02 /* C/D signal */ | |
| 229 | #define TSC_IOI 0x01 /* I/O signal */ | |
| 230 | ||
| 231 | ||
| 232 | /*----------------------------------------------------------------------*/ | |
| 233 | /* bit definition for Tulip SCSI Status 0 Register */ | |
| 234 | /*----------------------------------------------------------------------*/ | |
| 235 | #define TSS_INT_PENDING 0x80 /* Interrupt pending */ | |
| 236 | #define TSS_SEQ_ACTIVE 0x40 /* Sequencer active */ | |
| 237 | #define TSS_XFER_CNT 0x20 /* Transfer counter zero */ | |
| 238 | #define TSS_FIFO_EMPTY 0x10 /* FIFO empty */ | |
| 239 | #define TSS_PAR_ERROR 0x08 /* SCSI parity error */ | |
| 240 | #define TSS_PH_MASK 0x07 /* SCSI phase mask */ | |
| 241 | ||
| 242 | /*----------------------------------------------------------------------*/ | |
| 243 | /* bit definition for Tulip SCSI Status 1 Register */ | |
| 244 | /*----------------------------------------------------------------------*/ | |
| 245 | #define TSS_STATUS_RCV 0x08 /* Status received */ | |
| 246 | #define TSS_MSG_SEND 0x40 /* Message sent */ | |
| 247 | #define TSS_CMD_PH_CMP 0x20 /* command phase done */ | |
| 248 | #define TSS_DATA_PH_CMP 0x10 /* Data phase done */ | |
| 249 | #define TSS_STATUS_SEND 0x08 /* Status sent */ | |
| 250 | #define TSS_XFER_CMP 0x04 /* Transfer completed */ | |
| 251 | #define TSS_SEL_CMP 0x02 /* Selection completed */ | |
| 252 | #define TSS_ARB_CMP 0x01 /* Arbitration completed */ | |
| 253 | ||
| 254 | /*----------------------------------------------------------------------*/ | |
| 255 | /* bit definition for Tulip SCSI Status 2 Register */ | |
| 256 | /*----------------------------------------------------------------------*/ | |
| 257 | #define TSS_CMD_ABTED 0x80 /* Command aborted */ | |
| 258 | #define TSS_OFFSET_0 0x40 /* Offset counter zero */ | |
| 259 | #define TSS_FIFO_FULL 0x20 /* FIFO full */ | |
| 260 | #define TSS_TIMEOUT_0 0x10 /* Timeout counter zero */ | |
| 261 | #define TSS_BUSY_RLS 0x08 /* Busy release */ | |
| 262 | #define TSS_PH_MISMATCH 0x04 /* Phase mismatch */ | |
| 263 | #define TSS_SCSI_BUS_EN 0x02 /* SCSI data bus enable */ | |
| 264 | #define TSS_SCSIRST 0x01 /* SCSI bus reset in progress */ | |
| 265 | ||
| 266 | /*----------------------------------------------------------------------*/ | |
| 267 | /* bit definition for Tulip SCSI Interrupt Register */ | |
| 268 | /*----------------------------------------------------------------------*/ | |
| 269 | #define TSS_RESEL_INT 0x80 /* Reselected interrupt */ | |
| 270 | #define TSS_SEL_TIMEOUT 0x40 /* Selected/reselected timeout */ | |
| 271 | #define TSS_BUS_SERV 0x20 | |
| 272 | #define TSS_SCSIRST_INT 0x10 /* SCSI bus reset detected */ | |
| 273 | #define TSS_DISC_INT 0x08 /* Disconnected interrupt */ | |
| 274 | #define TSS_SEL_INT 0x04 /* Select interrupt */ | |
| 275 | #define TSS_SCAM_SEL 0x02 /* SCAM selected */ | |
| 276 | #define TSS_FUNC_COMP 0x01 | |
| 277 | ||
| 278 | /*----------------------------------------------------------------------*/ | |
| 279 | /* SCSI Phase Codes. */ | |
| 280 | /*----------------------------------------------------------------------*/ | |
| 281 | #define DATA_OUT 0 | |
| 282 | #define DATA_IN 1 /* 4 */ | |
| 283 | #define CMD_OUT 2 | |
| 284 | #define STATUS_IN 3 /* 6 */ | |
| 285 | #define MSG_OUT 6 /* 3 */ | |
| 286 | #define MSG_IN 7 | |
| 287 | ||
| 288 | ||
| 289 | ||
| 290 | /*----------------------------------------------------------------------*/ | |
| 291 | /* Command Codes of Tulip xfer Command register */ | |
| 292 | /*----------------------------------------------------------------------*/ | |
| 293 | #define TAX_X_FORC 0x02 | |
| 294 | #define TAX_X_ABT 0x04 | |
| 295 | #define TAX_X_CLR_FIFO 0x08 | |
| 296 | ||
| 297 | #define TAX_X_IN 0x21 | |
| 298 | #define TAX_X_OUT 0x01 | |
| 299 | #define TAX_SG_IN 0xA1 | |
| 300 | #define TAX_SG_OUT 0x81 | |
| 301 | ||
| 302 | /*----------------------------------------------------------------------*/ | |
| 303 | /* Tulip Interrupt Register */ | |
| 304 | /*----------------------------------------------------------------------*/ | |
| 305 | #define XCMP 0x01 | |
| 306 | #define FCMP 0x02 | |
| 307 | #define XABT 0x04 | |
| 308 | #define XERR 0x08 | |
| 309 | #define SCMP 0x10 | |
| 310 | #define IPEND 0x80 | |
| 311 | ||
| 312 | /*----------------------------------------------------------------------*/ | |
| 313 | /* Tulip DMA Status Register */ | |
| 314 | /*----------------------------------------------------------------------*/ | |
| 315 | #define XPEND 0x01 /* Transfer pending */ | |
| 316 | #define FEMPTY 0x02 /* FIFO empty */ | |
| 317 | ||
| 318 | ||
| 319 | ||
| 320 | /*----------------------------------------------------------------------*/ | |
| 321 | /* bit definition for TUL_GCTRL */ | |
| 322 | /*----------------------------------------------------------------------*/ | |
| 323 | #define EXTSG 0x80 | |
| 324 | #define EXTAD 0x60 | |
| 325 | #define SEG4K 0x08 | |
| 326 | #define EEPRG 0x04 | |
| 327 | #define MRMUL 0x02 | |
| 328 | ||
| 329 | /*----------------------------------------------------------------------*/ | |
| 330 | /* bit definition for TUL_NVRAM */ | |
| 331 | /*----------------------------------------------------------------------*/ | |
| 332 | #define SE2CS 0x08 | |
| 333 | #define SE2CLK 0x04 | |
| 334 | #define SE2DO 0x02 | |
| 335 | #define SE2DI 0x01 | |
| 336 | ||
| 337 | ||
| 338 | /************************************************************************/ | |
| 339 | /* Scatter-Gather Element Structure */ | |
| 340 | /************************************************************************/ | |
| 72d39fea AC |
341 | struct sg_entry { |
| 342 | u32 data; /* Data Pointer */ | |
| 343 | u32 len; /* Data Length */ | |
| 344 | }; | |
| 1da177e4 LT |
345 | |
| 346 | /*********************************************************************** | |
| 347 | SCSI Control Block | |
| 348 | ************************************************************************/ | |
| 72d39fea AC |
349 | struct scsi_ctrl_blk { |
| 350 | struct scsi_ctrl_blk *next; | |
| 351 | u8 status; /*4 */ | |
| 352 | u8 next_state; /*5 */ | |
| 353 | u8 mode; /*6 */ | |
| 354 | u8 msgin; /*7 SCB_Res0 */ | |
| 355 | u16 sgidx; /*8 */ | |
| 356 | u16 sgmax; /*A */ | |
| 1da177e4 | 357 | #ifdef ALPHA |
| 72d39fea | 358 | u32 reserved[2]; /*C */ |
| 1da177e4 | 359 | #else |
| 72d39fea | 360 | u32 reserved[3]; /*C */ |
| 1da177e4 LT |
361 | #endif |
| 362 | ||
| 72d39fea AC |
363 | u32 xferlen; /*18 Current xfer len */ |
| 364 | u32 totxlen; /*1C Total xfer len */ | |
| 365 | u32 paddr; /*20 SCB phy. Addr. */ | |
| 366 | ||
| 367 | u8 opcode; /*24 SCB command code */ | |
| 368 | u8 flags; /*25 SCB Flags */ | |
| 369 | u8 target; /*26 Target Id */ | |
| 370 | u8 lun; /*27 Lun */ | |
| 371 | u32 bufptr; /*28 Data Buffer Pointer */ | |
| 372 | u32 buflen; /*2C Data Allocation Length */ | |
| 373 | u8 sglen; /*30 SG list # */ | |
| 374 | u8 senselen; /*31 Sense Allocation Length */ | |
| 375 | u8 hastat; /*32 */ | |
| 376 | u8 tastat; /*33 */ | |
| 377 | u8 cdblen; /*34 CDB Length */ | |
| 378 | u8 ident; /*35 Identify */ | |
| 379 | u8 tagmsg; /*36 Tag Message */ | |
| 380 | u8 tagid; /*37 Queue Tag */ | |
| 381 | u8 cdb[12]; /*38 */ | |
| 382 | u32 sgpaddr; /*44 SG List/Sense Buf phy. Addr. */ | |
| 383 | u32 senseptr; /*48 Sense data pointer */ | |
| 384 | void (*post) (u8 *, u8 *); /*4C POST routine */ | |
| 385 | struct scsi_cmnd *srb; /*50 SRB Pointer */ | |
| 386 | struct sg_entry sglist[TOTAL_SG_ENTRY]; /*54 Start of SG list */ | |
| 387 | }; | |
| 388 | ||
| 389 | /* Bit Definition for status */ | |
| 1da177e4 LT |
390 | #define SCB_RENT 0x01 |
| 391 | #define SCB_PEND 0x02 | |
| 25985edc | 392 | #define SCB_CONTIG 0x04 /* Contingent Allegiance */ |
| 1da177e4 LT |
393 | #define SCB_SELECT 0x08 |
| 394 | #define SCB_BUSY 0x10 | |
| 395 | #define SCB_DONE 0x20 | |
| 396 | ||
| 397 | ||
| 72d39fea | 398 | /* Opcodes for opcode */ |
| 1da177e4 LT |
399 | #define ExecSCSI 0x1 |
| 400 | #define BusDevRst 0x2 | |
| 401 | #define AbortCmd 0x3 | |
| 402 | ||
| 403 | ||
| 72d39fea | 404 | /* Bit Definition for mode */ |
| 1da177e4 LT |
405 | #define SCM_RSENS 0x01 /* request sense mode */ |
| 406 | ||
| 407 | ||
| 72d39fea | 408 | /* Bit Definition for flags */ |
| 1da177e4 LT |
409 | #define SCF_DONE 0x01 |
| 410 | #define SCF_POST 0x02 | |
| 411 | #define SCF_SENSE 0x04 | |
| 412 | #define SCF_DIR 0x18 | |
| 413 | #define SCF_NO_DCHK 0x00 | |
| 414 | #define SCF_DIN 0x08 | |
| 415 | #define SCF_DOUT 0x10 | |
| 416 | #define SCF_NO_XF 0x18 | |
| 417 | #define SCF_WR_VF 0x20 /* Write verify turn on */ | |
| 418 | #define SCF_POLL 0x40 | |
| 419 | #define SCF_SG 0x80 | |
| 420 | ||
| 421 | /* Error Codes for SCB_HaStat */ | |
| 422 | #define HOST_SEL_TOUT 0x11 | |
| 423 | #define HOST_DO_DU 0x12 | |
| 424 | #define HOST_BUS_FREE 0x13 | |
| 425 | #define HOST_BAD_PHAS 0x14 | |
| 426 | #define HOST_INV_CMD 0x16 | |
| 427 | #define HOST_ABORTED 0x1A /* 07/21/98 */ | |
| 428 | #define HOST_SCSI_RST 0x1B | |
| 429 | #define HOST_DEV_RST 0x1C | |
| 430 | ||
| 431 | /* Error Codes for SCB_TaStat */ | |
| 432 | #define TARGET_CHKCOND 0x02 | |
| 433 | #define TARGET_BUSY 0x08 | |
| 434 | #define INI_QUEUE_FULL 0x28 | |
| 435 | ||
| 436 | /* SCSI MESSAGE */ | |
| 437 | #define MSG_COMP 0x00 | |
| 438 | #define MSG_EXTEND 0x01 | |
| 439 | #define MSG_SDP 0x02 | |
| 440 | #define MSG_RESTORE 0x03 | |
| 441 | #define MSG_DISC 0x04 | |
| 442 | #define MSG_IDE 0x05 | |
| 443 | #define MSG_ABORT 0x06 | |
| 444 | #define MSG_REJ 0x07 | |
| 445 | #define MSG_NOP 0x08 | |
| 446 | #define MSG_PARITY 0x09 | |
| 447 | #define MSG_LINK_COMP 0x0A | |
| 448 | #define MSG_LINK_FLAG 0x0B | |
| 449 | #define MSG_DEVRST 0x0C | |
| 450 | #define MSG_ABORT_TAG 0x0D | |
| 451 | ||
| 452 | /* Queue tag msg: Simple_quque_tag, Head_of_queue_tag, Ordered_queue_tag */ | |
| 453 | #define MSG_STAG 0x20 | |
| 454 | #define MSG_HTAG 0x21 | |
| 455 | #define MSG_OTAG 0x22 | |
| 456 | ||
| 457 | #define MSG_IGNOREWIDE 0x23 | |
| 458 | ||
| 459 | #define MSG_IDENT 0x80 | |
| 460 | ||
| 461 | /*********************************************************************** | |
| 462 | Target Device Control Structure | |
| 463 | **********************************************************************/ | |
| 464 | ||
| 72d39fea AC |
465 | struct target_control { |
| 466 | u16 flags; | |
| 467 | u8 js_period; | |
| 468 | u8 sconfig0; | |
| 469 | u16 drv_flags; | |
| 470 | u8 heads; | |
| 471 | u8 sectors; | |
| 472 | }; | |
| 1da177e4 LT |
473 | |
| 474 | /*********************************************************************** | |
| 475 | Target Device Control Structure | |
| 476 | **********************************************************************/ | |
| 477 | ||
| 478 | /* Bit Definition for TCF_Flags */ | |
| 479 | #define TCF_SCSI_RATE 0x0007 | |
| 480 | #define TCF_EN_DISC 0x0008 | |
| 481 | #define TCF_NO_SYNC_NEGO 0x0010 | |
| 482 | #define TCF_NO_WDTR 0x0020 | |
| 483 | #define TCF_EN_255 0x0040 | |
| 484 | #define TCF_EN_START 0x0080 | |
| 485 | #define TCF_WDTR_DONE 0x0100 | |
| 486 | #define TCF_SYNC_DONE 0x0200 | |
| 487 | #define TCF_BUSY 0x0400 | |
| 488 | ||
| 489 | ||
| 490 | /* Bit Definition for TCF_DrvFlags */ | |
| 491 | #define TCF_DRV_BUSY 0x01 /* Indicate target busy(driver) */ | |
| 492 | #define TCF_DRV_EN_TAG 0x0800 | |
| 493 | #define TCF_DRV_255_63 0x0400 | |
| 494 | ||
| 1da177e4 LT |
495 | /*********************************************************************** |
| 496 | Host Adapter Control Structure | |
| 497 | ************************************************************************/ | |
| 72d39fea AC |
498 | struct initio_host { |
| 499 | u16 addr; /* 00 */ | |
| 500 | u16 bios_addr; /* 02 */ | |
| 501 | u8 irq; /* 04 */ | |
| 502 | u8 scsi_id; /* 05 */ | |
| 503 | u8 max_tar; /* 06 */ | |
| 504 | u8 num_scbs; /* 07 */ | |
| 505 | ||
| 506 | u8 flags; /* 08 */ | |
| 507 | u8 index; /* 09 */ | |
| 508 | u8 ha_id; /* 0A */ | |
| 509 | u8 config; /* 0B */ | |
| 510 | u16 idmask; /* 0C */ | |
| 511 | u8 semaph; /* 0E */ | |
| 512 | u8 phase; /* 0F */ | |
| 513 | u8 jsstatus0; /* 10 */ | |
| 514 | u8 jsint; /* 11 */ | |
| 515 | u8 jsstatus1; /* 12 */ | |
| 516 | u8 sconf1; /* 13 */ | |
| 517 | ||
| 518 | u8 msg[8]; /* 14 */ | |
| 519 | struct scsi_ctrl_blk *next_avail; /* 1C */ | |
| 520 | struct scsi_ctrl_blk *scb; /* 20 */ | |
| 521 | struct scsi_ctrl_blk *scb_end; /* 24 */ /*UNUSED*/ | |
| 522 | struct scsi_ctrl_blk *next_pending; /* 28 */ | |
| 523 | struct scsi_ctrl_blk *next_contig; /* 2C */ /*UNUSED*/ | |
| 524 | struct scsi_ctrl_blk *active; /* 30 */ | |
| 525 | struct target_control *active_tc; /* 34 */ | |
| 526 | ||
| 527 | struct scsi_ctrl_blk *first_avail; /* 38 */ | |
| 528 | struct scsi_ctrl_blk *last_avail; /* 3C */ | |
| 529 | struct scsi_ctrl_blk *first_pending; /* 40 */ | |
| 530 | struct scsi_ctrl_blk *last_pending; /* 44 */ | |
| 531 | struct scsi_ctrl_blk *first_busy; /* 48 */ | |
| 532 | struct scsi_ctrl_blk *last_busy; /* 4C */ | |
| 533 | struct scsi_ctrl_blk *first_done; /* 50 */ | |
| 534 | struct scsi_ctrl_blk *last_done; /* 54 */ | |
| 535 | u8 max_tags[16]; /* 58 */ | |
| 536 | u8 act_tags[16]; /* 68 */ | |
| 537 | struct target_control targets[MAX_TARGETS]; /* 78 */ | |
| 538 | spinlock_t avail_lock; | |
| 539 | spinlock_t semaph_lock; | |
| 1da177e4 | 540 | struct pci_dev *pci_dev; |
| 72d39fea | 541 | }; |
| 1da177e4 LT |
542 | |
| 543 | /* Bit Definition for HCB_Config */ | |
| 544 | #define HCC_SCSI_RESET 0x01 | |
| 545 | #define HCC_EN_PAR 0x02 | |
| 546 | #define HCC_ACT_TERM1 0x04 | |
| 547 | #define HCC_ACT_TERM2 0x08 | |
| 548 | #define HCC_AUTO_TERM 0x10 | |
| 549 | #define HCC_EN_PWR 0x80 | |
| 550 | ||
| 551 | /* Bit Definition for HCB_Flags */ | |
| 552 | #define HCF_EXPECT_DISC 0x01 | |
| 553 | #define HCF_EXPECT_SELECT 0x02 | |
| 554 | #define HCF_EXPECT_RESET 0x10 | |
| 555 | #define HCF_EXPECT_DONE_DISC 0x20 | |
| 556 | ||
| 557 | /****************************************************************** | |
| 558 | Serial EEProm | |
| 559 | *******************************************************************/ | |
| 560 | ||
| 561 | typedef struct _NVRAM_SCSI { /* SCSI channel configuration */ | |
| 72d39fea AC |
562 | u8 NVM_ChSCSIID; /* 0Ch -> Channel SCSI ID */ |
| 563 | u8 NVM_ChConfig1; /* 0Dh -> Channel config 1 */ | |
| 564 | u8 NVM_ChConfig2; /* 0Eh -> Channel config 2 */ | |
| 565 | u8 NVM_NumOfTarg; /* 0Fh -> Number of SCSI target */ | |
| 1da177e4 | 566 | /* SCSI target configuration */ |
| 72d39fea AC |
567 | u8 NVM_Targ0Config; /* 10h -> Target 0 configuration */ |
| 568 | u8 NVM_Targ1Config; /* 11h -> Target 1 configuration */ | |
| 569 | u8 NVM_Targ2Config; /* 12h -> Target 2 configuration */ | |
| 570 | u8 NVM_Targ3Config; /* 13h -> Target 3 configuration */ | |
| 571 | u8 NVM_Targ4Config; /* 14h -> Target 4 configuration */ | |
| 572 | u8 NVM_Targ5Config; /* 15h -> Target 5 configuration */ | |
| 573 | u8 NVM_Targ6Config; /* 16h -> Target 6 configuration */ | |
| 574 | u8 NVM_Targ7Config; /* 17h -> Target 7 configuration */ | |
| 575 | u8 NVM_Targ8Config; /* 18h -> Target 8 configuration */ | |
| 576 | u8 NVM_Targ9Config; /* 19h -> Target 9 configuration */ | |
| 577 | u8 NVM_TargAConfig; /* 1Ah -> Target A configuration */ | |
| 578 | u8 NVM_TargBConfig; /* 1Bh -> Target B configuration */ | |
| 579 | u8 NVM_TargCConfig; /* 1Ch -> Target C configuration */ | |
| 580 | u8 NVM_TargDConfig; /* 1Dh -> Target D configuration */ | |
| 581 | u8 NVM_TargEConfig; /* 1Eh -> Target E configuration */ | |
| 582 | u8 NVM_TargFConfig; /* 1Fh -> Target F configuration */ | |
| 1da177e4 LT |
583 | } NVRAM_SCSI; |
| 584 | ||
| 585 | typedef struct _NVRAM { | |
| 586 | /*----------header ---------------*/ | |
| 72d39fea AC |
587 | u16 NVM_Signature; /* 0,1: Signature */ |
| 588 | u8 NVM_Size; /* 2: Size of data structure */ | |
| 589 | u8 NVM_Revision; /* 3: Revision of data structure */ | |
| 1da177e4 | 590 | /* ----Host Adapter Structure ---- */ |
| 72d39fea AC |
591 | u8 NVM_ModelByte0; /* 4: Model number (byte 0) */ |
| 592 | u8 NVM_ModelByte1; /* 5: Model number (byte 1) */ | |
| 593 | u8 NVM_ModelInfo; /* 6: Model information */ | |
| 594 | u8 NVM_NumOfCh; /* 7: Number of SCSI channel */ | |
| 595 | u8 NVM_BIOSConfig1; /* 8: BIOS configuration 1 */ | |
| 596 | u8 NVM_BIOSConfig2; /* 9: BIOS configuration 2 */ | |
| 597 | u8 NVM_HAConfig1; /* A: Hoat adapter configuration 1 */ | |
| 598 | u8 NVM_HAConfig2; /* B: Hoat adapter configuration 2 */ | |
| 1da177e4 | 599 | NVRAM_SCSI NVM_SCSIInfo[2]; |
| 72d39fea | 600 | u8 NVM_reserved[10]; |
| 1da177e4 | 601 | /* ---------- CheckSum ---------- */ |
| 72d39fea | 602 | u16 NVM_CheckSum; /* 0x3E, 0x3F: Checksum of NVRam */ |
| 1da177e4 LT |
603 | } NVRAM, *PNVRAM; |
| 604 | ||
| 605 | /* Bios Configuration for nvram->BIOSConfig1 */ | |
| 606 | #define NBC1_ENABLE 0x01 /* BIOS enable */ | |
| 607 | #define NBC1_8DRIVE 0x02 /* Support more than 2 drives */ | |
| 608 | #define NBC1_REMOVABLE 0x04 /* Support removable drive */ | |
| 609 | #define NBC1_INT19 0x08 /* Intercept int 19h */ | |
| 610 | #define NBC1_BIOSSCAN 0x10 /* Dynamic BIOS scan */ | |
| 611 | #define NBC1_LUNSUPPORT 0x40 /* Support LUN */ | |
| 612 | ||
| 613 | /* HA Configuration Byte 1 */ | |
| 614 | #define NHC1_BOOTIDMASK 0x0F /* Boot ID number */ | |
| 615 | #define NHC1_LUNMASK 0x70 /* Boot LUN number */ | |
| 616 | #define NHC1_CHANMASK 0x80 /* Boot Channel number */ | |
| 617 | ||
| 618 | /* Bit definition for nvram->SCSIconfig1 */ | |
| 619 | #define NCC1_BUSRESET 0x01 /* Reset SCSI bus at power up */ | |
| 620 | #define NCC1_PARITYCHK 0x02 /* SCSI parity enable */ | |
| 621 | #define NCC1_ACTTERM1 0x04 /* Enable active terminator 1 */ | |
| 622 | #define NCC1_ACTTERM2 0x08 /* Enable active terminator 2 */ | |
| 623 | #define NCC1_AUTOTERM 0x10 /* Enable auto terminator */ | |
| 624 | #define NCC1_PWRMGR 0x80 /* Enable power management */ | |
| 625 | ||
| 626 | /* Bit definition for SCSI Target configuration byte */ | |
| 627 | #define NTC_DISCONNECT 0x08 /* Enable SCSI disconnect */ | |
| 628 | #define NTC_SYNC 0x10 /* SYNC_NEGO */ | |
| 629 | #define NTC_NO_WDTR 0x20 /* SYNC_NEGO */ | |
| 630 | #define NTC_1GIGA 0x40 /* 255 head / 63 sectors (64/32) */ | |
| 631 | #define NTC_SPINUP 0x80 /* Start disk drive */ | |
| 632 | ||
| 633 | /* Default NVRam values */ | |
| 634 | #define INI_SIGNATURE 0xC925 | |
| 635 | #define NBC1_DEFAULT (NBC1_ENABLE) | |
| 636 | #define NCC1_DEFAULT (NCC1_BUSRESET | NCC1_AUTOTERM | NCC1_PARITYCHK) | |
| 637 | #define NTC_DEFAULT (NTC_NO_WDTR | NTC_1GIGA | NTC_DISCONNECT) | |
| 638 | ||
| 639 | /* SCSI related definition */ | |
| 640 | #define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */ | |
| 641 | #define DISC_ALLOW 0xC0 /* Disconnect is allowed */ | |
| 642 | #define SCSICMD_RequestSense 0x03 | |
| 643 | ||
| 1da177e4 LT |
644 | #define SCSI_ABORT_SNOOZE 0 |
| 645 | #define SCSI_ABORT_SUCCESS 1 | |
| 646 | #define SCSI_ABORT_PENDING 2 | |
| 647 | #define SCSI_ABORT_BUSY 3 | |
| 648 | #define SCSI_ABORT_NOT_RUNNING 4 | |
| 649 | #define SCSI_ABORT_ERROR 5 | |
| 650 | ||
| 651 | #define SCSI_RESET_SNOOZE 0 | |
| 652 | #define SCSI_RESET_PUNT 1 | |
| 653 | #define SCSI_RESET_SUCCESS 2 | |
| 654 | #define SCSI_RESET_PENDING 3 | |
| 655 | #define SCSI_RESET_WAKEUP 4 | |
| 656 | #define SCSI_RESET_NOT_RUNNING 5 | |
| 657 | #define SCSI_RESET_ERROR 6 | |
| 658 | ||
| 659 | #define SCSI_RESET_SYNCHRONOUS 0x01 | |
| 660 | #define SCSI_RESET_ASYNCHRONOUS 0x02 | |
| 661 | #define SCSI_RESET_SUGGEST_BUS_RESET 0x04 | |
| 662 | #define SCSI_RESET_SUGGEST_HOST_RESET 0x08 | |
| 663 | ||
| 664 | #define SCSI_RESET_BUS_RESET 0x100 | |
| 665 | #define SCSI_RESET_HOST_RESET 0x200 | |
| 666 | #define SCSI_RESET_ACTION 0xff | |
| 667 |