[linux.git] / drivers / clk / qcom / clk-rpmh.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 */

#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <soc/qcom/cmd-db.h>
#include <soc/qcom/rpmh.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#define CLK_RPMH_ARC_EN_OFFSET		0
#define CLK_RPMH_VRM_EN_OFFSET		4

/**
 * struct clk_rpmh - individual rpmh clock data structure
 * @hw:			handle between common and hardware-specific interfaces
 * @res_name:		resource name for the rpmh clock
 * @div:		clock divider to compute the clock rate
 * @res_addr:		base address of the rpmh resource within the RPMh
 * @res_on_val:		rpmh clock enable value
 * @state:		rpmh clock requested state
 * @aggr_state:		rpmh clock aggregated state
 * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh
 * @valid_state_mask:	mask to determine the state of the rpmh clock
 * @dev:		device to which it is attached
 * @peer:		pointer to the clock rpmh sibling
 */
struct clk_rpmh {
	struct clk_hw hw;
	const char *res_name;
	u8 div;
	u32 res_addr;
	u32 res_on_val;
	u32 state;
	u32 aggr_state;
	u32 last_sent_aggr_state;
	u32 valid_state_mask;
	struct device *dev;
	struct clk_rpmh *peer;
};

struct clk_rpmh_desc {
	struct clk_hw **clks;
	size_t num_clks;
};

static DEFINE_MUTEX(rpmh_clk_lock);

#define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,	\
			  _res_en_offset, _res_on, _div)		\
	static struct clk_rpmh _platform##_##_name_active;		\
	static struct clk_rpmh _platform##_##_name = {			\
		.res_name = _res_name,					\
		.res_addr = _res_en_offset,				\
		.res_on_val = _res_on,					\
		.div = _div,						\
		.peer = &_platform##_##_name_active,			\
		.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) |	\
				      BIT(RPMH_ACTIVE_ONLY_STATE) |	\
				      BIT(RPMH_SLEEP_STATE)),		\
		.hw.init = &(struct clk_init_data){			\
			.ops = &clk_rpmh_ops,				\
			.name = #_name,					\
			.parent_names = (const char *[]){ "xo_board" },	\
			.num_parents = 1,				\
		},							\
	};								\
	static struct clk_rpmh _platform##_##_name_active = {		\
		.res_name = _res_name,					\
		.res_addr = _res_en_offset,				\
		.res_on_val = _res_on,					\
		.div = _div,						\
		.peer = &_platform##_##_name,				\
		.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) |	\
					BIT(RPMH_ACTIVE_ONLY_STATE)),	\
		.hw.init = &(struct clk_init_data){			\
			.ops = &clk_rpmh_ops,				\
			.name = #_name_active,				\
			.parent_names = (const char *[]){ "xo_board" },	\
			.num_parents = 1,				\
		},							\
	}

#define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name,	\
			    _res_on, _div)				\
	__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,	\
			  CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)

#define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name,	\
				_div)					\
	__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,	\
			  CLK_RPMH_VRM_EN_OFFSET, 1, _div)

static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)
{
	return container_of(_hw, struct clk_rpmh, hw);
}

static inline bool has_state_changed(struct clk_rpmh *c, u32 state)
{
	return (c->last_sent_aggr_state & BIT(state))
		!= (c->aggr_state & BIT(state));
}

static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)
{
	struct tcs_cmd cmd = { 0 };
	u32 cmd_state, on_val;
	enum rpmh_state state = RPMH_SLEEP_STATE;
	int ret;

	cmd.addr = c->res_addr;
	cmd_state = c->aggr_state;
	on_val = c->res_on_val;

	for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) {
		if (has_state_changed(c, state)) {
			if (cmd_state & BIT(state))
				cmd.data = on_val;

			ret = rpmh_write_async(c->dev, state, &cmd, 1);
			if (ret) {
				dev_err(c->dev, "set %s state of %s failed: (%d)\n",
					!state ? "sleep" :
					state == RPMH_WAKE_ONLY_STATE	?
					"wake" : "active", c->res_name, ret);
				return ret;
			}
		}
	}

	c->last_sent_aggr_state = c->aggr_state;
	c->peer->last_sent_aggr_state =  c->last_sent_aggr_state;

	return 0;
}

/*
 * Update state and aggregate state values based on enable value.
 */
static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c,
						bool enable)
{
	int ret;

	/* Nothing required to be done if already off or on */
	if (enable == c->state)
		return 0;

	c->state = enable ? c->valid_state_mask : 0;
	c->aggr_state = c->state | c->peer->state;
	c->peer->aggr_state = c->aggr_state;

	ret = clk_rpmh_send_aggregate_command(c);
	if (!ret)
		return 0;

	if (ret && enable)
		c->state = 0;
	else if (ret)
		c->state = c->valid_state_mask;

	WARN(1, "clk: %s failed to %s\n", c->res_name,
	     enable ? "enable" : "disable");
	return ret;
}

static int clk_rpmh_prepare(struct clk_hw *hw)
{
	struct clk_rpmh *c = to_clk_rpmh(hw);
	int ret = 0;

	mutex_lock(&rpmh_clk_lock);
	ret = clk_rpmh_aggregate_state_send_command(c, true);
	mutex_unlock(&rpmh_clk_lock);

	return ret;
};

static void clk_rpmh_unprepare(struct clk_hw *hw)
{
	struct clk_rpmh *c = to_clk_rpmh(hw);

	mutex_lock(&rpmh_clk_lock);
	clk_rpmh_aggregate_state_send_command(c, false);
	mutex_unlock(&rpmh_clk_lock);
};

static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw,
					unsigned long prate)
{
	struct clk_rpmh *r = to_clk_rpmh(hw);

	/*
	 * RPMh clocks have a fixed rate. Return static rate.
	 */
	return prate / r->div;
}

static const struct clk_ops clk_rpmh_ops = {
	.prepare	= clk_rpmh_prepare,
	.unprepare	= clk_rpmh_unprepare,
	.recalc_rate	= clk_rpmh_recalc_rate,
};

/* Resource name must match resource id present in cmd-db. */
DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);

static struct clk_hw *sdm845_rpmh_clocks[] = {
	[RPMH_CXO_CLK]		= &sdm845_bi_tcxo.hw,
	[RPMH_CXO_CLK_A]	= &sdm845_bi_tcxo_ao.hw,
	[RPMH_LN_BB_CLK2]	= &sdm845_ln_bb_clk2.hw,
	[RPMH_LN_BB_CLK2_A]	= &sdm845_ln_bb_clk2_ao.hw,
	[RPMH_LN_BB_CLK3]	= &sdm845_ln_bb_clk3.hw,
	[RPMH_LN_BB_CLK3_A]	= &sdm845_ln_bb_clk3_ao.hw,
	[RPMH_RF_CLK1]		= &sdm845_rf_clk1.hw,
	[RPMH_RF_CLK1_A]	= &sdm845_rf_clk1_ao.hw,
	[RPMH_RF_CLK2]		= &sdm845_rf_clk2.hw,
	[RPMH_RF_CLK2_A]	= &sdm845_rf_clk2_ao.hw,
	[RPMH_RF_CLK3]		= &sdm845_rf_clk3.hw,
	[RPMH_RF_CLK3_A]	= &sdm845_rf_clk3_ao.hw,
};

static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
	.clks = sdm845_rpmh_clocks,
	.num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
};

static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
					 void *data)
{
	struct clk_rpmh_desc *rpmh = data;
	unsigned int idx = clkspec->args[0];

	if (idx >= rpmh->num_clks) {
		pr_err("%s: invalid index %u\n", __func__, idx);
		return ERR_PTR(-EINVAL);
	}

	return rpmh->clks[idx];
}

static int clk_rpmh_probe(struct platform_device *pdev)
{
	struct clk_hw **hw_clks;
	struct clk_rpmh *rpmh_clk;
	const struct clk_rpmh_desc *desc;
	int ret, i;

	desc = of_device_get_match_data(&pdev->dev);
	if (!desc)
		return -ENODEV;

	hw_clks = desc->clks;

	for (i = 0; i < desc->num_clks; i++) {
		u32 res_addr;

		rpmh_clk = to_clk_rpmh(hw_clks[i]);
		res_addr = cmd_db_read_addr(rpmh_clk->res_name);
		if (!res_addr) {
			dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
				rpmh_clk->res_name);
			return -ENODEV;
		}
		rpmh_clk->res_addr += res_addr;
		rpmh_clk->dev = &pdev->dev;

		ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
		if (ret) {
			dev_err(&pdev->dev, "failed to register %s\n",
				hw_clks[i]->init->name);
			return ret;
		}
	}

	/* typecast to silence compiler warning */
	ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get,
					  (void *)desc);
	if (ret) {
		dev_err(&pdev->dev, "Failed to add clock provider\n");
		return ret;
	}

	dev_dbg(&pdev->dev, "Registered RPMh clocks\n");

	return 0;
}

static const struct of_device_id clk_rpmh_match_table[] = {
	{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
	{ }
};
MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);

static struct platform_driver clk_rpmh_driver = {
	.probe		= clk_rpmh_probe,
	.driver		= {
		.name	= "clk-rpmh",
		.of_match_table = clk_rpmh_match_table,
	},
};

static int __init clk_rpmh_init(void)
{
	return platform_driver_register(&clk_rpmh_driver);
}
subsys_initcall(clk_rpmh_init);

static void __exit clk_rpmh_exit(void)
{
	platform_driver_unregister(&clk_rpmh_driver);
}
module_exit(clk_rpmh_exit);

MODULE_DESCRIPTION("QCOM RPMh Clock Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9c7e4702 TD	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2018, The Linux Foundation. All rights reserved.
	4	*/
	5
	6	#include <linux/clk-provider.h>
	7	#include <linux/err.h>
	8	#include <linux/kernel.h>
	9	#include <linux/module.h>
	10	#include <linux/of.h>
	11	#include <linux/of_device.h>
	12	#include <linux/platform_device.h>
	13	#include <soc/qcom/cmd-db.h>
	14	#include <soc/qcom/rpmh.h>
	15
	16	#include <dt-bindings/clock/qcom,rpmh.h>
	17
	18	#define CLK_RPMH_ARC_EN_OFFSET 0
	19	#define CLK_RPMH_VRM_EN_OFFSET 4
	20
	21	/**
	22	* struct clk_rpmh - individual rpmh clock data structure
	23	* @hw: handle between common and hardware-specific interfaces
	24	* @res_name: resource name for the rpmh clock
	25	* @div: clock divider to compute the clock rate
	26	* @res_addr: base address of the rpmh resource within the RPMh
	27	* @res_on_val: rpmh clock enable value
	28	* @state: rpmh clock requested state
	29	* @aggr_state: rpmh clock aggregated state
	30	* @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh
	31	* @valid_state_mask: mask to determine the state of the rpmh clock
	32	* @dev: device to which it is attached
	33	* @peer: pointer to the clock rpmh sibling
	34	*/
	35	struct clk_rpmh {
	36	struct clk_hw hw;
	37	const char *res_name;
	38	u8 div;
	39	u32 res_addr;
	40	u32 res_on_val;
	41	u32 state;
	42	u32 aggr_state;
	43	u32 last_sent_aggr_state;
	44	u32 valid_state_mask;
	45	struct device *dev;
	46	struct clk_rpmh *peer;
	47	};
	48
	49	struct clk_rpmh_desc {
	50	struct clk_hw **clks;
	51	size_t num_clks;
	52	};
	53
	54	static DEFINE_MUTEX(rpmh_clk_lock);
	55
	56	#define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
	57	_res_en_offset, _res_on, _div) \
	58	static struct clk_rpmh _platform##_##_name_active; \
	59	static struct clk_rpmh _platform##_##_name = { \
	60	.res_name = _res_name, \
	61	.res_addr = _res_en_offset, \
	62	.res_on_val = _res_on, \
	63	.div = _div, \
	64	.peer = &_platform##_##_name_active, \
65	.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) \| \
66	BIT(RPMH_ACTIVE_ONLY_STATE) \| \
67	BIT(RPMH_SLEEP_STATE)), \
68	.hw.init = &(struct clk_init_data){ \
69	.ops = &clk_rpmh_ops, \
70	.name = #_name, \
71	.parent_names = (const char *[]){ "xo_board" }, \
72	.num_parents = 1, \
73	}, \
74	}; \
75	static struct clk_rpmh _platform##_##_name_active = { \
76	.res_name = _res_name, \
77	.res_addr = _res_en_offset, \
78	.res_on_val = _res_on, \
79	.div = _div, \
80	.peer = &_platform##_##_name, \
81	.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) \| \
82	BIT(RPMH_ACTIVE_ONLY_STATE)), \
83	.hw.init = &(struct clk_init_data){ \
84	.ops = &clk_rpmh_ops, \
85	.name = #_name_active, \
86	.parent_names = (const char *[]){ "xo_board" }, \
87	.num_parents = 1, \
88	}, \
89	}
90
91	#define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name, \
92	_res_on, _div) \
93	__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
94	CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
95
96	#define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name, \
97	_div) \
98	__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
99	CLK_RPMH_VRM_EN_OFFSET, 1, _div)
100
101	static inline struct clk_rpmh to_clk_rpmh(struct clk_hw _hw)
102	{
103	return container_of(_hw, struct clk_rpmh, hw);
104	}
105
106	static inline bool has_state_changed(struct clk_rpmh *c, u32 state)
107	{
108	return (c->last_sent_aggr_state & BIT(state))
109	!= (c->aggr_state & BIT(state));
110	}
111
112	static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)
113	{
114	struct tcs_cmd cmd = { 0 };
115	u32 cmd_state, on_val;
116	enum rpmh_state state = RPMH_SLEEP_STATE;
117	int ret;
118
119	cmd.addr = c->res_addr;
120	cmd_state = c->aggr_state;
121	on_val = c->res_on_val;
122
123	for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) {
124	if (has_state_changed(c, state)) {
125	if (cmd_state & BIT(state))
126	cmd.data = on_val;
127
128	ret = rpmh_write_async(c->dev, state, &cmd, 1);
129	if (ret) {
130	dev_err(c->dev, "set %s state of %s failed: (%d)\n",
131	!state ? "sleep" :
132	state == RPMH_WAKE_ONLY_STATE ?
133	"wake" : "active", c->res_name, ret);
134	return ret;
135	}
136	}
137	}
138
139	c->last_sent_aggr_state = c->aggr_state;
140	c->peer->last_sent_aggr_state = c->last_sent_aggr_state;
141
142	return 0;
143	}
144
145	/*
146	* Update state and aggregate state values based on enable value.
147	*/
148	static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c,
149	bool enable)
150	{
151	int ret;
152
153	/* Nothing required to be done if already off or on */
154	if (enable == c->state)
155	return 0;
156
157	c->state = enable ? c->valid_state_mask : 0;
158	c->aggr_state = c->state \| c->peer->state;
159	c->peer->aggr_state = c->aggr_state;
160
161	ret = clk_rpmh_send_aggregate_command(c);
162	if (!ret)
163	return 0;
164
165	if (ret && enable)
166	c->state = 0;
167	else if (ret)
168	c->state = c->valid_state_mask;
169
170	WARN(1, "clk: %s failed to %s\n", c->res_name,
171	enable ? "enable" : "disable");
172	return ret;
173	}
174
175	static int clk_rpmh_prepare(struct clk_hw *hw)
176	{
177	struct clk_rpmh *c = to_clk_rpmh(hw);
178	int ret = 0;
179
180	mutex_lock(&rpmh_clk_lock);
181	ret = clk_rpmh_aggregate_state_send_command(c, true);
182	mutex_unlock(&rpmh_clk_lock);
183
184	return ret;
185	};
186
187	static void clk_rpmh_unprepare(struct clk_hw *hw)
188	{
189	struct clk_rpmh *c = to_clk_rpmh(hw);
190
191	mutex_lock(&rpmh_clk_lock);
192	clk_rpmh_aggregate_state_send_command(c, false);
193	mutex_unlock(&rpmh_clk_lock);
194	};
195
196	static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw,
197	unsigned long prate)
198	{
199	struct clk_rpmh *r = to_clk_rpmh(hw);
200
201	/*
202	* RPMh clocks have a fixed rate. Return static rate.
203	*/
204	return prate / r->div;
205	}
206
207	static const struct clk_ops clk_rpmh_ops = {
208	.prepare = clk_rpmh_prepare,
209	.unprepare = clk_rpmh_unprepare,
210	.recalc_rate = clk_rpmh_recalc_rate,
211	};
212
213	/* Resource name must match resource id present in cmd-db. */
214	DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
215	DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
216	DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
217	DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
218	DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
219	DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
220
221	static struct clk_hw *sdm845_rpmh_clocks[] = {
222	[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
223	[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
224	[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
225	[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
226	[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
227	[RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
228	[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
229	[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
230	[RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
231	[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
232	[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
233	[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
234	};
235
236	static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
237	.clks = sdm845_rpmh_clocks,
238	.num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
239	};
240
241	static struct clk_hw of_clk_rpmh_hw_get(struct of_phandle_args clkspec,
242	void *data)
243	{
244	struct clk_rpmh_desc *rpmh = data;
245	unsigned int idx = clkspec->args[0];
246
247	if (idx >= rpmh->num_clks) {
248	pr_err("%s: invalid index %u\n", __func__, idx);
249	return ERR_PTR(-EINVAL);
250	}
251
252	return rpmh->clks[idx];
253	}
254
255	static int clk_rpmh_probe(struct platform_device *pdev)
256	{
257	struct clk_hw **hw_clks;
258	struct clk_rpmh *rpmh_clk;
259	const struct clk_rpmh_desc *desc;
260	int ret, i;
261
262	desc = of_device_get_match_data(&pdev->dev);
263	if (!desc)
264	return -ENODEV;
265
266	hw_clks = desc->clks;
267
268	for (i = 0; i < desc->num_clks; i++) {
269	u32 res_addr;
270
271	rpmh_clk = to_clk_rpmh(hw_clks[i]);
272	res_addr = cmd_db_read_addr(rpmh_clk->res_name);
273	if (!res_addr) {
274	dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
275	rpmh_clk->res_name);
276	return -ENODEV;
277	}
278	rpmh_clk->res_addr += res_addr;
279	rpmh_clk->dev = &pdev->dev;
280
281	ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
282	if (ret) {
283	dev_err(&pdev->dev, "failed to register %s\n",
284	hw_clks[i]->init->name);
285	return ret;
286	}
287	}
288
289	/* typecast to silence compiler warning */
290	ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get,
291	(void *)desc);
292	if (ret) {
293	dev_err(&pdev->dev, "Failed to add clock provider\n");
294	return ret;
295	}
296
297	dev_dbg(&pdev->dev, "Registered RPMh clocks\n");
298
299	return 0;
300	}
301
302	static const struct of_device_id clk_rpmh_match_table[] = {
303	{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
304	{ }
305	};
306	MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
307
308	static struct platform_driver clk_rpmh_driver = {
309	.probe = clk_rpmh_probe,
310	.driver = {
311	.name = "clk-rpmh",
312	.of_match_table = clk_rpmh_match_table,
313	},
314	};
315
316	static int __init clk_rpmh_init(void)
317	{
318	return platform_driver_register(&clk_rpmh_driver);
319	}
320	subsys_initcall(clk_rpmh_init);
321
322	static void __exit clk_rpmh_exit(void)
323	{
324	platform_driver_unregister(&clk_rpmh_driver);
325	}
326	module_exit(clk_rpmh_exit);
327
328	MODULE_DESCRIPTION("QCOM RPMh Clock Driver");
329	MODULE_LICENSE("GPL v2");