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Commit | Line | Data |
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57844a8f TG |
1 | /* |
2 | * Copyright (C) 2009 Thomas Gleixner <[email protected]> | |
3 | * | |
4 | * For licencing details see kernel-base/COPYING | |
5 | */ | |
6 | #include <linux/init.h> | |
9325a28c | 7 | #include <linux/ioport.h> |
72550b3a | 8 | #include <linux/module.h> |
294ee6f8 | 9 | #include <linux/pci.h> |
57844a8f | 10 | |
816c25e7 | 11 | #include <asm/bios_ebda.h> |
6f30c1ac | 12 | #include <asm/paravirt.h> |
b72d0db9 | 13 | #include <asm/pci_x86.h> |
294ee6f8 | 14 | #include <asm/pci.h> |
fd6c6661 | 15 | #include <asm/mpspec.h> |
8fee697d | 16 | #include <asm/setup.h> |
736decac | 17 | #include <asm/apic.h> |
6b18ae3e | 18 | #include <asm/e820.h> |
845b3944 | 19 | #include <asm/time.h> |
d9112f43 | 20 | #include <asm/irq.h> |
4a8e2a31 | 21 | #include <asm/io_apic.h> |
71054d88 | 22 | #include <asm/hpet.h> |
fd12a0d6 | 23 | #include <asm/pat.h> |
2d826404 | 24 | #include <asm/tsc.h> |
338bac52 | 25 | #include <asm/iommu.h> |
064a59b6 | 26 | #include <asm/mach_traps.h> |
57844a8f | 27 | |
148f9bb8 | 28 | void x86_init_noop(void) { } |
f4848472 | 29 | void __init x86_init_uint_noop(unsigned int unused) { } |
d07c1be0 | 30 | int __init iommu_init_noop(void) { return 0; } |
62ad33f6 | 31 | void iommu_shutdown_noop(void) { } |
57844a8f TG |
32 | |
33 | /* | |
34 | * The platform setup functions are preset with the default functions | |
35 | * for standard PC hardware. | |
36 | */ | |
54e2603f | 37 | struct x86_init_ops x86_init __initdata = { |
f7cf5a5b TG |
38 | |
39 | .resources = { | |
5d94e81f | 40 | .probe_roms = probe_roms, |
8fee697d | 41 | .reserve_resources = reserve_standard_io_resources, |
6b18ae3e | 42 | .memory_setup = default_machine_specific_memory_setup, |
f7cf5a5b | 43 | }, |
f4848472 TG |
44 | |
45 | .mpparse = { | |
46 | .mpc_record = x86_init_uint_noop, | |
de934103 | 47 | .setup_ioapic_ids = x86_init_noop, |
fd6c6661 | 48 | .mpc_apic_id = default_mpc_apic_id, |
72302142 | 49 | .smp_read_mpc_oem = default_smp_read_mpc_oem, |
90e1c696 | 50 | .mpc_oem_bus_info = default_mpc_oem_bus_info, |
b3f1b617 TG |
51 | .find_smp_config = default_find_smp_config, |
52 | .get_smp_config = default_get_smp_config, | |
f4848472 | 53 | }, |
d9112f43 TG |
54 | |
55 | .irqs = { | |
56 | .pre_vector_init = init_ISA_irqs, | |
66bcaf0b | 57 | .intr_init = native_init_IRQ, |
428cf902 | 58 | .trap_init = x86_init_noop, |
d9112f43 | 59 | }, |
42bbdb43 TG |
60 | |
61 | .oem = { | |
62 | .arch_setup = x86_init_noop, | |
6f30c1ac | 63 | .banner = default_banner, |
42bbdb43 | 64 | }, |
030cb6c0 TG |
65 | |
66 | .paging = { | |
7737b215 | 67 | .pagetable_init = native_pagetable_init, |
030cb6c0 | 68 | }, |
736decac TG |
69 | |
70 | .timers = { | |
71 | .setup_percpu_clockev = setup_boot_APIC_clock, | |
845b3944 TG |
72 | .tsc_pre_init = x86_init_noop, |
73 | .timer_init = hpet_time_init, | |
6b617e22 | 74 | .wallclock_init = x86_init_noop, |
736decac | 75 | }, |
d07c1be0 FT |
76 | |
77 | .iommu = { | |
78 | .iommu_init = iommu_init_noop, | |
79 | }, | |
b72d0db9 TG |
80 | |
81 | .pci = { | |
82 | .init = x86_default_pci_init, | |
ab3b3793 | 83 | .init_irq = x86_default_pci_init_irq, |
9325a28c | 84 | .fixup_irqs = x86_default_pci_fixup_irqs, |
b72d0db9 | 85 | }, |
736decac TG |
86 | }; |
87 | ||
148f9bb8 | 88 | struct x86_cpuinit_ops x86_cpuinit = { |
df156f90 | 89 | .early_percpu_clock_init = x86_init_noop, |
736decac | 90 | .setup_percpu_clockev = setup_secondary_APIC_clock, |
57844a8f | 91 | }; |
2d826404 | 92 | |
78c06176 | 93 | static void default_nmi_init(void) { }; |
c516ac58 | 94 | static int default_i8042_detect(void) { return 1; }; |
78c06176 | 95 | |
2d826404 TG |
96 | struct x86_platform_ops x86_platform = { |
97 | .calibrate_tsc = native_calibrate_tsc, | |
7bd867df FT |
98 | .get_wallclock = mach_get_cmos_time, |
99 | .set_wallclock = mach_set_rtc_mmss, | |
338bac52 | 100 | .iommu_shutdown = iommu_shutdown_noop, |
eb41c8be | 101 | .is_untracked_pat_range = is_ISA_range, |
c516ac58 | 102 | .nmi_init = default_nmi_init, |
064a59b6 | 103 | .get_nmi_reason = default_get_nmi_reason, |
b74f05d6 MT |
104 | .i8042_detect = default_i8042_detect, |
105 | .save_sched_clock_state = tsc_save_sched_clock_state, | |
106 | .restore_sched_clock_state = tsc_restore_sched_clock_state, | |
2d826404 | 107 | }; |
72550b3a PA |
108 | |
109 | EXPORT_SYMBOL_GPL(x86_platform); | |
4287d824 TP |
110 | |
111 | #if defined(CONFIG_PCI_MSI) | |
294ee6f8 | 112 | struct x86_msi_ops x86_msi = { |
71054d88 | 113 | .setup_msi_irqs = native_setup_msi_irqs, |
7601384f | 114 | .compose_msi_msg = native_compose_msi_msg, |
71054d88 JR |
115 | .teardown_msi_irq = native_teardown_msi_irq, |
116 | .teardown_msi_irqs = default_teardown_msi_irqs, | |
117 | .restore_msi_irqs = default_restore_msi_irqs, | |
118 | .setup_hpet_msi = default_setup_hpet_msi, | |
294ee6f8 | 119 | }; |
4a8e2a31 | 120 | |
4287d824 TP |
121 | /* MSI arch specific hooks */ |
122 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
123 | { | |
124 | return x86_msi.setup_msi_irqs(dev, nvec, type); | |
125 | } | |
126 | ||
127 | void arch_teardown_msi_irqs(struct pci_dev *dev) | |
128 | { | |
129 | x86_msi.teardown_msi_irqs(dev); | |
130 | } | |
131 | ||
132 | void arch_teardown_msi_irq(unsigned int irq) | |
133 | { | |
134 | x86_msi.teardown_msi_irq(irq); | |
135 | } | |
136 | ||
ac8344c4 | 137 | void arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 138 | { |
ac8344c4 | 139 | x86_msi.restore_msi_irqs(dev); |
4287d824 TP |
140 | } |
141 | #endif | |
142 | ||
4a8e2a31 | 143 | struct x86_io_apic_ops x86_io_apic_ops = { |
1c4248ca JR |
144 | .init = native_io_apic_init_mappings, |
145 | .read = native_io_apic_read, | |
146 | .write = native_io_apic_write, | |
147 | .modify = native_io_apic_modify, | |
148 | .disable = native_disable_io_apic, | |
afcc8a40 | 149 | .print_entries = native_io_apic_print_entries, |
373dd7a2 | 150 | .set_affinity = native_ioapic_set_affinity, |
a6a25dd3 | 151 | .setup_entry = native_setup_ioapic_entry, |
da165322 | 152 | .eoi_ioapic_pin = native_eoi_ioapic_pin, |
4a8e2a31 | 153 | }; |